38 lines
662 B
Systemverilog
38 lines
662 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2024 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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package foo_pkg;
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function int foo_func;
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input int b;
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int b_current;
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return 0;
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endfunction
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endpackage
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module sub;
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int a = 1212;
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endmodule
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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int cyc;
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import foo_pkg::*;
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sub sub();
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always @ (posedge clk) begin
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cyc <= cyc + 1;
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if (cyc == 10) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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