37 lines
716 B
Systemverilog
37 lines
716 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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wire u1;
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wire u2;
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wire u3;
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wire u4;
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wire u5;
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wire u6;
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pullup (supply1) pu1(a);
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pullup (strong1) pu2(a);
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pullup (pull1) pu3(a);
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pullup (weak1) pu4(a);
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pullup (supply1, supply0) pu5(a);
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pullup (strong0, strong1) pu6(a);
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wire d1;
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wire d2;
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wire d3;
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wire d4;
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wire d5;
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wire d6;
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pulldown (supply0) pd1(a);
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pulldown (strong0) pd2(a);
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pulldown (pull0) pd3(a);
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pulldown (weak0) pd4(a);
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pulldown (supply0, supply1) pd5(a);
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pulldown (strong1, strong0) pd6(a);
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endmodule
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