verilator/test_regress/t/t_udp_bad_illegal_output.out

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%Error: t/t_udp_bad_illegal_output.v:9:8: For sequential UDP, the output must be of 'reg' data type
: ... note: In instance 'top'
9 | output dout;
| ^~~~
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error: t/t_udp_bad_illegal_output.v:16:22: Illegal value for sequential UDP line output
: ... note: In instance 'top'
16 | 1 1 ? : ?: *;
| ^
%Error: t/t_udp_bad_illegal_output.v:17:11: There can be only one edge tigger signal
: ... note: In instance 'top'
17 | f r 0 : ?: 0;
| ^
%Error: t/t_udp_bad_illegal_output.v:18:22: Illegal value for sequential UDP line output
: ... note: In instance 'top'
18 | 0 0 0 : ?: *;
| ^
%Error: t/t_udp_bad_illegal_output.v:29:9: There should not be a edge trigger for combinational UDP table line
: ... note: In instance 'top'
29 | r ? 1 : 1;
| ^
%Error: t/t_udp_bad_illegal_output.v:31:20: Illegal value for combinational UDP line output
: ... note: In instance 'top'
31 | 1 1 ? : *;
| ^
%Error: t/t_udp_bad_illegal_output.v:33:20: Illegal value for combinational UDP line output
: ... note: In instance 'top'
33 | 0 0 0 : *;
| ^
%Error: Exiting due to