44 lines
860 B
Systemverilog
Executable File
44 lines
860 B
Systemverilog
Executable File
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2020 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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primitive t_gate_comb(dout, a, b, c);
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input a, b, c;
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output dout;
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table
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r 0 1 : ?: 1;
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r ? 1 : ?: 1;
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r ? 0 : ?: 1;
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0 1 0 : ?: 0;
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1 1 ? : ?: *;
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f r 0 : ?: 0;
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0 0 0 : ?: *;
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endtable
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endprimitive
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primitive t_gate_seq(dout, a, b, c);
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input a, b, c;
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output dout;
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table
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x 0 1 : 1;
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r ? 1 : 1;
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0 1 0 : 0;
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1 1 ? : *;
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1 0 0 : 0;
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0 0 0 : *;
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endtable
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endprimitive
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module top (a, b, c, o1, o2);
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input a, b, c;
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output o1, o2;
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t_gate_comb(o1, a, b, c);
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t_gate_seq(o2, a, b, c);
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endmodule
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