67 lines
1.4 KiB
Systemverilog
67 lines
1.4 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2015 by Mike Thyer.
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// SPDX-License-Identifier: CC0-1.0
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primitive d_edge_ff (q, clock, data);
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output q; reg q;
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input clock, data;
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initial q = 1'b1;
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table
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// clock data q q+
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// obtain output on rising edge of clock
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F 0 : ? : 0 ;
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(10) 1 : ? : 1 ;
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R 0 : ? : 1 ;
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(0?) 1 : ? : 0 ;
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endtable
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endprimitive
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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reg d, q;
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d_edge_ff g (q, clk, d);
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int cycle=0;
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initial d = 0;
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always @(posedge clk or negedge clk) begin
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cycle <= cycle+1;
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if (cycle==0) begin
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d = 1;
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end
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else if (cycle==1) begin
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d = 0;
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if (q != 1) $stop;
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end
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else if (cycle==2) begin
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if (q != 1) $stop;
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end
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else if (cycle==3) begin
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if (q != 0) $stop;
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end
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else if (cycle==4) begin
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d = 1;
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if (q != 1) $stop;
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end
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else if (cycle==5) begin
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$display("d=%d clk=%d cycle=%0d", d, clk, cycle);
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if (q != 1) $stop;
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end
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else if (cycle==6) begin
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if (q != 0) $stop;
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end
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else if (cycle==7) begin
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if (q != 1) $stop;
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end
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else if (cycle >= 8) begin
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if (q != 0) $stop;;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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