28 lines
550 B
Systemverilog
Executable File
28 lines
550 B
Systemverilog
Executable File
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2020 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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primitive or_gate(dout, a, b, c);
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output dout;
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input a, b, c;
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reg dout;
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table
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x 0 1 : 1;
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0 ? 1 : 1;
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0 1 0 : 0;
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1 1 ? : 1;
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1 0 0 : 0;
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0 0 0 : 1;
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endtable
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endprimitive
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module top (a, b, c, o);
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input a, b, c;
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output o;
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or_gate(o, a, b, c);
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endmodule
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