37 lines
820 B
Systemverilog
37 lines
820 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2024 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t(/*AUTOARG*/);
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union soft {
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bit [7:0] val1;
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bit [3:0] val2;
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} u;
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union soft packed {
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bit [7 : 0] val1;
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bit [3 : 0] val2;
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} u2;
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initial begin
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u.val1 = 8'h7c;
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if (u.val1 != 8'h7c) $stop;
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u.val2 = 4'h6;
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if (u.val2 != 4'h6) $stop;
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$display("%p", u);
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if(u.val1 != 8'h76) $stop;
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u2.val1 = 8'h7c;
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if(u2.val1 != 8'h7c) $stop;
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u2.val2 = 4'h6;
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if(u2.val2 != 4'h6) $stop;
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$display("%p", u2);
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if(u2.val1 != 8'h76) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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