98 lines
2.6 KiB
Systemverilog
98 lines
2.6 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2023 by Yutetsu TAKATSUKASA.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/);
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typedef int ai3_t[1:3];
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ai3_t a3;
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int a9[1:9];
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logic [2:0] s0;
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logic [2:0] s1[1:3];
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logic [2:0] s1b[3:1];
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logic [2:0] s3[2:8];
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logic [2:0] s3b[8:2];
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initial begin
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s0 = 3'd1;
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s1[1] = 3'd2;
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s1[2] = 3'd3;
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s1[3] = 3'd4;
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s1b[1] = 3'd5;
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s1b[2] = 3'd6;
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s1b[3] = 3'd7;
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a3 = '{1, 2, 3};
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a9 = {a3, 4, 5, a3, 6};
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if (a9[1] != 1) $stop;
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if (a9[2] != 2) $stop;
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if (a9[3] != 3) $stop;
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if (a9[4] != 4) $stop;
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if (a9[5] != 5) $stop;
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if (a9[6] != 1) $stop;
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if (a9[7] != 2) $stop;
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if (a9[8] != 3) $stop;
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if (a9[9] != 6) $stop;
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s3 = {s0, s1, s1b};
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if (s3[2] != s0) $stop;
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if (s3[3] != s1[1]) $stop;
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if (s3[4] != s1[2]) $stop;
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if (s3[5] != s1[3]) $stop;
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if (s3[6] != s1b[3]) $stop;
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if (s3[7] != s1b[2]) $stop;
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if (s3[8] != s1b[1]) $stop;
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s3[2:8] = {s0, s1[1:2], s1[3], s1b[3], s1b[2:1]};
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if (s3[2] != s0) $stop;
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if (s3[3] != s1[1]) $stop;
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if (s3[4] != s1[2]) $stop;
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if (s3[5] != s1[3]) $stop;
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if (s3[6] != s1b[3]) $stop;
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if (s3[7] != s1b[2]) $stop;
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if (s3[8] != s1b[1]) $stop;
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s3 = {s0, s1[1], s1[2:3], s1b[3:2], s1b[1]};
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if (s3[2] != s0) $stop;
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if (s3[3] != s1[1]) $stop;
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if (s3[4] != s1[2]) $stop;
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if (s3[5] != s1[3]) $stop;
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if (s3[6] != s1b[3]) $stop;
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if (s3[7] != s1b[2]) $stop;
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if (s3[8] != s1b[1]) $stop;
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s3b = {s0, s1, s1b};
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if (s3b[8] != s0) $stop;
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if (s3b[7] != s1[1]) $stop;
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if (s3b[6] != s1[2]) $stop;
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if (s3b[5] != s1[3]) $stop;
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if (s3b[4] != s1b[3]) $stop;
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if (s3b[3] != s1b[2]) $stop;
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if (s3b[2] != s1b[1]) $stop;
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s3b[8:2] = {s0, s1[1:2], s1[3], s1b[3], s1b[2:1]};
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if (s3b[8] != s0) $stop;
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if (s3b[7] != s1[1]) $stop;
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if (s3b[6] != s1[2]) $stop;
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if (s3b[5] != s1[3]) $stop;
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if (s3b[4] != s1b[3]) $stop;
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if (s3b[3] != s1b[2]) $stop;
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if (s3b[2] != s1b[1]) $stop;
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s3b = {s0, s1[1], s1[2:3], s1b[3:2], s1b[1]};
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if (s3b[8] != s0) $stop;
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if (s3b[7] != s1[1]) $stop;
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if (s3b[6] != s1[2]) $stop;
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if (s3b[5] != s1[3]) $stop;
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if (s3b[4] != s1b[3]) $stop;
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if (s3b[3] != s1b[2]) $stop;
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if (s3b[2] != s1b[1]) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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