45 lines
946 B
Systemverilog
45 lines
946 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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typedef struct packed {
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logic [149:0] hdr;
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logic [1:0] vc;
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} packet_t;
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module t;
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logic clk;
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typedef struct {packet_t [1:0] pkt_i;} dut_if_t;
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dut_if_t dut[2];
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initial begin
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clk = 0;
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forever #(0.5) clk = ~clk;
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end
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task automatic send_req_packets(int module_id, int channel);
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packet_t packet = '0;
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dut[module_id].pkt_i[channel] = packet;
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@(posedge clk); // If you comment out this line. It will build.
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endtask
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initial begin
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for (int m = 0; m < 2; m++) begin
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for (int i = 0; i < 2; i++) begin
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automatic int mod = m;
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automatic int ch = i;
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send_req_packets(mod, ch);
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end
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end
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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