45 lines
992 B
Systemverilog
45 lines
992 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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`define stop $stop
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0);
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interface Ifc;
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bit [7:0] rdata;
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endinterface
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class drv_c;
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virtual Ifc vif;
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virtual task run();
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#100;
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`checkh(vif.rdata, 8'haa);
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#100;
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`checkh(vif.rdata, 8'haa);
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#100;
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endtask
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endclass
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module dut (output wire [7:0] rd_val);
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assign rd_val = 8'haa;
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endmodule
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module m;
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drv_c d_0;
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Ifc u_Ifc ();
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dut u_dut (.rd_val (u_Ifc.rdata));
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initial begin
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d_0 = new();
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d_0.vif = u_Ifc;
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//u_Ifc.rdata = 10;
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d_0.run();
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$write("*-* All Finished *-*\n");
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$finish(2);
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end
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endmodule
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