80 lines
1.8 KiB
Systemverilog
Executable File
80 lines
1.8 KiB
Systemverilog
Executable File
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by PlanV GmbH.
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// SPDX-License-Identifier: CC0-1.0
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`timescale 1ns/1ps
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interface INTF;
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logic x;
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logic y;
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logic z;
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logic [7:0] data;
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endinterface
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class Dummy;
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virtual INTF vif;
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function new(virtual INTF vif);
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this.vif = vif;
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endfunction
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task write_data(logic [7:0] d);
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vif.data = d;
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endtask
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endclass
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module t_virtual_interface_member_trigger();
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// === Part 1: logic trigger false loop test ===
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logic s1, s2, src_val;
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INTF intf_loop();
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virtual INTF vif_loop;
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assign intf_loop.x = s1;
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assign intf_loop.y = src_val;
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assign intf_loop.z = !intf_loop.y;
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assign s2 = intf_loop.z;
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assign s1 = s2;
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// === Part 2: data transfer chain test ===
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logic [7:0] data;
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INTF intf_read();
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INTF intf_write();
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assign intf_read.data = data;
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assign data = intf_write.data;
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virtual INTF vif_read, vif_write;
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Dummy cl_1, cl_2;
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initial begin
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// Test 1: no false loop with member-level trigger
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#1ns;
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vif_loop = intf_loop;
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cl_1 = new(vif_loop);
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#1ns;
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src_val = 0;
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#1ns;
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if (!(cl_1.vif.x == 1 && cl_1.vif.y == 0 && cl_1.vif.z == 1 && s1 == 1 && s2 == 1)) $stop;
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// Test 2: write from module
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#1ns;
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vif_read = intf_read;
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vif_write = intf_write;
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#1ns;
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vif_write.data = 8'hA5;
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#1ns;
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if (vif_read.data !== 8'hA5) $stop;
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// Test 3: write from class
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#1ns;
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cl_2 = new(vif_write);
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#1ns;
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cl_2.write_data(8'hB7);
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#1ns;
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if (vif_read.data !== 8'hB7) $stop;
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#5ns;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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