65 lines
1.3 KiB
Systemverilog
65 lines
1.3 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Yilou Wang.
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// SPDX-License-Identifier: CC0-1.0
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package my_pkg;
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virtual class CallBackBase;
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pure virtual function void add(int a, int b);
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endclass
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class my_class extends CallBackBase;
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virtual my_interface vif;
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function new(virtual my_interface vif);
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this.vif = vif;
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$display("my_class::new");
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vif.register_callback(this);
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endfunction
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function void add(int a, int b);
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// $display("a + b = %0d", a + b);
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endfunction
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endclass
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endpackage
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interface my_interface;
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import my_pkg::*;
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CallBackBase callback_obj;
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function void register_callback(CallBackBase obj);
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callback_obj = obj;
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endfunction
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logic clk;
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always @(posedge clk) begin
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if (callback_obj != null)
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callback_obj.add(1, 2);
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else $display("callback_obj is null");
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end
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endinterface
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module t;
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import my_pkg::*;
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logic clk = 0;
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my_interface vif();
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my_class cl;
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assign vif.clk = clk;
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initial begin
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forever #5 clk = ~clk;
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end
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initial begin
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#10;
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cl = new(vif);
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#100;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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