12 lines
376 B
Plaintext
12 lines
376 B
Plaintext
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2022 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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`verilator_config
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timing_on --file "t/t_timing_off.v" --lines 23
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timing_off -file "t/t_timing_off.v" -lines 26-34
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timing_on -file "t/t_timing_off.v" -lines 35-38
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