106 lines
3.1 KiB
Systemverilog
106 lines
3.1 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// Copyright 2024 by Diego Roux. This program is free software; you can
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// redistribute it and/or modify it under the terms of either the GNU
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// Lesser General Public License Version 3 or the Perl Artistic License
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// Version 2.0.
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// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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`ifdef VERILATOR_COMMENTS
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`define PUBLIC_FLAT_RD /*verilator public_flat_rd*/
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`define PUBLIC_FLAT_RW /*verilator public_flat_rw*/
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`else
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`define PUBLIC_FLAT_RD
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`define PUBLIC_FLAT_RW
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`endif
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module test ();
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`ifdef VERILATOR
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`systemc_header
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extern "C" int mon_check();
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`verilog
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`endif
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reg [7:0] read_bytes [0:3] `PUBLIC_FLAT_RD;
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reg [7:0] read_bytes_nonzero_index [1:4] `PUBLIC_FLAT_RD;
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reg [7:0] read_bytes_rl [3:0] `PUBLIC_FLAT_RD;
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reg [15:0] read_shorts [0:3] `PUBLIC_FLAT_RD;
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reg [31:0] read_words [0:3] `PUBLIC_FLAT_RD;
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reg [31:0] read_words_rl [3:0] `PUBLIC_FLAT_RD;
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reg [63:0] read_longs [0:3] `PUBLIC_FLAT_RD;
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integer read_integers [0:3] `PUBLIC_FLAT_RD;
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reg [68:0] read_customs [0:3] `PUBLIC_FLAT_RD;
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reg [68:0] read_customs_nonzero_index_rl [4:1] `PUBLIC_FLAT_RD;
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reg [7:0] read_scalar `PUBLIC_FLAT_RD;
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reg [7:0] read_bounds [1:3] `PUBLIC_FLAT_RD;
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integer status;
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initial begin
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read_bytes[0] = 8'had;
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read_bytes[1] = 8'hde;
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read_bytes[2] = 8'hef;
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read_bytes[3] = 8'hbe;
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read_bytes_rl[3] = 8'had;
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read_bytes_rl[2] = 8'hde;
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read_bytes_rl[1] = 8'hef;
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read_bytes_rl[0] = 8'hbe;
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read_bytes_nonzero_index[1] = 8'had;
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read_bytes_nonzero_index[2] = 8'hde;
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read_bytes_nonzero_index[3] = 8'hef;
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read_bytes_nonzero_index[4] = 8'hbe;
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read_shorts[0] = 16'hdead;
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read_shorts[1] = 16'hbeef;
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read_shorts[2] = 16'hcafe;
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read_shorts[3] = 16'hf00d;
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read_words[0] = 32'hdeadbeef;
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read_words[1] = 32'hcafef00d;
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read_words[2] = 32'h00010203;
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read_words[3] = 32'h04050607;
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read_integers[0] = 32'hdeadbeef;
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read_integers[1] = 32'hcafef00d;
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read_integers[2] = 32'h00010203;
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read_integers[3] = 32'h04050607;
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read_longs[0] = 64'hdeadbeefcafef00d;
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read_longs[1] = 64'h0001020304050607;
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read_longs[2] = 64'h08090a0b0c0d0e0f;
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read_longs[3] = 64'h1011121314151617;
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read_customs[0] = 69'hFAdeadbeefcafef00d; //0x001F'FFFF'FFFF'FFFF'FFFF
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read_customs[1] = 69'hF50001020304050607;
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read_customs[2] = 69'h0A08090a0b0c0d0e0f;
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read_customs[3] = 69'h051011121314151617;
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read_customs_nonzero_index_rl[4] = 69'hFAdeadbeefcafef00d; //0x001F'FFFF'FFFF'FFFF'FFFF
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read_customs_nonzero_index_rl[3] = 69'hF50001020304050607;
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read_customs_nonzero_index_rl[2] = 69'h0A08090a0b0c0d0e0f;
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read_customs_nonzero_index_rl[1] = 69'h051011121314151617;
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`ifdef IVERILOG
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status = $mon_check;
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`endif
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`ifdef VERILATOR
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status = $c32("mon_check()");
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`endif
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if (status != 0) begin
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$write("%%Error: t_vpi_get_value_array.cpp:%0d: C Test failed\n", status);
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$stop;
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end
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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