45 lines
1.2 KiB
Systemverilog
45 lines
1.2 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// Copyright 2024 by Wilson Snyder. This program is free software; you can
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// redistribute it and/or modify it under the terms of either the GNU
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// Lesser General Public License Version 3 or the Perl Artistic License
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// Version 2.0.
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// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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); /*verilator public_module*/
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`ifdef VERILATOR
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`systemc_header
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extern "C" int mon_check();
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`verilog
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`endif
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input clk;
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logic [3:2][5:3] arr_cdata [1:0][2:1]; // 2x3 (6) bit words
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logic [7:6][12:7] arr_sdata [5:4][6:5]; // 2x6 (12) bit words
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logic [11:10][25:11] arr_idata [9:8][10:9]; // 2x15 (30) bit words
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logic [15:14][44:15] arr_qdata [13:12][14:13]; // 2x30 (60) bit words
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logic [19:18][81:19] arr_wdata [17:16][18:17]; // 2x63 (126) bit words
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int status;
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initial begin
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`ifdef VERILATOR
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status = $c32("mon_check()");
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`else
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status = $mon_check();
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`endif
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if (status!=0) begin
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$write("%%Error: t_vpi_multidim.cpp:%0d: C Test failed\n", status);
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$stop;
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end
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule : t
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