43 lines
1.1 KiB
Systemverilog
43 lines
1.1 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// Copyright 2010 by Wilson Snyder. This program is free software; you can
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// redistribute it and/or modify it under the terms of either the GNU
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// Lesser General Public License Version 3 or the Perl Artistic License
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// Version 2.0.
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// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import "DPI-C" context function int mon_check();
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parameter int dollarUnitInt = 3;
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package somepackage;
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parameter int someInt = 5;
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parameter int anotherInt = 6;
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endpackage
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module t (/*AUTOARG*/
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);
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parameter int someOtherInt = 7;
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parameter int yetAnotherInt = 9;
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parameter int stillAnotherInt = 17;
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parameter int register = 0;
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parameter int n_str = 2;
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// Edge case with pvi code generation
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parameter string someString [n_str] = '{default: ""};
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logic reference;
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integer status;
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initial begin
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status = mon_check();
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if (status!=0) begin
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$write("%%Error: t_vpi_package.cpp:%0d: C Test failed\n", status);
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$stop;
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end
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule : t
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