27 lines
739 B
Systemverilog
27 lines
739 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Geza Lore.
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// SPDX-License-Identifier: CC0-1.0
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import "DPI-C" pure function int identity(input int value);
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module t;
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initial begin
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int n = 0;
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logic [127:0] val = 128'b1;
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logic [15:0] one = 16'b1;
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// This condition involves multiple wide temporaries, and an over-width
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// shift, all of which requires V3Premit to fix up.
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while (|((val[ 7'(one >> identity(32)) +: 96] << n) >> n)) begin
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++n;
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end
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$display("n=%0d", n);
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if (n != 96) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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