39 lines
816 B
Systemverilog
39 lines
816 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module for prepareClone/atClone APIs
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//
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// This model counts from 0 to 8. It forks a child process (in C++) at 6
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// and waits for the child to simulate and exit for resumption (of the parent).
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2023 by Yinan Xu.
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// SPDX-License-Identifier: CC0-1.0
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module top(
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input clock,
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input reset,
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input is_parent,
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output do_clone
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);
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reg [3:0] counter;
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assign do_clone = counter == 4'h6;
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always @(posedge clock) begin
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if (reset) begin
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counter <= 4'h0;
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end
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else begin
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counter <= counter + 4'h1;
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$write("counter = %d\n", counter);
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end
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if (counter[3]) begin
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if (is_parent) begin
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$write("*-* All Finished *-*\n");
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end
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$finish(0);
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end
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end
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endmodule
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