77 lines
2.1 KiB
Systemverilog
77 lines
2.1 KiB
Systemverilog
// DESCRIPTION: Verilator: Confirm x randomization stability
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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int cyc = 0;
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logic [31:0] uninitialized;
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logic [31:0] x_assigned = '0;
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`ifdef ADD_SIGNAL
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logic [31:0] added;
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logic [31:0] x_assigned_added = '0;
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`endif
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logic [31:0] unused;
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logic [31:0] x_assigned_unused = '0;
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logic [31:0] uninitialized2;
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logic [255:0] big;
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int random_init = $random();
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sub_no_inline the_sub_no_inline_1();
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sub_no_inline the_sub_no_inline_2();
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sub_yes_inline the_sub_yes_inline_1();
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sub_yes_inline the_sub_yes_inline_2();
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initial begin
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$display("uninitialized = 0x%x", uninitialized);
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$display("x_assigned (initial) = 0x%x", x_assigned);
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$display("uninitialized2 = 0x%x", uninitialized2);
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$display("big = 0x%x", big);
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$display("random_init = 0x%x", random_init);
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end
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always @(posedge clk) begin
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x_assigned_unused = 'x;
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x_assigned <= 'x;
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`ifdef ADD_SIGNAL
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x_assigned_added <= 'x;
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`endif
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cyc <= cyc + 1;
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$display("rand = 0x%x", $random());
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if (cyc == 4) begin
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$display("x_assigned = 0x%x", x_assigned);
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`ifndef NOT_RAND
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if (uninitialized == uninitialized2) $stop();
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if (the_sub_yes_inline_1.no_init == the_sub_yes_inline_2.no_init) $stop();
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if (the_sub_no_inline_1.no_init == the_sub_no_inline_2.no_init) $stop();
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`endif
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`ifdef ADD_SIGNAL
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if (added == 0) $stop();
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if (x_assigned_added == 0) $stop();
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`endif
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$display("Last rand = 0x%x", $random());
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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module sub_no_inline; /* verilator no_inline_module */
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logic [63:0] no_init;
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initial $display("%m no_init 0x%0x", no_init);
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endmodule
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module sub_yes_inline; /* verilator inline_module */
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logic [63:0] no_init;
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initial $display("%m no_init 0x%0x", no_init);
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endmodule
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