parameterize clk_port_name and output_folder

Makefile

@@ -1,13 +1,15 @@
 PROJ_PATH = $(shell pwd)
 SHELL := /bin/bash
 
+O ?= $(PROJ_PATH)/result
 DESIGN ?= gcd
-SDC_FILE ?= $(PROJ_PATH)/example/gcd.sdc
+SDC_FILE ?= $(PROJ_PATH)/scripts/default.sdc
 RTL_FILES ?= $(shell find $(PROJ_PATH)/example -name "*.v")
 export CLK_FREQ_MHZ ?= 500
+export CLK_PORT_NAME ?= clk
 PDK = nangate45
 
-RESULT_DIR = $(PROJ_PATH)/result/$(DESIGN)-$(CLK_FREQ_MHZ)MHz
+RESULT_DIR = $(O)/$(DESIGN)-$(CLK_FREQ_MHZ)MHz
 SCRIPT_DIR = $(PROJ_PATH)/scripts
 NETLIST_SYN_V   = $(RESULT_DIR)/$(DESIGN).netlist.syn.v
 NETLIST_FIXED_V = $(RESULT_DIR)/$(DESIGN).netlist.fixed.v

README.md

@@ -69,7 +69,10 @@ make sta
 有两种操作方式：
 1. 命令行传参方式, 在命令行中指定其他设计的信息
    ```shell
-   make sta DESIGN=mydesign SDC_FILE=/path/to/my.sdc RTL_FILES="/path/to/mydesign.v /path/to/xxx.v ..." CLK_FREQ_MHZ=100
+   make -C /path/to/this_repo sta \
+       DESIGN=mydesign SDC_FILE=/path/to/my.sdc \
+       CLK_FREQ_MHZ=100 CLK_PORT_NAME=clk O=/path/to/pwd \
+       RTL_FILES="/path/to/mydesign.v /path/to/xxx.v ..."
    ```
 1. 修改变量方式, 在`Makefile`中修改上述变量, 然后运行`make sta`
 

scripts/default.sdc

@@ -1,11 +1,17 @@
-set clk_port_name clk
+set CLK_PORT_NAME clk
+if {[info exists env(CLK_PORT_NAME)]} {
+  set CLK_PORT_NAME $::env(CLK_PORT_NAME)
+} else {
+  puts "Warning: Environment CLK_PORT_NAME is not defined. Use $CLK_PORT_NAME by default."
+}
+
 set CLK_FREQ_MHZ 500
 if {[info exists env(CLK_FREQ_MHZ)]} {
   set CLK_FREQ_MHZ $::env(CLK_FREQ_MHZ)
 } else {
   puts "Warning: Environment CLK_FREQ_MHZ is not defined. Use $CLK_FREQ_MHZ MHz by default."
 }
-set clk_io_pct 0.2
 
-set clk_port [get_ports $clk_port_name]
+set clk_io_pct 0.2
+set clk_port [get_ports $CLK_PORT_NAME]
 create_clock -name core_clock -period [expr 1000.0 / $CLK_FREQ_MHZ] $clk_port