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yosys-sta
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yosys.tcl: pass by parameter

This commit is contained in:
Zihao Yu 2023-07-24 02:18:37 +08:00
parent 0d43cd7870
commit 2931248e8a
2 changed files with 13 additions and 16 deletions
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12
Makefile
View File

@ -1,7 +1,11 @@
export PROJ_PATH = $(shell pwd)
PROJ_PATH = $(shell pwd)
DESIGN = gcd
SDC_FILE = $(PROJ_PATH)/gcd/gcd.sdc
RTL_FILES = $(shell find $(PROJ_PATH)/gcd -name "*.v")
export FOUNDRY_PATH = $(PROJ_PATH)/nangate45
export RTL_PATH = $(PROJ_PATH)/gcd
export RESULT_PATH = $(PROJ_PATH)/result
export RESULT_PATH = $(PROJ_PATH)/result/syn
$(shell mkdir -p $(RESULT_PATH))
@ -9,6 +13,6 @@ init:
test -e nangate45 || (wget -O - https://ysyx.oscc.cc/slides/resources/archive/nangate45.tar.bz2 | tar xfj -)
syn:
yosys yosys_gcd.tcl | tee $(RESULT_PATH)/yosys.log
echo tcl yosys.tcl $(DESIGN) $(SDC_FILE) \"$(RTL_FILES)\" | yosys -s - | tee $(RESULT_PATH)/yosys.log
.PHONY: init syn

17
yosys_gcd.tcl → yosys.tcl
View File

@ -1,15 +1,11 @@
# export PROJ_PATH=??
# docker run --rm -v $PROJ_PATH:$PROJ_PATH -e PROJ_PATH=$PROJ_PATH hdlc/yosys yosys $PROJ_PATH/gcd/synth.yosys_0.9.tcl
#===========================================================
# set parameter
#===========================================================
set DESIGN "gcd"
set PROJ_PATH $::env(PROJ_PATH)
set DESIGN [lindex $argv 0]
set FOUNDRY_PATH $::env(FOUNDRY_PATH)
set RESULT_PATH $::env(RESULT_PATH)
set RPT_PATH $::env(RESULT_PATH)
set RTL_PATH $::env(RTL_PATH)
set SDC_FILE "$RTL_PATH/$DESIGN.sdc"
set SDC_FILE [lindex $argv 1]
set VERILOG_FILES [string map {"\"" ""} [lindex $argv 2]]
set MERGED_LIB_FILE "$FOUNDRY_PATH/lib/merged.lib"
set BLACKBOX_V_FILE "$FOUNDRY_PATH/verilog/blackbox.v"
@ -24,9 +20,6 @@ set MIN_BUF_CELL_AND_PORTS "BUF_X1 A Z"
set VERILOG_INCLUDE_DIRS "\
"
set VERILOG_FILES " \
$RTL_PATH/$DESIGN.v \
"
#===========================================================
# main running
@ -121,8 +114,8 @@ insbuf -buf {*}$MIN_BUF_CELL_AND_PORTS
opt_clean -purge
# reports
tee -o $RPT_PATH/synth_check.txt check
tee -o $RPT_PATH/synth_stat.txt stat -liberty $MERGED_LIB_FILE
tee -o $RESULT_PATH/synth_check.txt check
tee -o $RESULT_PATH/synth_stat.txt stat -liberty $MERGED_LIB_FILE
# write synthesized design
#write_verilog -norename -noattr -noexpr -nohex -nodec $RESULTS_DIR/1_1_yosys.v