let iNO read verilog instead of def file

Makefile

@@ -9,8 +9,6 @@ RESULT_DIR = $(PROJ_PATH)/result/$(DESIGN)-$(CLK_FREQ_MHZ)MHz
 SCRIPT_DIR = $(PROJ_PATH)/scripts
 NETLIST_SYN_V   = $(RESULT_DIR)/$(DESIGN).netlist.syn.v
 NETLIST_FIXED_V = $(RESULT_DIR)/$(DESIGN).netlist.fixed.v
-SYN_DEF = $(RESULT_DIR)/$(DESIGN).syn.def
-FIXED_DEF = $(RESULT_DIR)/$(DESIGN).fixed.def
 TIMING_RPT = $(RESULT_DIR)/$(DESIGN).rpt
 
 init:
@@ -21,19 +19,15 @@ $(NETLIST_SYN_V): $(RTL_FILES) $(SCRIPT_DIR)/yosys.tcl
 	mkdir -p $(@D)
 	echo tcl $(SCRIPT_DIR)/yosys.tcl $(DESIGN) \"$(RTL_FILES)\" $@ | yosys -l $(@D)/yosys.log -s -
 
-def: $(SYN_DEF)
-$(SYN_DEF): $(SCRIPT_DIR)/def.tcl $(NETLIST_SYN_V)
-	LD_LIBRARY_PATH=bin/ ./bin/iEDA $^ $(DESIGN) $@ | tee $(RESULT_DIR)/gen-def.log
-
 fix-fanout: $(NETLIST_FIXED_V)
-$(NETLIST_FIXED_V): $(SCRIPT_DIR)/fix-fanout.tcl $(SDC_FILE) $(SYN_DEF)
-	LD_LIBRARY_PATH=bin/ ./bin/iEDA -script $^ $@ 2>&1 | tee $(RESULT_DIR)/fix-fanout.log
+$(NETLIST_FIXED_V): $(SCRIPT_DIR)/fix-fanout.tcl $(SDC_FILE) $(NETLIST_SYN_V)
+	./bin/iEDA -script $^ $(DESIGN) $@ 2>&1 | tee $(RESULT_DIR)/fix-fanout.log
 
 sta: $(TIMING_RPT)
 $(TIMING_RPT): $(SCRIPT_DIR)/sta.tcl $(SDC_FILE) $(NETLIST_FIXED_V)
-	LD_LIBRARY_PATH=bin/ ./bin/iEDA -script $^ $(DESIGN) 2>&1 | tee $(RESULT_DIR)/sta.log
+	./bin/iEDA -script $^ $(DESIGN) 2>&1 | tee $(RESULT_DIR)/sta.log
 
 clean:
 	-rm -rf result/
 
-.PHONY: init syn def fix-fanout sta clean
+.PHONY: init syn fix-fanout sta clean

README.md

@@ -40,11 +40,8 @@ make sta
 * `synth_stat.txt` - Yosys综合的面积报告
 * `synth_check.txt` - Yosys综合的检查报告, 用户需仔细阅读并决定是否需要排除相应警告
 * `yosys.log` - Yosys综合的完整日志
-* `gcd.syn.def` - 根据网表文件生成的def文件
-* `gen-def.log` - 根据网表文件生成def文件的日志
 * `gcd.netlist.fixed.v` - iNO优化扇出后的网表文件
 * `fix-fanout.log` - iNO优化扇出的日志
-  * 其中含有一些`Error pin grid coordinate, pin = xxx`的错误信息, 目前可忽略
 * `gcd.rpt` - iSTA的时序分析报告, 包含WNS, TNS和时序路径
 * `gcd.cap` - iSTA的电容违例报告
 * `gcd.fanout` - iSTA的扇出违例报告
@@ -72,4 +69,4 @@ make sta
 1. 相应的RTL设计
 1. sdc文件
 1. yosys生成的网表文件
-1. iEDA的版本号, 可通过命令`echo exit | LD_LIBRARY_PATH=bin/ ./bin/iEDA -v`获取
+1. iEDA的版本号, 可通过命令`echo exit | ./bin/iEDA -v`获取

scripts/def.tcl

@@ -1,10 +0,0 @@
-set PROJ_PATH "[file dirname [info script]]/.."
-set NETLIST_SYN_V [lindex $argv 0]
-set DESIGN        [lindex $argv 1]
-set DEF_FILE      [lindex $argv 2]
-
-set LEF_FILES "\
-  $PROJ_PATH/nangate45/lef/NangateOpenCellLibrary.tech.lef \
-  $PROJ_PATH/nangate45/lef/NangateOpenCellLibrary.macro.mod.lef"
-
-verilog_to_def -lef $LEF_FILES -verilog $NETLIST_SYN_V -top $DESIGN -def $DEF_FILE

scripts/fix-fanout.tcl

@@ -1,14 +1,14 @@
 set PROJ_PATH "[file dirname [info script]]/.."
 set SDC_FILE   [lindex $argv 0]
-set DEF_FILE   [lindex $argv 1]
-set NETLIST_FIXED_V [lindex $argv 2]
+set NETLIST_V  [lindex $argv 1]
+set DESIGN     [lindex $argv 2]
+set NETLIST_FIXED_V [lindex $argv 3]
 
 db_init -lib_path $PROJ_PATH/nangate45/lib/merged.lib
 db_init -sdc_path $SDC_FILE
 tech_lef_init -path $PROJ_PATH/nangate45/lef/NangateOpenCellLibrary.tech.lef
 lef_init -path $PROJ_PATH/nangate45/lef/NangateOpenCellLibrary.macro.mod.lef
 
-def_init -path $DEF_FILE
+verilog_init -path $NETLIST_V -top $DESIGN
 run_no_fixfanout -config $PROJ_PATH/scripts/fix-fanout.json
-#def_save -path fix_fanout_result.def
 netlist_save -path $NETLIST_FIXED_V -exclude_cell_names {}