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yosys-sta
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fix division

This commit is contained in:
Zihao Yu 2024-02-08 18:02:25 +08:00
parent 1b3bc721e4
commit 9b3f065b07
2 changed files with 2 additions and 2 deletions
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2
example/gcd.sdc
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@ -8,4 +8,4 @@ if {[info exists env(CLK_FREQ_MHZ)]} {
set clk_io_pct 0.2
set clk_port [get_ports $clk_port_name]
create_clock -name core_clock -period [expr 1000 / $CLK_FREQ_MHZ] $clk_port
create_clock -name core_clock -period [expr 1000.0 / $CLK_FREQ_MHZ] $clk_port

2
yosys.tcl
View File

@ -20,7 +20,7 @@ if {[info exists env(CLK_FREQ_MHZ)]} {
} else {
puts "Warning: Environment CLK_FREQ_MHZ is not defined. Use $CLK_FREQ_MHZ MHz by default."
}
set CLK_PERIOD_NS [expr 1000 / $CLK_FREQ_MHZ]
set CLK_PERIOD_NS [expr 1000.0 / $CLK_FREQ_MHZ]
set TIEHI_CELL_AND_PORT "LOGIC1_X1 Z"
set TIELO_CELL_AND_PORT "LOGIC0_X1 Z"