add iSTA and refactor tcl to remove environment variables

.gitignore

@@ -1,3 +1,4 @@
+bin/
 nangate45/
 result
 *.log

Makefile

@@ -4,15 +4,22 @@ DESIGN = gcd
 SDC_FILE = $(PROJ_PATH)/example/gcd.sdc
 RTL_FILES = $(shell find $(PROJ_PATH)/example -name "*.v")
 
-export FOUNDRY_PATH = $(PROJ_PATH)/nangate45
-export RESULT_PATH = $(PROJ_PATH)/result/syn
-
-$(shell mkdir -p $(RESULT_PATH))
+NETLIST_FILE = $(PROJ_PATH)/result/syn/$(DESIGN).v
+TIMING_RPT = $(PROJ_PATH)/result/sta/$(DESIGN).rpt
 
 init:
-	test -e nangate45 || (wget -O - https://ysyx.oscc.cc/slides/resources/archive/nangate45.tar.bz2 | tar xfj -)
+	bash -c "$$(wget -O - https://ysyx.oscc.cc/slides/resources/scripts/init-yosys-sta.sh)"
 
-syn:
-	echo tcl yosys.tcl $(DESIGN) $(SDC_FILE) \"$(RTL_FILES)\" | yosys -s - | tee $(RESULT_PATH)/yosys.log
+syn: $(NETLIST_FILE)
+$(NETLIST_FILE): $(SDC_FILE) $(RTL_FILES)
+	mkdir -p $(@D)
+	echo tcl yosys.tcl $(DESIGN) $(SDC_FILE) \"$(RTL_FILES)\" | yosys -s - | tee $(@D)/yosys.log
 
-.PHONY: init syn
+sta: $(TIMING_RPT)
+$(TIMING_RPT): $(SDC_FILE) $(NETLIST_FILE)
+	LD_LIBRARY_PATH=bin/ ./bin/iSTA $(PROJ_PATH)/sta.tcl $(DESIGN) $(SDC_FILE) $(NETLIST_FILE)
+
+clean:
+	-rm -rf result/
+
+.PHONY: init syn sta clean

sta.tcl

@@ -0,0 +1,12 @@
+set PROJ_PATH     [file dirname [info script]]
+set DESIGN        [lindex $argv 0]
+set SDC_FILE      [lindex $argv 1]
+set NETLIST_FILE  [lindex $argv 2]
+set LIB_FILES     $PROJ_PATH/nangate45/lib/merged.lib
+
+set_design_workspace $PROJ_PATH/result/sta/
+read_netlist $NETLIST_FILE
+read_liberty $LIB_FILES
+link_design $DESIGN
+read_sdc  $SDC_FILE
+report_timing

yosys.tcl

@@ -4,15 +4,15 @@
 set DESIGN                  [lindex $argv 0]
 set SDC_FILE                [lindex $argv 1]
 set VERILOG_FILES           [string map {"\"" ""} [lindex $argv 2]]
-set FOUNDRY_PATH            $::env(FOUNDRY_PATH)
-set RESULT_PATH             $::env(RESULT_PATH)
+set PROJ_PATH               [file dirname [info script]]
+set RESULT_PATH             $PROJ_PATH/result/syn
 set VERILOG_INCLUDE_DIRS    ""
 
-set MERGED_LIB_FILE         "$FOUNDRY_PATH/lib/merged.lib"
-set BLACKBOX_V_FILE         "$FOUNDRY_PATH/verilog/blackbox.v" 
-set CLKGATE_MAP_FILE        "$FOUNDRY_PATH/verilog/cells_clkgate.v" 
-set LATCH_MAP_FILE          "$FOUNDRY_PATH/verilog/cells_latch.v" 
-set BLACKBOX_MAP_TCL        "$FOUNDRY_PATH/blackbox_map.tcl" 
+set MERGED_LIB_FILE         "$PROJ_PATH/nangate45/lib/merged.lib"
+set BLACKBOX_V_FILE         "$PROJ_PATH/nangate45/verilog/blackbox.v" 
+set CLKGATE_MAP_FILE        "$PROJ_PATH/nangate45/verilog/cells_clkgate.v" 
+set LATCH_MAP_FILE          "$PROJ_PATH/nangate45/verilog/cells_latch.v" 
+set BLACKBOX_MAP_TCL        "$PROJ_PATH/nangate45/blackbox_map.tcl" 
 set CLOCK_PERIOD            "20.0" 
 
 set TIEHI_CELL_AND_PORT     "LOGIC1_X1 Z"