refacotr to support more PDKs

2025-01-23 21:22:18 +08:00 · 2025-01-23 21:22:18 +08:00 · f8339621ad
parent b474e9782b
commit f8339621ad
9 changed files with 53 additions and 41 deletions
--- a/.gitignore
+++ b/.gitignore
@ -1,4 +1,4 @@
 bin/
-nangate45/
+/pdk/
 result
-*.log
+*.log
--- a/9
+++ b/9
@ -4,6 +4,7 @@ DESIGN ?= gcd
 SDC_FILE ?= $(PROJ_PATH)/example/gcd.sdc
 RTL_FILES ?= $(shell find $(PROJ_PATH)/example -name "*.v")
 export CLK_FREQ_MHZ ?= 500
+PDK = nangate45

 RESULT_DIR = $(PROJ_PATH)/result/$(DESIGN)-$(CLK_FREQ_MHZ)MHz
 SCRIPT_DIR = $(PROJ_PATH)/scripts
@ -17,16 +18,16 @@ init:
 syn: $(NETLIST_SYN_V)
 $(NETLIST_SYN_V): $(RTL_FILES) $(SCRIPT_DIR)/yosys.tcl
 	mkdir -p $(@D)
-	echo tcl $(SCRIPT_DIR)/yosys.tcl $(DESIGN) \"$(RTL_FILES)\" $@ | yosys -l $(@D)/yosys.log -s -
+	echo tcl $(SCRIPT_DIR)/yosys.tcl $(DESIGN) $(PDK) \"$(RTL_FILES)\" $@ | yosys -l $(@D)/yosys.log -s -

 fix-fanout: $(NETLIST_FIXED_V)
 $(NETLIST_FIXED_V): $(SCRIPT_DIR)/fix-fanout.tcl $(SDC_FILE) $(NETLIST_SYN_V)
-	./bin/iEDA -script $^ $(DESIGN) $@ 2>&1 | tee $(RESULT_DIR)/fix-fanout.log
-	echo tcl $(SCRIPT_DIR)/yosys-area.tcl $(DESIGN) $@ | yosys -l $(@D)/yosys-area.log -s -
+	./bin/iEDA -script $^ $(DESIGN) $(PDK) $@ 2>&1 | tee $(RESULT_DIR)/fix-fanout.log
+	echo tcl $(SCRIPT_DIR)/yosys-area.tcl $(DESIGN) $(PDK) $@ | yosys -l $(@D)/yosys-area.log -s -

 sta: $(TIMING_RPT)
 $(TIMING_RPT): $(SCRIPT_DIR)/sta.tcl $(SDC_FILE) $(NETLIST_FIXED_V)
-	./bin/iEDA -script $^ $(DESIGN) 2>&1 | tee $(RESULT_DIR)/sta.log
+	./bin/iEDA -script $^ $(DESIGN) $(PDK) 2>&1 | tee $(RESULT_DIR)/sta.log

 clean:
 	-rm -rf result/
--- a/scripts/common.tcl
+++ b/scripts/common.tcl
@ -0,0 +1,2 @@
+set PROJ_HOME "[file dirname [info script]]/.."
+source $PROJ_HOME/scripts/pdk/$PDK.tcl
--- a/scripts/fix-fanout.json
+++ b/scripts/fix-fanout.json
@ -1,13 +1,10 @@
 {
    "file_path": {
-        "design_work_space": "",
        "sdc_file": "",
        "lib_files": "",
        "lef_files": "",
-        "def_file": "",
-        "output_def": "",
-        "report_file": ""
+        "def_file": ""
    },
    "insert_buffer": "BUF_X8",
    "max_fanout": 30
-}
+}
--- a/scripts/fix-fanout.tcl
+++ b/scripts/fix-fanout.tcl
@ -1,14 +1,18 @@
-set PROJ_PATH "[file dirname [info script]]/.."
 set SDC_FILE   [lindex $argv 0]
 set NETLIST_V  [lindex $argv 1]
 set DESIGN     [lindex $argv 2]
-set NETLIST_FIXED_V [lindex $argv 3]
+set PDK        [lindex $argv 3]
+set NETLIST_FIXED_V [lindex $argv 4]

-db_init -lib_path $PROJ_PATH/nangate45/lib/merged.lib
+source "[file dirname [info script]]/common.tcl"
+set JSON_FILE "$PROJ_HOME/scripts/fix-fanout.json"
+
+db_init -lib_path $LIB_FILE
 db_init -sdc_path $SDC_FILE
-tech_lef_init -path $PROJ_PATH/nangate45/lef/NangateOpenCellLibrary.tech.lef
-lef_init -path $PROJ_PATH/nangate45/lef/NangateOpenCellLibrary.macro.mod.lef
+tech_lef_init -path $TECH_LEF_FILE
+lef_init -path $STDCELL_LEF_FILE

 verilog_init -path $NETLIST_V -top $DESIGN
-run_no_fixfanout -config $PROJ_PATH/scripts/fix-fanout.json
+no_config -config_json_path $JSON_FILE -max_fanout 30 -insert_buffer $INO_INSERT_BUF
+run_no_fixfanout -config $JSON_FILE
 netlist_save -path $NETLIST_FIXED_V -exclude_cell_names {} -add_space
--- a/scripts/pdk/nangate45.tcl
+++ b/scripts/pdk/nangate45.tcl
@ -0,0 +1,13 @@
+set FOUNDARY_PATH           "$PROJ_HOME/pdk/nangate45"
+set LIB_FILE                "$FOUNDARY_PATH/lib/Nangate45_typ.lib"
+set TECH_LEF_FILE           "$FOUNDARY_PATH/lef/Nangate45_tech.lef"
+set STDCELL_LEF_FILE        "$FOUNDARY_PATH/lef/Nangate45_stdcell.lef"
+set BLACKBOX_V_FILE         "$FOUNDARY_PATH/verilog/blackbox.v"
+set CLKGATE_MAP_FILE        "$FOUNDARY_PATH/verilog/cells_clkgate.v"
+set LATCH_MAP_FILE          "$FOUNDARY_PATH/verilog/cells_latch.v"
+set BLACKBOX_MAP_TCL        "$FOUNDARY_PATH/blackbox_map.tcl"
+
+set TIEHI_CELL_AND_PORT     "LOGIC1_X1 Z"
+set TIELO_CELL_AND_PORT     "LOGIC0_X1 Z"
+set MIN_BUF_CELL_AND_PORTS  "BUF_X1 A Z"
+set INO_INSERT_BUF          "BUF_X8"
--- a/scripts/sta.tcl
+++ b/scripts/sta.tcl
@ -1,13 +1,14 @@
-set PROJ_PATH "[file dirname [info script]]/.."
 set SDC_FILE   [lindex $argv 0]
 set NETLIST_V  [lindex $argv 1]
 set DESIGN     [lindex $argv 2]
+set PDK        [lindex $argv 3]
 set RESULT_DIR [file dirname $NETLIST_V]
-set LIB_FILES  $PROJ_PATH/nangate45/lib/merged.lib
+
+source "[file dirname [info script]]/common.tcl"

 set_design_workspace $RESULT_DIR
 read_netlist $NETLIST_V
-read_liberty $LIB_FILES
+read_liberty $LIB_FILE
 link_design $DESIGN
 read_sdc  $SDC_FILE
 report_timing -max_path 5
--- a/scripts/yosys-area.tcl
+++ b/scripts/yosys-area.tcl
@ -1,13 +1,13 @@
 set DESIGN                  [lindex $argv 0]
-set NETLIST_V               [lindex $argv 1]
+set PDK                     [lindex $argv 1]
+set NETLIST_V               [lindex $argv 2]
 set RESULT_DIR              [file dirname $NETLIST_V]

-set FOUNDARY_PATH           "[file dirname [info script]]/../nangate45"
-set MERGED_LIB_FILE         "$FOUNDARY_PATH/lib/merged.lib"
+source "[file dirname [info script]]/common.tcl"

 yosys -import
 read_verilog $NETLIST_V
-read_liberty -lib $MERGED_LIB_FILE
+read_liberty -lib $LIB_FILE
 hierarchy -check -top $DESIGN
 tee -o $RESULT_DIR/synth_check_fixed.txt check -mapped
-tee -o $RESULT_DIR/synth_stat_fixed.txt stat -liberty $MERGED_LIB_FILE
+tee -o $RESULT_DIR/synth_stat_fixed.txt stat -liberty $LIB_FILE
--- a/scripts/yosys.tcl
+++ b/scripts/yosys.tcl
@ -2,17 +2,13 @@
 #   set parameter
 #===========================================================
 set DESIGN                  [lindex $argv 0]
-set VERILOG_FILES           [string map {"\"" ""} [lindex $argv 1]]
-set NETLIST_SYN_V           [lindex $argv 2]
+set PDK                     [lindex $argv 1]
+set VERILOG_FILES           [string map {"\"" ""} [lindex $argv 2]]
+set NETLIST_SYN_V           [lindex $argv 3]
 set VERILOG_INCLUDE_DIRS    ""
 set RESULT_DIR              [file dirname $NETLIST_SYN_V]

-set FOUNDARY_PATH           "[file dirname [info script]]/../nangate45"
-set MERGED_LIB_FILE         "$FOUNDARY_PATH/lib/merged.lib"
-set BLACKBOX_V_FILE         "$FOUNDARY_PATH/verilog/blackbox.v"
-set CLKGATE_MAP_FILE        "$FOUNDARY_PATH/verilog/cells_clkgate.v"
-set LATCH_MAP_FILE          "$FOUNDARY_PATH/verilog/cells_latch.v"
-set BLACKBOX_MAP_TCL        "$FOUNDARY_PATH/blackbox_map.tcl"
+source "[file dirname [info script]]/common.tcl"

 set CLK_FREQ_MHZ            500
 if {[info exists env(CLK_FREQ_MHZ)]} {
@ -22,10 +18,6 @@ if {[info exists env(CLK_FREQ_MHZ)]} {
 }
 set CLK_PERIOD_NS           [expr 1000.0 / $CLK_FREQ_MHZ]

-set TIEHI_CELL_AND_PORT     "LOGIC1_X1 Z"
-set TIELO_CELL_AND_PORT     "LOGIC0_X1 Z"
-set MIN_BUF_CELL_AND_PORTS  "BUF_X1 A Z"
-
 #===========================================================
 #   main running
 #===========================================================
@ -55,7 +47,9 @@ foreach file $VERILOG_FILES {

 # Read blackbox stubs of standard/io/ip/memory cells. This allows for standard/io/ip/memory cell (or
 # structural netlist support in the input verilog
-read_verilog $BLACKBOX_V_FILE
+if {[info exist BLACKBOX_V_FILE]} {
+  read_verilog $BLACKBOX_V_FILE
+}

 # Apply toplevel parameters (if exist
 if {[info exist VERILOG_TOP_PARAMS]} {
@ -88,12 +82,12 @@ if {[info exist LATCH_MAP_FILE]} {
 }

 # technology mapping of flip-flops
-dfflibmap -liberty $MERGED_LIB_FILE
+dfflibmap -liberty $LIB_FILE
 opt -undriven

 # Technology mapping for cells
 abc -D [expr $CLK_PERIOD_NS * 1000] \
-    -liberty $MERGED_LIB_FILE \
+    -liberty $LIB_FILE \
    -showtmp \
    -script $abc_script

@ -117,7 +111,7 @@ opt_clean -purge

 # reports
 tee -o $RESULT_DIR/synth_check.txt check
-tee -o $RESULT_DIR/synth_stat.txt stat -liberty $MERGED_LIB_FILE
+tee -o $RESULT_DIR/synth_stat.txt stat -liberty $LIB_FILE

 # write synthesized design
 write_verilog -noattr -noexpr -nohex -nodec $NETLIST_SYN_V