119 lines
3.2 KiB
Tcl
119 lines
3.2 KiB
Tcl
#===========================================================
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# set parameter
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#===========================================================
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set DESIGN [lindex $argv 0]
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set PDK [lindex $argv 1]
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set VERILOG_FILES [string map {"\"" ""} [lindex $argv 2]]
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set NETLIST_SYN_V [lindex $argv 3]
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set VERILOG_INCLUDE_DIRS ""
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set RESULT_DIR [file dirname $NETLIST_SYN_V]
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source "[file dirname [info script]]/common.tcl"
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set CLK_FREQ_MHZ 500
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if {[info exists env(CLK_FREQ_MHZ)]} {
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set CLK_FREQ_MHZ $::env(CLK_FREQ_MHZ)
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} else {
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puts "Warning: Environment CLK_FREQ_MHZ is not defined. Use $CLK_FREQ_MHZ MHz by default."
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}
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set CLK_PERIOD_NS [expr 1000.0 / $CLK_FREQ_MHZ]
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#===========================================================
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# main running
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#===========================================================
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yosys -import
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# Don't change these unless you know what you are doing
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set stat_ext "_stat.rep"
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set gl_ext "_gl.v"
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set abc_script "+strash;ifraig;retime,{D},-M,6;strash;dch,-f;map,-p,-M,1,{D},-f;topo;dnsize;buffer,-p;upsize;"
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# Setup verilog include directories
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set vIdirsArgs ""
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if {[info exist VERILOG_INCLUDE_DIRS]} {
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foreach dir $VERILOG_INCLUDE_DIRS {
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lappend vIdirsArgs "-I$dir"
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}
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set vIdirsArgs [join $vIdirsArgs]
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}
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# read verilog files
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foreach file $VERILOG_FILES {
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read_verilog -sv {*}$vIdirsArgs $file
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}
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# Read blackbox stubs of standard/io/ip/memory cells. This allows for standard/io/ip/memory cell (or
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# structural netlist support in the input verilog
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if {[info exist BLACKBOX_V_FILE]} {
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read_verilog $BLACKBOX_V_FILE
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}
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# Apply toplevel parameters (if exist
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if {[info exist VERILOG_TOP_PARAMS]} {
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dict for {key value} $VERILOG_TOP_PARAMS {
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chparam -set $key $value $DESIGN
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}
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}
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# Read platform specific mapfile for OPENROAD_CLKGATE cells
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if {[info exist CLKGATE_MAP_FILE]} {
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read_verilog $CLKGATE_MAP_FILE
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}
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# Use hierarchy to automatically generate blackboxes for known memory macro.
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# Pins are enumerated for proper mapping
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if {[info exist BLACKBOX_MAP_TCL]} {
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source $BLACKBOX_MAP_TCL
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}
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# generic synthesis
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synth -top $DESIGN -flatten
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# make better name
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autoname
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renames -wire
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# Splitting nets resolves unwanted compound assign statements in netlist (assign {..} = {..}
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splitnets -ports
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# Optimize the design
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opt -purge
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# technology mapping for clockgate
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clockgate -liberty $LIB_FILE
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# technology mapping for flip-flops
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dfflibmap -liberty $LIB_FILE
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opt -undriven
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# technology mapping for cells
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abc -D [expr $CLK_PERIOD_NS * 1000] \
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-liberty $LIB_FILE \
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-showtmp \
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-script $abc_script
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# technology mapping for constant hi- and/or lo-drivers
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hilomap -singleton \
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-hicell {*}$TIEHI_CELL_AND_PORT \
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-locell {*}$TIELO_CELL_AND_PORT
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# replace undef values with defined constants
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setundef -zero
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# remove unused cells and wires
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opt_clean -purge
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# load liberty file before checking
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read_liberty -lib $LIB_FILE
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# reports
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tee -o $RESULT_DIR/synth_check.txt check -mapped
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tee -o $RESULT_DIR/synth_stat.txt stat -liberty $LIB_FILE
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# write synthesized design
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write_verilog -noattr -noexpr -nohex -nodec $NETLIST_SYN_V
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