dnrops
/
dotnet_runtime
mirror of https://github.com/dotnet/runtime
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Merge cff502802d into 02596ba8d9

This commit is contained in:
Tomasz Sowiński 2025-07-30 15:56:19 +02:00 committed by GitHub
parent 02596ba8d9 cff502802d
commit 1fb27d3118
No known key found for this signature in database
GPG Key ID: B5690EEEBB952194
3 changed files with 17 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

21
src/coreclr/jit/codegenriscv64.cpp
View File

@ -2187,16 +2187,25 @@ void CodeGen::genTableBasedSwitch(GenTree* treeNode)
regNumber idxReg = treeNode->AsOp()->gtOp1->GetRegNum();
regNumber baseReg = treeNode->AsOp()->gtOp2->GetRegNum();
regNumber tmpReg = internalRegisters.GetSingle(treeNode);
// load the ip-relative offset (which is relative to start of fgFirstBB)
GetEmitter()->emitIns_R_R_I(INS_slli, EA_8BYTE, tmpReg, idxReg, 2);
GetEmitter()->emitIns_R_R_R(INS_add, EA_8BYTE, baseReg, baseReg, tmpReg);
assert(treeNode->gtGetOp2()->TypeIs(TYP_I_IMPL));
if (compiler->compOpportunisticallyDependsOn(InstructionSet_Zba))
{
emitAttr idxSize = emitTypeSize(treeNode->gtGetOp1());
instruction sh2add = (idxSize == EA_4BYTE) ? INS_sh2add_uw : INS_sh2add;
GetEmitter()->emitIns_R_R_R(sh2add, idxSize, baseReg, idxReg, baseReg);
}
else
{
assert(treeNode->gtGetOp1()->TypeIs(TYP_I_IMPL));
GetEmitter()->emitIns_R_R_I(INS_slli, EA_8BYTE, idxReg, idxReg, 2);
GetEmitter()->emitIns_R_R_R(INS_add, EA_8BYTE, baseReg, baseReg, idxReg);
}
GetEmitter()->emitIns_R_R_I(INS_lw, EA_4BYTE, baseReg, baseReg, 0);
// add it to the absolute address of fgFirstBB
GetEmitter()->emitIns_R_L(INS_lea, EA_PTRSIZE, compiler->fgFirstBB, tmpReg);
GetEmitter()->emitIns_R_R_R(INS_add, EA_PTRSIZE, baseReg, baseReg, tmpReg);
GetEmitter()->emitIns_R_L(INS_lea, EA_PTRSIZE, compiler->fgFirstBB, idxReg);
GetEmitter()->emitIns_R_R_R(INS_add, EA_PTRSIZE, baseReg, baseReg, idxReg);
// jr baseReg
GetEmitter()->emitIns_R_R_I(INS_jalr, emitActualTypeSize(TYP_I_IMPL), REG_R0, baseReg, 0);

3
src/coreclr/jit/lower.cpp
View File

@ -1222,7 +1222,8 @@ GenTree* Lowering::LowerSwitch(GenTree* node)
JITDUMP("Lowering switch " FMT_BB ": using jump table expansion\n", originalSwitchBB->bbNum);
#ifdef TARGET_64BIT
if (tempLclType != TYP_I_IMPL)
if (RISCV64_ONLY(!comp->compOpportunisticallyDependsOn(InstructionSet_Zba)&&) // shXadd.uw 0-extends index
tempLclType != TYP_I_IMPL)
{
// SWITCH_TABLE expects the switch value (the index into the jump table) to be TYP_I_IMPL.
// Note that the switch value is unsigned so the cast should be unsigned as well.

1
src/coreclr/jit/lsrariscv64.cpp
View File

@ -226,7 +226,6 @@ int LinearScan::BuildNode(GenTree* tree)
break;
case GT_SWITCH_TABLE:
buildInternalIntRegisterDefForNode(tree);
srcCount = BuildBinaryUses(tree->AsOp());
assert(dstCount == 0);
break;