feat(fvp-a-aarch32): add missing and unify fvp-a-aarch32 configs
This commit is contained in:
Jose Martins
parent
e4afeb2555
commit
bcf5980bf2
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@ -22,7 +22,7 @@ struct config config = {
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.entry = 0xa0000000,
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.platform = {
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.cpu_num = 3,
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.cpu_num = 2,
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.region_num = 1,
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.regions = (struct vm_mem_region[]) {
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@ -0,0 +1,127 @@
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#include <config.h>
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VM_IMAGE(zephyr_image, XSTR(BAO_DEMOS_WRKDIR_IMGS/zephyr.bin));
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VM_IMAGE(baremetal_image, XSTR(BAO_DEMOS_WRKDIR_IMGS/baremetal.bin));
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struct config config = {
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.shmemlist_size = 1,
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.shmemlist = (struct shmem[]) {
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[0] = { .size = 0x00010000, }
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},
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.vmlist_size = 2,
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.vmlist = {
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{
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.image = {
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.base_addr = 0x20000000,
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.load_addr = VM_IMAGE_OFFSET(zephyr_image),
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.size = VM_IMAGE_SIZE(zephyr_image)
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},
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.entry = 0x20000000,
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.platform = {
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.cpu_num = 1,
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.region_num = 1,
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.regions = (struct vm_mem_region[]) {
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{
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.base = 0x20000000,
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.size = 0x8000000
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}
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},
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.ipc_num = 1,
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.ipcs = (struct ipc[]) {
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{
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.base = 0x70000000,
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.size = 0x00010000,
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.shmem_id = 0,
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.interrupt_num = 1,
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.interrupts = (irqid_t[]) {52}
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}
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},
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.dev_num = 2,
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.devs = (struct vm_dev_region[]) {
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{
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/* UART2, PL011 */
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.pa = 0x1c0b0000,
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.va = 0x9c0b0000,
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.size = 0x10000,
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.interrupt_num = 1,
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.interrupts = (irqid_t[]) {39}
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},
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{
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.interrupt_num = 1,
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.interrupts = (irqid_t[]) {27}
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}
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},
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.arch = {
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.gic = {
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.gicd_addr = 0xaf000000,
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.gicr_addr = 0xaf100000,
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}
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}
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},
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},
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{
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.image = {
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.base_addr = 0x0,
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.load_addr = VM_IMAGE_OFFSET(baremetal_image),
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.size = VM_IMAGE_SIZE(baremetal_image)
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},
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.entry = 0x0,
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.platform = {
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.cpu_num = 2,
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.region_num = 1,
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.regions = (struct vm_mem_region[]) {
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{
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.base = 0x0,
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.size = 0x8000000,
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}
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},
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.ipc_num = 1,
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.ipcs = (struct ipc[]) {
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{
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.base = 0x70000000,
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.size = 0x00010000,
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.shmem_id = 0,
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.interrupt_num = 1,
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.interrupts = (irqid_t[]) {52}
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}
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},
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.dev_num = 2,
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.devs = (struct vm_dev_region[]) {
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{
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/* UART2, PL011 */
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.pa = 0x1c090000,
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.va = 0xff000000,
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.size = 0x10000,
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.interrupt_num = 1,
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.interrupts = (irqid_t[]) {37}
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},
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{
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.interrupt_num = 1,
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.interrupts = (irqid_t[]) {27}
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}
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},
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.arch = {
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.gic = {
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.gicd_addr = 0xf9010000,
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.gicr_addr = 0xf9020000,
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}
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}
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},
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},
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},
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};
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@ -0,0 +1,7 @@
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# Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved.
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# Copyright (c) 2022 IoT.bzh
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# SPDX-License-Identifier: Apache-2.0
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config BOARD_FVP_BASER_AEMV8R_AARCH32
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bool "Bao VM for FVP BaseR AEMv8R AArch32 simulation board"
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depends on SOC_FVP_AEMV8R_AARCH32
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@ -0,0 +1,13 @@
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# Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved.
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# Copyright (c) 2022 IoT.bzh
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# SPDX-License-Identifier: Apache-2.0
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if BOARD_FVP_BASER_AEMV8R_AARCH32
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config BUILD_OUTPUT_BIN
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default y
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config BOARD
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default "baovm_fvp-r-aarch32"
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endif # BOARD_FVP_BASER_AEMV8R_AARCH32
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@ -0,0 +1,39 @@
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/*
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* Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved.
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* SPDX-License-Identifier: Apache-2.0
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*/
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/dts-v1/;
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#include <arm64/fvp/fvp-aemv8r.dtsi>
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/ {
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model = "Bao VM for FVP BaseR AEMv8R AArch32";
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chosen {
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/*
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* The SRAM node is actually located in the
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* DRAM region of the FVP BaseR AEMv8R.
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*/
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zephyr,sram = &dram0;
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zephyr,console = &uart2;
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zephyr,shell-uart = &uart2;
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};
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psci {
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compatible = "arm,psci-0.2";
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method = "hvc";
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};
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soc {
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dram0: memory@20000000 {
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compatible = "mmio-dram";
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reg = <0x20000000 DT_SIZE_M(128)>;
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};
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};
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};
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&uart2 {
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status = "okay";
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current-speed = <115200>;
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};
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@ -5,7 +5,6 @@
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CONFIG_SOC_SERIES_FVP_AEMV8R_AARCH32=y
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CONFIG_SOC_FVP_AEMV8R_AARCH32=y
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CONFIG_BOARD_FVP_BASER_AEMV8R_AARCH32=y
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CONFIG_ARM_MPU=y
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CONFIG_ISR_STACK_SIZE=1024
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CONFIG_THREAD_STACK_INFO=y
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