complete DEMO table with linux-ivshmem-net

README.md

@@ -6,6 +6,7 @@ systems and targeting several supported platforms. The available demos are:
 
 * [Single-guest Baremetal](demos/baremetal/README.md)
 * [Dual-guest Linux+FreeRTOS](demos/linux+freertos/README.md)
+* [Dual-Linux connected via IVSHMEM-NET](demos/linux-ivshmem-net/README.md)
 
 ---
 
@@ -152,6 +153,7 @@ Build guests according to the target demo:
 
 * [Single Baremetal Guest](demos/baremetal/README.md)
 * [Dual-guest Linux+FreeRTOS](demos/linux+freertos/README.md)
+* [Dual-Linux connected via IVSHMEM-NET](demos/linux-ivshmem-net/README.md)
 
 
 ### B.4) Build Bao
@@ -229,6 +231,7 @@ Build the firmware and deploy the system according to the target platform:
 |--|--|
 | Baremetal guest | baremetal |
 | Linux+FreeRTOS | linux+freertos |
+| Dual-Linux IVSHMEM-NET | linux-ivshmem-net |
 
 <!-- TODO: Add Accepted Platform/Demos table -->
 

demos/README.md

@@ -4,6 +4,7 @@ The following demos are available:
 
 * [Bare Metal Application](../demos/baremetal/README.md)
 * [Dual-Guest Linux+FreeRTOS](../demos/linux+freertos/README.md)
+* [Dual-Linux connected via IVSHMEM-NET](../demos/linux-ivshmem-net/README.md)
 
 More demos, showcasing different Bao features, guests and configurations will
  be available in the future.

demos/linux-ivshmem-net/README.md

@@ -0,0 +1,11 @@
+# Dual-Linux, pseudo IVSHMEM-NET Demo
+
+This demo features two Linux guests connected via ab inter-VM communication 
+object (i.e. shared memory plus a doorbell mechanism) communication using a 
+port of the IVSHMEM-NET driver which exposes the object as a network interface. 
+
+While one of the guests is assigned the platform's main UART, the second Linux 
+instance is "hidden" from the world and only reachable through this
+communication mechanism via ssh at the static address *192.168.42.16*.
+
+Follow the [instructions to build Linux](../../guests/linux/README.md).

demos/linux-ivshmem-net/configs/imx8qm.c

@@ -0,0 +1,152 @@
+#include <config.h>
+
+VM_IMAGE(linux1, XSTR(BAO_DEMOS_WRKDIR_IMGS/linux1.bin));
+VM_IMAGE(linux2, XSTR(BAO_DEMOS_WRKDIR_IMGS/linux2.bin));
+
+
+struct config config = {
+    
+    CONFIG_HEADER
+
+    .shmemlist_size = 1,
+    .shmemlist = (struct shmem[]) {
+        [0] = { .size = 0x00010000, }
+    },
+    
+    .vmlist_size = 2,
+    .vmlist = {
+        { 
+            .image = {
+                .base_addr = 0x80200000,
+                .load_addr = VM_IMAGE_OFFSET(linux1),
+                .size = VM_IMAGE_SIZE(linux1)
+            },
+
+            .entry = 0x80200000,
+            .cpu_affinity = 0b000001,
+
+            .platform = {
+                .cpu_num = 1,   
+                
+                .region_num = 1,
+                .regions =  (struct mem_region[]) {
+                    {
+                        .base = 0x80000000,
+                        .size = 0x40000000
+                    }
+                },
+
+                .ipc_num = 1,
+                .ipcs = (struct ipc[]) {
+                    {
+                        .base = 0x60000000,
+                        .size = 0x00010000,
+                        .shmem_id = 0,
+                        .interrupt_num = 2,
+                        .interrupts = (uint64_t[]) {184,185}
+                    }
+                },
+
+                .dev_num = 5,
+                .devs =  (struct dev_region[]) {    
+                    {   
+                        /* lpuart0 */
+                        .pa = 0x5a060000,
+                        .va = 0x5a060000,
+                        .size = 0x1000,
+                        .interrupt_num = 1,
+                        .interrupts = (uint64_t[]) {377}                           
+                    },
+                    {   
+                        /* lpuart0 clock generator */
+                        .pa = 0x5a460000,
+                        .va = 0x5a460000,
+                        .size = 0x10000                        
+                    },
+                    {   
+                        /* edma0 channels 12 and 13 */
+                        .pa = 0x5a2c0000,
+                        .va = 0x5a2c0000,
+                        .size = 0x20000,
+                        .interrupt_num = 2,
+                        .interrupts = (uint64_t[]) {466, 467},    
+                        /**
+                         * this streamid must be configured in atf or uboot 
+                         * through a call to scfw
+                         */
+                        .id = 0x1,
+                    },
+                    {
+                        /* message unit 1 */
+                        .pa = 0x5d1c0000,
+                        .va = 0x5d1c0000,
+                        .size = 0x10000,
+                        .interrupt_num = 1,
+                        .interrupts = (uint64_t[]) {209},    
+                    },
+                    {   
+                        /* Arch timer interrupt */
+                        .interrupt_num = 1,
+                        .interrupts = (uint64_t[]) {27}                         
+                    }
+                },
+
+                .arch = {
+                    .gic = {
+                       .gicd_addr = 0x51a00000,
+                       .gicr_addr = 0x51b00000
+                    },
+                },
+            },
+        },
+        { 
+            .image = {
+                .base_addr = 0x80200000,
+                .load_addr = VM_IMAGE_OFFSET(linux2),
+                .size = VM_IMAGE_SIZE(linux2)
+            },
+
+            .entry = 0x80200000,
+            .cpu_affinity = 0b111110,
+
+            .platform = {
+                .cpu_num = 5,   
+                
+                .region_num = 1,
+                .regions =  (struct mem_region[]) {
+                    {
+                        .base = 0x80000000,
+                        .size = 0x40000000
+                    }
+                },
+
+                .ipc_num = 1,
+                .ipcs = (struct ipc[]) {
+                    {
+                        .base = 0x60000000,
+                        .size = 0x00010000,
+                        .shmem_id = 0,
+                        .interrupt_num = 2,
+                        .interrupts = (uint64_t[]) {184,185}
+                    }
+                },
+
+                .dev_num = 1,
+                .devs =  (struct dev_region[]) {    
+                    {   
+                        /* Arch timer interrupt */
+                        .interrupt_num = 1,
+                        .interrupts = (uint64_t[]) {27}                         
+                    },
+                },
+
+                .arch = {
+                    .gic = {
+                       .gicd_addr = 0x51a00000,
+                       .gicr_addr = 0x51b00000
+                    },
+                },   
+            },
+        }
+    },
+};

demos/linux-ivshmem-net/configs/qemu-aarch64-virt.c

@@ -0,0 +1,125 @@
+#include <config.h>
+
+VM_IMAGE(linux1, XSTR(BAO_DEMOS_WRKDIR_IMGS/linux1.bin));
+VM_IMAGE(linux2, XSTR(BAO_DEMOS_WRKDIR_IMGS/linux2.bin));
+
+struct config config = {
+    
+    CONFIG_HEADER
+
+    .shmemlist_size = 1,
+    .shmemlist = (struct shmem[]) {
+        [0] = { .size = 0x00010000, }
+    },
+
+    .vmlist_size = 2,
+    .vmlist = {
+        { 
+            .image = {
+                .base_addr = 0x40000000,
+                .load_addr = VM_IMAGE_OFFSET(linux1),
+                .size = VM_IMAGE_SIZE(linux1)
+            },
+
+            .entry = 0x40000000,
+            .cpu_affinity = 0b1,
+
+            .platform = {
+                .cpu_num = 1,
+                
+                .region_num = 1,
+                .regions =  (struct mem_region[]) {
+                    {
+                        .base = 0x40000000,
+                        .size = 0x20000000,
+                    }
+                },
+
+                .ipc_num = 1,
+                .ipcs = (struct ipc[]) {
+                    {
+                        .base = 0x60000000,
+                        .size = 0x00010000,
+                        .shmem_id = 0,
+                        .interrupt_num = 2,
+                        .interrupts = (uint64_t[]) {184,185}
+                    }
+                },
+
+                .dev_num = 2,
+                .devs =  (struct dev_region[]) {
+                    {   
+                        /* PL011 */
+                        .pa = 0x9000000,
+                        .va = 0x9000000,
+                        .size = 0x1000,
+                        .interrupt_num = 1,
+                        .interrupts =  (uint64_t[]) {33}                           
+                    },
+                    {   
+                        /* Arch timer interrupt */
+                        .interrupt_num = 1,
+                        .interrupts = (uint64_t[]) {27}                         
+                    }
+                },
+
+                .arch = {
+                    .gic = {
+                       .gicd_addr = 0x8000000,
+                       .gicr_addr = 0x80A0000
+                    }
+                }
+            },
+        },
+        { 
+            .image = {
+                .base_addr = 0x40000000,
+                .load_addr = VM_IMAGE_OFFSET(linux2),
+                .size = VM_IMAGE_SIZE(linux2)
+            },
+
+            .entry = 0x40000000,
+            .cpu_affinity = 0b1110,
+
+            .platform = {
+                .cpu_num = 3,
+                
+                .region_num = 1,
+                .regions =  (struct mem_region[]) {
+                    {
+                        .base = 0x40000000,
+                        .size = 0x20000000
+                    }
+                },
+
+                .ipc_num = 1,
+                .ipcs = (struct ipc[]) {
+                    {
+                        .base = 0x60000000,
+                        .size = 0x00010000,
+                        .shmem_id = 0,
+                        .interrupt_num = 2,
+                        .interrupts = (uint64_t[]) {184,185}
+                    }
+                },
+
+                .dev_num = 1,
+                .devs =  (struct dev_region[]) {
+                    {   
+                        /* Arch timer interrupt */
+                        .interrupt_num = 1,
+                        .interrupts = 
+                            (uint64_t[]) {27}                         
+                    }
+                },
+
+                .arch = {
+                    .gic = {
+                       .gicd_addr = 0x8000000,
+                       .gicr_addr = 0x80A0000
+                    }
+                }
+            },
+        }
+    },
+};

demos/linux-ivshmem-net/configs/qemu-riscv64-virt.c

@@ -0,0 +1,117 @@
+
+#include <config.h>
+
+VM_IMAGE(linux1, XSTR(BAO_DEMOS_WRKDIR_IMGS/linux1.bin));
+VM_IMAGE(linux2, XSTR(BAO_DEMOS_WRKDIR_IMGS/linux2.bin));
+
+struct config config = {
+    
+    CONFIG_HEADER
+
+    .shmemlist_size = 1,
+    .shmemlist = (struct shmem[]) {
+        [0] = { .size = 0x00010000, }
+    },
+    
+    .vmlist_size = 2,
+    .vmlist = {
+        { 
+            .image = {
+                .base_addr = 0x80200000,
+                .load_addr = VM_IMAGE_OFFSET(linux1),
+                .size = VM_IMAGE_SIZE(linux1)
+            },
+
+            .entry = 0x80200000,
+
+            .platform = {
+                .cpu_num = 1,
+                
+                .region_num = 1,
+                .regions =  (struct mem_region[]) {
+                    {
+                        .base = 0x80000000,
+                        .size = 0x40000000
+                    }
+                },
+
+                .ipc_num = 1,
+                .ipcs = (struct ipc[]) {
+                    {
+                        .base = 0xf0000000,
+                        .size = 0x00010000,
+                        .shmem_id = 0,
+                        .interrupt_num = 2,
+                        .interrupts = (uint64_t[]) {52, 53}
+                    }
+                },
+
+                .dev_num = 1,
+                .devs =  (struct dev_region[]) {
+                    {
+                        /* UART */
+                        .pa = 0x10000000,   
+                        .va = 0x10000000,  
+                        .size = 0x1000,
+                        .interrupt_num = 1,
+                        .interrupts = (uint64_t[]) {10}
+                    },
+                },
+
+                .arch = {
+                   .plic_base = 0xc000000,
+                }
+            },
+        },
+        { 
+            .image = {
+                .base_addr = 0xa0200000,
+                .load_addr = VM_IMAGE_OFFSET(linux2),
+                .size = VM_IMAGE_SIZE(linux2)
+            },
+
+            .entry = 0xa0200000,
+
+            .platform = {
+                .cpu_num = 3,
+                
+                .region_num = 1,
+                .regions =  (struct mem_region[]) {
+                    {
+                        .base = 0xa0000000,
+                        .size = 0x40000000, //128MB
+                        .place_phys = true,
+                        .phys = 0xa0000000,
+                    }
+                },
+
+                .ipc_num = 1,
+                .ipcs = (struct ipc[]) {
+                    {
+                        .base = 0xf0000000,
+                        .size = 0x00010000,
+                        .shmem_id = 0,
+                        .interrupt_num = 2,
+                        .interrupts = (uint64_t[]) {52, 53}
+                    }
+                },
+
+                .dev_num = 1,
+                .devs =  (struct dev_region[]) {
+                    {
+                        /* virtio devices */
+                        .pa = 0x10001000,   
+                        .va = 0x10001000,  
+                        .size = 0x8000, 
+                        .interrupt_num = 8,
+                        .interrupts = (uint64_t[]) {1,2,3,4,5,6,7,8}
+                    },
+                },
+
+                .arch = {
+                   .plic_base = 0xc000000,
+                }
+            },
+        },
+    }
+};

demos/linux-ivshmem-net/devicetrees/imx8qm/linux1.dts

@@ -0,0 +1,176 @@
+/dts-v1/;
+
+/ {   
+	#size-cells = <0x2>;
+	#address-cells = <0x2>;
+
+	cpus {
+		#size-cells = <0x0>;
+		#address-cells = <0x1>;
+
+		cpu@0 {
+			compatible = "arm,armv8";
+			device_type = "cpu";
+			enable-method = "psci";
+			reg = <0x0>;
+		};
+
+	};
+
+	psci {
+		compatible = "arm,psci-0.2";
+		method = "smc";
+	};
+
+
+	memory@80000000 {
+		reg = <0x0 0x80000000 0x0 0x20000000>;
+		device_type = "memory";
+	};
+
+	gic: intc@8000000 {
+		interrupts = <0x01 0x09 0x04>;
+		reg = <0x00 0x51a00000 0x00 0x10000 0x00 0x51b00000 0x00 0xf60000>;
+		#redistributor-regions = <0x01>;
+		compatible = "arm,gic-v3";
+		interrupt-controller;
+		#interrupt-cells = <0x03>;
+        interrupt-parent = <&gic>;
+	};
+
+   	timer {
+		compatible = "arm,armv8-timer";
+		interrupt-parent = <&gic>;
+		interrupts = <0x1 0xd 0xf08 0x1 0xe 0xf08 0x1 0xb 0xf08 0x1 0xa 0xf08>;
+	};
+
+	xtal32k: clock-xtal32k {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <32768>;
+		clock-output-names = "xtal_32KHz";
+	};
+
+	xtal24m: clock-xtal24m {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <24000000>;
+		clock-output-names = "xtal_24MHz";
+	};
+
+	dma_ipg_clk: clock-dma-ipg {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <120000000>;
+		clock-output-names = "dma_ipg_clk";
+	};
+
+	/**
+	 * We are assigning a mu to the linux guest because the linux drivers 
+	 * assume linux can directly interact with the SCU to configure its devices.
+	 * Therefore, this guest will be able to configure peripherals not assigned
+	 * to it. In the future we will have to either to move the cores 
+	 * belonging to this guest to a separate scfw partition or paravirtualise 
+	 * the MU1 and interpose the guest's communcation to the SCU, to limit 
+	 * which resource it might configure.
+	 */ 
+	lsio_mu1: mailbox@5d1c0000 {
+		compatible = "fsl,imx8qm-mu", "fsl,imx6sx-mu";
+		reg = <0x0 0x5d1c0000 0x0 0x10000>;
+		interrupt-parent = <&gic>;
+		interrupts = <0 177 4>;
+		#mbox-cells = <2>;
+		status = "okay";
+	};
+
+	scu {
+		compatible = "fsl,imx-scu";
+
+		mbox-names = "tx0", "tx1", "tx2", "tx3",
+			     "rx0", "rx1", "rx2", "rx3",
+			     "gip3";
+
+		mboxes = <&lsio_mu1 0 0
+			  &lsio_mu1 0 1
+			  &lsio_mu1 0 2
+			  &lsio_mu1 0 3
+			  &lsio_mu1 1 0
+			  &lsio_mu1 1 1
+			  &lsio_mu1 1 2
+			  &lsio_mu1 1 3
+			  &lsio_mu1 3 3>;
+
+		pd: imx8qx-pd {
+			compatible = "fsl,imx8qm-scu-pd", "fsl,scu-pd";
+			#power-domain-cells = <1>;
+		};
+
+		clk: clock-controller {
+			compatible = "fsl,imx8qm-clk", "fsl,scu-clk";
+			#clock-cells = <2>;
+			clocks = <&xtal32k &xtal24m>;
+			clock-names = "xtal_32KHz", "xtal_24Mhz";
+		};
+	};
+
+	edma0: dma-controller@5a2c0000 {
+		compatible = "fsl,imx8qm-edma";
+		reg = <0x0 0x5a2c0000 0x0 0x10000>, /* channel12 UART0 rx */
+		      <0x0 0x5a2d0000 0x0 0x10000>; /* channel13 UART0 tx */
+		#dma-cells = <3>;
+		dma-channels = <2>;
+		interrupts = <0 434 4>, <0 435 4>;
+		interrupt-parent = <&gic>;
+		interrupt-names = "edma0-chan12-rx", "edma0-chan13-tx";
+		power-domains =   <&pd 76>, <&pd 77>; /* lpuart0 */
+		power-domain-names = "edma0-chan12", "edma0-chan13";
+		status = "okay";
+	};
+
+	uart0_lpcg: clock-controller@5a460000 {
+		compatible = "fsl,imx8qxp-lpcg";
+		reg = <0x0 0x5a460000 0x0 0x10000>;
+		#clock-cells = <1>;
+		clocks = <&clk 57 2>,
+			 <&dma_ipg_clk>;
+		bit-offset = <0 16>;
+		clock-output-names = "uart0_lpcg_baud_clk",
+				     "uart0_lpcg_ipg_clk";
+		power-domains = <&pd 57>;
+	};
+
+	lpuart0: serial@5a060000 {
+		compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart";
+		reg = <0x0 0x5a060000 0x0 0x1000>;
+        interrupt-parent = <&gic>;
+        interrupts = <0 345 4>;
+		clocks = <&uart0_lpcg 1>, <&uart0_lpcg 0>;
+		clock-names = "ipg", "baud";
+		assigned-clocks = <&clk 57 2>;
+		assigned-clock-rates = <80000000>;
+		power-domains = <&pd 57>;
+		power-domain-names = "uart";
+		dmas = <&edma0 13 0 0>, <&edma0 12 0 1>;
+		dma-names = "tx","rx";
+	    status = "okay";
+	};
+
+    bao-ipc@60000000 {
+        compatible = "bao,pseudo-ivshmem-net";
+        #address-cells = <2>;
+        #size-cells = <2>;
+        reg = <0x0 0x60000000 0x0 0x00010000>;
+        interrupt-parent = <&gic>;
+        interrupts = <0x0 152 0x4 0x0 153 0x4>;
+        id = <0>;
+    };
+
+	aliases {
+		serial0 = &lpuart0;
+	};
+
+	chosen {
+		bootargs = "clk_ignore_unused ip=192.168.42.15 carrier_timeout=0";
+		stdout-path = &lpuart0;
+	};
+};

demos/linux-ivshmem-net/devicetrees/imx8qm/linux2.dts

@@ -0,0 +1,88 @@
+/dts-v1/;
+
+/ {   
+	#size-cells = <0x2>;
+	#address-cells = <0x2>;
+
+	cpus {
+		#size-cells = <0x0>;
+		#address-cells = <0x1>;
+
+		cpu@0 {
+			compatible = "arm,armv8";
+			device_type = "cpu";
+			enable-method = "psci";
+			reg = <0x0>;
+		};
+
+		cpu@1 {
+			compatible = "arm,armv8";
+			device_type = "cpu";
+			enable-method = "psci";
+			reg = <0x1>;
+		};
+
+		cpu@2 {
+			reg = <0x2>;
+			compatible = "arm,armv8";
+			device_type = "cpu";
+			enable-method = "psci";
+		};
+
+		cpu@3 {
+			reg = <0x3>;
+			compatible = "arm,armv8";
+			device_type = "cpu";
+			enable-method = "psci";
+		};
+
+		cpu@4 {
+			compatible = "arm,armv8";
+			device_type = "cpu";
+			reg = <0x4>;
+			enable-method = "psci";
+		};
+
+	};
+
+	psci {
+		compatible = "arm,psci-0.2";
+		method = "smc";
+	};
+
+
+	memory@80000000 {
+		reg = <0x0 0x80000000 0x0 0x40000000>;
+		device_type = "memory";
+	};
+
+	gic: intc@8000000 {
+		interrupts = <0x01 0x09 0x04>;
+		reg = <0x00 0x51a00000 0x00 0x10000 0x00 0x51b00000 0x00 0xf60000>;
+		#redistributor-regions = <0x01>;
+		compatible = "arm,gic-v3";
+		interrupt-controller;
+		#interrupt-cells = <0x03>;
+        interrupt-parent = <&gic>;
+	};
+
+   	timer {
+		compatible = "arm,armv8-timer";
+		interrupt-parent = <&gic>;
+		interrupts = <0x1 0xd 0xf08 0x1 0xe 0xf08 0x1 0xb 0xf08 0x1 0xa 0xf08>;
+	};
+
+    bao-ipc@60000000 {
+        compatible = "bao,pseudo-ivshmem-net";
+        #address-cells = <2>;
+        #size-cells = <2>;
+        reg = <0x0 0x60000000 0x0 0x00010000>;
+        interrupt-parent = <&gic>;
+        interrupts = <0x0 152 0x4 0x0 153 0x4>;
+        id = <0>;
+    };
+
+	chosen {
+		bootargs = "clk_ignore_unused ip=192.168.42.16 carrier_timeout=0";
+	};
+};

demos/linux-ivshmem-net/devicetrees/qemu-aarch64-virt/linux1.dts

@@ -0,0 +1,83 @@
+/dts-v1/;
+
+/ {
+	#size-cells = <0x2>;
+	#address-cells = <0x2>;
+	interrupt-parent = <&gic>;
+
+	cpus {
+		#size-cells = <0x0>;
+		#address-cells = <0x1>;
+
+		cpu@0 {
+			compatible = "arm,cortex-a53", "arm,armv8";
+			device_type = "cpu";
+			enable-method = "psci";
+			reg = <0x0>;
+		};
+
+	};
+
+	psci {
+		compatible = "arm,psci-0.2";
+		method = "smc";
+	};
+
+	memory@40000000 {
+		reg = <0x0 0x40000000 0x0 0x20000000>;
+		device_type = "memory";
+	};
+
+    gic: intc@8000000 {
+		interrupts = <0x01 0x09 0x04>;
+		reg = <0x00 0x8000000 0x00 0x10000 0x00 0x80a0000 0x00 0xf60000>;
+		#redistributor-regions = <0x01>;
+		compatible = "arm,gic-v3";
+		ranges;
+		#size-cells = <0x02>;
+		#address-cells = <0x02>;
+		interrupt-controller;
+		#interrupt-cells = <0x03>;
+	};
+
+	timer {
+		interrupts = <0x1 0xd 0xf04 0x1 0xe 0xf04 0x1 0xb 0xf04 0x1 0xa 0xf04>;
+		always-on;
+		compatible = "arm,armv8-timer", "arm,armv7-timer";
+	};
+
+	uart0: pl011@9000000 {
+		clock-names = "uartclk", "apb_pclk";
+		clocks = <0x8000 0x8000>;
+		interrupts = <0x0 0x1 0x4>;
+		reg = <0x0 0x9000000 0x0 0x1000>;
+		compatible = "arm,pl011", "arm,primecell";
+	};
+
+    bao-ipc@f0000000 {
+        compatible = "bao,pseudo-ivshmem-net";
+        #address-cells = <2>;
+        #size-cells = <2>;
+        reg = <0x0 0xf0000000 0x0 0x00010000>;
+        interrupt-parent = <&gic>;
+        interrupts = <0x0 152 0x4 0x0 153 0x4>;
+        id = <0>;
+    };
+
+	apb-pclk {
+		phandle = <0x8000>;
+		clock-output-names = "clk24mhz";
+		clock-frequency = <0x16e3600>;
+		#clock-cells = <0x0>;
+		compatible = "fixed-clock";
+	};
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	chosen {
+        bootargs = "earlycon console=ttyAMA0 ip=192.168.42.15 carrier_timeout=0";
+	     stdout-path = &uart0;
+	};
+};

demos/linux-ivshmem-net/devicetrees/qemu-aarch64-virt/linux2.dts

@@ -0,0 +1,76 @@
+/dts-v1/;
+
+/ {
+	#size-cells = <0x2>;
+	#address-cells = <0x2>;
+	interrupt-parent = <&gic>;
+
+	cpus {
+		#size-cells = <0x0>;
+		#address-cells = <0x1>;
+
+		cpu@0 {
+			compatible = "arm,cortex-a53", "arm,armv8";
+			device_type = "cpu";
+			enable-method = "psci";
+			reg = <0x0>;
+		};
+
+		cpu@1 {
+			compatible = "arm,cortex-a53", "arm,armv8";
+			device_type = "cpu";
+			enable-method = "psci";
+			reg = <0x1>;
+		};
+
+		cpu@2 {
+			compatible = "arm,cortex-a53", "arm,armv8";
+			device_type = "cpu";
+			enable-method = "psci";
+			reg = <0x2>;
+		};
+	};
+
+	psci {
+		compatible = "arm,psci-0.2";
+		method = "smc";
+	};
+
+	memory@40000000 {
+		reg = <0x0 0x40000000 0x0 0x20000000>;
+		device_type = "memory";
+	};
+
+    gic: intc@8000000 {
+		phandle = <0x8001>;
+		interrupts = <0x01 0x09 0x04>;
+		reg = <0x00 0x8000000 0x00 0x10000 0x00 0x80a0000 0x00 0xf60000>;
+		#redistributor-regions = <0x01>;
+		compatible = "arm,gic-v3";
+		ranges;
+		#size-cells = <0x02>;
+		#address-cells = <0x02>;
+		interrupt-controller;
+		#interrupt-cells = <0x03>;
+	};
+
+	timer {
+		interrupts = <0x1 0xd 0xf04 0x1 0xe 0xf04 0x1 0xb 0xf04 0x1 0xa 0xf04>;
+		always-on;
+		compatible = "arm,armv8-timer", "arm,armv7-timer";
+	};
+
+    bao-ipc@60000000 {
+        compatible = "bao,pseudo-ivshmem-net";
+        #address-cells = <2>;
+        #size-cells = <2>;
+        reg = <0x0 0x60000000 0x0 0x00010000>;
+        interrupt-parent = <&gic>;
+        interrupts = <0x0 152 0x4 0x0 153 0x4>;
+        id = <0>;
+    };
+
+	chosen {
+        bootargs = "earlycon ip=192.168.42.16 carrier_timeout=0";
+	};
+};

demos/linux-ivshmem-net/devicetrees/qemu-riscv64-virt/linux1.dts

@@ -0,0 +1,67 @@
+/dts-v1/;
+
+/ {
+	#address-cells = <0x2>;
+	#size-cells = <0x2>;
+
+	cpus {
+		#address-cells = <0x1>;
+		#size-cells = <0x0>;
+		timebase-frequency = <10000000>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			reg = <0x0>;
+			status = "okay";
+			compatible = "riscv";
+			riscv,isa = "rv64imafdcsu";
+			mmu-type = "riscv,sv48";
+
+			cpu0_intc: interrupt-controller {
+				#interrupt-cells = <0x1>;
+				interrupt-controller;
+				compatible = "riscv,cpu-intc";
+			};
+		};
+
+	};
+
+	memory@80000000 {
+		device_type = "memory";
+		reg = <0x0 0x80000000 0x0 0x40000000>;
+	};
+
+	plic: interrupt-controller@c000000 {
+		riscv,ndev = <60>;
+		reg = <0x0 0xc000000 0x0 0x4000000>;
+		interrupts-extended = <
+			&cpu0_intc 11 &cpu0_intc 9 
+		>;
+		interrupt-controller;
+		compatible = "riscv,plic0";
+		#interrupt-cells = <0x1>;
+	};
+
+	uart0: uart@10000000 {
+		interrupts = <10>;
+		interrupt-parent = <&plic>;
+		clock-frequency = <0x384000>;
+		reg = <0x0 0x10000000 0x0 0x100>;
+		compatible = "ns16550a";
+	};
+
+    bao-ipc@f0000000 {
+        compatible = "bao,pseudo-ivshmem-net";
+        #address-cells = <2>;
+        #size-cells = <2>;
+        reg = <0x0 0xf0000000 0x0 0x00010000>;
+        interrupt-parent = <&plic>;
+        interrupts = <52 53>;
+		id = <0>;
+    };
+
+	chosen {
+		bootargs = "earlycon console=ttyS0 ip=192.168.42.15 carrier_timeout=0";
+		stdout-path = &uart0;
+	};
+};

demos/linux-ivshmem-net/devicetrees/qemu-riscv64-virt/linux2.dts

@@ -0,0 +1,149 @@
+/dts-v1/;
+
+/ {
+	#address-cells = <0x2>;
+	#size-cells = <0x2>;
+
+	cpus {
+		#address-cells = <0x1>;
+		#size-cells = <0x0>;
+		timebase-frequency = <10000000>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			reg = <0x0>;
+			status = "okay";
+			compatible = "riscv";
+			riscv,isa = "rv64imafdcsu";
+			mmu-type = "riscv,sv48";
+
+			cpu0_intc: interrupt-controller {
+				#interrupt-cells = <0x1>;
+				interrupt-controller;
+				compatible = "riscv,cpu-intc";
+			};
+		};
+
+		cpu1: cpu@1 {
+			device_type = "cpu";
+			reg = <0x1>;
+			status = "okay";
+			compatible = "riscv";
+			riscv,isa = "rv64imafdcsu";
+			mmu-type = "riscv,sv48";
+
+			cpu1_intc: interrupt-controller {
+				#interrupt-cells = <0x1>;
+				interrupt-controller;
+				compatible = "riscv,cpu-intc";
+			};
+		};
+
+		cpu2: cpu@2 {
+			device_type = "cpu";
+			reg = <0x2>;
+			status = "okay";
+			compatible = "riscv";
+			riscv,isa = "rv64imafdcsu";
+			mmu-type = "riscv,sv48";
+
+			cpu2_intc: interrupt-controller {
+				#interrupt-cells = <0x1>;
+				interrupt-controller;
+				compatible = "riscv,cpu-intc";
+			};
+		};
+
+
+	};
+
+	memory@a0000000 {
+		device_type = "memory";
+		reg = <0x0 0xa0000000 0x0 0x40000000>;
+	};
+
+	plic: interrupt-controller@c000000 {
+		riscv,ndev = <60>;
+		reg = <0x0 0xc000000 0x0 0x4000000>;
+		interrupts-extended = <
+			&cpu0_intc 11 &cpu0_intc 9 
+			&cpu1_intc 11 &cpu1_intc 9 
+			&cpu2_intc 11 &cpu2_intc 9 
+		>;
+		interrupt-controller;
+		compatible = "riscv,plic0";
+		#interrupt-cells = <0x1>;
+		#address-cells = <0x0>;
+	};
+
+	// virtio_mmio@10008000 {
+	// 	interrupts = <0x8>;
+	// 	interrupt-parent = <&plic>;
+	// 	reg = <0x0 0x10008000 0x0 0x1000>;
+	// 	compatible = "virtio,mmio";
+	// };
+
+	virtio_serial: virtio_mmio@10007000 {
+		interrupts = <0x7>;
+		interrupt-parent = <&plic>;
+		reg = <0x0 0x10007000 0x0 0x1000>;
+		compatible = "virtio,mmio";
+	};
+
+	// virtio_mmio@10006000 {
+	// 	interrupts = <0x6>;
+	// 	interrupt-parent = <&plic>;
+	// 	reg = <0x0 0x10006000 0x0 0x1000>;
+	// 	compatible = "virtio,mmio";
+	// };
+
+	// virtio_mmio@10005000 {
+	// 	interrupts = <0x5>;
+	// 	interrupt-parent = <&plic>;
+	// 	reg = <0x0 0x10005000 0x0 0x1000>;
+	// 	compatible = "virtio,mmio";
+	// };
+
+	// virtio_mmio@10004000 {
+	// 	interrupts = <0x4>;
+	// 	interrupt-parent = <&plic>;
+	// 	reg = <0x0 0x10004000 0x0 0x1000>;
+	// 	compatible = "virtio,mmio";
+	// };
+
+	// virtio_mmio@10003000 {
+	// 	interrupts = <0x3>;
+	// 	interrupt-parent = <&plic>;
+	// 	reg = <0x0 0x10003000 0x0 0x1000>;
+	// 	compatible = "virtio,mmio";
+	// };
+
+	// virtio_mmio@10002000 {
+	// 	interrupts = <0x2>;
+	// 	interrupt-parent = <&plic>;
+	// 	reg = <0x0 0x10002000 0x0 0x1000>;
+	// 	compatible = "virtio,mmio";
+	// };
+
+	// virtio_mmio@10001000 {
+	// 	interrupts = <0x1>;
+	// 	interrupt-parent = <&plic>;
+	// 	reg = <0x0 0x10001000 0x0 0x1000>;
+	// 	compatible = "virtio,mmio";
+	// };
+
+    bao-ipc@f0000000 {
+        compatible = "bao,pseudo-ivshmem-net";
+        #address-cells = <2>;
+        #size-cells = <2>;
+        reg = <0x0 0xf0000000 0x0 0x00010000>;
+        interrupt-parent = <&plic>;
+        interrupts = <52 53>;
+		id = <0>;
+    };
+
+	chosen {
+		bootargs = "earlycon console=hvc1 ip=192.168.42.16 carrier_timeout=0";
+		stdout-path = &virtio_serial;
+	};
+};

demos/linux-ivshmem-net/make.mk

@@ -0,0 +1,11 @@
+include $(bao_demos)/guests/linux/make.mk
+
+linux1_image=$(wrkdir_demo_imgs)/linux1.bin
+linux1_dts=$(bao_demos)/demos/$(DEMO)/devicetrees/$(PLATFORM)/linux1.dts
+$(eval $(call build-linux, $(linux1_image), $(linux1_dts)))
+
+linux2_image=$(wrkdir_demo_imgs)/linux2.bin
+linux2_dts=$(bao_demos)/demos/$(DEMO)/devicetrees/$(PLATFORM)/linux2.dts
+$(eval $(call build-linux, $(linux2_image), $(linux2_dts)))
+
+guest_images:=$(linux1_image) $(linux2_image)

guests/linux/configs/base.config

@@ -1 +1,2 @@
 CONFIG_BAO_SHMEM=y
+CONFIG_BAO_PSEUDO_IVSHMEM_NET=y

guests/linux/patches/rel_imx_5.4.24_2.1.0/0001-add-bao-ipcshmem-driver.patch

@@ -1,16 +1,16 @@
-From fec89b9845b4d518ed8841f42f41d90370908be6 Mon Sep 17 00:00:00 2001
+From 798b55da03b090dfe19aacea9a248348e322e032 Mon Sep 17 00:00:00 2001
 From: Jose Martins <josemartins90@gmail.com>
-Date: Sat, 6 Mar 2021 22:51:24 +0000
+Date: Mon, 5 Apr 2021 21:25:28 +0100
-Subject: [PATCH] add bao ipcshmem driver
+Subject: [PATCH 1/2] add bao ipcshmem driver
 
 Signed-off-by: Jose Martins <josemartins90@gmail.com>
 ---
  drivers/Kconfig            |   2 +
  drivers/Makefile           |   1 +
  drivers/bao/Kconfig        |   5 +
- drivers/bao/Makefile       |   2 +
+ drivers/bao/Makefile       |   1 +
  drivers/bao/bao-ipcshmem.c | 288 +++++++++++++++++++++++++++++++++++++
- 5 files changed, 298 insertions(+)
+ 5 files changed, 297 insertions(+)
  create mode 100755 drivers/bao/Kconfig
  create mode 100644 drivers/bao/Makefile
  create mode 100644 drivers/bao/bao-ipcshmem.c
@@ -37,23 +37,22 @@ index 5792caca1..61ef5b5fd 100644
 +obj-$(CONFIG_BAO_SHMEM)	+= bao/
 diff --git a/drivers/bao/Kconfig b/drivers/bao/Kconfig
 new file mode 100755
-index 000000000..dc5e9fc08
+index 000000000..aee249429
 --- /dev/null
 +++ b/drivers/bao/Kconfig
 @@ -0,0 +1,5 @@
 +config BAO_SHMEM
-+	tristate "Bao shared memory support"
++	tristate "Bao sample shared memory char device"
 +
 +	help
-+	  This implements an interface to communicate with bao hosted guests.
++	  A sample driver to communicate between Bao hosted guests.
 diff --git a/drivers/bao/Makefile b/drivers/bao/Makefile
 new file mode 100644
-index 000000000..f900be88e
+index 000000000..7265404bb
 --- /dev/null
 +++ b/drivers/bao/Makefile
-@@ -0,0 +1,2 @@
+@@ -0,0 +1 @@
-+obj-$(CONFIG_BAO_SHMEM) += bao.o
++obj-$(CONFIG_BAO_SHMEM) += bao-ipcshmem.o
-+bao-objs += bao-ipcshmem.o
 diff --git a/drivers/bao/bao-ipcshmem.c b/drivers/bao/bao-ipcshmem.c
 new file mode 100644
 index 000000000..9a25367b0

guests/linux/patches/v5.11/0001-add-bao-ipcshmem-driver.patch

@@ -1,16 +1,16 @@
-From 8b6f77465ca53540dfca7f0fda06620689543c11 Mon Sep 17 00:00:00 2001
+From 5cbf7374cdca92eeb260ddadb2a8e2d9d3e51a36 Mon Sep 17 00:00:00 2001
 From: Jose Martins <josemartins90@gmail.com>
 Date: Tue, 16 Feb 2021 16:37:13 +0000
-Subject: [PATCH] add bao ipcshmem driver
+Subject: [PATCH 1/2] add bao ipcshmem driver
 
 Signed-off-by: Jose Martins <josemartins90@gmail.com>
 ---
  drivers/Kconfig            |   2 +
  drivers/Makefile           |   1 +
  drivers/bao/Kconfig        |   5 +
- drivers/bao/Makefile       |   2 +
+ drivers/bao/Makefile       |   1 +
  drivers/bao/bao-ipcshmem.c | 288 +++++++++++++++++++++++++++++++++++++
- 5 files changed, 298 insertions(+)
+ 5 files changed, 297 insertions(+)
  create mode 100755 drivers/bao/Kconfig
  create mode 100644 drivers/bao/Makefile
  create mode 100644 drivers/bao/bao-ipcshmem.c
@@ -37,23 +37,22 @@ index 576228037..5f45b99be 100644
 +obj-$(CONFIG_BAO_SHMEM)	+= bao/
 diff --git a/drivers/bao/Kconfig b/drivers/bao/Kconfig
 new file mode 100755
-index 000000000..dc5e9fc08
+index 000000000..aee249429
 --- /dev/null
 +++ b/drivers/bao/Kconfig
 @@ -0,0 +1,5 @@
 +config BAO_SHMEM
-+	tristate "Bao shared memory support"
++	tristate "Bao sample shared memory char device"
 +
 +	help
-+	  This implements an interface to communicate with bao hosted guests.
++	  A sample driver to communicate between Bao hosted guests.
 diff --git a/drivers/bao/Makefile b/drivers/bao/Makefile
 new file mode 100644
-index 000000000..f900be88e
+index 000000000..7265404bb
 --- /dev/null
 +++ b/drivers/bao/Makefile
-@@ -0,0 +1,2 @@
+@@ -0,0 +1 @@
-+obj-$(CONFIG_BAO_SHMEM) += bao.o
++obj-$(CONFIG_BAO_SHMEM) += bao-ipcshmem.o
-+bao-objs += bao-ipcshmem.o
 diff --git a/drivers/bao/bao-ipcshmem.c b/drivers/bao/bao-ipcshmem.c
 new file mode 100644
 index 000000000..9a25367b0