Compare commits
4 Commits
| Author | SHA1 | Date |
|---|---|---|
Jose Martins
|
5e3b8f0998 | |
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Jose Martins
|
1ba56f017b | |
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Jose Martins
|
60bfecc4f5 | |
|
Jose Martins
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09e9ea3b4e |
2
Makefile
2
Makefile
|
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@ -71,7 +71,7 @@ environment+=BAO_DEMOS_SDCARD=/media/$$USER/boot
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all: platform
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all: platform
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bao_repo:=https://github.com/bao-project/bao-hypervisor
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bao_repo:=https://github.com/bao-project/bao-hypervisor
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bao_version:=v0.1.0
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bao_version:=wip/riscv-rocket
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bao_src:=$(wrkdir_src)/bao
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bao_src:=$(wrkdir_src)/bao
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bao_cfg_repo:=$(wrkdir_demo_imgs)/config
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bao_cfg_repo:=$(wrkdir_demo_imgs)/config
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wrkdirs+=$(bao_cfg_repo)
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wrkdirs+=$(bao_cfg_repo)
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@ -161,7 +161,7 @@ Clone Bao's repo to the the working directory:
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```
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```
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export BAO_DEMOS_BAO=$BAO_DEMOS_WRKDIR_SRC/bao
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export BAO_DEMOS_BAO=$BAO_DEMOS_WRKDIR_SRC/bao
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git clone https://github.com/bao-project/bao-hypervisor $BAO_DEMOS_BAO\
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git clone https://github.com/bao-project/bao-hypervisor $BAO_DEMOS_BAO\
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--branch v0.1.0
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--branch wip/riscv-rocket
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```
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```
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Copy your config to the working directory:
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Copy your config to the working directory:
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@ -203,6 +203,7 @@ Build the firmware and deploy the system according to the target platform:
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#### RISC-V platforms:
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#### RISC-V platforms:
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* [QEMU virt](platforms/qemu-riscv64-virt/README.md)
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* [QEMU virt](platforms/qemu-riscv64-virt/README.md)
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* [Rocket/Chipyard on ZCU104 FPGA](platforms/rocket-fpga-common/README.md)
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---
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---
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@ -217,6 +218,7 @@ Build the firmware and deploy the system according to the target platform:
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| Raspberry 4 Model B | rpi4 | aarch64
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| Raspberry 4 Model B | rpi4 | aarch64
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| QEMU Aarch64 virt | qemu-aarch64-virt | aarch64
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| QEMU Aarch64 virt | qemu-aarch64-virt | aarch64
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| QEMU RV64 virt | qemu-riscv64-virt | riscv
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| QEMU RV64 virt | qemu-riscv64-virt | riscv
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| Rocket/Chipyard on ZCU104 FPGA | rocket-fpga-zcu104 | riscv
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<!-- TODO -->
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<!-- TODO -->
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<!-- | NXP i.MX8MQ | imx8mq | -->
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<!-- | NXP i.MX8MQ | imx8mq | -->
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<!-- | Avnet Ultra96 | ultra96 | -->
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<!-- | Avnet Ultra96 | ultra96 | -->
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@ -246,6 +248,7 @@ Build the firmware and deploy the system according to the target platform:
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| mkimage | 20.10 |
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| mkimage | 20.10 |
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| cmake | 3.16.3 |
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| cmake | 3.16.3 |
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| ninja | 1.10.1 |
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| ninja | 1.10.1 |
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| Vivado | 2020.1.1 |
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<!-- Links -->
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<!-- Links -->
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@ -0,0 +1,48 @@
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#include <config.h>
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VM_IMAGE(baremetal_image, XSTR(BAO_DEMOS_WRKDIR_IMGS/baremetal.bin));
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struct config config = {
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CONFIG_HEADER
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.vmlist_size = 1,
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.vmlist = {
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{
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.image = {
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.base_addr = 0x40200000,
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.load_addr = VM_IMAGE_OFFSET(baremetal_image),
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.size = VM_IMAGE_SIZE(baremetal_image)
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},
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.entry = 0x40200000,
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.platform = {
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.cpu_num = 4,
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.region_num = 1,
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.regions = (struct mem_region[]) {
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{
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.base = 0x40200000,
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.size = 0x1000000 //128MB
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}
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},
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.dev_num = 1,
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.devs = (struct dev_region[]) {
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{
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.pa = 0xff000000,
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.va = 0xff000000,
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.size = 0x1000,
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.interrupt_num = 1,
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.interrupts = (uint64_t[]) {1}
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},
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},
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.arch = {
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.plic_base = 0xc000000,
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}
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},
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},
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}
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};
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@ -0,0 +1,113 @@
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#include <config.h>
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VM_IMAGE(linux_image, XSTR(BAO_DEMOS_WRKDIR_IMGS/linux.bin));
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VM_IMAGE(freertos_image, XSTR(BAO_DEMOS_WRKDIR_IMGS/freertos.bin));
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struct config config = {
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CONFIG_HEADER
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.shmemlist_size = 1,
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.shmemlist = (struct shmem[]) {
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[0] = { .size = 0x00010000, }
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},
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.vmlist_size = 2,
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.vmlist = {
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{
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.image = {
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.base_addr = 0x40200000,
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.load_addr = VM_IMAGE_OFFSET(linux_image),
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.size = VM_IMAGE_SIZE(linux_image)
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},
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.entry = 0x40200000,
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.platform = {
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.cpu_num = 3,
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.region_num = 1,
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.regions = (struct mem_region[]) {
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{
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.base = 0x40200000,
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.size = 0x10000000
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}
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},
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.ipc_num = 1,
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.ipcs = (struct ipc[]) {
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{
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.base = 0xf0000000,
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.size = 0x00010000,
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.shmem_id = 0,
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.interrupt_num = 1,
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.interrupts = (uint64_t[]) {52}
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}
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},
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.dev_num = 1,
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.devs = (struct dev_region[]) {
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{
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.pa = 0xff010000,
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.va = 0xff010000,
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.size = 0x1000,
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.interrupt_num = 1,
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.interrupts = (uint64_t[]) {2}
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},
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},
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.arch = {
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.plic_base = 0xc000000,
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}
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},
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},
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{
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.image = {
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.base_addr = 0x40200000,
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.load_addr = VM_IMAGE_OFFSET(freertos_image),
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.size = VM_IMAGE_SIZE(freertos_image)
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},
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.entry = 0x40200000,
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.platform = {
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.cpu_num = 1,
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.region_num = 1,
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.regions = (struct mem_region[]) {
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{
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.base = 0x40200000,
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.size = 0x01000000
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}
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},
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.ipc_num = 1,
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.ipcs = (struct ipc[]) {
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{
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.base = 0x70000000,
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.size = 0x00010000,
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.shmem_id = 0,
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.interrupt_num = 1,
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.interrupts = (uint64_t[]) {52}
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}
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},
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.dev_num = 1,
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.devs = (struct dev_region[]) {
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{
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.pa = 0xff000000,
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.va = 0xff000000,
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.size = 0x1000,
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.interrupt_num = 1,
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.interrupts = (uint64_t[]) {1}
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},
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},
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.arch = {
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.plic_base = 0xc000000,
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}
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},
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},
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}
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};
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@ -0,0 +1,110 @@
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/dts-v1/;
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/ {
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#address-cells = <0x2>;
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#size-cells = <0x2>;
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cpus {
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#address-cells = <0x1>;
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#size-cells = <0x0>;
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timebase-frequency = <1000000>;
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cpu0: cpu@0 {
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device_type = "cpu";
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reg = <0x0>;
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status = "okay";
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compatible = "riscv";
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riscv,isa = "rv64imafdcsu";
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mmu-type = "riscv,sv48";
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cpu0_intc: interrupt-controller {
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#interrupt-cells = <0x1>;
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interrupt-controller;
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compatible = "riscv,cpu-intc";
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};
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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reg = <0x1>;
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status = "okay";
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compatible = "riscv";
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riscv,isa = "rv64imafdcsu";
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mmu-type = "riscv,sv48";
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cpu1_intc: interrupt-controller {
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#interrupt-cells = <0x1>;
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interrupt-controller;
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compatible = "riscv,cpu-intc";
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};
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};
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cpu2: cpu@2 {
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device_type = "cpu";
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reg = <0x2>;
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status = "okay";
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compatible = "riscv";
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riscv,isa = "rv64imafdcsu";
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mmu-type = "riscv,sv48";
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cpu2_intc: interrupt-controller {
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#interrupt-cells = <0x1>;
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interrupt-controller;
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compatible = "riscv,cpu-intc";
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};
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};
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};
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memory@40200000 {
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device_type = "memory";
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reg = <0x0 0x40200000 0x0 0x10000000>;
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};
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plic: interrupt-controller@c000000 {
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riscv,ndev = <60>;
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reg = <0x0 0xc000000 0x0 0x4000000>;
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interrupts-extended = <
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&cpu0_intc 11 &cpu0_intc 9
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&cpu1_intc 11 &cpu1_intc 9
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&cpu2_intc 11 &cpu2_intc 9
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>;
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interrupt-controller;
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compatible = "riscv,plic0";
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#interrupt-cells = <0x1>;
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};
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uartclk: uartclk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <100000000>;
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};
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serial@ff010000 {
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compatible = "cdns,uart-r1p12";
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status = "okay";
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interrupts = <2>;
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interrupt-parent = <&plic>;
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reg = <0x0 0xff010000 0x0 0x1000>;
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clock-names = "uart_clk", "pclk";
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clocks = <&uartclk>, <&uartclk>;
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};
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bao-ipc@f0000000 {
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compatible = "bao,ipcshmem";
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reg = <0x0 0xf0000000 0x0 0x00010000>;
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read-channel = <0x0 0x2000>;
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write-channel = <0x2000 0x2000>;
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interrupt-parent = <&plic>;
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interrupts = <52>;
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id = <0>;
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};
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||||||
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aliases {
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serial0 = "/serial@ff010000";
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};
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chosen {
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bootargs = "earlycon console=ttyPS0,115200n8";
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stdout-path = "/serial@ff010000";
|
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};
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};
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|
@ -10,7 +10,7 @@ Clone and build the bao bare-metal guest application:
|
||||||
|
|
||||||
```
|
```
|
||||||
git clone https://github.com/bao-project/bao-baremetal-guest.git\
|
git clone https://github.com/bao-project/bao-baremetal-guest.git\
|
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$BAO_DEMOS_BAREMETAL
|
$BAO_DEMOS_BAREMETAL --branch rocket
|
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make -C $BAO_DEMOS_BAREMETAL PLATFORM=$PLATFORM
|
make -C $BAO_DEMOS_BAREMETAL PLATFORM=$PLATFORM
|
||||||
```
|
```
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||||||
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|
||||||
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||||||
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@ -1,6 +1,6 @@
|
||||||
baremetal_src:=$(wrkdir_src)/baremetal
|
baremetal_src:=$(wrkdir_src)/baremetal
|
||||||
baremetal_repo:=https://github.com/bao-project/bao-baremetal-guest.git
|
baremetal_repo:=https://github.com/bao-project/bao-baremetal-guest.git
|
||||||
baremetal_branch:=master
|
baremetal_branch:=rocket
|
||||||
|
|
||||||
$(baremetal_src):
|
$(baremetal_src):
|
||||||
git clone $(baremetal_repo) $@ --branch $(baremetal_branch)
|
git clone $(baremetal_repo) $@ --branch $(baremetal_branch)
|
||||||
|
|
|
||||||
|
|
@ -11,7 +11,7 @@ Then clone and build the FreeRTOS:
|
||||||
```
|
```
|
||||||
git clone --recursive --shallow-submodules\
|
git clone --recursive --shallow-submodules\
|
||||||
https://github.com/bao-project/freertos-over-bao.git\
|
https://github.com/bao-project/freertos-over-bao.git\
|
||||||
$BAO_DEMOS_FREERTOS --branch demo
|
$BAO_DEMOS_FREERTOS --branch demo-rocket
|
||||||
make -C $BAO_DEMOS_FREERTOS PLATFORM=$PLATFORM
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make -C $BAO_DEMOS_FREERTOS PLATFORM=$PLATFORM
|
||||||
```
|
```
|
||||||
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|
||||||
|
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|
||||||
|
|
@ -1,6 +1,6 @@
|
||||||
freertos_src:=$(wrkdir_src)/freertos
|
freertos_src:=$(wrkdir_src)/freertos
|
||||||
freertos_repo:=https://github.com/bao-project/freertos-over-bao.git
|
freertos_repo:=https://github.com/bao-project/freertos-over-bao.git
|
||||||
freertos_branch:=demo
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freertos_branch:=demo-rocket
|
||||||
|
|
||||||
$(freertos_src):
|
$(freertos_src):
|
||||||
git clone --recursive --shallow-submodules --branch $(freertos_branch) \
|
git clone --recursive --shallow-submodules --branch $(freertos_branch) \
|
||||||
|
|
|
||||||
|
|
@ -0,0 +1,2 @@
|
||||||
|
CONFIG_SERIAL_XILINX_PS_UART=y
|
||||||
|
CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y
|
||||||
|
|
@ -1,5 +1,5 @@
|
||||||
opensbi_repo:=https://github.com/bao-project/opensbi.git
|
opensbi_repo:=https://github.com/bao-project/opensbi.git
|
||||||
opensbi_version:=bao
|
opensbi_version:=bao/rocket
|
||||||
opensbi_src:=$(wrkdir_src)/opensbi
|
opensbi_src:=$(wrkdir_src)/opensbi
|
||||||
|
|
||||||
$(opensbi_src):
|
$(opensbi_src):
|
||||||
|
|
@ -7,9 +7,9 @@ $(opensbi_src):
|
||||||
|
|
||||||
define build-opensbi-payload
|
define build-opensbi-payload
|
||||||
$(strip $1): $(strip $2) $(opensbi_src)
|
$(strip $1): $(strip $2) $(opensbi_src)
|
||||||
$(MAKE) -C $(opensbi_src) PLATFORM=generic \
|
$(MAKE) -C $(opensbi_src) PLATFORM=$(strip $3) \
|
||||||
FW_PAYLOAD=y \
|
FW_PAYLOAD=y \
|
||||||
FW_PAYLOAD_FDT_ADDR=0x80100000\
|
FW_PAYLOAD_FDT_ADDR=$(strip $4)\
|
||||||
FW_PAYLOAD_PATH=$(strip $2)
|
FW_PAYLOAD_PATH=$(strip $2)
|
||||||
cp $(opensbi_src)/build/platform/generic/firmware/fw_payload.elf $$@
|
cp $(opensbi_src)/build/platform/$(strip $3)/firmware/fw_payload$(suffix $1) $$@
|
||||||
endef
|
endef
|
||||||
|
|
@ -4,7 +4,7 @@ include $(bao_demos)/platforms/qemu.mk
|
||||||
include $(bao_demos)/platforms/opensbi.mk
|
include $(bao_demos)/platforms/opensbi.mk
|
||||||
|
|
||||||
opensbi_image:=$(wrkdir_demo_imgs)/opensbi.elf
|
opensbi_image:=$(wrkdir_demo_imgs)/opensbi.elf
|
||||||
$(eval $(call build-opensbi-payload, $(opensbi_image), $(bao_image)))
|
$(eval $(call build-opensbi-payload, $(opensbi_image), $(bao_image), generic, 0x80100000))
|
||||||
|
|
||||||
platform: $(opensbi_image)
|
platform: $(opensbi_image)
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -0,0 +1,116 @@
|
||||||
|
# Rocket/Chypyard on Xilinx FPGA
|
||||||
|
|
||||||
|
<!--- instruction#1 -->
|
||||||
|
|
||||||
|
## 0) Setup environment
|
||||||
|
|
||||||
|
You will need to [install the necessary Chipyard and Rocket-chip dependencies](https://github.com/chipsalliance/rocket-chip#install-necessary-dependencies) such as Chisel to build Rocket RTL.
|
||||||
|
|
||||||
|
If you don't have Vivado already installed, do it by following
|
||||||
|
[Installing the Vivado Design Suite Tools](https://www.xilinx.com/content/dam/xilinx/support/documentation/sw_manuals/xilinx2020_2/ug973-vivado-release-notes-install-license.pdf). Then, make
|
||||||
|
sure the Vivado tools binary directory is in your **PATH** environment variable.
|
||||||
|
|
||||||
|
<!--- instruction#end -->
|
||||||
|
|
||||||
|
## 1) Generate the Rocket/Chipyard SoC RTL design
|
||||||
|
|
||||||
|
Clone and setup the Chipyard/Rocket-Chip repos:
|
||||||
|
|
||||||
|
```
|
||||||
|
export BAO_DEMOS_CHIPYARD=$BAO_DEMOS_WRKDIR_SRC/chipyard
|
||||||
|
export BAO_DEMOS_ROCKETCHIP=$BAO_DEMOS_CHIPYARD/generators/rocket-chip
|
||||||
|
git clone https://github.com/ucb-bar/chipyard.git $BAO_DEMOS_CHIPYARD
|
||||||
|
cd $BAO_DEMOS_CHIPYARD
|
||||||
|
git checkout 64632c8
|
||||||
|
./scripts/init-submodules-no-riscv-tools.sh
|
||||||
|
git apply $BAO_DEMOS/platforms/$PLATFORM/patches/0001-add-rocket-hyp-fpga-support.patch
|
||||||
|
git -C generators/boom apply $BAO_DEMOS/platforms/$PLATFORM/patches/0001-boom-add-usehyp-option.patch
|
||||||
|
git -C generators/ariane apply $BAO_DEMOS/platforms/$PLATFORM/patches/0001-ariane-add-usehyp-option.patch
|
||||||
|
cd $BAO_DEMOS_ROCKETCHIP
|
||||||
|
git remote add hyp https://github.com/josecm/rocket-chip.git
|
||||||
|
git fetch hyp
|
||||||
|
git checkout hyp
|
||||||
|
```
|
||||||
|
|
||||||
|
Build the bootrom:
|
||||||
|
|
||||||
|
```
|
||||||
|
make -C $BAO_DEMOS_CHIPYARD/bootromFPGA
|
||||||
|
```
|
||||||
|
|
||||||
|
Generate the verilog:
|
||||||
|
|
||||||
|
```
|
||||||
|
export BAO_DEMOS_ROCKET_CONFIG=RocketHypConfig$(echo $PLATFORM | awk '{split($0,A,"-"); print A[length(A)]}')
|
||||||
|
make -C $BAO_DEMOS_CHIPYARD/sims/vcs verilog SUB_PROJECT=rocket \
|
||||||
|
CONFIG=$BAO_DEMOS_ROCKET_CONFIG
|
||||||
|
```
|
||||||
|
|
||||||
|
## 2) Build the design using Vivado
|
||||||
|
|
||||||
|
Now run the Vivado tcl scripts which will create a Vivado project and run all
|
||||||
|
the build steps.
|
||||||
|
|
||||||
|
First set the number of theads you want vivado to use on the
|
||||||
|
build in the **VIVADO_CORES** environment variable. For example, to use all
|
||||||
|
available cores:
|
||||||
|
|
||||||
|
```
|
||||||
|
export VIVADO_CORES=$(nproc)
|
||||||
|
```
|
||||||
|
|
||||||
|
Then run the tcl scripts to create and build the vivado designs:
|
||||||
|
|
||||||
|
```
|
||||||
|
export BAO_DEMOS_VIVADO_SCRIPTS=$BAO_DEMOS/platforms/$PLATFORM/scripts
|
||||||
|
vivado -nolog -nojournal -mode batch -source $BAO_DEMOS_VIVADO_SCRIPTS/create_ip.tcl
|
||||||
|
vivado -nolog -nojournal -mode batch -source $BAO_DEMOS_VIVADO_SCRIPTS/create_design.tcl
|
||||||
|
vivado -nolog -nojournal -mode batch -source $BAO_DEMOS_VIVADO_SCRIPTS/build.tcl
|
||||||
|
```
|
||||||
|
|
||||||
|
## 3) Compile OpenSBI
|
||||||
|
|
||||||
|
Clone and build OpenSBI firmware that runs in machine mode:
|
||||||
|
|
||||||
|
```
|
||||||
|
export BAO_DEMOS_OPENSBI=$BAO_DEMOS_WRKDIR_SRC/opensbi
|
||||||
|
git clone https://github.com/bao-project/opensbi.git $BAO_DEMOS_OPENSBI\
|
||||||
|
--depth 1 --branch bao/rocket
|
||||||
|
make -C $BAO_DEMOS_OPENSBI PLATFORM=$PLATFORM \
|
||||||
|
FW_PAYLOAD=y \
|
||||||
|
FW_PAYLOAD_FDT_ADDR=0x40100000\
|
||||||
|
FW_PAYLOAD_PATH=$BAO_DEMOS_WRKDIR_IMGS/bao.bin
|
||||||
|
cp $BAO_DEMOS_OPENSBI/build/platform/$PLATFORM/firmware/fw_payload.bin\
|
||||||
|
$BAO_DEMOS_WRKDIR_IMGS/opensbi.bin
|
||||||
|
```
|
||||||
|
|
||||||
|
<!--- instruction#2 -->
|
||||||
|
|
||||||
|
## 4) Setup board
|
||||||
|
|
||||||
|
First make sure you have the board's boot mode configured as JTAG. If you
|
||||||
|
are not sure how, check the the board's user guide provided by Xilinx.
|
||||||
|
Then, connect to the baord via the available micro-USB JTAG/UART port.
|
||||||
|
|
||||||
|
Connect to both UARTs available on the board (baud 115200) (in our setup
|
||||||
|
*/dev/ttyUSB1* and */dev/ttyUSB2* for ZCU104) and connect to them using a tool
|
||||||
|
such as screen. For example:
|
||||||
|
|
||||||
|
```
|
||||||
|
screen /dev/ttyUSB1 115200
|
||||||
|
```
|
||||||
|
|
||||||
|
Turn on/reset your board.
|
||||||
|
|
||||||
|
<!--- instruction#end -->
|
||||||
|
|
||||||
|
## 5) Flash bitsream and run
|
||||||
|
|
||||||
|
Execute the deploy script using the xilinx command line tools which will load
|
||||||
|
the system image and flash the bitsteam:
|
||||||
|
|
||||||
|
```
|
||||||
|
xsct $BAO_DEMOS_VIVADO_SCRIPTS/deploy.tcl $BAO_DEMOS_WRKDIR_IMGS/opensbi.bin
|
||||||
|
```
|
||||||
|
|
||||||
|
You should start seeing OpenSBI, Bao and the guests' ouputs.
|
||||||
|
|
@ -0,0 +1,68 @@
|
||||||
|
|
||||||
|
ARCH:=riscv
|
||||||
|
board:=$(lastword $(subst -, ,$(PLATFORM)))
|
||||||
|
instructions:=$(bao_demos)/platforms/$(PLATFORM)/README.md
|
||||||
|
|
||||||
|
chipyard_repo:=https://github.com/ucb-bar/chipyard.git
|
||||||
|
chipyard_commit:=64632c8
|
||||||
|
chipyard_src:=$(wrkdir_src)/chipyard
|
||||||
|
chipyard_patches:=$(bao_demos)/platforms/$(PLATFORM)/patches
|
||||||
|
rocketchip_src:=$(chipyard_src)/generators/rocket-chip
|
||||||
|
rocketchip_repo:=https://github.com/josecm/rocket-chip.git
|
||||||
|
bootrom_src:=$(chipyard_src)/bootromFPGA
|
||||||
|
bootrom_img:=$(bootrom_src)/bootrom_zynqmp.img
|
||||||
|
rocket_config:=RocketHypConfig$(board)
|
||||||
|
verilog_srcs:=$(chipyard_src)/sims/vcs/generated-src/freechips.rocketchip.system.TestHarness.$(rocket_config)
|
||||||
|
|
||||||
|
VIVADO_CORES:=$(shell nproc)
|
||||||
|
vivado_scripts:=$(bao_demos)/platforms/$(PLATFORM)/scripts
|
||||||
|
|
||||||
|
ip_project:=$(wrkdir_plat_imgs)/rocket_ip
|
||||||
|
project_name:=rocket_system_$(board)
|
||||||
|
system_project:=$(wrkdir_plat_imgs)/$(project_name)
|
||||||
|
bitstream:=$(wrkdir_plat_imgs)/$(project_name)/$(project_name).bit
|
||||||
|
|
||||||
|
environment+=BAO_DEMOS_CHIPYARD=$(chipyard_src)
|
||||||
|
environment+=BAO_DEMOS_ROCKET_CONFIG=$(rocket_config)
|
||||||
|
environment+=VIVADO_CORES=$(VIVADO_CORES)
|
||||||
|
|
||||||
|
$(chipyard_src):
|
||||||
|
$(call print-instructions, $(instructions), 1, false)
|
||||||
|
git clone $(chipyard_repo) $(chipyard_src)
|
||||||
|
git -C $(chipyard_src) checkout $(chipyard_commit)
|
||||||
|
cd $(chipyard_src) && ./scripts/init-submodules-no-riscv-tools.sh
|
||||||
|
git -C $(chipyard_src) apply $(chipyard_patches)/0001-add-rocket-hyp-fpga-support.patch
|
||||||
|
git -C $(chipyard_src)/generators/boom apply $(chipyard_patches)/0001-boom-add-usehyp-option.patch
|
||||||
|
git -C $(chipyard_src)/generators/ariane apply $(chipyard_patches)/0001-ariane-add-usehyp-option.patch
|
||||||
|
git -C $(rocketchip_src) remote add hyp $(rocketchip_repo)
|
||||||
|
git -C $(rocketchip_src) fetch hyp
|
||||||
|
git -C $(rocketchip_src) checkout hyp
|
||||||
|
|
||||||
|
$(bootrom_img): | $(chipyard_src)
|
||||||
|
make -C $(bootrom_src)
|
||||||
|
|
||||||
|
$(verilog_srcs): | $(chipyard_src) $(bootrom_img)
|
||||||
|
make -C $(chipyard_src)/sims/vcs verilog SUB_PROJECT=rocket \
|
||||||
|
CONFIG=$(rocket_config)
|
||||||
|
|
||||||
|
$(ip_project): | $(verilog_srcs)
|
||||||
|
$(environment) vivado -nolog -nojournal -mode batch -source $(vivado_scripts)/create_ip.tcl
|
||||||
|
|
||||||
|
$(system_project): | $(ip_project)
|
||||||
|
$(environment) vivado -nolog -nojournal -mode batch -source $(vivado_scripts)/create_design.tcl
|
||||||
|
|
||||||
|
$(bitstream): | $(system_project)
|
||||||
|
$(environment) vivado -nolog -nojournal -mode batch -source $(vivado_scripts)/build.tcl
|
||||||
|
|
||||||
|
include $(bao_demos)/platforms/opensbi.mk
|
||||||
|
opensbi_image:=$(wrkdir_demo_imgs)/opensbi.bin
|
||||||
|
$(eval $(call build-opensbi-payload, $(opensbi_image), $(bao_image), $(PLATFORM), 0x40100000))
|
||||||
|
|
||||||
|
platform: $(bitstream) $(opensbi_image)
|
||||||
|
|
||||||
|
run: $(bitstream) $(opensbi_image)
|
||||||
|
$(call print-instructions, $(instructions), 2, false)
|
||||||
|
$(environment) xsct $(vivado_scripts)/deploy.tcl $(opensbi_image)
|
||||||
|
|
||||||
|
all:
|
||||||
|
@printf "\nTo load system image and flash the bitstream execute \"make PLATFORM=$(PLATFORM) DEMO=$(DEMO) run\"\n\n"
|
||||||
|
|
@ -0,0 +1,186 @@
|
||||||
|
From 533ffa1fba44396e915b01ddc9cf1034309a065f Mon Sep 17 00:00:00 2001
|
||||||
|
From: Jose Martins <josemartins90@gmail.com>
|
||||||
|
Date: Thu, 24 Jun 2021 22:46:52 +0100
|
||||||
|
Subject: [PATCH] add rocket hyp fpga support
|
||||||
|
|
||||||
|
Signed-off-by: Jose Martins <josemartins90@gmail.com>
|
||||||
|
---
|
||||||
|
bootromFPGA/Makefile | 27 ++++++++++
|
||||||
|
bootromFPGA/bootrom.S | 27 ++++++++++
|
||||||
|
bootromFPGA/linker.ld | 11 ++++
|
||||||
|
.../scala/config/RocketHypFPGAConfigs.scala | 52 +++++++++++++++++++
|
||||||
|
variables.mk | 12 +++++
|
||||||
|
5 files changed, 129 insertions(+)
|
||||||
|
create mode 100644 bootromFPGA/Makefile
|
||||||
|
create mode 100644 bootromFPGA/bootrom.S
|
||||||
|
create mode 100644 bootromFPGA/linker.ld
|
||||||
|
create mode 100644 generators/chipyard/src/main/scala/config/RocketHypFPGAConfigs.scala
|
||||||
|
|
||||||
|
diff --git a/bootromFPGA/Makefile b/bootromFPGA/Makefile
|
||||||
|
new file mode 100644
|
||||||
|
index 00000000..6a269631
|
||||||
|
--- /dev/null
|
||||||
|
+++ b/bootromFPGA/Makefile
|
||||||
|
@@ -0,0 +1,27 @@
|
||||||
|
+BOARD:=$(patsubst rocket-fpga-%,%,$(PLATFORM))
|
||||||
|
+ifneq ($(filter $(BOARD), zcu104),)
|
||||||
|
+ DRAM_BASE:=0x40000000
|
||||||
|
+ SUFFIX:=zynqmp
|
||||||
|
+else ifneq ($(filter $(BOARD), zybo),)
|
||||||
|
+ DRAM_BASE:=0x10000000
|
||||||
|
+ SUFFIX:=zynq
|
||||||
|
+else
|
||||||
|
+ $(error unknown target $(PLATFORM))
|
||||||
|
+endif
|
||||||
|
+
|
||||||
|
+GCC=riscv64-unknown-elf-gcc
|
||||||
|
+OBJCOPY=riscv64-unknown-elf-objcopy
|
||||||
|
+
|
||||||
|
+all: bootrom_$(SUFFIX).img
|
||||||
|
+
|
||||||
|
+%.img: %.bin
|
||||||
|
+ dd if=$< of=$@ bs=128 count=1
|
||||||
|
+
|
||||||
|
+%.bin: %.elf
|
||||||
|
+ $(OBJCOPY) -O binary $< $@
|
||||||
|
+
|
||||||
|
+%.elf: bootrom.S linker.ld
|
||||||
|
+ $(GCC) -Tlinker.ld $< -nostdlib -static -Wl,--no-gc-sections -DDRAM_BASE=$(DRAM_BASE) -o $@
|
||||||
|
+
|
||||||
|
+clean:
|
||||||
|
+ -rm *.img
|
||||||
|
\ No newline at end of file
|
||||||
|
diff --git a/bootromFPGA/bootrom.S b/bootromFPGA/bootrom.S
|
||||||
|
new file mode 100644
|
||||||
|
index 00000000..21cf5bca
|
||||||
|
--- /dev/null
|
||||||
|
+++ b/bootromFPGA/bootrom.S
|
||||||
|
@@ -0,0 +1,27 @@
|
||||||
|
+.section .text.start, "ax", @progbits
|
||||||
|
+.globl _start
|
||||||
|
+_start:
|
||||||
|
+ csrwi 0x7c1, 0 // disable chicken bits
|
||||||
|
+ li s0, DRAM_BASE
|
||||||
|
+ csrr a0, mhartid
|
||||||
|
+ la a1, _dtb
|
||||||
|
+ jr s0
|
||||||
|
+
|
||||||
|
+.section .text.hang, "ax", @progbits
|
||||||
|
+.globl _hang
|
||||||
|
+_hang:
|
||||||
|
+ csrwi 0x7c1, 0 // disable chicken bits
|
||||||
|
+ li s0, DRAM_BASE
|
||||||
|
+ csrr a0, mhartid
|
||||||
|
+ la a1, _dtb
|
||||||
|
+ jr s0
|
||||||
|
+1:
|
||||||
|
+ wfi
|
||||||
|
+ j 1b
|
||||||
|
+
|
||||||
|
+.section .rodata.dtb, "a", @progbits
|
||||||
|
+.globl _dtb
|
||||||
|
+.align 5, 0
|
||||||
|
+_dtb:
|
||||||
|
+ .word 0
|
||||||
|
+ .word 0
|
||||||
|
diff --git a/bootromFPGA/linker.ld b/bootromFPGA/linker.ld
|
||||||
|
new file mode 100644
|
||||||
|
index 00000000..43bc012a
|
||||||
|
--- /dev/null
|
||||||
|
+++ b/bootromFPGA/linker.ld
|
||||||
|
@@ -0,0 +1,11 @@
|
||||||
|
+SECTIONS
|
||||||
|
+{
|
||||||
|
+ ROM_BASE = 0x10000; /* ... but actually position independent */
|
||||||
|
+
|
||||||
|
+ . = ROM_BASE;
|
||||||
|
+ .text.start : { *(.text.start) }
|
||||||
|
+ . = ROM_BASE + 0x40;
|
||||||
|
+ .text.hang : { *(.text.hang) }
|
||||||
|
+ . = ROM_BASE + 0x80;
|
||||||
|
+ .rodata.dtb : { *(.rodata.dtb) }
|
||||||
|
+}
|
||||||
|
diff --git a/generators/chipyard/src/main/scala/config/RocketHypFPGAConfigs.scala b/generators/chipyard/src/main/scala/config/RocketHypFPGAConfigs.scala
|
||||||
|
new file mode 100644
|
||||||
|
index 00000000..d49b8692
|
||||||
|
--- /dev/null
|
||||||
|
+++ b/generators/chipyard/src/main/scala/config/RocketHypFPGAConfigs.scala
|
||||||
|
@@ -0,0 +1,52 @@
|
||||||
|
+package chipyard
|
||||||
|
+
|
||||||
|
+import freechips.rocketchip.config.{Config}
|
||||||
|
+
|
||||||
|
+import freechips.rocketchip.subsystem._
|
||||||
|
+import freechips.rocketchip.config._
|
||||||
|
+import freechips.rocketchip.devices.debug._
|
||||||
|
+import freechips.rocketchip.devices.tilelink._
|
||||||
|
+import freechips.rocketchip.diplomacy._
|
||||||
|
+import freechips.rocketchip.rocket._
|
||||||
|
+import freechips.rocketchip.tile._
|
||||||
|
+import freechips.rocketchip.tilelink._
|
||||||
|
+import freechips.rocketchip.util._
|
||||||
|
+
|
||||||
|
+class RocketHypConfigzcu104 extends RocketHypZCU(4)
|
||||||
|
+
|
||||||
|
+class RocketHypZCU(numHarts: Int) extends Config(
|
||||||
|
+ new Config((site, here, up) => {
|
||||||
|
+ case ExtMem => Some(MemoryPortParams(MasterPortParams(
|
||||||
|
+ base = 0x40000000L,
|
||||||
|
+ size = 0x40000000L,
|
||||||
|
+ beatBytes = site(MemoryBusKey).beatBytes,
|
||||||
|
+ idBits = 4), 1))
|
||||||
|
+ case ExtBus => Some(MasterPortParams(
|
||||||
|
+ base = 0xFF000000L,
|
||||||
|
+ size = 0x01000000L,
|
||||||
|
+ beatBytes = site(MemoryBusKey).beatBytes,
|
||||||
|
+ idBits = 4))
|
||||||
|
+ }) ++
|
||||||
|
+ new freechips.rocketchip.subsystem.WithNExtTopInterrupts(2) ++
|
||||||
|
+ new freechips.rocketchip.subsystem.WithBootROMFile(s"./bootromFPGA/bootrom_zynqmp.img") ++
|
||||||
|
+ new RocketFPGAConfig(numHarts)
|
||||||
|
+)
|
||||||
|
+
|
||||||
|
+class RocketFPGAConfig(numHarts: Int) extends Config(
|
||||||
|
+ new Config((site, here, up)=> {
|
||||||
|
+ case RocketTilesKey => up(RocketTilesKey, site) map { r =>
|
||||||
|
+ r.copy(core = r.core.copy(haveCFlush = true))
|
||||||
|
+ }
|
||||||
|
+ }) ++
|
||||||
|
+ new freechips.rocketchip.subsystem.WithHyp ++
|
||||||
|
+ new freechips.rocketchip.subsystem.WithNBigCores(numHarts) ++
|
||||||
|
+ new Config((site, up, here) => {
|
||||||
|
+ case DebugModuleKey => None
|
||||||
|
+ }) ++
|
||||||
|
+ new chipyard.config.WithL2TLBs(1024) ++ // use L2 TLBs
|
||||||
|
+ new freechips.rocketchip.subsystem.WithNoSlavePort ++ // no top-level MMIO slave port (overrides default set in rocketchip)
|
||||||
|
+ new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use Sifive L2 cache
|
||||||
|
+ new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ // hierarchical buses including mbus+l2
|
||||||
|
+ new freechips.rocketchip.system.BaseConfig
|
||||||
|
+)
|
||||||
|
+
|
||||||
|
diff --git a/variables.mk b/variables.mk
|
||||||
|
index 4d49d5fe..f740e62e 100644
|
||||||
|
--- a/variables.mk
|
||||||
|
+++ b/variables.mk
|
||||||
|
@@ -27,6 +27,18 @@
|
||||||
|
#########################################################################################
|
||||||
|
SUB_PROJECT ?= chipyard
|
||||||
|
|
||||||
|
+ifeq ($(SUB_PROJECT),rocket)
|
||||||
|
+ SBT_PROJECT ?= chipyard
|
||||||
|
+ MODEL ?= TestHarness
|
||||||
|
+ VLOG_MODEL ?= TestHarness
|
||||||
|
+ MODEL_PACKAGE ?= freechips.rocketchip.system
|
||||||
|
+ CONFIG ?= RocketConfig
|
||||||
|
+ CONFIG_PACKAGE ?= $(SBT_PROJECT)
|
||||||
|
+ GENERATOR_PACKAGE ?= $(SBT_PROJECT)
|
||||||
|
+ TB ?= TestDriver
|
||||||
|
+ TOP ?= ExampleRocketSystem
|
||||||
|
+endif
|
||||||
|
+
|
||||||
|
ifeq ($(SUB_PROJECT),chipyard)
|
||||||
|
SBT_PROJECT ?= chipyard
|
||||||
|
MODEL ?= TestHarness
|
||||||
|
--
|
||||||
|
2.30.2
|
||||||
|
|
||||||
|
|
@ -0,0 +1,25 @@
|
||||||
|
From b11870ab40db0fa046ed00189e66d73a08c4ee6a Mon Sep 17 00:00:00 2001
|
||||||
|
From: Jose Martins <josemartins90@gmail.com>
|
||||||
|
Date: Mon, 2 Nov 2020 10:16:03 +0000
|
||||||
|
Subject: [PATCH] add usehyp option
|
||||||
|
|
||||||
|
Signed-off-by: Jose Martins <josemartins90@gmail.com>
|
||||||
|
---
|
||||||
|
src/main/scala/ArianeTile.scala | 1 +
|
||||||
|
1 file changed, 1 insertion(+)
|
||||||
|
|
||||||
|
diff --git a/src/main/scala/ArianeTile.scala b/src/main/scala/ArianeTile.scala
|
||||||
|
index 8983baf..cf62daf 100644
|
||||||
|
--- a/src/main/scala/ArianeTile.scala
|
||||||
|
+++ b/src/main/scala/ArianeTile.scala
|
||||||
|
@@ -43,6 +43,7 @@ case class ArianeCoreParams(
|
||||||
|
val useVM: Boolean = true
|
||||||
|
val useUser: Boolean = true
|
||||||
|
val useSupervisor: Boolean = false
|
||||||
|
+ val useHype: Boolean = false
|
||||||
|
val useDebug: Boolean = true
|
||||||
|
val useAtomics: Boolean = true
|
||||||
|
val useAtomicsOnlyForIO: Boolean = false // copied from Rocket
|
||||||
|
--
|
||||||
|
2.25.1
|
||||||
|
|
||||||
|
|
@ -0,0 +1,25 @@
|
||||||
|
From 02157c1ee9fbe863ad47d005b66f428faeefb512 Mon Sep 17 00:00:00 2001
|
||||||
|
From: Jose Martins <josemartins90@gmail.com>
|
||||||
|
Date: Mon, 2 Nov 2020 10:16:33 +0000
|
||||||
|
Subject: [PATCH] add usehyp option
|
||||||
|
|
||||||
|
Signed-off-by: Jose Martins <josemartins90@gmail.com>
|
||||||
|
---
|
||||||
|
src/main/scala/common/parameters.scala | 1 +
|
||||||
|
1 file changed, 1 insertion(+)
|
||||||
|
|
||||||
|
diff --git a/src/main/scala/common/parameters.scala b/src/main/scala/common/parameters.scala
|
||||||
|
index 1a0c25fd..51f1b11c 100644
|
||||||
|
--- a/src/main/scala/common/parameters.scala
|
||||||
|
+++ b/src/main/scala/common/parameters.scala
|
||||||
|
@@ -85,6 +85,7 @@ case class BoomCoreParams(
|
||||||
|
useDebug: Boolean = true,
|
||||||
|
useUser: Boolean = true,
|
||||||
|
useSupervisor: Boolean = false,
|
||||||
|
+ useHype: Boolean = false,
|
||||||
|
useVM: Boolean = true,
|
||||||
|
useSCIE: Boolean = false,
|
||||||
|
useRVE: Boolean = false,
|
||||||
|
--
|
||||||
|
2.25.1
|
||||||
|
|
||||||
|
|
@ -0,0 +1,19 @@
|
||||||
|
source $::env(BAO_DEMOS)/platforms/$::env(PLATFORM)/scripts/env.tcl
|
||||||
|
|
||||||
|
open_project $project_dir/$project_name.xpr
|
||||||
|
|
||||||
|
# Launch synthesis
|
||||||
|
reset_run synth_1
|
||||||
|
launch_runs synth_1 -jobs $num_cpus
|
||||||
|
wait_on_run synth_1
|
||||||
|
|
||||||
|
# Launch implementation and generate bitstream
|
||||||
|
|
||||||
|
launch_runs impl_1 -jobs $num_cpus -to_step write_bitstream
|
||||||
|
wait_on_run impl_1
|
||||||
|
|
||||||
|
# Export bitstream to fpga/hw dir
|
||||||
|
write_hw_platform -fixed -include_bit -force -file $output_xsa
|
||||||
|
hsi::open_hw_design $output_xsa
|
||||||
|
|
||||||
|
close_project
|
||||||
|
|
@ -0,0 +1,70 @@
|
||||||
|
source $::env(BAO_DEMOS)/platforms/$::env(PLATFORM)/scripts/env.tcl
|
||||||
|
|
||||||
|
# Create SoC
|
||||||
|
create_project $project_name $project_dir -part $part
|
||||||
|
set_property board_part $board_part [current_project]
|
||||||
|
set_property ip_repo_paths $ip_repo [current_project]
|
||||||
|
update_ip_catalog
|
||||||
|
|
||||||
|
#Create Design
|
||||||
|
create_bd_design "rocket_design"
|
||||||
|
update_compile_order -fileset sources_1
|
||||||
|
|
||||||
|
proc creat_design_zynqmp {} {
|
||||||
|
|
||||||
|
# Create Zynq PS and Config
|
||||||
|
create_bd_cell -type ip -vlnv xilinx.com:ip:zynq_ultra_ps_e:3.3 zynq_ultra_ps_e_0
|
||||||
|
apply_bd_automation -rule xilinx.com:bd_rule:zynq_ultra_ps_e -config {apply_board_preset "1" } [get_bd_cells zynq_ultra_ps_e_0]
|
||||||
|
set_property -dict [list CONFIG.PSU__USE__M_AXI_GP0 {0} CONFIG.PSU__USE__M_AXI_GP1 {0} CONFIG.PSU__USE__S_AXI_GP2 {1} CONFIG.PSU__SAXIGP2__DATA_WIDTH {64} CONFIG.PSU__USE__S_AXI_GP6 {1} CONFIG.PSU__SAXIGP6__DATA_WIDTH {64}] [get_bd_cells zynq_ultra_ps_e_0]
|
||||||
|
set_property -dict [list CONFIG.PSU__IRQ_P2F_UART0__INT {1} CONFIG.PSU__IRQ_P2F_UART1__INT {1}] [get_bd_cells zynq_ultra_ps_e_0]
|
||||||
|
|
||||||
|
# Add AXI interconnects for MMIO and MEM
|
||||||
|
create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_0
|
||||||
|
set_property -dict [list CONFIG.NUM_MI {1}] [get_bd_cells axi_interconnect_0]
|
||||||
|
create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_1
|
||||||
|
set_property -dict [list CONFIG.NUM_MI {1}] [get_bd_cells axi_interconnect_1]
|
||||||
|
|
||||||
|
# Add rocket ip
|
||||||
|
create_bd_cell -type ip -vlnv user.org:user:rocket_top:1.0 rocket_0
|
||||||
|
|
||||||
|
# Add concat ip for uart interrupt concatenation
|
||||||
|
create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_0
|
||||||
|
|
||||||
|
# Connect all elements
|
||||||
|
connect_bd_intf_net [get_bd_intf_pins rocket_0/mem_axi] -boundary_type upper [get_bd_intf_pins axi_interconnect_0/S00_AXI]
|
||||||
|
connect_bd_intf_net [get_bd_intf_pins rocket_0/mmio_axi] -boundary_type upper [get_bd_intf_pins axi_interconnect_1/S00_AXI]
|
||||||
|
connect_bd_intf_net -boundary_type upper [get_bd_intf_pins axi_interconnect_0/M00_AXI] [get_bd_intf_pins zynq_ultra_ps_e_0/S_AXI_HP0_FPD]
|
||||||
|
connect_bd_intf_net -boundary_type upper [get_bd_intf_pins axi_interconnect_1/M00_AXI] [get_bd_intf_pins zynq_ultra_ps_e_0/S_AXI_LPD]
|
||||||
|
connect_bd_net [get_bd_pins xlconcat_0/dout] [get_bd_pins rocket_0/interrupts]
|
||||||
|
connect_bd_net [get_bd_pins zynq_ultra_ps_e_0/ps_pl_irq_uart0] [get_bd_pins xlconcat_0/In0]
|
||||||
|
connect_bd_net [get_bd_pins zynq_ultra_ps_e_0/ps_pl_irq_uart1] [get_bd_pins xlconcat_0/In1]
|
||||||
|
apply_bd_automation -rule xilinx.com:bd_rule:clkrst -config { Clk {/zynq_ultra_ps_e_0/pl_clk0 (100 MHz)} Freq {100} Ref_Clk0 {} Ref_Clk1 {} Ref_Clk2 {}} [get_bd_pins axi_interconnect_0/ACLK]
|
||||||
|
apply_bd_automation -rule xilinx.com:bd_rule:clkrst -config { Clk {/zynq_ultra_ps_e_0/pl_clk0 (100 MHz)} Freq {100} Ref_Clk0 {} Ref_Clk1 {} Ref_Clk2 {}} [get_bd_pins axi_interconnect_0/M00_ACLK]
|
||||||
|
apply_bd_automation -rule xilinx.com:bd_rule:clkrst -config { Clk {/zynq_ultra_ps_e_0/pl_clk0 (100 MHz)} Freq {100} Ref_Clk0 {} Ref_Clk1 {} Ref_Clk2 {}} [get_bd_pins axi_interconnect_0/S00_ACLK]
|
||||||
|
apply_bd_automation -rule xilinx.com:bd_rule:clkrst -config { Clk {/zynq_ultra_ps_e_0/pl_clk0 (100 MHz)} Freq {100} Ref_Clk0 {} Ref_Clk1 {} Ref_Clk2 {}} [get_bd_pins axi_interconnect_1/ACLK]
|
||||||
|
apply_bd_automation -rule xilinx.com:bd_rule:clkrst -config { Clk {/zynq_ultra_ps_e_0/pl_clk0 (100 MHz)} Freq {100} Ref_Clk0 {} Ref_Clk1 {} Ref_Clk2 {}} [get_bd_pins axi_interconnect_1/M00_ACLK]
|
||||||
|
apply_bd_automation -rule xilinx.com:bd_rule:clkrst -config { Clk {/zynq_ultra_ps_e_0/pl_clk0 (100 MHz)} Freq {100} Ref_Clk0 {} Ref_Clk1 {} Ref_Clk2 {}} [get_bd_pins axi_interconnect_1/S00_ACLK]
|
||||||
|
apply_bd_automation -rule xilinx.com:bd_rule:clkrst -config { Clk {/zynq_ultra_ps_e_0/pl_clk0 (100 MHz)} Freq {100} Ref_Clk0 {} Ref_Clk1 {} Ref_Clk2 {}} [get_bd_pins rocket_0/mem_axi_aclk]
|
||||||
|
apply_bd_automation -rule xilinx.com:bd_rule:clkrst -config { Clk {/zynq_ultra_ps_e_0/pl_clk0 (100 MHz)} Freq {100} Ref_Clk0 {} Ref_Clk1 {} Ref_Clk2 {}} [get_bd_pins rocket_0/mmio_axi_aclk]
|
||||||
|
|
||||||
|
# Create address segments
|
||||||
|
assign_bd_address -offset 0x40000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces rocket_0/mem_axi] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP2/HP0_DDR_LOW] -force
|
||||||
|
assign_bd_address -offset 0xFF000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces rocket_0/mmio_axi] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP6/LPD_LPS_OCM] -force
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
switch -regexp $board {
|
||||||
|
zcu(.*) {
|
||||||
|
creat_design_zynqmp
|
||||||
|
}
|
||||||
|
default {
|
||||||
|
puts "Platform $board not supported!\n"
|
||||||
|
exit -1
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
# Make wrapper and generate output products
|
||||||
|
make_wrapper -files [get_files $project_dir/$project_name.srcs/sources_1/bd/rocket_design/rocket_design.bd] -top
|
||||||
|
add_files -norecurse $project_dir/$project_name.srcs/sources_1/bd/rocket_design/hdl/rocket_design_wrapper.v
|
||||||
|
generate_target all [get_files $project_dir/$project_name.srcs/sources_1/bd/rocket_design/rocket_design.bd]
|
||||||
|
close_project
|
||||||
|
|
@ -0,0 +1,28 @@
|
||||||
|
source $::env(BAO_DEMOS)/platforms/$::env(PLATFORM)/scripts/env.tcl
|
||||||
|
|
||||||
|
set src_dir $::env(BAO_DEMOS)/platforms/$::env(PLATFORM)/srcs/
|
||||||
|
set rocket_config freechips.rocketchip.system.TestHarness.$::env(BAO_DEMOS_ROCKET_CONFIG)
|
||||||
|
set generated_srcs $::env(BAO_DEMOS_CHIPYARD)/sims/vcs/generated-src
|
||||||
|
|
||||||
|
create_project $ip_name $ip_repo -part $part
|
||||||
|
set_property board_part $board_part [current_project]
|
||||||
|
import_files $src_dir/rocket_top.v
|
||||||
|
import_files $generated_srcs/$rocket_config/$rocket_config.top.v
|
||||||
|
import_files $generated_srcs/$rocket_config/$rocket_config.top.mems.v
|
||||||
|
import_files $generated_srcs/$rocket_config/plusarg_reader.v
|
||||||
|
set_property top rocket_top [get_filesets sim_1]
|
||||||
|
set_property top_lib xil_defaultlib [get_filesets sim_1]
|
||||||
|
update_compile_order -fileset sources_1
|
||||||
|
ipx::package_project -root_dir $ip_repo -vendor user.org -library user -taxonomy /UserIP
|
||||||
|
set_property core_revision 2 [ipx::current_core]
|
||||||
|
set_property value 64 [ipx::get_user_parameters C_MMIO_AXI_ADDR_WIDTH -of_objects [ipx::current_core]]
|
||||||
|
set_property value 64 [ipx::get_hdl_parameters C_MMIO_AXI_ADDR_WIDTH -of_objects [ipx::current_core]]
|
||||||
|
set_property value 64 [ipx::get_user_parameters C_MEM_AXI_ADDR_WIDTH -of_objects [ipx::current_core]]
|
||||||
|
set_property value 64 [ipx::get_hdl_parameters C_MEM_AXI_ADDR_WIDTH -of_objects [ipx::current_core]]
|
||||||
|
ipx::create_xgui_files [ipx::current_core]
|
||||||
|
ipx::update_checksums [ipx::current_core]
|
||||||
|
ipx::check_integrity [ipx::current_core]
|
||||||
|
ipx::save_core [ipx::current_core]
|
||||||
|
set_property ip_repo_paths $ip_repo [current_project]
|
||||||
|
update_ip_catalog
|
||||||
|
close_project
|
||||||
|
|
@ -0,0 +1,31 @@
|
||||||
|
source $::env(BAO_DEMOS)/platforms/$::env(PLATFORM)/scripts/env.tcl
|
||||||
|
|
||||||
|
connect
|
||||||
|
targets -set -filter {name =~ "PSU"}
|
||||||
|
|
||||||
|
source $output_psu_init
|
||||||
|
psu_init
|
||||||
|
after 1000
|
||||||
|
psu_ps_pl_isolation_removal
|
||||||
|
after 1000
|
||||||
|
psu_ps_pl_reset_config
|
||||||
|
|
||||||
|
set file [lindex $argv 0]
|
||||||
|
|
||||||
|
switch -regexp $board {
|
||||||
|
zcu(.*) {
|
||||||
|
set addr 0x40000000
|
||||||
|
}
|
||||||
|
default {
|
||||||
|
puts "Platform not supported!\n"
|
||||||
|
exit -1
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
puts "loading $file to $addr"
|
||||||
|
dow -data $file $addr
|
||||||
|
|
||||||
|
puts "flashing bitstream $output_bit"
|
||||||
|
fpga -f $output_bit
|
||||||
|
|
||||||
|
disconnect
|
||||||
|
|
@ -0,0 +1,21 @@
|
||||||
|
set board [lindex [split $::env(PLATFORM) -] end]
|
||||||
|
set build_dir $::env(BAO_DEMOS_WRKDIR_PLAT)
|
||||||
|
set ip_repo $build_dir/rocket_ip
|
||||||
|
set ip_name rocket_ip
|
||||||
|
set project_name rocket_system_$board
|
||||||
|
set project_dir $build_dir/$project_name
|
||||||
|
set num_cpus $::env(VIVADO_CORES)
|
||||||
|
set output_xsa $build_dir/$project_name/$project_name.xsa
|
||||||
|
set output_bit $build_dir/$project_name/$project_name.bit
|
||||||
|
set output_psu_init $build_dir/$project_name/psu_init.tcl
|
||||||
|
|
||||||
|
switch $board {
|
||||||
|
zcu104 {
|
||||||
|
set part xczu7ev-ffvc1156-2-e
|
||||||
|
set board_part xilinx.com:zcu104:part0:1.1
|
||||||
|
}
|
||||||
|
default {
|
||||||
|
puts "Platform not supported!\n"
|
||||||
|
exit -1
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,219 @@
|
||||||
|
`timescale 1 ns / 1 ps
|
||||||
|
|
||||||
|
module rocket_top #
|
||||||
|
(
|
||||||
|
// Users to add parameters here
|
||||||
|
|
||||||
|
// User parameters ends
|
||||||
|
// Do not modify the parameters beyond this line
|
||||||
|
|
||||||
|
|
||||||
|
// Parameters of Axi Master Bus Interface MMIO_AXI
|
||||||
|
parameter integer C_MMIO_AXI_ID_WIDTH = 4,
|
||||||
|
parameter integer C_MMIO_AXI_ADDR_WIDTH = 32,
|
||||||
|
parameter integer C_MMIO_AXI_DATA_WIDTH = 64,
|
||||||
|
parameter integer C_MMIO_AXI_AWUSER_WIDTH = 0,
|
||||||
|
parameter integer C_MMIO_AXI_ARUSER_WIDTH = 0,
|
||||||
|
parameter integer C_MMIO_AXI_WUSER_WIDTH = 0,
|
||||||
|
parameter integer C_MMIO_AXI_RUSER_WIDTH = 0,
|
||||||
|
parameter integer C_MMIO_AXI_BUSER_WIDTH = 0,
|
||||||
|
|
||||||
|
// Parameters of Axi Master Bus Interface MEM_AXI
|
||||||
|
parameter integer C_MEM_AXI_ID_WIDTH = 4,
|
||||||
|
parameter integer C_MEM_AXI_ADDR_WIDTH = 32,
|
||||||
|
parameter integer C_MEM_AXI_DATA_WIDTH = 64,
|
||||||
|
parameter integer C_MEM_AXI_AWUSER_WIDTH = 0,
|
||||||
|
parameter integer C_MEM_AXI_ARUSER_WIDTH = 0,
|
||||||
|
parameter integer C_MEM_AXI_WUSER_WIDTH = 0,
|
||||||
|
parameter integer C_MEM_AXI_RUSER_WIDTH = 0,
|
||||||
|
parameter integer C_MEM_AXI_BUSER_WIDTH = 0
|
||||||
|
)
|
||||||
|
(
|
||||||
|
// Users to add ports here
|
||||||
|
input wire clock,
|
||||||
|
input wire reset,
|
||||||
|
|
||||||
|
// User ports ends
|
||||||
|
// Do not modify the ports beyond this line
|
||||||
|
|
||||||
|
|
||||||
|
// Ports of Axi Master Bus Interface MMIO_AXI
|
||||||
|
input wire mmio_axi_aclk,
|
||||||
|
input wire mmio_axi_aresetn,
|
||||||
|
output wire [C_MMIO_AXI_ID_WIDTH-1 : 0] mmio_axi_awid,
|
||||||
|
output wire [C_MMIO_AXI_ADDR_WIDTH-1 : 0] mmio_axi_awaddr,
|
||||||
|
output wire [7 : 0] mmio_axi_awlen,
|
||||||
|
output wire [2 : 0] mmio_axi_awsize,
|
||||||
|
output wire [1 : 0] mmio_axi_awburst,
|
||||||
|
output wire mmio_axi_awlock,
|
||||||
|
output wire [3 : 0] mmio_axi_awcache,
|
||||||
|
output wire [2 : 0] mmio_axi_awprot,
|
||||||
|
output wire [3 : 0] mmio_axi_awqos,
|
||||||
|
output wire [C_MMIO_AXI_AWUSER_WIDTH-1 : 0] mmio_axi_awuser,
|
||||||
|
output wire mmio_axi_awvalid,
|
||||||
|
input wire mmio_axi_awready,
|
||||||
|
output wire [C_MMIO_AXI_DATA_WIDTH-1 : 0] mmio_axi_wdata,
|
||||||
|
output wire [C_MMIO_AXI_DATA_WIDTH/8-1 : 0] mmio_axi_wstrb,
|
||||||
|
output wire mmio_axi_wlast,
|
||||||
|
output wire [C_MMIO_AXI_WUSER_WIDTH-1 : 0] mmio_axi_wuser,
|
||||||
|
output wire mmio_axi_wvalid,
|
||||||
|
input wire mmio_axi_wready,
|
||||||
|
input wire [C_MMIO_AXI_ID_WIDTH-1 : 0] mmio_axi_bid,
|
||||||
|
input wire [1 : 0] mmio_axi_bresp,
|
||||||
|
input wire [C_MMIO_AXI_BUSER_WIDTH-1 : 0] mmio_axi_buser,
|
||||||
|
input wire mmio_axi_bvalid,
|
||||||
|
output wire mmio_axi_bready,
|
||||||
|
output wire [C_MMIO_AXI_ID_WIDTH-1 : 0] mmio_axi_arid,
|
||||||
|
output wire [C_MMIO_AXI_ADDR_WIDTH-1 : 0] mmio_axi_araddr,
|
||||||
|
output wire [7 : 0] mmio_axi_arlen,
|
||||||
|
output wire [2 : 0] mmio_axi_arsize,
|
||||||
|
output wire [1 : 0] mmio_axi_arburst,
|
||||||
|
output wire mmio_axi_arlock,
|
||||||
|
output wire [3 : 0] mmio_axi_arcache,
|
||||||
|
output wire [2 : 0] mmio_axi_arprot,
|
||||||
|
output wire [3 : 0] mmio_axi_arqos,
|
||||||
|
output wire [C_MMIO_AXI_ARUSER_WIDTH-1 : 0] mmio_axi_aruser,
|
||||||
|
output wire mmio_axi_arvalid,
|
||||||
|
input wire mmio_axi_arready,
|
||||||
|
input wire [C_MMIO_AXI_ID_WIDTH-1 : 0] mmio_axi_rid,
|
||||||
|
input wire [C_MMIO_AXI_DATA_WIDTH-1 : 0] mmio_axi_rdata,
|
||||||
|
input wire [1 : 0] mmio_axi_rresp,
|
||||||
|
input wire mmio_axi_rlast,
|
||||||
|
input wire [C_MMIO_AXI_RUSER_WIDTH-1 : 0] mmio_axi_ruser,
|
||||||
|
input wire mmio_axi_rvalid,
|
||||||
|
output wire mmio_axi_rready,
|
||||||
|
|
||||||
|
// Ports of Axi Master Bus Interface MEM_AXI
|
||||||
|
input wire mem_axi_aclk,
|
||||||
|
input wire mem_axi_aresetn,
|
||||||
|
output wire [C_MEM_AXI_ID_WIDTH-1 : 0] mem_axi_awid,
|
||||||
|
output wire [C_MEM_AXI_ADDR_WIDTH-1 : 0] mem_axi_awaddr,
|
||||||
|
output wire [7 : 0] mem_axi_awlen,
|
||||||
|
output wire [2 : 0] mem_axi_awsize,
|
||||||
|
output wire [1 : 0] mem_axi_awburst,
|
||||||
|
output wire mem_axi_awlock,
|
||||||
|
output wire [3 : 0] mem_axi_awcache,
|
||||||
|
output wire [2 : 0] mem_axi_awprot,
|
||||||
|
output wire [3 : 0] mem_axi_awqos,
|
||||||
|
output wire [C_MEM_AXI_AWUSER_WIDTH-1 : 0] mem_axi_awuser,
|
||||||
|
output wire mem_axi_awvalid,
|
||||||
|
input wire mem_axi_awready,
|
||||||
|
output wire [C_MEM_AXI_DATA_WIDTH-1 : 0] mem_axi_wdata,
|
||||||
|
output wire [C_MEM_AXI_DATA_WIDTH/8-1 : 0] mem_axi_wstrb,
|
||||||
|
output wire mem_axi_wlast,
|
||||||
|
output wire [C_MEM_AXI_WUSER_WIDTH-1 : 0] mem_axi_wuser,
|
||||||
|
output wire mem_axi_wvalid,
|
||||||
|
input wire mem_axi_wready,
|
||||||
|
input wire [C_MEM_AXI_ID_WIDTH-1 : 0] mem_axi_bid,
|
||||||
|
input wire [1 : 0] mem_axi_bresp,
|
||||||
|
input wire [C_MEM_AXI_BUSER_WIDTH-1 : 0] mem_axi_buser,
|
||||||
|
input wire mem_axi_bvalid,
|
||||||
|
output wire mem_axi_bready,
|
||||||
|
output wire [C_MEM_AXI_ID_WIDTH-1 : 0] mem_axi_arid,
|
||||||
|
output wire [C_MEM_AXI_ADDR_WIDTH-1 : 0] mem_axi_araddr,
|
||||||
|
output wire [7 : 0] mem_axi_arlen,
|
||||||
|
output wire [2 : 0] mem_axi_arsize,
|
||||||
|
output wire [1 : 0] mem_axi_arburst,
|
||||||
|
output wire mem_axi_arlock,
|
||||||
|
output wire [3 : 0] mem_axi_arcache,
|
||||||
|
output wire [2 : 0] mem_axi_arprot,
|
||||||
|
output wire [3 : 0] mem_axi_arqos,
|
||||||
|
output wire [C_MEM_AXI_ARUSER_WIDTH-1 : 0] mem_axi_aruser,
|
||||||
|
output wire mem_axi_arvalid,
|
||||||
|
input wire mem_axi_arready,
|
||||||
|
input wire [C_MEM_AXI_ID_WIDTH-1 : 0] mem_axi_rid,
|
||||||
|
input wire [C_MEM_AXI_DATA_WIDTH-1 : 0] mem_axi_rdata,
|
||||||
|
input wire [1 : 0] mem_axi_rresp,
|
||||||
|
input wire mem_axi_rlast,
|
||||||
|
input wire [C_MEM_AXI_RUSER_WIDTH-1 : 0] mem_axi_ruser,
|
||||||
|
input wire mem_axi_rvalid,
|
||||||
|
output wire mem_axi_rready,
|
||||||
|
input wire [1:0] interrupts
|
||||||
|
);
|
||||||
|
wire temp = !reset;
|
||||||
|
|
||||||
|
ExampleRocketSystem ldut ( // @[TestHarness.scala 17:19:freechips.rocketchip.system.MyConfig.fir@114013.4]
|
||||||
|
.clock(clock),
|
||||||
|
.reset(temp),
|
||||||
|
.mem_axi4_0_aw_ready(mem_axi_awready),
|
||||||
|
.mem_axi4_0_aw_valid(mem_axi_awvalid),
|
||||||
|
.mem_axi4_0_aw_bits_id(mem_axi_awid),
|
||||||
|
.mem_axi4_0_aw_bits_addr(mem_axi_awaddr),
|
||||||
|
.mem_axi4_0_aw_bits_len(mem_axi_awlen),
|
||||||
|
.mem_axi4_0_aw_bits_size(mem_axi_awsize),
|
||||||
|
.mem_axi4_0_aw_bits_burst(mem_axi_awburst),
|
||||||
|
.mem_axi4_0_aw_bits_lock(mem_axi_awlock),
|
||||||
|
.mem_axi4_0_aw_bits_cache(mem_axi_awcache),
|
||||||
|
.mem_axi4_0_aw_bits_prot(mem_axi_awprot),
|
||||||
|
.mem_axi4_0_aw_bits_qos(mem_axi_awqos),
|
||||||
|
.mem_axi4_0_w_ready(mem_axi_wready),
|
||||||
|
.mem_axi4_0_w_valid(mem_axi_wvalid),
|
||||||
|
.mem_axi4_0_w_bits_data(mem_axi_wdata),
|
||||||
|
.mem_axi4_0_w_bits_strb(mem_axi_wstrb),
|
||||||
|
.mem_axi4_0_w_bits_last(mem_axi_wlast),
|
||||||
|
.mem_axi4_0_b_ready(mem_axi_bready),
|
||||||
|
.mem_axi4_0_b_valid(mem_axi_bvalid),
|
||||||
|
.mem_axi4_0_b_bits_id(mem_axi_bid),
|
||||||
|
.mem_axi4_0_b_bits_resp(mem_axi_bresp),
|
||||||
|
.mem_axi4_0_ar_ready(mem_axi_arready),
|
||||||
|
.mem_axi4_0_ar_valid(mem_axi_arvalid),
|
||||||
|
.mem_axi4_0_ar_bits_id(mem_axi_arid),
|
||||||
|
.mem_axi4_0_ar_bits_addr(mem_axi_araddr),
|
||||||
|
.mem_axi4_0_ar_bits_len(mem_axi_arlen),
|
||||||
|
.mem_axi4_0_ar_bits_size(mem_axi_arsize),
|
||||||
|
.mem_axi4_0_ar_bits_burst(mem_axi_arburst),
|
||||||
|
.mem_axi4_0_ar_bits_lock(mem_axi_arlock),
|
||||||
|
.mem_axi4_0_ar_bits_cache(mem_axi_arcache),
|
||||||
|
.mem_axi4_0_ar_bits_prot(mem_axi_arprot),
|
||||||
|
.mem_axi4_0_ar_bits_qos(mem_axi_arqos),
|
||||||
|
.mem_axi4_0_r_ready(mem_axi_rready),
|
||||||
|
.mem_axi4_0_r_valid(mem_axi_rvalid),
|
||||||
|
.mem_axi4_0_r_bits_id(mem_axi_rid),
|
||||||
|
.mem_axi4_0_r_bits_data(mem_axi_rdata),
|
||||||
|
.mem_axi4_0_r_bits_resp(mem_axi_rresp),
|
||||||
|
.mem_axi4_0_r_bits_last(mem_axi_rlast),
|
||||||
|
.mmio_axi4_0_aw_ready(mmio_axi_awready),
|
||||||
|
.mmio_axi4_0_aw_valid(mmio_axi_awvalid),
|
||||||
|
.mmio_axi4_0_aw_bits_id(mmio_axi_awid),
|
||||||
|
.mmio_axi4_0_aw_bits_addr(mmio_axi_awaddr),
|
||||||
|
.mmio_axi4_0_aw_bits_len(mmio_axi_awlen),
|
||||||
|
.mmio_axi4_0_aw_bits_size(mmio_axi_awsize),
|
||||||
|
.mmio_axi4_0_aw_bits_burst(mmio_axi_awburst),
|
||||||
|
.mmio_axi4_0_aw_bits_lock(mmio_axi_awlock),
|
||||||
|
.mmio_axi4_0_aw_bits_cache(mmio_axi_awcache),
|
||||||
|
.mmio_axi4_0_aw_bits_prot(mmio_axi_awprot),
|
||||||
|
.mmio_axi4_0_aw_bits_qos(mmio_axi_awqos),
|
||||||
|
.mmio_axi4_0_w_ready(mmio_axi_wready),
|
||||||
|
.mmio_axi4_0_w_valid(mmio_axi_wvalid),
|
||||||
|
.mmio_axi4_0_w_bits_data(mmio_axi_wdata),
|
||||||
|
.mmio_axi4_0_w_bits_strb(mmio_axi_wstrb),
|
||||||
|
.mmio_axi4_0_w_bits_last(mmio_axi_wlast),
|
||||||
|
.mmio_axi4_0_b_ready(mmio_axi_bready),
|
||||||
|
.mmio_axi4_0_b_valid(mmio_axi_bvalid),
|
||||||
|
.mmio_axi4_0_b_bits_id(mmio_axi_bid),
|
||||||
|
.mmio_axi4_0_b_bits_resp(mmio_axi_bresp),
|
||||||
|
.mmio_axi4_0_ar_ready(mmio_axi_arready),
|
||||||
|
.mmio_axi4_0_ar_valid(mmio_axi_arvalid),
|
||||||
|
.mmio_axi4_0_ar_bits_id(mmio_axi_arid),
|
||||||
|
.mmio_axi4_0_ar_bits_addr(mmio_axi_araddr),
|
||||||
|
.mmio_axi4_0_ar_bits_len(mmio_axi_arlen),
|
||||||
|
.mmio_axi4_0_ar_bits_size(mmio_axi_arsize),
|
||||||
|
.mmio_axi4_0_ar_bits_burst(mmio_axi_arburst),
|
||||||
|
.mmio_axi4_0_ar_bits_lock(mmio_axi_arlock),
|
||||||
|
.mmio_axi4_0_ar_bits_cache(mmio_axi_arcache),
|
||||||
|
.mmio_axi4_0_ar_bits_prot(mmio_axi_arprot),
|
||||||
|
.mmio_axi4_0_ar_bits_qos(mmio_axi_arqos),
|
||||||
|
.mmio_axi4_0_r_ready(mmio_axi_rready),
|
||||||
|
.mmio_axi4_0_r_valid(mmio_axi_rvalid),
|
||||||
|
.mmio_axi4_0_r_bits_id(mmio_axi_rid),
|
||||||
|
.mmio_axi4_0_r_bits_data(mmio_axi_rdata),
|
||||||
|
.mmio_axi4_0_r_bits_resp(mmio_axi_rresp),
|
||||||
|
.mmio_axi4_0_r_bits_last(mmio_axi_rlast),
|
||||||
|
.interrupts(interrupts)
|
||||||
|
);
|
||||||
|
|
||||||
|
// Add user logic here
|
||||||
|
|
||||||
|
// User logic ends
|
||||||
|
|
||||||
|
endmodule
|
||||||
|
|
@ -0,0 +1 @@
|
||||||
|
rocket-fpga-common
|
||||||
Loading…
Reference in New Issue