realtek: mdio: RTL838x: move functions over to bus
The mdio bus functions are still split between ethernet and dsa driver. Before moving everthing out to a separate mdio driver we decided to collect everything in the ethernet driver with the rtmdio prefix. Take over the remaining RTL838x functions. Remark: This is more or less a copy/paste with function renaming. As there are still some consumers in the DSA driver the definitions and inclusions must be flipped. Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de> Link: https://github.com/openwrt/openwrt/pull/19484 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
This commit is contained in:
Markus Stockhausen
Hauke Mehrtens
parent
6e8042ed97
commit
a3bfb67072
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@ -29,6 +29,9 @@ extern const struct dsa_switch_ops rtl930x_switch_ops;
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extern const struct phylink_pcs_ops rtl83xx_pcs_ops;
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extern const struct phylink_pcs_ops rtl93xx_pcs_ops;
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extern int rtmdio_838x_read_phy(u32 port, u32 page, u32 reg, u32 *val);
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extern int rtmdio_838x_write_phy(u32 port, u32 page, u32 reg, u32 val);
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DEFINE_MUTEX(smi_lock);
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int rtl83xx_port_get_stp_state(struct rtl838x_switch_priv *priv, int port)
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@ -244,7 +247,7 @@ int read_phy(u32 port, u32 page, u32 reg, u32 *val)
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{
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switch (soc_info.family) {
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case RTL8380_FAMILY_ID:
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return rtl838x_read_phy(port, page, reg, val);
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return rtmdio_838x_read_phy(port, page, reg, val);
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case RTL8390_FAMILY_ID:
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return rtl839x_read_phy(port, page, reg, val);
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case RTL9300_FAMILY_ID:
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@ -260,7 +263,7 @@ int write_phy(u32 port, u32 page, u32 reg, u32 val)
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{
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switch (soc_info.family) {
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case RTL8380_FAMILY_ID:
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return rtl838x_write_phy(port, page, reg, val);
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return rtmdio_838x_write_phy(port, page, reg, val);
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case RTL8390_FAMILY_ID:
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return rtl839x_write_phy(port, page, reg, val);
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case RTL9300_FAMILY_ID:
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@ -1768,169 +1768,6 @@ irqreturn_t rtl838x_switch_irq(int irq, void *dev_id)
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return IRQ_HANDLED;
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}
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int rtl838x_smi_wait_op(int timeout)
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{
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int ret = 0;
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u32 val;
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ret = readx_poll_timeout(sw_r32, RTL838X_SMI_ACCESS_PHY_CTRL_1,
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val, !(val & 0x1), 20, timeout);
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if (ret)
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pr_err("%s: timeout\n", __func__);
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return ret;
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}
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/* Reads a register in a page from the PHY */
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int rtl838x_read_phy(u32 port, u32 page, u32 reg, u32 *val)
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{
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u32 v, park_page = 0x1f << 15;
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int err;
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if (port > 31) {
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*val = 0xffff;
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return 0;
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}
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if (page > 4095 || reg > 31)
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return -ENOTSUPP;
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mutex_lock(&smi_lock);
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err = rtl838x_smi_wait_op(100000);
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if (err)
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goto errout;
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sw_w32_mask(0xffff0000, port << 16, RTL838X_SMI_ACCESS_PHY_CTRL_2);
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v = reg << 20 | page << 3;
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sw_w32(v | park_page, RTL838X_SMI_ACCESS_PHY_CTRL_1);
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sw_w32_mask(0, 1, RTL838X_SMI_ACCESS_PHY_CTRL_1);
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err = rtl838x_smi_wait_op(100000);
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if (err)
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goto errout;
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*val = sw_r32(RTL838X_SMI_ACCESS_PHY_CTRL_2) & 0xffff;
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err = 0;
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errout:
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mutex_unlock(&smi_lock);
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return err;
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}
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/* Write to a register in a page of the PHY */
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int rtl838x_write_phy(u32 port, u32 page, u32 reg, u32 val)
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{
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u32 v, park_page = 0x1f << 15;
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int err;
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val &= 0xffff;
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if (port > 31 || page > 4095 || reg > 31)
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return -ENOTSUPP;
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mutex_lock(&smi_lock);
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err = rtl838x_smi_wait_op(100000);
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if (err)
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goto errout;
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sw_w32(BIT(port), RTL838X_SMI_ACCESS_PHY_CTRL_0);
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mdelay(10);
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sw_w32_mask(0xffff0000, val << 16, RTL838X_SMI_ACCESS_PHY_CTRL_2);
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v = reg << 20 | page << 3 | 0x4;
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sw_w32(v | park_page, RTL838X_SMI_ACCESS_PHY_CTRL_1);
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sw_w32_mask(0, 1, RTL838X_SMI_ACCESS_PHY_CTRL_1);
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err = rtl838x_smi_wait_op(100000);
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if (err)
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goto errout;
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err = 0;
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errout:
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mutex_unlock(&smi_lock);
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return err;
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}
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/* Read an mmd register of a PHY */
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int rtl838x_read_mmd_phy(u32 port, u32 addr, u32 reg, u32 *val)
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{
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int err;
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u32 v;
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mutex_lock(&smi_lock);
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err = rtl838x_smi_wait_op(100000);
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if (err)
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goto errout;
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sw_w32(1 << port, RTL838X_SMI_ACCESS_PHY_CTRL_0);
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mdelay(10);
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sw_w32_mask(0xffff0000, port << 16, RTL838X_SMI_ACCESS_PHY_CTRL_2);
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v = addr << 16 | reg;
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sw_w32(v, RTL838X_SMI_ACCESS_PHY_CTRL_3);
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/* mmd-access | read | cmd-start */
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v = 1 << 1 | 0 << 2 | 1;
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sw_w32(v, RTL838X_SMI_ACCESS_PHY_CTRL_1);
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err = rtl838x_smi_wait_op(100000);
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if (err)
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goto errout;
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*val = sw_r32(RTL838X_SMI_ACCESS_PHY_CTRL_2) & 0xffff;
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err = 0;
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errout:
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mutex_unlock(&smi_lock);
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return err;
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}
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/* Write to an mmd register of a PHY */
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int rtl838x_write_mmd_phy(u32 port, u32 addr, u32 reg, u32 val)
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{
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int err;
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u32 v;
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pr_debug("MMD write: port %d, dev %d, reg %d, val %x\n", port, addr, reg, val);
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val &= 0xffff;
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mutex_lock(&smi_lock);
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err = rtl838x_smi_wait_op(100000);
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if (err)
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goto errout;
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sw_w32(1 << port, RTL838X_SMI_ACCESS_PHY_CTRL_0);
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mdelay(10);
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sw_w32_mask(0xffff0000, val << 16, RTL838X_SMI_ACCESS_PHY_CTRL_2);
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sw_w32_mask(0x1f << 16, addr << 16, RTL838X_SMI_ACCESS_PHY_CTRL_3);
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sw_w32_mask(0xffff, reg, RTL838X_SMI_ACCESS_PHY_CTRL_3);
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/* mmd-access | write | cmd-start */
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v = 1 << 1 | 1 << 2 | 1;
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sw_w32(v, RTL838X_SMI_ACCESS_PHY_CTRL_1);
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err = rtl838x_smi_wait_op(100000);
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if (err)
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goto errout;
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err = 0;
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errout:
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mutex_unlock(&smi_lock);
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return err;
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}
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void rtl8380_get_version(struct rtl838x_switch_priv *priv)
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{
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u32 rw_save, info_save;
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@ -27,11 +27,6 @@ extern struct rtl83xx_soc_info soc_info;
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extern int rtl83xx_setup_tc(struct net_device *dev, enum tc_setup_type type, void *type_data);
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extern int rtl838x_read_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 *val);
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extern int rtl838x_read_phy(u32 port, u32 page, u32 reg, u32 *val);
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extern int rtl838x_write_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 val);
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extern int rtl838x_write_phy(u32 port, u32 page, u32 reg, u32 val);
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extern int rtl839x_read_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 *val);
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extern int rtl839x_read_phy(u32 port, u32 page, u32 reg, u32 *val);
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extern int rtl839x_read_sds_phy(int phy_addr, int phy_reg);
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@ -1640,6 +1635,8 @@ static int rtl838x_set_link_ksettings(struct net_device *ndev,
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* reimplemented. For now it should be sufficient.
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*/
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DEFINE_MUTEX(rtmdio_lock);
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struct rtmdio_bus_priv {
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u16 id;
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u16 family_id;
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@ -1769,6 +1766,171 @@ static int rtmdio_838x_write_sds(int addr, int regnum, u16 val)
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return 0;
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}
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/* RTL838x specific MDIO functions */
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static int rtmdio_838x_smi_wait_op(int timeout)
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{
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int ret = 0;
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u32 val;
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ret = readx_poll_timeout(sw_r32, RTL838X_SMI_ACCESS_PHY_CTRL_1,
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val, !(val & 0x1), 20, timeout);
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if (ret)
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pr_err("%s: timeout\n", __func__);
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return ret;
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}
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/* Reads a register in a page from the PHY */
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int rtmdio_838x_read_phy(u32 port, u32 page, u32 reg, u32 *val)
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{
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u32 v, park_page = 0x1f << 15;
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int err;
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if (port > 31) {
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*val = 0xffff;
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return 0;
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}
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if (page > 4095 || reg > 31)
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return -ENOTSUPP;
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mutex_lock(&rtmdio_lock);
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err = rtmdio_838x_smi_wait_op(100000);
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if (err)
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goto errout;
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sw_w32_mask(0xffff0000, port << 16, RTL838X_SMI_ACCESS_PHY_CTRL_2);
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v = reg << 20 | page << 3;
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sw_w32(v | park_page, RTL838X_SMI_ACCESS_PHY_CTRL_1);
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sw_w32_mask(0, 1, RTL838X_SMI_ACCESS_PHY_CTRL_1);
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err = rtmdio_838x_smi_wait_op(100000);
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if (err)
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goto errout;
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*val = sw_r32(RTL838X_SMI_ACCESS_PHY_CTRL_2) & 0xffff;
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err = 0;
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errout:
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mutex_unlock(&rtmdio_lock);
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return err;
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}
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/* Write to a register in a page of the PHY */
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int rtmdio_838x_write_phy(u32 port, u32 page, u32 reg, u32 val)
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{
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u32 v, park_page = 0x1f << 15;
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int err;
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val &= 0xffff;
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if (port > 31 || page > 4095 || reg > 31)
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return -ENOTSUPP;
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mutex_lock(&rtmdio_lock);
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err = rtmdio_838x_smi_wait_op(100000);
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if (err)
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goto errout;
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sw_w32(BIT(port), RTL838X_SMI_ACCESS_PHY_CTRL_0);
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mdelay(10);
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sw_w32_mask(0xffff0000, val << 16, RTL838X_SMI_ACCESS_PHY_CTRL_2);
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v = reg << 20 | page << 3 | 0x4;
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sw_w32(v | park_page, RTL838X_SMI_ACCESS_PHY_CTRL_1);
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sw_w32_mask(0, 1, RTL838X_SMI_ACCESS_PHY_CTRL_1);
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err = rtmdio_838x_smi_wait_op(100000);
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if (err)
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goto errout;
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err = 0;
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errout:
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mutex_unlock(&rtmdio_lock);
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return err;
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}
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/* Read an mmd register of a PHY */
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static int rtmdio_838x_read_mmd_phy(u32 port, u32 addr, u32 reg, u32 *val)
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{
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int err;
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u32 v;
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mutex_lock(&rtmdio_lock);
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err = rtmdio_838x_smi_wait_op(100000);
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if (err)
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goto errout;
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sw_w32(1 << port, RTL838X_SMI_ACCESS_PHY_CTRL_0);
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mdelay(10);
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sw_w32_mask(0xffff0000, port << 16, RTL838X_SMI_ACCESS_PHY_CTRL_2);
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v = addr << 16 | reg;
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sw_w32(v, RTL838X_SMI_ACCESS_PHY_CTRL_3);
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/* mmd-access | read | cmd-start */
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v = 1 << 1 | 0 << 2 | 1;
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sw_w32(v, RTL838X_SMI_ACCESS_PHY_CTRL_1);
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err = rtmdio_838x_smi_wait_op(100000);
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if (err)
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goto errout;
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*val = sw_r32(RTL838X_SMI_ACCESS_PHY_CTRL_2) & 0xffff;
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err = 0;
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errout:
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mutex_unlock(&rtmdio_lock);
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return err;
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}
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/* Write to an mmd register of a PHY */
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static int rtmdio_838x_write_mmd_phy(u32 port, u32 addr, u32 reg, u32 val)
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{
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int err;
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u32 v;
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pr_debug("MMD write: port %d, dev %d, reg %d, val %x\n", port, addr, reg, val);
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val &= 0xffff;
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mutex_lock(&rtmdio_lock);
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err = rtmdio_838x_smi_wait_op(100000);
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if (err)
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goto errout;
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sw_w32(1 << port, RTL838X_SMI_ACCESS_PHY_CTRL_0);
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mdelay(10);
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sw_w32_mask(0xffff0000, val << 16, RTL838X_SMI_ACCESS_PHY_CTRL_2);
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sw_w32_mask(0x1f << 16, addr << 16, RTL838X_SMI_ACCESS_PHY_CTRL_3);
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sw_w32_mask(0xffff, reg, RTL838X_SMI_ACCESS_PHY_CTRL_3);
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/* mmd-access | write | cmd-start */
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v = 1 << 1 | 1 << 2 | 1;
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sw_w32(v, RTL838X_SMI_ACCESS_PHY_CTRL_1);
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err = rtmdio_838x_smi_wait_op(100000);
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if (err)
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goto errout;
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err = 0;
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errout:
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mutex_unlock(&rtmdio_lock);
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return err;
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}
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/* These are the core functions of our new Realtek SoC MDIO bus. */
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static int rtmdio_read_c45(struct mii_bus *bus, int addr, int devnum, int regnum)
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@ -2215,10 +2377,10 @@ static int rtl838x_mdio_init(struct rtl838x_eth_priv *priv)
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priv->mii_bus->read = rtmdio_83xx_read;
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priv->mii_bus->write = rtmdio_83xx_write;
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priv->mii_bus->reset = rtmdio_838x_reset;
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bus_priv->read_mmd_phy = rtl838x_read_mmd_phy;
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bus_priv->write_mmd_phy = rtl838x_write_mmd_phy;
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bus_priv->read_phy = rtl838x_read_phy;
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bus_priv->write_phy = rtl838x_write_phy;
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bus_priv->read_mmd_phy = rtmdio_838x_read_mmd_phy;
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bus_priv->write_mmd_phy = rtmdio_838x_write_mmd_phy;
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bus_priv->read_phy = rtmdio_838x_read_phy;
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bus_priv->write_phy = rtmdio_838x_write_phy;
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bus_priv->cpu_port = RTL838X_CPU_PORT;
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bus_priv->rawpage = 0xfff;
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break;
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@ -453,4 +453,7 @@ int phy_package_write_paged(struct phy_device *phydev, int page, u32 regnum, u16
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int phy_port_read_paged(struct phy_device *phydev, int port, int page, u32 regnum);
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int phy_port_write_paged(struct phy_device *phydev, int port, int page, u32 regnum, u16 val);
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int rtmdio_838x_read_phy(u32 port, u32 page, u32 reg, u32 *val);
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int rtmdio_838x_write_phy(u32 port, u32 page, u32 reg, u32 val);
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#endif /* _RTL838X_ETH_H */
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