anolis: sw64: cpufreq: optimize the granularity of cpufreq
ANBZ: #4688 Optimize the granularity of cpufreq according to the actual clock domain to improve system energy efficiency. Signed-off-by: Jing Li <jingli@wxiat.com> Reviewed-by: He Sheng <hesheng@wxiat.com> Signed-off-by: Gu Zitao <guzitao@wxiat.com> Reviewed-by: Min Li <gumi@linux.alibaba.com> Link: https://gitee.com/anolis/cloud-kernel/pulls/5445
This commit is contained in:
Jing Li
小龙
parent
fdfde0c984
commit
4e55364061
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@ -6,6 +6,9 @@
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#include <linux/kernel.h>
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#include <linux/cacheinfo.h>
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#define KHZ (1000UL)
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#define MHZ (1000UL * 1000UL)
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#define current_cpu_data cpu_data[smp_processor_id()]
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enum hmcall_cpuid_cmd {
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@ -47,10 +50,23 @@ extern struct cpuinfo_sw64 cpu_data[NR_CPUS];
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extern cpumask_t cpu_offline;
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extern void store_cpu_data(int cpu);
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extern unsigned long get_cpu_freq(void);
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extern void update_cpu_freq(unsigned long khz);
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extern unsigned int get_cpu_cache_size(int cpu, int level, enum cache_type type);
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extern unsigned int get_cpu_cacheline_size(int cpu, int level, enum cache_type type);
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/* Hz */
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static inline unsigned long sunway_max_cpu_freq(void)
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{
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return cpuid(GET_CPU_FREQ, 0) * MHZ;
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}
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#ifdef CONFIG_SW64_CPUFREQ
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extern unsigned long get_cpu_freq(unsigned int cpu);
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#else
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static inline unsigned long get_cpu_freq(unsigned int cpu)
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{
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return sunway_max_cpu_freq();
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}
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#endif
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#endif /* _ASM_SW64_CPU_H */
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@ -2,6 +2,7 @@
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#include <linux/cacheinfo.h>
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#include <linux/cpu.h>
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#include <linux/cpufreq.h>
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#include <linux/cpumask.h>
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#include <linux/delay.h>
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#include <linux/seq_file.h>
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@ -40,25 +41,11 @@ EXPORT_SYMBOL(cpu_data);
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cpumask_t cpu_offline = CPU_MASK_NONE;
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static unsigned long cpu_freq;
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static unsigned long cpu_info;
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static __u16 family;
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static char vendor_id[64];
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static char model_id[64];
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unsigned long get_cpu_freq(void)
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{
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if (likely(cpu_freq))
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return cpu_freq;
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return cpuid(GET_CPU_FREQ, 0) * 1000UL * 1000UL;
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}
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void update_cpu_freq(unsigned long khz)
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{
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cpu_freq = khz * 1000;
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}
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/* Move global data into per-processor storage */
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void store_cpu_data(int cpu)
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{
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@ -240,7 +227,7 @@ static int show_cpuinfo(struct seq_file *f, void *slot)
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unsigned int l3_cache_size, l3_cachline_size;
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unsigned long freq;
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freq = cpuid(GET_CPU_FREQ, 0);
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freq = sunway_max_cpu_freq() / MHZ;
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for_each_online_cpu(i) {
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l3_cache_size = get_cpu_cache_size(i, 3, CACHE_TYPE_UNIFIED);
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@ -267,7 +254,7 @@ static int show_cpuinfo(struct seq_file *f, void *slot)
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"cache size\t: %u KB\n"
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"physical id\t: %d\n"
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"bogomips\t: %lu.%02lu\n",
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get_cpu_freq() / 1000 / 1000, l3_cache_size >> 10,
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get_cpu_freq(i) / 1000 / 1000, l3_cache_size >> 10,
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cpu_topology[i].package_id,
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loops_per_jiffy / (500000/HZ),
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(loops_per_jiffy / (5000/HZ)) % 100);
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@ -312,3 +299,17 @@ bool arch_match_cpu_phys_id(int cpu, u64 phys_id)
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{
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return phys_id == cpu_physical_id(cpu);
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}
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#ifdef CONFIG_SW64_CPUFREQ
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unsigned long get_cpu_freq(unsigned int cpu)
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{
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unsigned long freq = cpufreq_quick_get(cpu);
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if (likely(freq))
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return freq * KHZ;
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return sunway_max_cpu_freq();
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}
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#endif
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@ -138,7 +138,7 @@ EXPORT_SYMBOL(screen_info);
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#ifdef CONFIG_HARDLOCKUP_DETECTOR_PERF
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u64 hw_nmi_get_sample_period(int watchdog_thresh)
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{
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return get_cpu_freq() * watchdog_thresh;
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return sunway_max_cpu_freq() * watchdog_thresh;
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}
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#endif
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@ -31,7 +31,7 @@ time_init(void)
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{
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unsigned long cycle_freq;
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cycle_freq = get_cpu_freq();
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cycle_freq = sunway_max_cpu_freq();
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pr_info("CPU Cycle frequency = %ld Hz\n", cycle_freq);
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@ -32,7 +32,7 @@ EXPORT_SYMBOL(__delay);
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void udelay(unsigned long usecs)
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{
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unsigned long loops = usecs * get_cpu_freq() / 1000000;
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unsigned long loops = usecs * get_cpu_freq(smp_processor_id()) / 1000000;
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unsigned long tmp;
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__asm__ __volatile__(
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@ -47,7 +47,7 @@ EXPORT_SYMBOL(udelay);
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void ndelay(unsigned long nsecs)
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{
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unsigned long loops = nsecs * get_cpu_freq() / 1000000000;
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unsigned long loops = nsecs * get_cpu_freq(smp_processor_id()) / 1000000000;
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unsigned long tmp;
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__asm__ __volatile__(
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@ -174,7 +174,7 @@ void __init sw64_setup_clocksource(void)
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else
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clocksource_register_khz(&clocksource_vtime, mclk_khz);
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#else
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clocksource_register_hz(&clocksource_tc, get_cpu_freq());
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clocksource_register_hz(&clocksource_tc, sunway_max_cpu_freq());
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pr_info("Setup clocksource TC, mult = %d\n", clocksource_tc.mult);
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#endif
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}
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@ -208,23 +208,13 @@ void __init setup_sched_clock(void)
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sc_shift = 7;
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step = 1UL << sc_shift;
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sc_multi = step * NSEC_PER_SEC / get_cpu_freq();
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sc_multi = step * NSEC_PER_SEC / sunway_max_cpu_freq();
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calibrate_sched_clock();
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pr_info("sched_clock: sc_multi=%llu, sc_shift=%llu\n", sc_multi, sc_shift);
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}
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#ifdef CONFIG_GENERIC_SCHED_CLOCK
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static u64 notrace read_sched_clock(void)
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{
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return (rdtc() - sc_start) >> sc_shift;
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}
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void __init sw64_sched_clock_init(void)
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{
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sched_clock_register(sched_clock_read, BITS_PER_LONG, get_cpu_freq() >> sc_shift);
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}
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#else /* !CONFIG_GENERIC_SCHED_CLOCK */
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#ifndef CONFIG_GENERIC_SCHED_CLOCK
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/*
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* scheduler clock - returns current time in nanoseconds.
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*/
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@ -428,7 +418,7 @@ void sw64_setup_timer(void)
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struct clock_event_device *swevt = &per_cpu(timer_events, cpu);
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/* min_delta ticks => 100ns */
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min_delta = get_cpu_freq()/1000/1000/10;
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min_delta = sunway_max_cpu_freq()/1000/1000/10;
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if (is_in_guest()) {
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memcpy(swevt, &vtimer_clockevent, sizeof(*swevt));
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@ -443,7 +433,7 @@ void sw64_setup_timer(void)
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}
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swevt->cpumask = cpumask_of(cpu);
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swevt->set_state_shutdown(swevt);
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clockevents_config_and_register(swevt, get_cpu_freq(), min_delta, ULONG_MAX);
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clockevents_config_and_register(swevt, sunway_max_cpu_freq(), min_delta, ULONG_MAX);
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}
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void sw64_timer_interrupt(void)
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@ -77,9 +77,6 @@ struct cpufreq_frequency_table freq_table[] = {
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FV(2850, 0),
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{0, 0, CPUFREQ_TABLE_END},
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};
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static void __init fill_freq_table(struct cpufreq_frequency_table *ft)
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{
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}
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#endif
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#ifdef CONFIG_PLATFORM_XUELANG
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@ -135,11 +132,14 @@ static void __init fill_freq_table(struct cpufreq_frequency_table *ft)
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static unsigned int sunway_get_rate(struct cpufreq_policy *policy)
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{
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int i;
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int i, node;
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u64 val;
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void __iomem *spbu_base = misc_platform_get_spbu_base(0);
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void __iomem *spbu_base;
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struct cpufreq_frequency_table *ft = policy->freq_table;
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node = per_cpu(hard_node_id, policy->cpu);
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spbu_base = misc_platform_get_spbu_base(node);
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/* PLL2 provides working frequency for core */
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val = readq(spbu_base + OFFSET_CLK_CTL) >> CORE_PLL2_CFG_SHIFT;
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val &= CORE_PLL2_CFG_MASK;
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@ -147,7 +147,7 @@ static unsigned int sunway_get_rate(struct cpufreq_policy *policy)
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for (i = 0; ft[i].frequency != CPUFREQ_TABLE_END; i++) {
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if (val == i) {
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if (ft[i].frequency == CPUFREQ_ENTRY_INVALID)
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return cpuid(GET_CPU_FREQ, 0) * 1000UL;
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return sunway_max_cpu_freq() / KHZ;
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return ft[i].frequency;
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}
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}
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@ -155,40 +155,42 @@ static unsigned int sunway_get_rate(struct cpufreq_policy *policy)
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return 0;
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}
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static int sunway_set_rate(unsigned int index)
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static int sunway_set_rate(struct cpufreq_policy *policy, unsigned int index)
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{
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int i, retry, cpu_num;
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int retry, node;
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void __iomem *spbu_base;
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cpu_num = sw64_chip->get_cpu_num();
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for (i = 0; i < cpu_num; i++) {
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spbu_base = misc_platform_get_spbu_base(i);
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node = per_cpu(hard_node_id, policy->cpu);
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spbu_base = misc_platform_get_spbu_base(node);
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/* select PLL0/PLL1 */
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writeq(CLK_LV1_SEL_PROTECT, spbu_base + OFFSET_CLU_LV1_SEL);
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/* reset PLL2 */
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writeq(CLK2_PROTECT | CORE_CLK2_RESET | CORE_CLK2_VALID, spbu_base + OFFSET_CLK_CTL);
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/* configure PLL2_CFG */
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writeq(CLK2_PROTECT | CORE_CLK2_VALID | (unsigned long)index << CORE_PLL2_CFG_SHIFT,
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spbu_base + OFFSET_CLK_CTL);
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udelay(1);
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/* reset over */
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writeq(CORE_CLK2_VALID, spbu_base + OFFSET_CLK_CTL);
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retry = 0;
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while (retry < MAX_RETRY) {
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if (readq(spbu_base + OFFSET_CLK_CTL) & CORE_CLK2_LOCK)
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break;
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retry++;
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udelay(100);
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}
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if (retry == MAX_RETRY)
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return -ETIME;
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/* configure over */
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writeq(0, spbu_base + OFFSET_CLK_CTL);
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/* select PLL2/PLL2 */
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writeq(CLK_LV1_SEL_MUXA | CLK_LV1_SEL_MUXB | CLK_LV1_SEL_PROTECT,
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spbu_base + OFFSET_CLU_LV1_SEL);
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/* select PLL0/PLL1 */
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writeq(CLK_LV1_SEL_PROTECT, spbu_base + OFFSET_CLU_LV1_SEL);
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/* reset PLL2 */
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writeq(CLK2_PROTECT | CORE_CLK2_RESET | CORE_CLK2_VALID, spbu_base + OFFSET_CLK_CTL);
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/* configure PLL2_CFG */
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writeq(CLK2_PROTECT | CORE_CLK2_VALID | (unsigned long)index << CORE_PLL2_CFG_SHIFT,
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spbu_base + OFFSET_CLK_CTL);
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udelay(1);
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/* reset over */
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writeq(CORE_CLK2_VALID, spbu_base + OFFSET_CLK_CTL);
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retry = 0;
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while (retry < MAX_RETRY) {
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if (readq(spbu_base + OFFSET_CLK_CTL) & CORE_CLK2_LOCK)
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break;
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retry++;
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udelay(100);
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}
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if (retry == MAX_RETRY)
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return -ETIME;
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/* configure over */
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writeq(0, spbu_base + OFFSET_CLK_CTL);
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/* select PLL2/PLL2 */
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writeq(CLK_LV1_SEL_MUXA | CLK_LV1_SEL_MUXB | CLK_LV1_SEL_PROTECT,
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spbu_base + OFFSET_CLU_LV1_SEL);
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return 0;
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}
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@ -205,9 +207,6 @@ static unsigned int sunway_cpufreq_get(unsigned int cpu)
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return sunway_get_rate(policy);
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}
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/*
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* Here we notify other drivers of the proposed change and the final change.
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*/
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static int sunway_cpufreq_target(struct cpufreq_policy *policy,
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unsigned int index)
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{
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@ -218,26 +217,29 @@ static int sunway_cpufreq_target(struct cpufreq_policy *policy,
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return -ENODEV;
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/* setting the cpu frequency */
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ret = sunway_set_rate(index);
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ret = sunway_set_rate(policy, index);
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if (ret)
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return ret;
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update_cpu_freq(freq_table[index].frequency);
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return 0;
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}
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static int sunway_cpufreq_init(struct cpufreq_policy *policy)
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{
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cpufreq_generic_init(policy, freq_table, 0);
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int cpu, node;
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node = per_cpu(hard_node_id, policy->cpu);
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for_each_possible_cpu(cpu) {
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if (per_cpu(hard_node_id, cpu) == node)
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cpumask_set_cpu(cpu, policy->cpus);
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}
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policy->freq_table = freq_table;
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return 0;
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}
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static int sunway_cpufreq_verify(struct cpufreq_policy_data *policy)
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{
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return cpufreq_frequency_table_verify(policy, freq_table);
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}
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static int sunway_cpufreq_exit(struct cpufreq_policy *policy)
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{
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return 0;
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@ -251,7 +253,7 @@ static struct cpufreq_driver sunway_cpufreq_driver = {
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.name = "sunway-cpufreq",
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.flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK,
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.init = sunway_cpufreq_init,
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.verify = sunway_cpufreq_verify,
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.verify = cpufreq_generic_frequency_table_verify,
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.target_index = sunway_cpufreq_target,
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.get = sunway_cpufreq_get,
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.exit = sunway_cpufreq_exit,
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@ -261,14 +263,17 @@ static struct cpufreq_driver sunway_cpufreq_driver = {
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static int __init cpufreq_init(void)
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{
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int i, ret;
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unsigned long max_rate = get_cpu_freq() / 1000;
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unsigned long max_rate = sunway_max_cpu_freq() / KHZ; /* KHz */
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if (!is_in_host()) {
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pr_warn("cpufreq driver of Sunway platforms is only supported in host mode\n");
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return -ENODEV;
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}
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#ifdef CONFIG_PLATFORM_XUELANG
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fill_freq_table(freq_table);
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#endif
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for (i = 0; freq_table[i].frequency != CPUFREQ_TABLE_END; i++) {
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if (max_rate == freq_table[i].frequency)
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freq_table[i+1].frequency = CPUFREQ_TABLE_END;
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