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iommu/vt-d: Avoid unnecessary global DMA cache invalidation 

commit 6ad931a232 upstream

ANBZ: #8786

Some VT-d hardware implementations invalidate all DMA remapping hardware
translation caches as part of SRTP flow. The VT-d spec adds a ESRTPS
(Enhanced Set Root Table Pointer Support, section 11.4.2 in VT-d spec)
capability bit to indicate this. With this bit set, software has no need
to issue the global invalidation request.

Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com>
Reviewed-by: Jerry Snitselaar <jsnitsel@redhat.com>
Reviewed-by: Kevin Tian <kevin.tian@intel.com>
Link: https://lore.kernel.org/r/20220919062523.3438951-3-baolu.lu@linux.intel.com
Signed-off-by: Joerg Roedel <jroedel@suse.de>
Signed-off-by: Zelin Deng <zelin.deng@linux.alibaba.com>
Link: https://gitee.com/anolis/cloud-kernel/pulls/3072
This commit is contained in:
Lu Baolu 2022-09-26 21:15:29 +08:00 committed by 小龙
parent 518d58b41f
commit b653dc4ae9
2 changed files with 8 additions and 0 deletions
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7
drivers/iommu/intel/iommu.c
View File

@ -1401,6 +1401,13 @@ static void iommu_set_root_entry(struct intel_iommu *iommu)
raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
/*
* Hardware invalidates all DMA remapping hardware translation
* caches as part of SRTP flow.
*/
if (cap_esrtps(iommu->cap))
return;
iommu->flush.flush_context(iommu, 0, 0, 0, DMA_CCMD_GLOBAL_INVL);
if (sm_supported(iommu))
qi_flush_pasid_cache(iommu, 0, QI_PC_GLOBAL, 0);

1
include/linux/intel-iommu.h
View File

@ -159,6 +159,7 @@
/*
* Decoding Capability Register
*/
#define cap_esrtps(c) (((c) >> 63) & 1)
#define cap_esirtps(c) (((c) >> 62) & 1)
#define cap_ecmds(c) (((c) >> 61) & 1)
#define cap_fl5lp_support(c) (((c) >> 60) & 1)