mirrors
/
anolis-cloud-kernel
mirror of https://gitee.com/anolis/cloud-kernel.git
8
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

anolis: sw64: pci: rename some functions 

ANBZ: #4688

Rename some PCI related functions to improve code readability.

Signed-off-by: Jing Li <jingli@wxiat.com>
Reviewed-by: He Sheng <hesheng@wxiat.com>
Signed-off-by: Gu Zitao <guzitao@wxiat.com>
Reviewed-by: Min Li <gumi@linux.alibaba.com>
Reviewed-by: Xunlei Pang <xlpang@linux.alibaba.com>
Link: https://gitee.com/anolis/cloud-kernel/pulls/3807
This commit is contained in:
Jing Li 2024-08-16 14:45:58 +08:00 committed by guzitao
parent 1a046899ff
commit d3c6046b7b
8 changed files with 60 additions and 76 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
arch/sw_64/include/asm/pci.h
View File

@ -158,7 +158,6 @@ extern void __init sw64_device_interrupt(unsigned long vector);
extern void setup_intx_irqs(struct pci_controller *hose);
extern void __init sw64_init_irq(void);
extern void __init sw64_init_arch(void);
extern struct pci_ops sw64_pci_ops;
extern int sw64_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
extern struct pci_controller *hose_head;
extern bool sunway_legacy_pci;
@ -173,14 +172,14 @@ extern struct pci_controller *
pci_bus_to_pci_controller(const struct pci_bus *bus);
extern struct pci_controller *bus_num_to_pci_controller(unsigned long bus_num);
extern void sw64_pci_root_bridge_scan_finish_up(struct pci_host_bridge *bridge);
extern int sw64_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
extern int sunway_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
extern void sunway_pci_root_bridge_scan_finish(struct pci_host_bridge *bridge);
extern void __iomem *sw64_pcie_map_bus(struct pci_bus *bus,
extern void __iomem *sunway_pci_map_bus(struct pci_bus *bus,
unsigned int devfn, int where);
extern int sw64_pcie_config_write(struct pci_bus *bus, unsigned int devfn,
extern int sunway_pci_config_write(struct pci_bus *bus, unsigned int devfn,
int where, int size, u32 val);
extern int sw64_pcie_config_read(struct pci_bus *bus, unsigned int devfn,
extern int sunway_pci_config_read(struct pci_bus *bus, unsigned int devfn,
int where, int size, u32 *val);
extern void pci_mark_rc_linkup(struct pci_controller *hose);

1
arch/sw_64/include/asm/sw64_init.h
View File

@ -14,7 +14,6 @@ struct sw64_early_init_ops {
};
struct sw64_pci_init_ops {
int (*map_irq)(const struct pci_dev *dev, u8 slot, u8 pin);
unsigned long (*get_rc_enable)(unsigned long node);
void (*hose_init)(struct pci_controller *hose);
void (*set_rc_piu)(struct pci_controller *hose);

11
arch/sw_64/pci/acpi.c
View File

@ -85,7 +85,7 @@ pci_acpi_setup_ecam_mapping(struct acpi_pci_root *root)
return cfg;
}
static int upper_32_bits_of_ep_mem_32_base(struct acpi_device *adev, u64 *memh)
static int ep_32bits_memio_base(struct acpi_device *adev, u64 *memh)
{
int status = 0;
u64 val;
@ -125,7 +125,7 @@ static int pci_acpi_prepare_root_resources(struct acpi_pci_root_info *ci)
*
* Get the upper 32 bits here.
*/
status = upper_32_bits_of_ep_mem_32_base(device, &memh);
status = ep_32bits_memio_base(device, &memh);
if (status)
return status;
@ -219,11 +219,8 @@ struct pci_bus *pci_acpi_scan_root(struct acpi_pci_root *root)
if (!bus)
return NULL;
/**
* Some quirks for pci controller of Sunway
* after scanning Root Complex
*/
sw64_pci_root_bridge_scan_finish_up(pci_find_host_bridge(bus));
/* Some quirks for Sunway PCIe controller after scanning */
sunway_pci_root_bridge_scan_finish(pci_find_host_bridge(bus));
pci_bus_size_bridges(bus);
pci_bus_assign_resources(bus);

21
arch/sw_64/pci/pci-legacy.c
View File

@ -70,6 +70,12 @@ int __weak chip_pcie_configure(struct pci_controller *hose)
return 0;
}
static struct pci_ops sunway_pci_ops = {
.map_bus = sunway_pci_map_bus,
.read = sunway_pci_config_read,
.write = sunway_pci_config_write,
};
unsigned char last_bus = PCI0_BUS;
void __init common_init_pci(void)
{
@ -102,9 +108,9 @@ void __init common_init_pci(void)
bridge->dev.parent = NULL;
bridge->sysdata = hose;
bridge->busnr = hose->busn_space->start;
bridge->ops = &sw64_pci_ops;
bridge->ops = &sunway_pci_ops;
bridge->swizzle_irq = pci_common_swizzle;
bridge->map_irq = sw64_map_irq;
bridge->map_irq = sunway_pci_map_irq;
ret = pci_scan_root_bus_bridge(bridge);
if (ret) {
@ -200,17 +206,6 @@ no_io:
return;
}
struct pci_ops sw64_pci_ops = {
.map_bus = sw64_pcie_map_bus,
.read = sw64_pcie_config_read,
.write = sw64_pcie_config_write,
};
int sw64_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
return sw64_chip_init->pci_init.map_irq(dev, slot, pin);
}
static bool rc_linkup[MAX_NUMNODES][MAX_NR_RCS_PER_NODE];
static void __init

8
arch/sw_64/pci/pci.c
View File

@ -283,7 +283,7 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, enable_sw_dca);
*/
static unsigned char last_bus;
static void sw64_pci_root_bridge_prepare(struct pci_host_bridge *bridge)
static void sunway_pci_root_bridge_prepare(struct pci_host_bridge *bridge)
{
struct pci_controller *hose = NULL;
struct resource_entry *entry = NULL;
@ -327,7 +327,7 @@ static void sw64_pci_root_bridge_prepare(struct pci_host_bridge *bridge)
bus->number = last_bus;
bridge->swizzle_irq = pci_common_swizzle;
bridge->map_irq = sw64_pci_map_irq;
bridge->map_irq = sunway_pci_map_irq;
init_busnr = (0xff << 16) + ((last_bus + 1) << 8) + (last_bus);
writel(init_busnr, (hose->rc_config_space_base + RC_PRIMARY_BUS));
@ -367,7 +367,7 @@ sw64_pci_root_bridge_reserve_legacy_io(struct pci_host_bridge *bridge)
}
}
void sw64_pci_root_bridge_scan_finish_up(struct pci_host_bridge *bridge)
void sunway_pci_root_bridge_scan_finish(struct pci_host_bridge *bridge)
{
struct pci_controller *hose = NULL;
struct pci_bus *bus = NULL;
@ -443,7 +443,7 @@ int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
set_dev_node(bus_dev, hose->node);
/* Some quirks for Sunway PCIe controller before scanning */
sw64_pci_root_bridge_prepare(bridge);
sunway_pci_root_bridge_prepare(bridge);
return 0;
}

18
drivers/acpi/pci_mcfg.c
View File

@ -190,15 +190,15 @@ static struct mcfg_fixup mcfg_quirks[] = {
{ "SUNWAY", table_id, rev, ((node) * MAX_NR_RCS_PER_NODE + 10), MCFG_BUS_ANY, ops }, \
{ "SUNWAY", table_id, rev, ((node) * MAX_NR_RCS_PER_NODE + 11), MCFG_BUS_ANY, ops } \
/* up to 8 nodes for SW64 series */
SW64_ECAM_QUIRK("SUNWAY ", 1, 0x00, &sw64_pci_ecam_ops),
SW64_ECAM_QUIRK("SUNWAY ", 1, 0x01, &sw64_pci_ecam_ops),
SW64_ECAM_QUIRK("SUNWAY ", 1, 0x02, &sw64_pci_ecam_ops),
SW64_ECAM_QUIRK("SUNWAY ", 1, 0x03, &sw64_pci_ecam_ops),
SW64_ECAM_QUIRK("SUNWAY ", 1, 0x04, &sw64_pci_ecam_ops),
SW64_ECAM_QUIRK("SUNWAY ", 1, 0x05, &sw64_pci_ecam_ops),
SW64_ECAM_QUIRK("SUNWAY ", 1, 0x06, &sw64_pci_ecam_ops),
SW64_ECAM_QUIRK("SUNWAY ", 1, 0x07, &sw64_pci_ecam_ops),
/* Up to 8 nodes for Sunway PCIe controller */
SW64_ECAM_QUIRK("SUNWAY ", 1, 0x00, &sunway_pci_ecam_ops),
SW64_ECAM_QUIRK("SUNWAY ", 1, 0x01, &sunway_pci_ecam_ops),
SW64_ECAM_QUIRK("SUNWAY ", 1, 0x02, &sunway_pci_ecam_ops),
SW64_ECAM_QUIRK("SUNWAY ", 1, 0x03, &sunway_pci_ecam_ops),
SW64_ECAM_QUIRK("SUNWAY ", 1, 0x04, &sunway_pci_ecam_ops),
SW64_ECAM_QUIRK("SUNWAY ", 1, 0x05, &sunway_pci_ecam_ops),
SW64_ECAM_QUIRK("SUNWAY ", 1, 0x06, &sunway_pci_ecam_ops),
SW64_ECAM_QUIRK("SUNWAY ", 1, 0x07, &sunway_pci_ecam_ops),
#endif /* SW64 */
};

64
drivers/pci/controller/pci-sunway.c
View File

@ -261,7 +261,7 @@ static unsigned long get_rc_enable(unsigned long node)
return rc_enable;
}
static int map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
int sunway_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
struct pci_controller *hose = pci_bus_to_pci_controller(dev->bus);
@ -323,7 +323,6 @@ static void hose_init(struct pci_controller *hose)
};
static struct sw64_pci_init_ops chip_pci_init_ops = {
.map_irq = map_irq,
.get_rc_enable = get_rc_enable,
.hose_init = hose_init,
.set_rc_piu = set_rc_piu,
@ -399,7 +398,7 @@ EXPORT_SYMBOL(pci_bus_to_pci_controller);
/**
* PCIe Root Complex read config space operations
*/
static int sw64_pcie_read_rc_cfg(struct pci_bus *bus, unsigned int devfn,
static int pci_read_rc_cfg(struct pci_bus *bus, unsigned int devfn,
int where, int size, u32 *val)
{
u32 data;
@ -449,7 +448,7 @@ static int sw64_pcie_read_rc_cfg(struct pci_bus *bus, unsigned int devfn,
/**
* PCIe Root Complex write config space operations
*/
static int sw64_pcie_write_rc_cfg(struct pci_bus *bus, unsigned int devfn,
static int pci_write_rc_cfg(struct pci_bus *bus, unsigned int devfn,
int where, int size, u32 val)
{
u32 data;
@ -488,7 +487,7 @@ static int sw64_pcie_write_rc_cfg(struct pci_bus *bus, unsigned int devfn,
}
/**
* sw64_pcie_valid_device - check if a valid device is present
* pci_valid_device - check if a valid device is present
* on bus
*
* @bus : PCI bus structure
@ -496,7 +495,7 @@ static int sw64_pcie_write_rc_cfg(struct pci_bus *bus, unsigned int devfn,
*
* @return: 'true' on success and 'false' if invalid device is found
*/
static bool sw64_pcie_valid_device(struct pci_bus *bus, unsigned int devfn)
static bool pci_valid_device(struct pci_bus *bus, unsigned int devfn)
{
struct pci_controller *hose = pci_bus_to_pci_controller(bus);
@ -510,7 +509,7 @@ static bool sw64_pcie_valid_device(struct pci_bus *bus, unsigned int devfn)
}
/**
* sw64_pcie_config_read - read val from config space of
* sunway_pci_config_read - read val from config space of
* PCI host controller or device
*
* @bus : PCI bus structure
@ -521,7 +520,7 @@ static bool sw64_pcie_valid_device(struct pci_bus *bus, unsigned int devfn)
*
* @return: Whether read operation success
*/
int sw64_pcie_config_read(struct pci_bus *bus, unsigned int devfn,
int sunway_pci_config_read(struct pci_bus *bus, unsigned int devfn,
int where, int size, u32 *val)
{
struct pci_controller *hose = pci_bus_to_pci_controller(bus);
@ -533,7 +532,7 @@ int sw64_pcie_config_read(struct pci_bus *bus, unsigned int devfn,
hose->self_busno = hose->busn_space->start;
if (unlikely(bus->number == hose->self_busno)) {
ret = sw64_pcie_read_rc_cfg(bus, devfn, where, size, val);
ret = pci_read_rc_cfg(bus, devfn, where, size, val);
} else {
if (pci_get_rc_linkup(hose)) {
ret = pci_generic_config_read(bus, devfn,
@ -544,10 +543,10 @@ int sw64_pcie_config_read(struct pci_bus *bus, unsigned int devfn,
}
return ret;
}
EXPORT_SYMBOL(sw64_pcie_config_read);
EXPORT_SYMBOL(sunway_pci_config_read);
/**
* sw64_pcie_config_write - write val to config space of PCI
* sunway_pci_config_write - write val to config space of PCI
* host controller or device
*
* @bus : PCI bus structure
@ -558,7 +557,7 @@ EXPORT_SYMBOL(sw64_pcie_config_read);
*
* @return: Whether write operation success
*/
int sw64_pcie_config_write(struct pci_bus *bus, unsigned int devfn,
int sunway_pci_config_write(struct pci_bus *bus, unsigned int devfn,
int where, int size, u32 val)
{
struct pci_controller *hose = pci_bus_to_pci_controller(bus);
@ -569,14 +568,14 @@ int sw64_pcie_config_write(struct pci_bus *bus, unsigned int devfn,
hose->self_busno = hose->busn_space->start;
if (unlikely(bus->number == hose->self_busno))
return sw64_pcie_write_rc_cfg(bus, devfn, where, size, val);
return pci_write_rc_cfg(bus, devfn, where, size, val);
else
return pci_generic_config_write(bus, devfn, where, size, val);
}
EXPORT_SYMBOL(sw64_pcie_config_write);
EXPORT_SYMBOL(sunway_pci_config_write);
/**
* sw64_pcie_map_bus - get configuration base address
* sunway_pci_map_bus - get configuration base address
* @bus : PCI bus structure
* @devfn: device/function
* @where: offset from base
@ -584,14 +583,14 @@ EXPORT_SYMBOL(sw64_pcie_config_write);
* @return: base address of the configuration space needed to be
* accessed.
*/
void __iomem *sw64_pcie_map_bus(struct pci_bus *bus,
void __iomem *sunway_pci_map_bus(struct pci_bus *bus,
unsigned int devfn, int where)
{
struct pci_controller *hose = pci_bus_to_pci_controller(bus);
void __iomem *cfg_iobase;
unsigned long relbus;
if (!sw64_pcie_valid_device(bus, devfn))
if (!pci_valid_device(bus, devfn))
return NULL;
/**
@ -613,12 +612,7 @@ void __iomem *sw64_pcie_map_bus(struct pci_bus *bus,
cfg_iobase, bus->number, devfn, where);
return cfg_iobase;
}
EXPORT_SYMBOL(sw64_pcie_map_bus);
int sw64_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
return map_irq(dev, slot, pin);
}
EXPORT_SYMBOL(sunway_pci_map_bus);
enum pci_props {
PROP_RC_CONFIG_BASE = 0,
@ -681,7 +675,7 @@ static void pci_controller_set_node(struct pci_controller *hose,
}
#endif
static int sw64_pci_prepare_controller(struct pci_controller *hose,
static int pci_prepare_controller(struct pci_controller *hose,
struct fwnode_handle *fwnode)
{
u64 props[PROP_NUM];
@ -758,7 +752,7 @@ static int sw64_pci_prepare_controller(struct pci_controller *hose,
}
#ifdef CONFIG_ACPI
static int sw64_pci_acpi_present(struct device *dev)
static int pci_acpi_present(struct device *dev)
{
struct acpi_device *adev = to_acpi_device(dev);
int ret;
@ -791,7 +785,7 @@ static int sw64_pci_acpi_present(struct device *dev)
/**
* Use the information from ACPI or DTB to init pci_controller
*/
static int sw64_pci_ecam_init(struct pci_config_window *cfg)
static int sunway_pci_ecam_init(struct pci_config_window *cfg)
{
struct pci_controller *hose = NULL;
struct device *dev = cfg->parent;
@ -800,7 +794,7 @@ static int sw64_pci_ecam_init(struct pci_config_window *cfg)
#ifdef CONFIG_ACPI
if (!acpi_disabled) {
ret = sw64_pci_acpi_present(dev);
ret = pci_acpi_present(dev);
if (ret)
return ret;
@ -813,7 +807,7 @@ static int sw64_pci_ecam_init(struct pci_config_window *cfg)
return -ENOMEM;
/* Init pci_controller */
ret = sw64_pci_prepare_controller(hose, fwnode);
ret = pci_prepare_controller(hose, fwnode);
if (ret) {
kfree(hose);
dev_err(dev, "failed to init pci controller\n");
@ -825,13 +819,13 @@ static int sw64_pci_ecam_init(struct pci_config_window *cfg)
return 0;
}
const struct pci_ecam_ops sw64_pci_ecam_ops = {
const struct pci_ecam_ops sunway_pci_ecam_ops = {
.bus_shift = 24,
.init = sw64_pci_ecam_init,
.init = sunway_pci_ecam_init,
.pci_ops = {
.map_bus = sw64_pcie_map_bus,
.read = sw64_pcie_config_read,
.write = sw64_pcie_config_write,
.map_bus = sunway_pci_map_bus,
.read = sunway_pci_config_read,
.write = sunway_pci_config_write,
}
};
@ -839,7 +833,7 @@ const struct pci_ecam_ops sw64_pci_ecam_ops = {
static const struct of_device_id sunway_pcie_of_match[] = {
{
.compatible = "sunway,pcie",
.data = &sw64_pci_ecam_ops,
.data = &sunway_pci_ecam_ops,
},
{},
};
@ -926,7 +920,7 @@ static int sunway_pcie_probe(struct platform_device *pdev)
* Some quirks for Sunway PCIe controller after scanning,
* that's why we don't directly call function pci_host_probe().
*/
sw64_pci_root_bridge_scan_finish_up(bridge);
sunway_pci_root_bridge_scan_finish(bridge);
pci_bus_size_bridges(bus);
pci_bus_assign_resources(bus);

2
include/linux/pci-ecam.h
View File

@ -59,7 +59,7 @@ extern const struct pci_ecam_ops xgene_v1_pcie_ecam_ops; /* APM X-Gene PCIe v1 *
extern const struct pci_ecam_ops xgene_v2_pcie_ecam_ops; /* APM X-Gene PCIe v2.x */
extern const struct pci_ecam_ops al_pcie_ops; /* Amazon Annapurna Labs PCIe */
extern const struct pci_ecam_ops loongson_pci_ecam_ops; /* Loongson PCIe */
extern const struct pci_ecam_ops sw64_pci_ecam_ops; /* SW64 PCIe */
extern const struct pci_ecam_ops sunway_pci_ecam_ops; /* Sunway PCIe */
#endif
#if IS_ENABLED(CONFIG_PCI_HOST_COMMON)