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clocksource/drivers/arm_arch_timer: Remove any trace of the TVAL programming interface 

ANBZ: #11194

commit c9cf1f4ca3ea224c586656c422b5319c87a35e50 openeuler

mainline inclusion
from mainline-v5.16-rc1
commit 41f8d02a6a
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/I4QCBG
CVE: NA

----------------------

TVAL usage is now long gone, get rid of the leftovers.

Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20211017124225.3018098-11-maz@kernel.org
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Xiongfeng Wang <wangxiongfeng2@huawei.com>
Reviewed-by: Hanjun Guo <guohanjun@huawei.com>
Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
Signed-off-by: Slim6882 <yangjunshuo@huawei.com>
Signed-off-by: Min Li <gumi@linux.alibaba.com>
Reviewed-by: Guanghui Feng <guanghuifeng@linux.alibaba.com>
Reviewed-by: Jay Chen <jkchen@linux.alibaba.com>
Reviewed-by: Guixin Liu <kanie@linux.alibaba.com>
Reviewed-by: Xunlei Pang <xlpang@linux.alibaba.com>
Link: https://gitee.com/anolis/cloud-kernel/pulls/4258
This commit is contained in:
Marc Zyngier 2022-01-17 21:06:50 +08:00 committed by 小龙
parent 83ee495e2f
commit dbf6e3ad96
2 changed files with 0 additions and 9 deletions
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8
drivers/clocksource/arm_arch_timer.c
View File

@ -48,10 +48,8 @@
#define CNTPCT_LO 0x08
#define CNTFRQ 0x10
#define CNTP_CVAL_LO 0x20
#define CNTP_TVAL 0x28
#define CNTP_CTL 0x2c
#define CNTV_CVAL_LO 0x30
#define CNTV_TVAL 0x38
#define CNTV_CTL 0x3c
static unsigned arch_timers_present __initdata;
@ -103,9 +101,6 @@ void arch_timer_reg_write(int access, enum arch_timer_reg reg, u64 val,
case ARCH_TIMER_REG_CTRL:
writel_relaxed((u32)val, timer->base + CNTP_CTL);
break;
case ARCH_TIMER_REG_TVAL:
writel_relaxed((u32)val, timer->base + CNTP_TVAL);
break;
case ARCH_TIMER_REG_CVAL:
/*
* Not guaranteed to be atomic, so the timer
@ -122,9 +117,6 @@ void arch_timer_reg_write(int access, enum arch_timer_reg reg, u64 val,
case ARCH_TIMER_REG_CTRL:
writel_relaxed((u32)val, timer->base + CNTV_CTL);
break;
case ARCH_TIMER_REG_TVAL:
writel_relaxed((u32)val, timer->base + CNTV_TVAL);
break;
case ARCH_TIMER_REG_CVAL:
/* Same restriction as above */
writeq_relaxed(val, timer->base + CNTV_CVAL_LO);

1
include/clocksource/arm_arch_timer.h
View File

@ -24,7 +24,6 @@
enum arch_timer_reg {
ARCH_TIMER_REG_CTRL,
ARCH_TIMER_REG_TVAL,
ARCH_TIMER_REG_CVAL,
};