Arm: Initial functionality.

Makefile

@@ -63,7 +63,11 @@ OBJ	:= $(patsubst %.ld,$(PAT_OBJ), $(patsubst %.S,$(PAT_OBJ), $(patsubst %.cpp,$
 OBJ_DEP	:= $(OBJ:%.o=%.d)
 
 DIG	:= $(BLD_DIR)/digest
+ifeq ($(ARCH),aarch64)
+HYP	:= $(BLD_DIR)/$(ARCH)-$(BOARD)-nova
+else
 HYP	:= $(BLD_DIR)/$(ARCH)-nova
+endif
 ELF	:= $(HYP).elf
 BIN	:= $(HYP).bin
 
@@ -87,7 +91,10 @@ VPATH	:= $(SRC_DIR)
 # Optimization options
 DFLAGS	:= -MP -MMD -pipe
 OFLAGS	:= -Os
-ifeq ($(ARCH),x86_64)
+ifeq ($(ARCH),aarch64)
+AFLAGS	:= -march=armv8-a -mcmodel=large -mgeneral-regs-only $(call check,-mno-outline-atomics) -mstrict-align
+DEFINES	+= BOARD_$(BOARD)
+else ifeq ($(ARCH),x86_64)
 AFLAGS	:= -Wa,--divide,--noexecstack -march=x86-64-v2 -mcmodel=kernel -mgeneral-regs-only -mno-red-zone
 else
 $(error $(ARCH) is not a valid architecture)

inc/aarch64/extern.hpp

@@ -0,0 +1,22 @@
+/*
+ * External Symbols
+ *
+ * Copyright (C) 2019-2025 Udo Steinberg, BlueRock Security, Inc.
+ *
+ * This file is part of the NOVA microhypervisor.
+ *
+ * NOVA is free software: you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * NOVA is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License version 2 for more details.
+ */
+
+#pragma once
+
+#include "types.hpp"
+
+extern char GIT_VER;

inc/aarch64/lowlevel.hpp

@@ -0,0 +1,31 @@
+/*
+ * Low-Level Functions
+ *
+ * Copyright (C) 2019-2025 Udo Steinberg, BlueRock Security, Inc.
+ *
+ * This file is part of the NOVA microhypervisor.
+ *
+ * NOVA is free software: you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * NOVA is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License version 2 for more details.
+ */
+
+#pragma once
+
+#include "compiler.hpp"
+
+static inline void pause()
+{
+    asm volatile ("yield" : : : "memory");
+}
+
+[[noreturn]] static inline void shutdown()
+{
+    for (;;)
+        asm volatile ("wfi" : : : "memory");
+}

inc/aarch64/memory.hpp

@@ -0,0 +1,41 @@
+/*
+ * Virtual-Memory Layout
+ *
+ * Copyright (C) 2019-2025 Udo Steinberg, BlueRock Security, Inc.
+ *
+ * This file is part of the NOVA microhypervisor.
+ *
+ * NOVA is free software: you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * NOVA is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License version 2 for more details.
+ */
+
+#pragma once
+
+#include "alignment.hpp"
+#include "board.hpp"
+
+#ifndef RAM_SIZE
+#define RAM_SIZE        0x80000000              // Assume 2GiB populated
+#endif
+
+#ifndef RAM_BASE
+#define LOAD_ADDR       0
+#else
+#define LOAD_ADDR       (RAM_BASE + RAM_SIZE - 0x2000000)
+#endif
+
+#define PTE_BPL         9
+#define PAGE_BITS       12
+#define LEVL_BITS(L)    ((L) * PTE_BPL + PAGE_BITS)
+#define PAGE_SIZE(L)    BITN (LEVL_BITS (L))
+#define OFFS_MASK(L)    (PAGE_SIZE (L) - 1)
+
+#define LINK_ADDR       LOAD_ADDR
+#define MMAP_CPU_DATA   0
+#define OFFSET          (LINK_ADDR - LOAD_ADDR)

src/aarch64/start.S

@@ -0,0 +1,88 @@
+/*
+ * Startup Code
+ *
+ * Copyright (C) 2019-2025 Udo Steinberg, BlueRock Security, Inc.
+ *
+ * This file is part of the NOVA microhypervisor.
+ *
+ * NOVA is free software: you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * NOVA is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License version 2 for more details.
+ */
+
+#include "arch.hpp"
+#include "memory.hpp"
+
+.global                 __init_bsp
+
+/*
+ * Macros
+ */
+.macro                  DCACHE  OP
+                        mrs     x3, ctr_el0
+                        ubfm    x3, x3, #16, #19
+                        mov     x2, #4
+                        lsl     x2, x2, x3
+                        add     x1, x0, x1
+                        sub     x3, x2, #1
+                        bic     x0, x0, x3
+1:                      dc     \OP, x0
+                        add     x0, x0, x2
+                        cmp     x0, x1
+                        blo     1b
+                        dsb     sy
+.endm
+
+/*
+ * Initialization Code
+ */
+.section .init
+
+__init_bsp:
+                        // Determine image boundaries
+                        adrp    x22, NOVA_HPAS
+                        adrp    x23, NOVA_HPAE
+                        mov     x24, LINK_ADDR
+                        sub     x24, x24, x22
+
+                        // Refuse invalid load address
+                        and     x2, x22, #ALIGNMENT_OFFS (ALIGNMENT_NOVA)
+                        cbnz    x2, .
+
+                        // Clean image to PoC
+                        mov     x0, x22
+                        sub     x1, x23, x22
+                        DCACHE  cvac
+
+1:                      msr     daifset, #0xf
+                        msr     spsel,   #0x1
+
+                        // Enable I$, D$, Disable MMU
+                        mrs     x0, sctlr_el2
+                        orr     x0, x0, #SCTLR_I
+                        orr     x0, x0, #SCTLR_C
+                        bic     x0, x0, #SCTLR_M
+                        msr     sctlr_el2, x0
+                        isb
+
+                        // Zero BSS
+                        adr     x0, ZERO_HPAS
+.Lbss_loop:             str     xzr, [x0], #__SIZEOF_POINTER__
+                        cmp     x0, x23
+                        blo     .Lbss_loop
+
+                        // Invalidate stale cache lines
+                        adr     x0, ZERO_HPAS
+                        sub     x1, x23, x0
+                        DCACHE  ivac
+
+                        // Switch to boot stack
+                        adr     x0, STACK
+                        mov     sp, x0
+
+                        b       .