x86: Added CET support.
This commit is contained in:
Udo Steinberg
parent
027d2b1065
commit
ce88d30867
2
Makefile
2
Makefile
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@ -25,6 +25,7 @@
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ARCH ?= x86_64
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BOARD ?= acpi
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COMP ?= gcc
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CFP ?= none
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# Tools
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INSTALL ?= install -m 644
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@ -97,6 +98,7 @@ PFLAGS := $(addprefix -D, $(DEFINES)) $(addprefix -I, $(INC_DIR))
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# Language options
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FFLAGS := $(or $(call check,-std=gnu++26), $(call check,-std=gnu++23), $(call check,-std=gnu++20))
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FFLAGS += -ffreestanding -fdata-sections -ffunction-sections -fno-asynchronous-unwind-tables -fno-exceptions -fno-rtti -fno-use-cxa-atexit -fomit-frame-pointer
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FFLAGS += $(call check,-fcf-protection=$(CFP))
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FFLAGS += $(call check,-fdiagnostics-color=auto)
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FFLAGS += $(call check,-fno-pic)
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FFLAGS += $(call check,-fno-stack-protector)
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@ -32,6 +32,10 @@ BOARD ?= acpi
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# Permitted values are: gcc
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COMP ?= gcc
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# Configure control-flow protection
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# Permitted values are: none, branch, return, full
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CFP ?= none
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# Configure build directory
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BLD_DIR ?= build-$(ARCH)
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14
README.md
14
README.md
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@ -68,6 +68,20 @@ and boards with Advanced Configuration and Power Interface (ACPI).
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| :------------------------------------ | :----------------- |
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| Generic x86 ACPI Platform | `make ARCH=x86_64` |
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##### Control-Flow Enforcement Technology (CET)
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NOVA can be built with support for control-flow protection. Because
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control-flow protected binaries require a CPU with CET support and because
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of the resulting performance overhead, CFP is disabled by default.
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Protection features can be enabled at build time as follows:
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| **Feature Level** | **Build Command** |
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| :------------------------------------ | :---------------------------- |
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| No Control-Flow Protection (Default) | `make ARCH=x86_64 CFP=none` |
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| CET Indirect Branch Tracking (IBT) | `make ARCH=x86_64 CFP=branch` |
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| CET Supervisor Shadow Stacks (SSS) | `make ARCH=x86_64 CFP=return` |
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| CET IBT and CET SSS | `make ARCH=x86_64 CFP=full` |
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## Booting
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See the NOVA interface specification in the `doc` directory for details
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@ -0,0 +1,52 @@
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/*
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* Control-Flow Enforcement Technology (CET)
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*
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* Copyright (C) 2019-2025 Udo Steinberg, BlueRock Security, Inc.
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*
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* This file is part of the NOVA microhypervisor.
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*
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* NOVA is free software: you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* NOVA is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License version 2 for more details.
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*/
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#pragma once
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#include "compiler.hpp"
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#include "extern.hpp"
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#include "patch.hpp"
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#include "types.hpp"
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class Cet final
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{
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public:
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/*
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* Deactivate supervisor shadow stack by marking the token as not busy
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*/
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ALWAYS_INLINE
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static inline void sss_deactivate()
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{
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#if defined(__CET__) && (__CET__ & 2)
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#define ASM_CET_1 clrssbsy %0;
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asm volatile (EXPAND (PATCH (ASM_CET_1,,PATCH_CET_SSS)) : : "m" (DSHD_TOP));
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#endif
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}
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/*
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* Unwind supervisor shadow stack up to the token
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*/
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ALWAYS_INLINE
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static inline void sss_unwind()
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{
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#if defined(__CET__) && (__CET__ & 2)
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uintptr_t ssp;
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#define ASM_CET_2 rdsspq %0; sub %0, %1; shr $3, %1; incsspq %1;
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asm volatile (EXPAND (PATCH (ASM_CET_2,,PATCH_CET_SSS)) : "=&r" (ssp) : "r" (&DSHD_TOP));
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#endif
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}
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};
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@ -119,11 +119,13 @@ class Cpu final
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SMAP = 3 * 32 + 20, // Supervisor Mode Access Prevention
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// EAX=0x7 ECX=0x0 (ECX)
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UMIP = 4 * 32 + 2, // User Mode Instruction Prevention
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CET_SS = 4 * 32 + 7, // CET Shadow Stack
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SGX_LC = 4 * 32 + 30, // SGX Launch Configuration
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// EAX=0x7 ECX=0x0 (EDX)
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SRBDS_CTRL = 5 * 32 + 9, // Special Register Buffer Data Sampling
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MD_CLEAR = 5 * 32 + 10, // Microarchitectural Data Clear
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HYBRID = 5 * 32 + 15, // Hybrid Processor
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CET_IBT = 5 * 32 + 20, // CET Indirect Branch Tracking
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IBRS = 5 * 32 + 26, // Indirect Branch Restricted Speculation
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STIBP = 5 * 32 + 27, // Single Thread Indirect Branch Predictors
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L1D_FLUSH = 5 * 32 + 28, // L1 Data Cache Flushing
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@ -134,6 +136,7 @@ class Cpu final
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// EAX=0x7 ECX=0x1 (EBX)
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// EAX=0x7 ECX=0x1 (ECX)
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// EAX=0x7 ECX=0x1 (EDX)
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CET_SSS = 9 * 32 + 18, // CET Supervisor Shadow Stack
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APX_F = 9 * 32 + 21, // APX Foundation
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// EAX=0x7 ECX=0x2 (EDX)
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PSFD = 10 * 32 + 0,
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@ -22,6 +22,7 @@
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#pragma once
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#include "cet.hpp"
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#include "ec.hpp"
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#include "extern.hpp"
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#include "space_hst.hpp"
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@ -126,6 +127,8 @@ class Ec_arch final : private Ec
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hst->make_current();
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Cet::sss_unwind();
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// Reset stack
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asm volatile ("lea %0, %%rsp" : : "m" (DSTK_TOP) : "memory");
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@ -23,7 +23,7 @@
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#include "types.hpp"
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extern char GIT_VER, NOVA_HPAS, KMEM_HVAS, KMEM_HVAF, PTAB_HVAS, DSTK_TOP;
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extern char GIT_VER, NOVA_HPAS, KMEM_HVAS, KMEM_HVAF, PTAB_HVAS, DSTK_TOP, DSHD_TOP;
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extern void (*CTORS_S[])(), (*CTORS_E[])(), (*CTORS_C[])(), (*CTORS_L[])();
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extern char entry_sys;
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@ -97,6 +97,13 @@ class Msr final
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IA32_VMX_CTRL_EXI_SEC = 0x493, // VMX
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IA32_MCG_EXT_CTL = 0x4d0, // MCA and IA32_MCG_CAP[MCG_LMCE_P]
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IA32_SGX_SVN_STATUS = 0x500, // SGX
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IA32_U_CET = 0x6a0, // CET_SS or CET_IBT
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IA32_S_CET = 0x6a2, // CET_SS or CET_IBT
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IA32_PL0_SSP = 0x6a4, // CET_SS
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IA32_PL1_SSP = 0x6a5, // CET_SS
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IA32_PL2_SSP = 0x6a6, // CET_SS
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IA32_PL3_SSP = 0x6a7, // CET_SS
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IA32_INTERRUPT_SSP_TABLE_ADDR = 0x6a8, // CET_SS
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IA32_TSC_DEADLINE = 0x6e0, // TSC_DEADLINE
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IA32_PM_ENABLE = 0x770, // HWP
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IA32_HWP_CAPABILITIES = 0x771, // HWP
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@ -21,3 +21,5 @@
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#define NOP_OPC 0x90
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#define PATCH_XSAVES 0
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#define PATCH_CET_IBT 1
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#define PATCH_CET_SSS 2
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@ -262,6 +262,8 @@ void Ec_arch::ret_user_hypercall (Ec *const self)
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trace (TRACE_CONT, "EC:%p %s to CS:%#x IP:%#lx", static_cast<void *>(self), __func__, SEL_USER_CODE, r.exc.ip());
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Cet::sss_deactivate();
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asm volatile ("lea %0, %%rsp;" EXPAND (LOAD_GPR) "mov %%r11, %%rsp; mov %1, %%r11; sysretq" : : "m" (r.exc), "i" (RFL_IF | RFL_1) : "memory");
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UNREACHED;
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@ -277,6 +279,8 @@ void Ec_arch::ret_user_exception (Ec *const self)
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trace (TRACE_CONT, "EC:%p %s to CS:%#lx IP:%#lx", static_cast<void *>(self), __func__, r.exc.cs, r.exc.rip);
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Cet::sss_unwind();
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asm volatile ("lea %0, %%rsp;" EXPAND (LOAD_GPR IRET) : : "m" (r.exc) : "memory");
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UNREACHED;
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@ -22,6 +22,7 @@
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#include "arch.hpp"
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#include "entry.hpp"
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#include "patch.hpp"
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#include "vectors.hpp"
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.data
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@ -39,6 +40,9 @@ handlers:
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.macro INTRGATE IDT
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.balign 4, 0x90
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1:
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#if defined(__CET__) && (__CET__ & 1)
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endbr64
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#endif
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.data
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.quad 1b + \IDT
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.previous
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@ -161,7 +165,14 @@ INTERRUPT VEC
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*/
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.balign 4, 0x90
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.global entry_sys
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entry_sys: mov %rsp, %r11
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entry_sys:
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#if defined(__CET__) && (__CET__ & 1)
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endbr64
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#endif
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#if defined(__CET__) && (__CET__ & 2)
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PATCH (setssbsy,,PATCH_CET_SSS)
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#endif
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mov %rsp, %r11
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mov tss_run + 4, %rsp
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lea -7 * __SIZEOF_POINTER__(%rsp), %rsp
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SAVE_GPR
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@ -112,6 +112,7 @@ SECTIONS
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PROVIDE_HIDDEN (NOVA_HPAE = . - OFFSET);
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PROVIDE_HIDDEN (DSTK_TOP = MMAP_CPU_DSTT);
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PROVIDE_HIDDEN (DSHD_TOP = MMAP_CPU_DTKN);
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.cpulocal MMAP_CPU_DATA :
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{
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@ -51,6 +51,20 @@ extern "C" uintptr_t kern_ptab_setup (apic_t t)
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// Allocate and map kernel intr stack
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hptp.update (MMAP_CPU_ISTB, Kmem::ptr_to_phys (Buddy::alloc (0, Buddy::Fill::BITS0)), 0, Paging::Permissions (Paging::G | Paging::W | Paging::R), Memattr::ram());
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#if defined(__CET__) && (__CET__ & 2)
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// Allocate and map data supervisor shadow stack
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auto const dsss { static_cast<uintptr_t *>(Buddy::alloc (0, Buddy::Fill::BITS0)) };
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hptp.update (MMAP_CPU_DSSS, Kmem::ptr_to_phys (dsss), 0, Paging::Permissions (Paging::SS | Paging::G | Paging::R), Memattr::ram());
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// Allocate and map intr supervisor shadow stack
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auto const isss { static_cast<uintptr_t *>(Buddy::alloc (0, Buddy::Fill::BITS0)) };
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hptp.update (MMAP_CPU_ISSS, Kmem::ptr_to_phys (isss), 0, Paging::Permissions (Paging::SS | Paging::G | Paging::R), Memattr::ram());
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// Install supervisor shadow stack tokens
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dsss[PAGE_SIZE (0) / sizeof (uintptr_t) - 1] = MMAP_CPU_DTKN;
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isss[PAGE_SIZE (0) / sizeof (uintptr_t) - 1] = MMAP_CPU_ITKN;
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#endif
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return hptp.root_addr();
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}
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@ -34,7 +34,13 @@ void Patch::detect()
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Fpu::compact = !!(eax & BIT (3));
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applied |= BIT (PATCH_XSAVES) * !Fpu::compact;
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[[fallthrough]];
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case 0x1 ... 0xc:
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case 0x7 ... 0xc:
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Cpu::cpuid (0x7, 0x0, eax, ebx, ecx, edx);
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applied |= BIT (PATCH_CET_IBT) * !(edx & BIT (20));
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Cpu::cpuid (0x7, 0x1, eax, ebx, ecx, edx);
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applied |= BIT (PATCH_CET_SSS) * !(edx & BIT (18));
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[[fallthrough]];
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case 0x1 ... 0x6:
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Cpu::cpuid (0x1, 0x0, eax, ebx, ecx, edx);
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Lapic::x2apic = ecx & BIT (21);
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[[fallthrough]];
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@ -23,6 +23,7 @@
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#include "memattr.hpp"
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#include "memory.hpp"
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#include "multiboot.hpp"
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#include "patch.hpp"
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#include "selectors.hpp"
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#define PTE_ATTR_P BIT (0) // Present
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@ -352,6 +353,66 @@ __init_all: mov $.Lhigh, %rax
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.Ltopo_end:
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call kern_ptab_setup
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mov %rax, %cr3
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#if defined(__CET__)
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// Track CET features in EAX
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xor %eax, %eax
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#if (__CET__ & 1)
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#define ASM_ENABLE_CET_1 or $(BIT_RANGE (5, 4) | BIT (2)), %al
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PATCH (ASM_ENABLE_CET_1,, PATCH_CET_IBT);
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#endif
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#if (__CET__ & 2)
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#define ASM_ENABLE_CET_2 or $BIT (0), %al
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PATCH (ASM_ENABLE_CET_2,, PATCH_CET_SSS);
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#endif
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// Check if any CET features are being enabled
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test %eax, %eax
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jz .Lcet_end
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// Enable CET
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mov %cr4, %rdx
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or $CR4_CET, %edx
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mov %rdx, %cr4
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// Enable CET features in EAX
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mov $0x6a2, %ecx
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xor %edx, %edx
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wrmsr
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#if (__CET__ & 2)
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// Check if CET_SSS is enabled
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test $BIT (0), %al
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jz .Lcet_end
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.pushsection .rodata
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.balign 64
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__interrupt_ssp_table: .quad 0
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.quad MMAP_CPU_ITKN
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.quad 0
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.quad 0
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.quad 0
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.quad 0
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.quad 0
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.quad 0
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.popsection
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// Initialize IA32_INTERRUPT_SSP_TABLE_ADDR
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mov $0x6a8, %ecx
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lea __interrupt_ssp_table, %rdx
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mov %rdx, %rax
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shr $0x20, %rdx
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wrmsr
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// Initialize IA32_PL0_SSP
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mov $0x6a4, %ecx
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lea DSHD_TOP, %rdx
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mov %rdx, %rax
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shr $0x20, %rdx
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wrmsr
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// Activate supervisor shadow stack
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setssbsy
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#endif
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.Lcet_end:
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#endif
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lea DSTK_TOP - __SIZEOF_POINTER__, %rsp
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jmp bootstrap
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@ -99,6 +99,14 @@ void Vmcs::init (uintptr_t gsp, uintptr_t hsp, uintptr_t cr3, uint64_t apic, uin
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if (Cpu::feature (Cpu::Feature::LM))
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write (Encoding::HOST_EFER, Msr::read (Msr::Reg64::IA32_EFER));
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if (Cpu::feature (Cpu::Feature::CET_SS) || Cpu::feature (Cpu::Feature::CET_IBT))
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write (Encoding::HOST_S_CET, Msr::read (Msr::Reg64::IA32_S_CET));
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if (Cpu::feature (Cpu::Feature::CET_SS)) {
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write (Encoding::HOST_SSP, MMAP_CPU_DTKN);
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write (Encoding::HOST_SSP_TABLE_ADDR, Msr::read (Msr::Reg64::IA32_INTERRUPT_SSP_TABLE_ADDR));
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}
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write (Encoding::PIN_CONTROLS, pin);
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write (Encoding::ENT_CONTROLS, ent);
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write (Encoding::EXI_CONTROLS_PRI, exi_pri);
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@ -125,12 +133,12 @@ void Vmcs::init()
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pin = (hyp_pin | static_cast<uint32_t>(vmx_pin)) & static_cast<uint32_t>(vmx_pin >> 32);
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// VM-Entry Controls
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constexpr auto hyp_ent { Ent::ENT_LOAD_EFER | Ent::ENT_LOAD_PAT };
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constexpr auto hyp_ent { Ent::ENT_LOAD_CET | Ent::ENT_LOAD_EFER | Ent::ENT_LOAD_PAT };
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auto const vmx_ent { Msr::read (ctrl ? Msr::Reg64::IA32_VMX_TRUE_ENT : Msr::Reg64::IA32_VMX_CTRL_ENT) };
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ent = (hyp_ent | static_cast<uint32_t>(vmx_ent)) & static_cast<uint32_t>(vmx_ent >> 32);
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// Primary VM-Exit Controls
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constexpr auto hyp_exi_pri { Exi_pri::EXI_SECONDARY | Exi_pri::EXI_LOAD_EFER | Exi_pri::EXI_SAVE_EFER | Exi_pri::EXI_LOAD_PAT | Exi_pri::EXI_SAVE_PAT | Exi_pri::EXI_INTA | Exi_pri::EXI_HOST_64 };
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constexpr auto hyp_exi_pri { Exi_pri::EXI_SECONDARY | Exi_pri::EXI_LOAD_CET | Exi_pri::EXI_LOAD_EFER | Exi_pri::EXI_SAVE_EFER | Exi_pri::EXI_LOAD_PAT | Exi_pri::EXI_SAVE_PAT | Exi_pri::EXI_INTA | Exi_pri::EXI_HOST_64 };
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auto const vmx_exi_pri { Msr::read (ctrl ? Msr::Reg64::IA32_VMX_TRUE_EXI : Msr::Reg64::IA32_VMX_CTRL_EXI_PRI) };
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exi_pri = (hyp_exi_pri | static_cast<uint32_t>(vmx_exi_pri)) & static_cast<uint32_t>(vmx_exi_pri >> 32);
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