mirror of https://github.com/l4ka/hazelnut.git
124 lines
2.5 KiB
ArmAsm
124 lines
2.5 KiB
ArmAsm
/*********************************************************************
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*
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* Copyright (C) 2001, Karlsruhe University
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*
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* File path: arm-booter/crt0-arm-dnard.S
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* Description: startup assembly code for DNARD board
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*
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* @LICENSE@
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*
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* $Id: crt0-arm-dnard.S,v 1.5 2001/12/11 19:54:22 ud3 Exp $
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*
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********************************************************************/
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/*
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DNARD initial memory map
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virt phys size
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F0000000 0e500000
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F7EFF000 40000000 4k
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We're loaded at f0000000, backed by 0e500000. This code is linked at
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0e500000. Thus the ldr r2,=1f will load 0e5000xy, not f00000xy. By
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jumping to r2 directly after turning off the MMU, we then run 1:1
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*/
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.globl _start
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_start:
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/* Turn off interrupts to keep control */
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mrs r0, cpsr
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orr r0, r0, #0xC0 /* IRQs and FIQs disabled */
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msr cpsr, r0
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/* Clean out the DCache */
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mrc p15, 0, r3, c1, c0
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bic r3, r3, #0xC /* Write Buffer and DCache */
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bic r3, r3, #0x1000 /* ICache */
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mcr p15, 0, r3, c1, c0 /* disabled */
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bic r3, r3, #0x1 /* prepare disabling of MMU */
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ldr r2, =1f /* load target address to jump
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to when MMU is off */
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mov r0, #0
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mcr p15, 0, r0, c7, c7 /* flush I,D caches on v4 */
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mcr p15, 0, r0, c7, c10, 4 /* drain write buffer on v4 */
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mcr p15, 0, r0, c8, c7 /* flush I,D TLBs on v4
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The next 4 instructions are
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fetched still using the just
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flushed TLB entries */
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mcr p15, 0, r3, c1, c0 /* disable MMU */
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mov pc, r2 /* jump to the next instruction */
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nop
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nop
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nop
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1:
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#define SLEEP \
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mov r1, #0x10000 ; 0: subs r1, r1, #1; bne 0b
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ldr r0, =0x400003f8
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mov r1, #0
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strb r1, [r0, #0x01] /* disable serial interrupt */
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SLEEP
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mov r1, #0x80
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strb r1, [r0, #0x03] /* switch to divisor mode */
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SLEEP
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mov r1, #1
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strb r1, [r0, #0x00] /* DLLO */
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SLEEP
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mov r1, #0
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strb r1, [r0, #0x01] /* DLHI */
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SLEEP
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mov r1, #0x03
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strb r1, [r0, #0x03] /* switch back */
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SLEEP
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mov r1, #0x06
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strb r1, [r0, #0x02] /* FCR */
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SLEEP
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mov r1, #0x00
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strb r1, [r0, #0x01] /* FCR */
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SLEEP
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ldr r1, [r0, #1]
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ldr r1, [r0, #2]
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ldr r1, [r0, #3]
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ldr r1, [r0, #4]
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ldr r1, [r0, #5]
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ldr r1, [r0, #6]
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SLEEP
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#if 0
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mov r2, #0x39
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1: ldr r0, =0x400003f8
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strb r2, [r0]
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SLEEP
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sub r2, r2, #1
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cmp r2, #0x2F
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bne 1b
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#endif
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/* here we actually start */
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2: ldr sp, =__stack_top
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bl main
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1: b 1b
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.globl __gccmain
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__gccmain:
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mov pc,lr
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.bss
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.align 4
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__stack_bottom:
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.space 1024
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__stack_top:
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