mirror of https://github.com/l4ka/hazelnut.git
290 lines
8.2 KiB
C
290 lines
8.2 KiB
C
/*********************************************************************
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*
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* Copyright (C) 2001, Karlsruhe University
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*
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* File path: pmc_values.h
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* Description: Definition macros for performance counters the x86
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* PentiumPro family of processors. (What's the point
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* of this file?)
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*
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* @LICENSE@
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*
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* $Id: pmc_values.h,v 1.2 2001/11/22 12:13:54 skoglund Exp $
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*
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********************************************************************/
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#ifndef __pmc_values_h__
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#define __pmc_values_h__
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/* Performance counter registers */
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#define PERFCTR0 193
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#define PERFCTR1 194
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#define PERFEVENTSEL0 390
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#define PERFEVENTSEL1 391
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/*
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* All these #defines come from the
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* Intel Archictecture Software Developer's Manual, Volume 3
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* available from http://developer.intel.com
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* which has more information about these counters.
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*/
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/* event masks */
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#define PMC_USER_MASK (1 << 16)
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#define PMC_OS_MASK (1 << 17)
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#define PMC_OCCURENCE_MASK (1 << 18)
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#define PMC_ENABLE_MASK ((1 << 22)|(1<<20))
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/* P6 Family Processor performance-monitoring events */
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/* (DCU) Unit */
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/* All memory references, both cacheable and noncacheable. */
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#define DATA_MEM_REFS (0x0043)
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/* Total lines allocated in the DCU. */
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#define DCU_LINES_IN (0x0045)
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/* Number of M state lines allocated in the DCU. */
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#define DCU_M_LINES_IN (0x0046)
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/* Number of M state lines evicted from the DCU. This includes evictions via
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snoop HITM, intervention or replacement. */
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#define DCU_M_LINES_OUT (0x0047)
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/*
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Weighted number of cycles while a DCU miss is outstanding. An access
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that also misses the L2 is short-changed by 2 cycles (i.e., if counts
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N cycles, should be N+2 cycles). Subsequent loads to the same cache
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line will not result in any additional counts. Count value not
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precise, but still useful.
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*/
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#define DCU_MISS_OUTSTANDING (0x0048)
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/* Instruction Fetch Unit (IFU) */
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/* Number of instruction fetches, both cacheable and noncacheable. */
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#define IFU_IFETCH (0x0080)
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/* Number of instruction fetch misses. */
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#define IFU_IFETCH_MISS (0x0081)
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/* Number of ITLB misses. */
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#define ITLB_MISS (0x0085)
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/* Number of cycles that the instruction fetch pipe stage is stalled, including cache misses, ITLB misses, ITLB faults, and victimcache evictions. */
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#define IFU_MEM_STALL (0x0086)
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/* Number of cycles that the instruction length decoder is stalled. */
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#define ILD_STALL (0x0087)
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/* L2 Cache events */
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/* Number of L2 instruction fetches. */
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#define L2_IFETCH (0xf28)
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/* Number of L2 data loads. */
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#define L2_LD (0x0f29)
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/* Number of L2 data stores. */
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#define L2_ST (0x0f2A)
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/* Number of lines allocated in the L2. */
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#define L2_LINES_IN (0x24)
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/* Number of lines removed from the L2 for any reason. */
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#define L2_LINES_OUT (0x26)
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/* Number of modified lines allocated in the L2. */
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#define L2_M_LINES_INM (0x25)
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/* Number of modified lines removed from the L2 for any reason. */
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#define L2_M_LINES_OUTM (0x27)
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/* Number of L2 requests. */
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#define L2_RQSTS (0x0f2E)
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/* Number of L2 address strobes. */
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#define L2_ADS (0x21)
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/* Number of cycles during which the data bus was busy. */
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#define L2_DBUS_BUSY (0x22)
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/* Number of cycles during which the data bus was busy transferring data from L2 to the processor. */
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#define L2_DBUS_BUSY_RD (0x23)
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/* External Bus Logic (EBL) */
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/* Number of clocks during which DRDY is asserted by CPU. */
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#define BUS_DRDY_CLOCKS_SELF (0x62)
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/* (Any) Number of clocks during which DRDY is asserted by any agent. */
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#define BUS_DRDY_CLOCKS_ANY (0x2062)
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/* Number of clocks during which LOCK is asserted. Always counts in processor clocks. */
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#define BUS_LOCK_CLOCKS_SELF (0x63)
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/* Number of clocks during which LOCK is asserted. Always counts in processor clocks. */
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#define BUS_LOCK_CLOCKS_ANY (0x2063)
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/* Number of bus requests outstanding. Counts only DCU full- line cacheable reads, not RFOs, writes, instruction fetches, or anything else. Counts "waiting for bus to complete" (last data chunk received).
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*/
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#define BUS_REQ_OUTSTANDING_SELF (0x60)
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/* Number of bus requests outstanding. Counts only DCU full- line cacheable reads, not RFOs, writes, instruction fetches, or anything else. Counts "waiting for bus to complete" (last data chunk received).
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*/
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#define BUS_REQ_OUTSTANDING_ANY (0x2060)
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/* Number of burst read transactions. */
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#define BUS_TRAN_BRD_SELF (0x65)
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/* Number of burst read transactions. */
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#define BUS_TRAN_BRD_ANY (0x2065)
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/* Number of read for ownership transactions. */
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#define BUS_TRAN_RFO (0x66)
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/* Number of write back transactions. */
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#define BUS_TRANS_WB (0x67)
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/* Number of instruction fetch transactions. */
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#define BUS_TRAN_IFETCH (0x68)
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/* Number of invalidate transactions. */
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#define BUS_TRAN_INVAL (0x69)
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/* Number of partial write transactions. */
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#define BUS_TRAN_PWR (0x6A)
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/* Number of partial transactions. */
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#define BUS_TRANS_P (0x6B)
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/* Number of I/O transactions. */
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#define BUS_TRANS_IO (0x6C)
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/* Number of deferred transactions. */
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#define BUS_TRAN_DEF (0x6D)
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/* Number of burst transactions. */
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#define BUS_TRAN_BURST (0x6E)
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/* Number of all transactions. */
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#define BUS_TRAN_ANY (0x70)
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/* Number of memory transactions. */
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#define BUS_TRAN_MEM (0x6F)
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/* Number of bus clock cycles during which this processor is receiving data. */
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#define BUS_DATA_RCV (0x64)
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/* Number of bus clock cycles during which this processor is driving the BNR pin. */
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#define BUS_BNR_DRV (0x61)
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/* Number of bus clock cycles during which this processor is driving the HIT pin. Includes cycles due to snoop stalls. */
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#define BUS_HIT_DRV (0x7A)
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/* Number of bus clock cycles during which this processor is driving the HITM pin. Includes cycles due to snoop stalls. */
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#define BUS_HITM_DRV (0x7B)
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/* (Self) Number of clock cycles during which the bus is snoop stalled. */
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#define BUS_SNOOP_STALL (0x7E)
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/* Floating- Point Unit */
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/* Number of computational floating-point operations retired. Counter 0 only */
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#define FLOPS (0xC1)
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/* Number of computational floating-point operations executed. Counter 0 only. */
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#define FP_COMP_OPS_EXE (0x10)
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/* Number of floating- point exception cases handled by microcode. Counter 1 only. */
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#define FP_ASSIST (0x11)
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/* Number of multiplies. Counter 1 only. */
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#define MUL (0x12)
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/* Number of divides. Counter 1 only. */
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#define DIV (0x13)
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/* Number of cycles during which the divider is busy. Counter 0 only. */
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#define CYCLES_DIV_BUSY (0x14)
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/* Memory Ordering */
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/* Number of store buffer blocks. */
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#define LD_BLOCKS (0x03)
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/* Number of store buffer drain cycles. */
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#define SB_DRAINS (0x04)
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/* Number of misaligned data memory references. */
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#define MISALIGN_MEM_REF (0x05)
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/* Instruction Decoding and Retirement */
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/* Number of instructions retired. */
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#define INST_RETIRED (0xC0)
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/* Number of UOPs retired. */
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#define UOPS_RETIRED (0xC2)
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/* Number of instructions decoded. */
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#define INST_DECODER (0xD0)
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/*Interrupts */
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/* Number of hardware interrupts received. */
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#define HW_INT_RX (0xC8)
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/* Number of processor cycles for which interrupts are disabled. */
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#define CYCLES_INT_MASKED (0xC6)
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/* Number of processor cycles for which interrupts are disabled and interrupts are pending. */
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#define CYCLES_INT_PENDING_AND_MASKED (0xC7)
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/* Branches */
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/* Number of branch instructions retired. */
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#define BR_INST_RETIRED (0xC4)
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/* Number of mispredicted branches retired. */
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#define BR_MISS_PRED_RETIRED (0xC5)
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/* Number of taken branches retired. */
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#define BR_TAKEN_RETIRED (0xC9)
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/* Number of taken mispredictions branches retired. */
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#define BR_MISS_PRED_NRET (0xCA)
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/* Number of branch instructions decoded. */
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#define BR_INST_DECODED (0xE0)
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/* Number of branches that miss the BTB. */
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#define BTB_MISSES (0xE2)
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/* Number of bogus branches. */
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#define BR_BOGUS (0xE4)
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/* Number of time BACLEAR is asserted. */
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#define BACLEARS (0xE6)
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/* Stalls */
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/* Number of cycles during which there are resource related stalls. */
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#define RESOURCE_STALLS (0xA2)
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/* Number of cycles or events for partial stalls. */
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#define PARTIAL_RAT_STALLS (0xD2)
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/* Segment Register Loads */
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/* Number of segment register loads. */
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#define SEGMENT_REG_LOADS (0x06)
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/*Clocks */
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/* Number of cycles during which the processor is not halted. */
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#define CPU_CLK_UNHALTED (0x79)
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#endif /* __pmc_values_h__ */
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