mirror of https://github.com/seL4/camkes.git
drop support for Cogent
The Cogent project is no longer actively developed on top of seL4, and the upstream build has broken. Signed-off-by: Gerwin Klein <gerwin.klein@proofcraft.systems>
This commit is contained in:
Gerwin Klein
Gerwin Klein
parent
aef13286d7
commit
3eff84e818
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@ -1,66 +0,0 @@
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#
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# Copyright 2019, Data61, CSIRO (ABN 41 687 119 230)
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#
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# SPDX-License-Identifier: BSD-2-Clause
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#
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cmake_minimum_required(VERSION 3.7.2)
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project(uart_cogent C)
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# This only works on sabre
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if(
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NOT
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"${KernelArch}"
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STREQUAL
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"arm"
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OR
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NOT
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"${KernelARMPlatform}"
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STREQUAL
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"sabre"
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)
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message(FATAL_ERROR "uart application only supported on Arm sabre")
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endif()
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find_program(COGENT_TOOL NAMES "cogent")
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set(driver_src_dir ${CMAKE_CURRENT_LIST_DIR}/components/Driver/src/)
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set(c_flags "$CPPIN -o $CPPOUT -E -P -I${COGENT_PATH}/lib")
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add_custom_command(
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OUTPUT ${CMAKE_CURRENT_BINARY_DIR}/serial_pp_inferred.c
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COMMAND cp ${driver_src_dir}/serial.cogent serial.cogent
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COMMAND cp ${driver_src_dir}/serial.ac serial.ac
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COMMAND
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${COGENT_TOOL} serial.cogent -g -Od -ogenerated
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--fno-fncall-as-macro
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--ffunc-purity-attr
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--Wno-warn
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--infer-c-funcs=serial.ac
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--cpp-args=${c_flags}
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--ext-types=${driver_src_dir}/types.cfg
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--entry-funcs=${driver_src_dir}/entrypoints.cfg
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VERBATIM
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DEPENDS
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${driver_src_dir}/serial.cogent
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${driver_src_dir}/serial.ac
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${driver_src_dir}/types.cfg
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${driver_src_dir}/entrypoints.cfg
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)
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DeclareCAmkESComponent(Client SOURCES components/Client/src/client.c)
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DeclareCAmkESComponent(
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Driver
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SOURCES
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${CMAKE_CURRENT_BINARY_DIR}/serial_pp_inferred.c
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INCLUDES
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${COGENT_PATH}/lib
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)
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DeclareCAmkESRootserver(uart.camkes)
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add_simulate_test([=[
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wait_for "This message is sent via UART."
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send "abcds"
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wait_for "Input from UART: s"
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]=])
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@ -1,51 +0,0 @@
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<!--
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Copyright 2019, Data61, CSIRO (ABN 41 687 119 230)
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SPDX-License-Identifier: CC-BY-SA-4.0
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-->
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# UART driver in Cogent
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Prototype cogent UART driver for sabre. Need to have cogent installed and repository
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checked out in `./tools/cogent`.
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## To build
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```sh
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mkdir build
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cd build
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../init-build.sh -DCAMKES_APP=uart_cogent -DPLATFORM=sabre
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ninja
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```
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## To run
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```
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$ ./simulate
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qemu-system-arm -machine sabrelite -nographic -s -serial null -serial mon:stdio -m size=1024M -kernel images/capdl-loader-image-arm-imx6
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ELF-loader started on CPU: ARM Ltd. Cortex-A9 r0p0
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paddr=[20000000..2025bfff]
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ELF-loading image 'kernel'
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paddr=[10000000..10036fff]
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vaddr=[e0000000..e0036fff]
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virt_entry=e0000000
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ELF-loading image 'capdl-loader'
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paddr=[10037000..10181fff]
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vaddr=[10000..15afff]
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virt_entry=1e518
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Enabling MMU and paging
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Jumping to kernel-image entry point...
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Bootstrapping kernel
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Warning: Could not infer GIC interrupt target ID, assuming 0.
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Booting all finished, dropped to user space
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This message is sent via UART.
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Input from UART: f
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Input from UART: g
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Input from UART: d
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Input from UART: g
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Input from UART: q
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UART client exit...
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```
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@ -1,10 +0,0 @@
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/*
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* Copyright 2019, Data61, CSIRO (ABN 41 687 119 230)
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*
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* SPDX-License-Identifier: BSD-2-Clause
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*/
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component Client {
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control;
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uses uart_inf uart;
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}
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/*
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* Copyright 2019, Data61, CSIRO (ABN 41 687 119 230)
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*
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* SPDX-License-Identifier: BSD-2-Clause
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*/
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#include <camkes.h>
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#include <string.h>
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#include <stdio.h>
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#include <limits.h>
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static size_t uart_write(void *buf, size_t count)
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{
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char *data = buf;
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for (size_t i = 0; i < count; ++i) {
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uart_put_char(data[i]);
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}
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return count;
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}
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int run(void)
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{
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signed char c;
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char *str = "This message is sent via UART.\n";
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uart_write(str, strlen(str));
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while (1) {
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c = uart_get_char();
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if (c != -1) {
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printf("Input from UART: %c\n", c);
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}
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if (c == 'q') {
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break;
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}
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}
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printf("UART client exit...\n");
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return 0;
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}
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/*
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* Copyright 2019, Data61, CSIRO (ABN 41 687 119 230)
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*
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* SPDX-License-Identifier: BSD-2-Clause
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*/
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component Driver {
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provides uart_inf uart;
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dataport Buf mem;
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consumes DataAvailable irq;
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}
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@ -1,7 +0,0 @@
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--
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-- Copyright 2019, Data61, CSIRO (ABN 41 687 119 230)
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--
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-- SPDX-License-Identifier: BSD-2-Clause
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--
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uart_init_cg
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@ -1,185 +0,0 @@
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/*
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* Copyright 2019, Data61, CSIRO (ABN 41 687 119 230)
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*
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* SPDX-License-Identifier: BSD-2-Clause
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*/
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$esc:(#include <stdint.h>)
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$esc:(#include <stdlib.h>)
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$esc:(#include <string.h>)
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$esc:(#include <camkes/io.h>)
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$esc:(#include <sel4/sel4.h>)
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/* Cogent types */
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typedef void *SysState;
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#include "generated.c"
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#define UART_SR1_RRDY BIT( 9)
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#define UART_SR1_TRDY BIT(13)
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/* CR1 */
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#define UART_CR1_UARTEN BIT( 0)
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#define UART_CR1_RRDYEN BIT( 9)
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/* CR2 */
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#define UART_CR2_SRST BIT( 0)
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#define UART_CR2_RXEN BIT( 1)
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#define UART_CR2_TXEN BIT( 2)
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#define UART_CR2_ATEN BIT( 3)
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#define UART_CR2_RTSEN BIT( 4)
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#define UART_CR2_WS BIT( 5)
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#define UART_CR2_STPB BIT( 6)
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#define UART_CR2_PROE BIT( 7)
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#define UART_CR2_PREN BIT( 8)
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#define UART_CR2_RTEC BIT( 9)
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#define UART_CR2_ESCEN BIT(11)
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#define UART_CR2_CTS BIT(12)
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#define UART_CR2_CTSC BIT(13)
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#define UART_CR2_IRTS BIT(14)
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#define UART_CR2_ESCI BIT(15)
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/* CR3 */
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#define UART_CR3_RXDMUXDEL BIT( 2)
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/* FCR */
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#define UART_FCR_RFDIV(x) ((x) * BIT(7))
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#define UART_FCR_RFDIV_MASK UART_FCR_RFDIV(0x7)
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#define UART_FCR_RXTL(x) ((x) * BIT(0))
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#define UART_FCR_RXTL_MASK UART_FCR_RXTL(0x1F)
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/* SR2 */
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#define UART_SR2_RXFIFO_RDR BIT(0)
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#define UART_SR2_TXFIFO_EMPTY BIT(14)
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/* RXD */
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#define UART_URXD_READY_MASK BIT(15)
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#define UART_BYTE_MASK 0xFF
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struct imx_uart_regs {
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uint32_t rxd; /* 0x000 Receiver Register */
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uint32_t res0[15];
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uint32_t txd; /* 0x040 Transmitter Register */
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uint32_t res1[15];
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uint32_t cr1; /* 0x080 Control Register 1 */
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uint32_t cr2; /* 0x084 Control Register 2 */
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uint32_t cr3; /* 0x088 Control Register 3 */
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uint32_t cr4; /* 0x08C Control Register 4 */
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uint32_t fcr; /* 0x090 FIFO Control Register */
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uint32_t sr1; /* 0x094 Status Register 1 */
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uint32_t sr2; /* 0x098 Status Register 2 */
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uint32_t esc; /* 0x09c Escape Character Register */
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uint32_t tim; /* 0x0a0 Escape Timer Register */
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uint32_t bir; /* 0x0a4 BRM Incremental Register */
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uint32_t bmr; /* 0x0a8 BRM Modulator Register */
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uint32_t brc; /* 0x0ac Baud Rate Counter Register */
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uint32_t onems; /* 0x0b0 One Millisecond Register */
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uint32_t ts; /* 0x0b4 Test Register */
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};
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typedef volatile struct imx_uart_regs imx_uart_regs_t;
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static imx_uart_regs_t *uart_regs = NULL;
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static imx_uart_regs_t *uart_regs_from_cg($ty:(#IMXUartRegs) cgregs)
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{
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imx_uart_regs_t *regs = uart_regs;
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regs->rxd = cgregs.rxd;
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regs->txd = cgregs.txd;
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regs->cr1 = cgregs.cr1;
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regs->cr2 = cgregs.cr2;
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regs->cr3 = cgregs.cr3;
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regs->cr4 = cgregs.cr4;
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regs->fcr = cgregs.fcr;
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regs->sr1 = cgregs.sr1;
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regs->sr2 = cgregs.sr2;
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regs->esc = cgregs.esc;
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regs->tim = cgregs.tim;
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regs->bir = cgregs.bir;
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regs->bmr = cgregs.bmr;
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regs->brc = cgregs.brc;
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regs->onems = cgregs.onems;
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regs->ts = cgregs.ts;
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return regs;
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}
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static $ty:(#IMXUartRegs) uart_regs_to_cg(imx_uart_regs_t *regs)
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{
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$ty:(#IMXUartRegs) cgregs;
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cgregs.rxd = regs->rxd;
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cgregs.txd = regs->txd;
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cgregs.cr1 = regs->cr1;
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cgregs.cr2 = regs->cr2;
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cgregs.cr3 = regs->cr3;
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cgregs.cr4 = regs->cr4;
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cgregs.fcr = regs->fcr;
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cgregs.sr1 = regs->sr1;
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cgregs.sr2 = regs->sr2;
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cgregs.esc = regs->esc;
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cgregs.tim = regs->tim;
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cgregs.bir = regs->bir;
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cgregs.bmr = regs->bmr;
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cgregs.brc = regs->brc;
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cgregs.onems = regs->onems;
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cgregs.ts = regs->ts;
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return cgregs;
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}
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void irq_handle(void)
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{
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/* TODO */
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}
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char uart_get_char()
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{
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imx_uart_regs_t* regs = uart_regs;
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uint32_t reg = 0;
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int c = -1;
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if (regs->sr2 & UART_SR2_RXFIFO_RDR) {
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reg = regs->rxd;
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if (reg & UART_URXD_READY_MASK) {
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c = reg & UART_BYTE_MASK;
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}
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}
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return c;
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}
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void uart_put_char(char c)
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{
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if (c == '\n') {
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uart_put_char('\r');
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}
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/* Block until space in FIFO */
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while (!(uart_regs->sr2 & UART_SR2_TXFIFO_EMPTY)) {}
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uart_regs->txd = c;
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}
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int uart__init(void)
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{
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ps_io_ops_t ops;
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$ty:(#IMXUartRegs) regscg;
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int error = camkes_io_ops(&ops);
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ZF_LOGF_IF(error, "Failed to get malloc ops");
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/* Attempt to map the virtual address, assure this works */
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uart_regs = ps_io_map(&ops.io_mapper, 0x021E8000, 0x1000, false, PS_MEM_NORMAL);
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if (uart_regs == NULL) {
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return -1;
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}
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regscg = uart_regs_to_cg(uart_regs);
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regscg = uart_init_cg(regscg);
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uart_regs = uart_regs_from_cg(regscg);
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/* Software reset */
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while (!(uart_regs->cr2 & UART_CR2_SRST));
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return 0;
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}
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static inline u32 u64_to_u32(u64 x)
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{
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return (u32) x;
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}
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@ -1,187 +0,0 @@
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--
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-- Copyright 2019, Data61, CSIRO (ABN 41 687 119 230)
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--
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-- SPDX-License-Identifier: GPL-2.0-only
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--
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include <gum/common/common.cogent>
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const_UART_REF_CLK : U32
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const_UART_REF_CLK = 50000000
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-- UART flags
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flag_UART_SR1_RRDY : U32
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flag_UART_SR1_RRDY = 1 << 9
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flag_UART_SR1_TRDY : U32
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flag_UART_SR1_TRDY = 1 << 13
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-- CR1
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flag_UART_CR1_UARTEN : U32
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flag_UART_CR1_UARTEN = 1 << 0
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flag_UART_CR1_RRDYEN : U32
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flag_UART_CR1_RRDYEN = 1 << 9
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-- CR2
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flag_UART_CR2_SRST : U32
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flag_UART_CR2_SRST = 1 << 0
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flag_UART_CR2_RXEN : U32
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flag_UART_CR2_RXEN = 1 << 1
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flag_UART_CR2_TXEN : U32
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flag_UART_CR2_TXEN = 1 << 2
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flag_UART_CR2_ATEN : U32
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flag_UART_CR2_ATEN = 1 << 3
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flag_UART_CR2_RTSEN : U32
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flag_UART_CR2_RTSEN = 1 << 4
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flag_UART_CR2_WS : U32
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flag_UART_CR2_WS = 1 << 5
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flag_UART_CR2_STPB : U32
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flag_UART_CR2_STPB = 1 << 6
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flag_UART_CR2_PROE : U32
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flag_UART_CR2_PROE = 1 << 7
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flag_UART_CR2_PREN : U32
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flag_UART_CR2_PREN = 1 << 8
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flag_UART_CR2_RTEC : U32
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flag_UART_CR2_RTEC = 1 << 9
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flag_UART_CR2_ESCEN : U32
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flag_UART_CR2_ESCEN = 1 << 11
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flag_UART_CR2_CTS : U32
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flag_UART_CR2_CTS = 1 << 12
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flag_UART_CR2_CTSC : U32
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flag_UART_CR2_CTSC = 1 << 13
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flag_UART_CR2_IRTS : U32
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flag_UART_CR2_IRTS = 1 << 14
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flag_UART_CR2_ESCI : U32
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flag_UART_CR2_ESCI = 1 << 15
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-- CR3
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flag_UART_CR3_RXDMUXDEL : U32
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flag_UART_CR3_RXDMUXDEL = 1 << 2
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-- FCR
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uart_FCR_RFDIV : U32 -> U32
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uart_FCR_RFDIV x = x * (1 << 7)
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uart_FCR_RFDIV_MASK : () -> U32
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uart_FCR_RFDIV_MASK () = uart_FCR_RFDIV 0x7
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uart_FCR_RXTL : U32 -> U32
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uart_FCR_RXTL x = x * (1 << 0)
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uart_FCR_RXTL_MASK : () -> U32
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uart_FCR_RXTL_MASK () = uart_FCR_RXTL 0x1F
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-- SR2
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flag_UART_SR2_RXFIFO_RDR : U32
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flag_UART_SR2_RXFIFO_RDR = 1 << 0
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flag_UART_SR2_TXFIFO_EMPTY : U32
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||||
flag_UART_SR2_TXFIFO_EMPTY = 1 << 14
|
||||
|
||||
-- RXD
|
||||
flag_UART_URXD_READY_MASK : U32
|
||||
flag_UART_URXD_READY_MASK = 1 << 15
|
||||
|
||||
flag_UART_BYTE_MASK : U32
|
||||
flag_UART_BYTE_MASK = 0xFF
|
||||
|
||||
type IMXUartRegs = #{
|
||||
rxd : U32 -- 0x000 Receiver Register
|
||||
, txd : U32 -- 0x040 Transmitter Register
|
||||
, cr1 : U32 -- 0x080 Control Register 1
|
||||
, cr2 : U32 -- 0x084 Control Register 2
|
||||
, cr3 : U32 -- 0x088 Control Register 3
|
||||
, cr4 : U32 -- 0x08C Control Register 4
|
||||
, fcr : U32 -- 0x090 FIFO Control Register
|
||||
, sr1 : U32 -- 0x094 Status Register 1
|
||||
, sr2 : U32 -- 0x098 Status Register 2
|
||||
, esc : U32 -- 0x09C Escape Character Register
|
||||
, tim : U32 -- 0x0A0 Escape Timer Register
|
||||
, bir : U32 -- 0x0A4 BRM Incremental Register
|
||||
, bmr : U32 -- 0x0A8 BRM Modulator Register
|
||||
, brc : U32 -- 0x0AC Baud Rate Counter Register
|
||||
, onems : U32 -- 0x0B0 One Millisecond Register
|
||||
, ts : U32 -- 0x0B4 Test Register
|
||||
}
|
||||
|
||||
imx_uart_set_baud_cg : (#IMXUartRegs, U64) -> #IMXUartRegs
|
||||
imx_uart_set_baud_cg (regs, bps) =
|
||||
let regs { fcr, bir, bmr } = regs
|
||||
and fcr = fcr .&. complement (uart_FCR_RFDIV_MASK ())
|
||||
and fcr = fcr .|. uart_FCR_RFDIV 4
|
||||
and bir = 0xF
|
||||
and bmr = const_UART_REF_CLK / (u64_to_u32 bps - 1)
|
||||
and regs = regs { fcr, bir, bmr }
|
||||
in regs
|
||||
|
||||
type Parity = < PARITY_NONE | PARITY_EVEN | PARITY_ODD >
|
||||
|
||||
compute_cr2_by_parity : (Parity, U32) -> U32
|
||||
compute_cr2_by_parity (p, cr2) = p
|
||||
| PARITY_NONE -> let cr2 = cr2 .&. complement flag_UART_CR2_PREN
|
||||
in cr2
|
||||
| PARITY_ODD -> let cr2 = cr2 .|. flag_UART_CR2_PREN
|
||||
and cr2 = cr2 .|. flag_UART_CR2_PROE
|
||||
in cr2
|
||||
| PARITY_EVEN -> let cr2 = cr2 .|. flag_UART_CR2_PREN
|
||||
and cr2 = cr2 .&. complement flag_UART_CR2_PROE
|
||||
in cr2
|
||||
|
||||
serial_configure_cg : (#IMXUartRegs, U64, U32, Parity, U32 ) -> #IMXUartRegs
|
||||
serial_configure_cg (regs, bps, char_size, parity, stop_bits) =
|
||||
let regs { cr2 } = regs
|
||||
and cr2 =
|
||||
-- character size
|
||||
if | char_size == 8 -> cr2 .|. flag_UART_CR2_WS
|
||||
| char_size == 7 -> cr2 .&. complement flag_UART_CR2_WS
|
||||
| else -> 0 -- Need to fail here
|
||||
and cr2 =
|
||||
-- stop bits
|
||||
if | stop_bits == 2 -> cr2 .|. flag_UART_CR2_STPB
|
||||
| stop_bits == 1 -> cr2 .&. complement flag_UART_CR2_STPB
|
||||
| else -> 0 -- Need to fail here
|
||||
and cr2 = compute_cr2_by_parity (parity, cr2)
|
||||
and regs = regs { cr2 }
|
||||
and regs = imx_uart_set_baud_cg (regs, bps)
|
||||
in regs
|
||||
|
||||
uart_sw_reset_cg : #IMXUartRegs -> #IMXUartRegs
|
||||
uart_sw_reset_cg regs =
|
||||
let regs { cr2 } = regs
|
||||
and cr2 = cr2 .&. complement flag_UART_CR2_SRST
|
||||
and regs = regs { cr2 }
|
||||
in regs
|
||||
|
||||
uart_init_cg : #IMXUartRegs -> #IMXUartRegs
|
||||
uart_init_cg regs =
|
||||
let regs = uart_sw_reset_cg regs
|
||||
and regs = serial_configure_cg (regs, 115200, 8, PARITY_NONE, 1)
|
||||
-- enable the UART
|
||||
and regs { cr1, cr2, cr3, fcr } = regs
|
||||
and cr1 = cr1 .|. flag_UART_CR1_UARTEN
|
||||
and cr2 = cr2 .|. flag_UART_CR2_RXEN .|. flag_UART_CR2_TXEN
|
||||
and cr2 = cr2 .|. flag_UART_CR2_IRTS
|
||||
and cr3 = cr3 .|. flag_UART_CR3_RXDMUXDEL
|
||||
-- initialise the receiver interrupt
|
||||
and cr1 = cr1 .&. complement flag_UART_CR1_RRDYEN
|
||||
and fcr = fcr .&. complement (uart_FCR_RXTL_MASK ())
|
||||
and fcr = fcr .|. uart_FCR_RXTL 1
|
||||
and cr1 = cr1 .|. flag_UART_CR1_RRDYEN
|
||||
and regs = regs { cr1, cr2, cr3, fcr }
|
||||
in regs
|
||||
|
|
@ -1,8 +0,0 @@
|
|||
--
|
||||
-- Copyright 2019, Data61, CSIRO (ABN 41 687 119 230)
|
||||
--
|
||||
-- SPDX-License-Identifier: BSD-2-Clause
|
||||
--
|
||||
|
||||
uint32_t
|
||||
ps_io_ops_t
|
||||
|
|
@ -1,10 +0,0 @@
|
|||
/*
|
||||
* Copyright 2019, Data61, CSIRO (ABN 41 687 119 230)
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-2-Clause
|
||||
*/
|
||||
|
||||
procedure uart_inf {
|
||||
char get_char();
|
||||
void put_char(in char c);
|
||||
};
|
||||
|
|
@ -1,37 +0,0 @@
|
|||
/*
|
||||
* Copyright 2019, Data61, CSIRO (ABN 41 687 119 230)
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-2-Clause
|
||||
*/
|
||||
|
||||
import <std_connector.camkes>;
|
||||
|
||||
import "interfaces/uart.idl4";
|
||||
import "components/Driver/Driver.camkes";
|
||||
import "components/Client/Client.camkes";
|
||||
|
||||
component UART {
|
||||
hardware;
|
||||
dataport Buf mem;
|
||||
emits DataAvailable irq;
|
||||
}
|
||||
|
||||
assembly {
|
||||
composition {
|
||||
component UART uart;
|
||||
component Driver drv;
|
||||
component Client client;
|
||||
|
||||
connection seL4HardwareInterrupt irq(from uart.irq, to drv.irq);
|
||||
connection seL4HardwareMMIO uart_mem(from drv.mem, to uart.mem);
|
||||
connection seL4RPCCall uart_inf(from client.uart, to drv.uart);
|
||||
}
|
||||
|
||||
configuration {
|
||||
uart.mem_paddr = 0x021E8000;
|
||||
uart.mem_size = 0x1000;
|
||||
uart.irq_irq_number = 59;
|
||||
|
||||
random.ID = 1;
|
||||
}
|
||||
}
|
||||
|
|
@ -19,7 +19,6 @@ list(
|
|||
|
||||
set(PICOTCP_PATH "${project_dir}/projects/picotcp" CACHE INTERNAL "")
|
||||
set(OPENSBI_PATH "${project_dir}/tools/opensbi" CACHE STRING "OpenSBI Folder location")
|
||||
set(COGENT_PATH ${project_dir}/tools/cogent/cogent CACHE INTERNAL "")
|
||||
set(RUMPRUN_PATH ${project_dir}/tools/rumprun CACHE INTERNAL "")
|
||||
|
||||
set(SEL4_CONFIG_DEFAULT_ADVANCED ON)
|
||||
|
|
|
|||
|
|
@ -67,7 +67,7 @@ set(cakeml_cmake "-DCAKEMLDIR=/cakeml -DCAKEML_BIN=/cake-x64-64/cake")
|
|||
add_test_variant(cakeml_hello x86_64_sim cakeml)
|
||||
add_test_variant(cakeml_tipc x86_64_sim cakeml)
|
||||
|
||||
foreach(app IN ITEMS fdtgen epit swapcounter testhwdataportlrgpages testnto1mmio uart_cogent)
|
||||
foreach(app IN ITEMS fdtgen epit swapcounter testhwdataportlrgpages testnto1mmio)
|
||||
add_test_variant(${app} sabre_sim "")
|
||||
list(APPEND exclude_apps ${app})
|
||||
endforeach()
|
||||
|
|
|
|||
Loading…
Reference in New Issue