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[HW] Change printer for modules (#6205) 

This is quite invasive.  This converts from the functiontype printer to the moduletype printer.

---------

Co-authored-by: Mike Urbach <mikeurbach@gmail.com>
This commit is contained in:
Andrew Lenharth 2023-09-28 14:30:15 -07:00 committed by GitHub
parent 39fad38d3a
commit 164dbaf9cd
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
231 changed files with 2291 additions and 2192 deletions
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14
include/circt/Dialect/HW/HWStructure.td
View File

@ -152,10 +152,10 @@ def HWModuleOp : HWModuleOpBase<"module",
}];
let arguments = (ins SymbolNameAttr:$sym_name,
TypeAttrOf<ModuleType>:$module_type,
DictArrayAttr:$per_port_attrs,
LocationArrayAttr:$portLocs,
OptionalAttr<DictArrayAttr>:$per_port_attrs,
OptionalAttr<LocationArrayAttr>:$port_locs,
ParamDeclArrayAttr:$parameters,
StrAttr:$comment);
OptionalAttr<StrAttr>:$comment);
let results = (outs);
let regions = (region SizedRegion<1>:$body);
@ -279,8 +279,8 @@ def HWModuleExternOp : HWModuleOpBase<"module.extern"> {
}];
let arguments = (ins SymbolNameAttr:$sym_name,
TypeAttrOf<ModuleType>:$module_type,
DictArrayAttr:$per_port_attrs,
LocationArrayAttr:$portLocs,
OptionalAttr<DictArrayAttr>:$per_port_attrs,
OptionalAttr<LocationArrayAttr>:$port_locs,
ParamDeclArrayAttr:$parameters,
OptionalAttr<StrAttr>:$verilogName);
let results = (outs);
@ -370,8 +370,8 @@ def HWModuleGeneratedOp : HWModuleOpBase<"module.generated", [
let arguments = (ins SymbolNameAttr:$sym_name,
FlatSymbolRefAttr:$generatorKind,
TypeAttrOf<ModuleType>:$module_type,
DictArrayAttr:$per_port_attrs,
LocationArrayAttr:$portLocs,
OptionalAttr<DictArrayAttr>:$per_port_attrs,
OptionalAttr<LocationArrayAttr>:$port_locs,
ParamDeclArrayAttr:$parameters,
OptionalAttr<StrAttr>:$verilogName);
let results = (outs);

1
include/circt/Dialect/HW/ModuleImplementation.h
View File

@ -26,6 +26,7 @@ namespace module_like_impl {
struct PortParse : OpAsmParser::Argument {
ModulePort::Direction direction;
std::string rawName;
};
/// This is a variant of mlir::parseFunctionSignature that allows names on

4
integration_test/Bindings/Python/dialects/esi.py
View File

@ -42,13 +42,13 @@ esi.service.decl @HostComms {
esi.service.to_client @Recv : !esi.channel<i8>
}
hw.module @MsTop (%clk: i1) -> (chksum: i8) {
hw.module @MsTop (in %clk : i1, out chksum : i8) {
%c = esi.service.instance svc @HostComms impl as "test" (%clk) : (i1) -> (i8)
hw.instance "m1" @MsLoopback (clk: %clk: i1) -> ()
hw.output %c : i8
}
hw.module @MsLoopback (%clk: i1) -> () {
hw.module @MsLoopback (in %clk : i1) {
%dataIn = esi.service.req.to_client <@HostComms::@Recv> (["loopback_tohw"]) : !esi.channel<i8>
esi.service.req.to_server %dataIn -> <@HostComms::@Send> (["loopback_fromhw"]) : !esi.channel<i8>
}

4
integration_test/Bindings/Python/dialects/esi_appid.py
View File

@ -50,9 +50,9 @@ with ir.Context() as ctx, ir.Location.unknown():
appid_idx = esi.AppIDIndex(mainmod.operation)
# CHECK: hw.module.extern @ExternModA()
# CHECK: hw.module @MyMod() {
# CHECK: hw.module @MyMod()
# CHECK: hw.instance "inst1" sym @inst1 @ExternModA() -> () {esi.appid = #esi.appid<"bar"[2]>}
# CHECK: hw.module @Top() {
# CHECK: hw.module @Top()
# CHECK: hw.instance "myMod" sym @myMod @MyMod() -> ()
# CHECK: hw.instance "ext_inst1" sym @ext_inst1 @ExternModA() -> () {esi.appid = #esi.appid<"ext"[0]>}
print(mainmod)

2
integration_test/Bindings/Python/dialects/om.py
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@ -78,7 +78,7 @@ with Context() as ctx, Location.unknown():
om.class.field @list_child, %0 : !om.list<!om.class.type<@Child>>
}
hw.module @Root(%clock: i1) -> () {
hw.module @Root(in %clock: i1) {
%0 = sv.wire sym @x : !hw.inout<i1>
}
}

6
integration_test/Bindings/Python/dialects/rtl.py
View File

@ -31,7 +31,7 @@ with Context() as ctx, Location.unknown():
m = Module.create()
with InsertionPoint(m.body):
# CHECK: hw.module @MyWidget(%my_input: i32) -> (my_output: i32)
# CHECK: hw.module @MyWidget(in %my_input : i32, out my_output : i32)
# CHECK: hw.output %my_input : i32
op = hw.HWModuleOp(
name='MyWidget',
@ -39,7 +39,7 @@ with Context() as ctx, Location.unknown():
output_ports=[('my_output', i32)],
body_builder=lambda module: hw.OutputOp([module.my_input]))
# CHECK: hw.module.extern @FancyThing(%input0: i32) -> (output0: i32)
# CHECK: hw.module.extern @FancyThing(in %input0 : i32, out output0 : i32)
extern = hw.HWModuleExternOp(name="FancyThing",
input_ports=[("input0", i32)],
output_ports=[("output0", i32)])
@ -101,7 +101,7 @@ with Context() as ctx, Location.unknown():
instance_builder_tests = hw.HWModuleOp(name="instance_builder_tests",
body_builder=instance_builder_body)
# CHECK: hw.module @block_args_test(%[[PORT_NAME:.+]]: i32) ->
# CHECK: hw.module @block_args_test(in %[[PORT_NAME:.+]] : i32, out
# CHECK: hw.output %[[PORT_NAME]]
hw.HWModuleOp(name="block_args_test",
input_ports=[("foo", i32)],

2
integration_test/Bindings/Python/dialects/rtl_errors.py
View File

@ -61,7 +61,7 @@ with Context() as ctx, Location.unknown():
# Note, the error here is actually caught and printed below.
# CHECK: Uninitialized backedges remain in circuit!
# CHECK: Backedge: [[PORT_NAME:.+]]
# CHECK: InstanceOf: hw.module @one_input(%[[PORT_NAME]]: i32)
# CHECK: InstanceOf: hw.module @one_input(in %[[PORT_NAME]] : i32)
# CHECK: Instance: hw.instance "inst1" @one_input({{.+}})
inst1 = one_input.instantiate("inst1")

13
integration_test/Bindings/Tcl/Inputs/simple.mlir
View File

@ -1,23 +1,23 @@
hw.module.extern @ichi(%a: i2, %b: i3) -> (c: i4, d: i5)
hw.module.extern @ichi(in %a: i2, in %b: i3, out c: i4, out d: i5)
hw.module @owo() -> (owo_result : i32) {
hw.module @owo(out owo_result : i32) {
%0 = hw.constant 3 : i32
hw.output %0 : i32
}
hw.module @uwu() -> () { }
hw.module @uwu() { }
hw.module @nya(%nya_input : i32) -> () {
hw.module @nya(in %nya_input : i32) {
hw.instance "uwu1" @uwu() -> ()
}
hw.module @test() -> (test_result : i32) {
hw.module @test(out test_result : i32) {
%myArray1 = sv.wire : !hw.inout<array<42 x i8>>
%0 = hw.instance "owo1" @owo() -> ("owo_result" : i32)
hw.instance "nya1" @nya("nya_input": %0 : i32) -> ()
hw.output %0 : i32
}
hw.module @always() -> () {
hw.module @always() {
%clock = hw.constant 1 : i1
%3 = sv.reg : !hw.inout<i1>
%false = hw.constant 0 : i1
@ -26,4 +26,3 @@ hw.module @always() -> () {
}
hw.output
}

8
integration_test/Bindings/Tcl/simple.tcl
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@ -6,19 +6,19 @@ set circuit [circt load MLIR [lindex $argv 2]/integration_test/Bindings/Tcl/Inpu
puts $circuit
# CHECK: module {
# CHECK: hw.module.extern @ichi(%a: i2, %b: i3) -> (c: i4, d: i5)
# CHECK: hw.module @owo() -> (owo_result: i32) {
# CHECK: hw.module.extern @ichi(in %a : i2, in %b : i3, out c : i4, out d : i5)
# CHECK: hw.module @owo(out owo_result : i32) {
# CHECK: %c3_i32 = hw.constant 3 : i32
# CHECK: hw.output %c3_i32 : i32
# CHECK: }
# CHECK: hw.module @uwu() {
# CHECK: hw.output
# CHECK: }
# CHECK: hw.module @nya(%nya_input: i32) {
# CHECK: hw.module @nya(in %nya_input : i32) {
# CHECK: hw.instance "uwu1" @uwu() -> ()
# CHECK: hw.output
# CHECK: }
# CHECK: hw.module @test() -> (test_result: i32) {
# CHECK: hw.module @test(out test_result : i32) {
# CHECK: %myArray1 = sv.wire : !hw.inout<array<42xi8>>
# CHECK: %owo1.owo_result = hw.instance "owo1" @owo() -> (owo_result: i32)
# CHECK: hw.instance "nya1" @nya(nya_input: %owo1.owo_result: i32) -> ()

2
integration_test/Dialect/Calyx/custom_port_name.mlir
View File

@ -2,7 +2,7 @@
// RUN: hlstool --calyx-hw --ir %s | FileCheck %s
// CHECK: hw.module @control
// CHECK: hw.module @main(%a: i32, %b: i32, %clk: i1, %reset: i1, %go: i1) -> (out: i1, done: i1)
// CHECK: hw.module @main(in %a : i32, in %b : i32, in %clk : i1, in %reset : i1, in %go : i1, out out : i1, out done : i1)
// CHECK: hw.instance "controller" @control
func.func @main(%arg0 : i32 {calyx.port_name = "a"}, %arg1 : i32 {calyx.port_name = "b"}) -> (i1 {calyx.port_name = "out"}) {
%0 = arith.cmpi slt, %arg0, %arg1 : i32

2
integration_test/Dialect/DC/max/max.mlir
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@ -20,7 +20,7 @@
// CHECK-NEXT: ** TESTS=2 PASS=2 FAIL=0 SKIP=0
// CHECK-NEXT: ********************************
hw.module @top(%in0: !dc.value<i64>, %in1: !dc.value<i64>, %in2: !dc.value<i64>, %in3: !dc.value<i64>, %in4: !dc.value<i64>, %in5: !dc.value<i64>, %in6: !dc.value<i64>, %in7: !dc.value<i64>, %in8: !dc.token, %clock : i1, %reset : i1) -> (out0: !dc.value<i64>, out1: !dc.token) {
hw.module @top(in %in0: !dc.value<i64>, in %in1: !dc.value<i64>, in %in2: !dc.value<i64>, in %in3: !dc.value<i64>, in %in4: !dc.value<i64>, in %in5: !dc.value<i64>, in %in6: !dc.value<i64>, in %in7: !dc.value<i64>, in %in8: !dc.token, in %clock : i1, in %reset : i1, out out0: !dc.value<i64>, out out1: !dc.token) {
%token, %outputs = dc.unpack %in0 : !dc.value<i64>
%token_0, %outputs_1 = dc.unpack %in1 : !dc.value<i64>
%token_2, %outputs_3 = dc.unpack %in2 : !dc.value<i64>

14
integration_test/Dialect/ESI/cosim/basic.mlir
View File

@ -9,17 +9,17 @@
// PY: rpc.testVectorSum(25)
// PY: rpc.testCrypto(25)
hw.module.extern @IntAccNoBP(%clk: !seq.clock, %rst: i1, %ints: !esi.channel<i32>) -> (totalOut: !esi.channel<i32>) attributes {esi.bundle}
hw.module.extern @IntArrSum(%clk: !seq.clock, %rst: i1, %arr: !esi.channel<!hw.array<4 x si13>>) -> (totalOut: !esi.channel<!hw.array<2 x ui24>>) attributes {esi.bundle}
hw.module.extern @IntAccNoBP(in %clk: !seq.clock, in %rst: i1, in %ints: !esi.channel<i32>, out totalOut: !esi.channel<i32>) attributes {esi.bundle}
hw.module.extern @IntArrSum(in %clk: !seq.clock, in %rst: i1, in %arr: !esi.channel<!hw.array<4 x si13>>, out totalOut: !esi.channel<!hw.array<2 x ui24>>) attributes {esi.bundle}
hw.module @ints(%clk: !seq.clock, %rst: i1) {
hw.module @ints(in %clk: !seq.clock, in %rst: i1) {
%intsIn = esi.cosim %clk, %rst, %intsTotalBuffered, "TestEP" : !esi.channel<i32> -> !esi.channel<i32>
%intsInBuffered = esi.buffer %clk, %rst, %intsIn {stages=2, name="intChan"} : i32
%intsTotal = hw.instance "acc" @IntAccNoBP(clk: %clk: !seq.clock, rst: %rst: i1, ints: %intsInBuffered: !esi.channel<i32>) -> (totalOut: !esi.channel<i32>)
%intsTotalBuffered = esi.buffer %clk, %rst, %intsTotal {stages=2, name="totalChan"} : i32
}
hw.module @array(%clk: !seq.clock, %rst: i1) {
hw.module @array(in %clk: !seq.clock, in %rst: i1) {
%arrIn = esi.cosim %clk, %rst, %arrTotalBuffered, "TestEP" : !esi.channel<!hw.array<2 x ui24>> -> !esi.channel<!hw.array<4 x si13>>
%arrInBuffered = esi.buffer %clk, %rst, %arrIn {stages=2, name="arrChan"} : !hw.array<4 x si13>
%arrTotal = hw.instance "acc" @IntArrSum(clk: %clk: !seq.clock, rst: %rst: i1, arr: %arrInBuffered: !esi.channel<!hw.array<4 x si13>>) -> (totalOut: !esi.channel<!hw.array<2 x ui24>>)
@ -31,9 +31,9 @@ hw.module @array(%clk: !seq.clock, %rst: i1) {
!Config = !hw.struct<encrypt: i1, otp: !hw.array<32 x i8>>
!cfgChan = !esi.channel<!Config>
hw.module.extern @Encryptor(%clk: !seq.clock, %rst: i1, %in: !pktChan, %cfg: !cfgChan) -> (x: !pktChan) attributes {esi.bundle}
hw.module.extern @Encryptor(in %clk: !seq.clock, in %rst: i1, in %in: !pktChan, in %cfg: !cfgChan, out x: !pktChan) attributes {esi.bundle}
hw.module @structs(%clk:!seq.clock, %rst:i1) -> () {
hw.module @structs(in %clk:!seq.clock, in %rst:i1) {
%compressedData = hw.instance "otpCryptor" @Encryptor(clk: %clk: !seq.clock, rst: %rst: i1, in: %inputData: !pktChan, cfg: %cfg: !cfgChan) -> (x: !pktChan)
%inputData = esi.cosim %clk, %rst, %compressedData, "CryptoData" : !pktChan -> !pktChan
%c0 = hw.constant 0 : i1
@ -41,7 +41,7 @@ hw.module @structs(%clk:!seq.clock, %rst:i1) -> () {
%cfg = esi.cosim %clk, %rst, %null, "CryptoConfig" : !esi.channel<i1> -> !cfgChan
}
hw.module @top(%clk: !seq.clock, %rst: i1) {
hw.module @top(in %clk: !seq.clock, in %rst: i1) {
hw.instance "ints" @ints (clk: %clk: !seq.clock, rst: %rst: i1) -> ()
hw.instance "array" @array(clk: %clk: !seq.clock, rst: %rst: i1) -> ()
hw.instance "structs" @structs(clk: %clk: !seq.clock, rst: %rst: i1) -> ()

8
integration_test/Dialect/ESI/cosim/loopback-cpp/loopback.mlir
View File

@ -35,13 +35,13 @@
// - ./loopback_test localhost:$port ../hw/schema.capn
hw.module @intLoopback(%clk: !seq.clock, %rst:i1) -> () {
hw.module @intLoopback(in %clk: !seq.clock, in %rst:i1) {
%cosimRecv = esi.cosim %clk, %rst, %bufferedResp, "IntTestEP" {name_ext="loopback"} : !esi.channel<i32> -> !esi.channel<i32>
%bufferedResp = esi.buffer %clk, %rst, %cosimRecv {stages=1} : i32
}
!KeyText = !hw.struct<text: !hw.array<6xi14>, key: !hw.array<4xi8>>
hw.module @twoListLoopback(%clk: !seq.clock, %rst:i1) -> () {
hw.module @twoListLoopback(in %clk: !seq.clock, in %rst:i1) {
%cosim = esi.cosim %clk, %rst, %resp, "KeyTextEP" : !esi.channel<!KeyText> -> !esi.channel<!KeyText>
%resp = esi.buffer %clk, %rst, %cosim {stages=4} : !KeyText
}
@ -51,12 +51,12 @@ esi.service.decl @HostComms {
esi.service.to_client @Recv : !esi.channel<i8>
}
hw.module @TwoChanLoopback(%clk: !seq.clock) -> () {
hw.module @TwoChanLoopback(in %clk: !seq.clock) {
%dataIn = esi.service.req.to_client <@HostComms::@Recv> (["loopback_tohw"]) : !esi.channel<i8>
esi.service.req.to_server %dataIn -> <@HostComms::@Send> (["loopback_fromhw"]) : !esi.channel<i8>
}
hw.module @top(%clk: !seq.clock, %rst:i1) -> () {
hw.module @top(in %clk: !seq.clock, in %rst:i1) {
hw.instance "intLoopbackInst" @intLoopback(clk: %clk: !seq.clock, rst: %rst: i1) -> ()
hw.instance "twoListLoopbackInst" @twoListLoopback(clk: %clk: !seq.clock, rst: %rst: i1) -> ()

8
integration_test/Dialect/ESI/cosim/loopback.mlir
View File

@ -7,13 +7,13 @@
// RUN: esi-cosim-runner.py --schema %t2.capnp --exec %S/loopback.py %t6/*.sv
hw.module @intLoopback(%clk: !seq.clock, %rst:i1) -> () {
hw.module @intLoopback(in %clk: !seq.clock, in %rst:i1) {
%cosimRecv = esi.cosim %clk, %rst, %bufferedResp, "IntTestEP" {name_ext="loopback"} : !esi.channel<i32> -> !esi.channel<i32>
%bufferedResp = esi.buffer %clk, %rst, %cosimRecv {stages=1} : i32
}
!KeyText = !hw.struct<text: !hw.array<6xi14>, key: !hw.array<4xi8>>
hw.module @twoListLoopback(%clk: !seq.clock, %rst:i1) -> () {
hw.module @twoListLoopback(in %clk: !seq.clock, in %rst:i1) {
%cosim = esi.cosim %clk, %rst, %resp, "KeyTextEP" : !esi.channel<!KeyText> -> !esi.channel<!KeyText>
%resp = esi.buffer %clk, %rst, %cosim {stages=4} : !KeyText
}
@ -23,12 +23,12 @@ esi.service.decl @HostComms {
esi.service.to_client @Recv : !esi.channel<i8>
}
hw.module @TwoChanLoopback(%clk: !seq.clock) -> () {
hw.module @TwoChanLoopback(in %clk: !seq.clock) {
%dataIn = esi.service.req.to_client <@HostComms::@Recv> (["loopback_tohw"]) : !esi.channel<i8>
esi.service.req.to_server %dataIn -> <@HostComms::@Send> (["loopback_fromhw"]) : !esi.channel<i8>
}
hw.module @top(%clk: !seq.clock, %rst:i1) -> () {
hw.module @top(in %clk: !seq.clock, in %rst:i1) {
hw.instance "intLoopbackInst" @intLoopback(clk: %clk: !seq.clock, rst: %rst: i1) -> ()
hw.instance "twoListLoopbackInst" @twoListLoopback(clk: %clk: !seq.clock, rst: %rst: i1) -> ()

6
integration_test/Dialect/ESI/system/basic.mlir
View File

@ -3,9 +3,9 @@
// RUN: circt-opt %t1.mlir -export-verilog -verify-diagnostics -o t3.mlir > %t2.sv
// RUN: circt-rtl-sim.py %t2.sv %ESI_COLLATERAL_PATH%/ESIPrimitives.sv %S/../supplements/integers.sv --cycles 150 | FileCheck %s
hw.module.extern @IntCountProd(%clk: !seq.clock, %rst: i1) -> (ints: !esi.channel<i32>) attributes {esi.bundle}
hw.module.extern @IntAcc(%clk: !seq.clock, %rst: i1, %ints: !esi.channel<i32>) -> (totalOut: i32) attributes {esi.bundle}
hw.module @top(%clk: !seq.clock, %rst: i1) -> (totalOut: i32) {
hw.module.extern @IntCountProd(in %clk: !seq.clock, in %rst: i1, out ints: !esi.channel<i32>) attributes {esi.bundle}
hw.module.extern @IntAcc(in %clk: !seq.clock, in %rst: i1, in %ints: !esi.channel<i32>, out totalOut: i32) attributes {esi.bundle}
hw.module @top(in %clk: !seq.clock, in %rst: i1, out totalOut: i32) {
%intStream = hw.instance "prod" @IntCountProd(clk: %clk: !seq.clock, rst: %rst: i1) -> (ints: !esi.channel<i32>)
%intStreamBuffered = esi.buffer %clk, %rst, %intStream {stages=2, name="intChan"} : i32
%totalOut = hw.instance "acc" @IntAcc(clk: %clk: !seq.clock, rst: %rst: i1, ints: %intStreamBuffered: !esi.channel<i32>) -> (totalOut: i32)

2
integration_test/Dialect/Pipeline/nonstallable/test1/nonstallable_test1.mlir
View File

@ -10,7 +10,7 @@
// CHECK: ** TEST
// CHECK: ** TESTS=[[N:.*]] PASS=[[N]] FAIL=0 SKIP=0
hw.module @nonstallable_test1(%arg0: i32, %go: i1, %clock: !seq.clock, %reset: i1, %stall: i1) -> (out: i32, done: i1) {
hw.module @nonstallable_test1(in %arg0: i32, in %go: i1, in %clock: !seq.clock, in %reset: i1, in %stall: i1, out out: i32, out done: i1) {
%out, %done = pipeline.scheduled "nonstallable_test1"(%a0 : i32 = %arg0)
stall(%stall) clock(%clock) reset(%reset) go(%go) entryEn(%s0_enable)
{stallability = [true, false, false, true, true]} -> (out : i32) {

2
integration_test/Dialect/Pipeline/nonstallable/test2/nonstallable_test2.mlir
View File

@ -10,7 +10,7 @@
// CHECK: ** TEST
// CHECK: ** TESTS=[[N:.*]] PASS=[[N]] FAIL=0 SKIP=0
hw.module @nonstallable_test2(%arg0: i32, %go: i1, %clock: !seq.clock, %reset: i1, %stall: i1) -> (out: i32, done : i1) {
hw.module @nonstallable_test2(in %arg0: i32, in %go: i1, in %clock: !seq.clock, in %reset: i1, in %stall: i1, out out: i32, out done : i1) {
%out, %done = pipeline.scheduled "nonstallable_test2"(%a0 : i32 = %arg0)
stall(%stall) clock(%clock) reset(%reset) go(%go) entryEn(%s0_enable)
{stallability = [true, false, true, false, true]} -> (out : i32) {

2
integration_test/Dialect/Pipeline/simple/simple.mlir
View File

@ -20,7 +20,7 @@
// CHECK: ** TEST
// CHECK: ** TESTS=[[N:.*]] PASS=[[N]] FAIL=0 SKIP=0
hw.module @simple(%arg0 : i32, %arg1 : i32, %go : i1, %clock : !seq.clock, %reset : i1) -> (out: i32, done : i1) {
hw.module @simple(in %arg0 : i32, in %arg1 : i32, in %go : i1, in %clock : !seq.clock, in %reset : i1, out out: i32, out done : i1) {
%out, %done = pipeline.scheduled(%a0 : i32 = %arg0, %a1 : i32 = %arg1) clock(%clock) reset(%reset) go(%go) entryEn(%s0_enable) -> (out: i32) {
%add0 = comb.add %a0, %a1 : i32
pipeline.stage ^bb1

2
integration_test/Dialect/Pipeline/stall/stallTest.mlir
View File

@ -20,7 +20,7 @@
// CHECK: ** TEST
// CHECK: ** TESTS=[[N:.*]] PASS=[[N]] FAIL=0 SKIP=0
hw.module @stallTest(%arg0 : i32, %arg1 : i32, %go : i1, %stall : i1, %clock : !seq.clock, %reset : i1) -> (out: i32, done : i1) {
hw.module @stallTest(in %arg0 : i32, in %arg1 : i32, in %go : i1, in %stall : i1, in %clock : !seq.clock, in %reset : i1, out out: i32, out done : i1) {
%out, %done = pipeline.scheduled(%a0 : i32 = %arg0, %a1 : i32 = %arg1) stall(%stall) clock(%clock) reset(%reset) go(%go) entryEn(%s0_enable) -> (out: i32) {
%add0 = comb.add %a0, %a1 : i32
pipeline.stage ^bb1

2
integration_test/Dialect/Seq/fifo/fifo.mlir
View File

@ -7,7 +7,7 @@
// CHECK: ** TEST
// CHECK: ** TESTS=[[N:.*]] PASS=[[N]] FAIL=0 SKIP=0
hw.module @fifo(%clk : !seq.clock, %rst : i1, %inp : i32, %rdEn : i1, %wrEn : i1) -> (out: i32, empty: i1, full: i1, almost_empty : i1, almost_full : i1) {
hw.module @fifo(in %clk : !seq.clock, in %rst : i1, in %inp : i32, in %rdEn : i1, in %wrEn : i1, out out: i32, out empty: i1, out full: i1, out almost_empty : i1, out almost_full : i1) {
%out, %full, %empty, %almostFull, %almostEmpty = seq.fifo depth 4 almost_full 2 almost_empty 1 in %inp rdEn %rdEn wrEn %wrEn clk %clk rst %rst : i32
hw.output %out, %empty, %full, %almostEmpty, %almostFull : i32, i1, i1, i1, i1
}

2
integration_test/Dialect/Seq/registers.mlir
View File

@ -11,7 +11,7 @@
sv.macro.decl @INIT_RANDOM_PROLOG_
sv.macro.def @INIT_RANDOM_PROLOG_ ""
hw.module @top(%clk: !seq.clock, %rst: i1) {
hw.module @top(in %clk: !seq.clock, in %rst: i1) {
%cst0 = hw.constant 0 : i32
%cst1 = hw.constant 1 : i32

6
integration_test/EmitVerilog/basic.mlir
View File

@ -5,7 +5,7 @@
module {
// The HW dialect doesn't have any sequential constructs yet. So don't do
// much.
hw.module @top(%clk: i1, %rst: i1) {
hw.module @top(in %clk: i1, in %rst: i1) {
%c1 = hw.instance "aaa" @AAA () -> (f: i1)
%c1Shl = hw.instance "shl" @shl (a: %c1: i1) -> (b: i1)
sv.always posedge %clk {
@ -14,12 +14,12 @@ module {
}
}
hw.module @AAA() -> (f: i1) {
hw.module @AAA(out f: i1) {
%z = hw.constant 1 : i1
hw.output %z : i1
}
hw.module @shl(%a: i1) -> (b: i1) {
hw.module @shl(in %a: i1, out b: i1) {
%0 = comb.shl %a, %a : i1
hw.output %0 : i1
}

38
integration_test/EmitVerilog/lint.mlir
View File

@ -8,44 +8,44 @@
// RUN: verilator --lint-only --top-module exprInlineTestIssue439 %t1.sv
// RUN: verilator --lint-only --top-module StructDecls %t1.sv
hw.module @B(%a: i1) -> (b: i1, c: i1) {
hw.module @B(in %a: i1, out b: i1, out c: i1) {
%0 = comb.or %a, %a : i1
%1 = comb.and %a, %a : i1
hw.output %0, %1 : i1, i1
}
hw.module @A(%d: i1, %e: i1) -> (f: i1) {
hw.module @A(in %d: i1, in %e: i1, out f: i1) {
%1 = comb.mux %d, %d, %e : i1
hw.output %1 : i1
}
hw.module @AAA(%d: i1, %e: i1) -> (f: i1) {
hw.module @AAA(in %d: i1, in %e: i1, out f: i1) {
%z = hw.constant 0 : i1
hw.output %z : i1
}
hw.module @AB(%w: i1, %x: i1) -> (y: i1, z: i1) {
hw.module @AB(in %w: i1, in %x: i1, out y: i1, out z: i1) {
%w2 = hw.instance "a1" @AAA(d: %w: i1, e: %w1: i1) -> (f: i1)
%w1, %y = hw.instance "b1" @B(a: %w2: i1) -> (b: i1, c: i1)
hw.output %y, %x : i1, i1
}
hw.module @shl(%a: i1) -> (b: i1) {
hw.module @shl(in %a: i1, out b: i1) {
%0 = comb.shl %a, %a : i1
hw.output %0 : i1
}
hw.module @TESTSIMPLE(%a: i4, %b: i4, %cond: i1, %array: !hw.array<10xi4>,
%uarray: !hw.uarray<16xi8>) -> (
r0: i4, r1: i4, r2: i4, r3: i4,
r4: i4, r5: i4, r6: i4, r7: i4,
r8: i4, r9: i4, r10: i4, r11: i4,
r12: i4, r13: i1,
r14: i1, r15: i1, r16: i1, r17: i1,
r18: i1, r19: i1, r20: i1, r21: i1,
r22: i1, r23: i1,
r24: i12, r25: i2, r27: i4, r28: i4,
r29: !hw.array<3xi4>
hw.module @TESTSIMPLE(in %a: i4, in %b: i4, in %cond: i1, in %array: !hw.array<10xi4>,
in %uarray: !hw.uarray<16xi8>,
out r0: i4, out r1: i4, out r2: i4, out r3: i4,
out r4: i4, out r5: i4, out r6: i4, out r7: i4,
out r8: i4, out r9: i4, out r10: i4, out r11: i4,
out r12: i4, out r13: i1,
out r14: i1, out r15: i1, out r16: i1, out r17: i1,
out r18: i1, out r19: i1, out r20: i1, out r21: i1,
out r22: i1, out r23: i1,
out r24: i12, out r25: i2, out r27: i4, out r28: i4,
out r29: !hw.array<3xi4>
) {
%0 = comb.add %a, %b : i4
@ -91,7 +91,7 @@ hw.module @TESTSIMPLE(%a: i4, %b: i4, %cond: i1, %array: !hw.array<10xi4>,
i12,i2, i4, i4, !hw.array<3xi4>
}
hw.module @exprInlineTestIssue439(%clk: i1) {
hw.module @exprInlineTestIssue439(in %clk: i1) {
%c = hw.constant 0 : i32
sv.always posedge %clk {
@ -102,7 +102,7 @@ hw.module @exprInlineTestIssue439(%clk: i1) {
}
}
hw.module @casts(%in1: i64) -> (r1: !hw.array<5xi8>) {
hw.module @casts(in %in1: i64, out r1: !hw.array<5xi8>) {
%bits = hw.bitcast %in1 : (i64) -> !hw.array<64xi1>
%idx = hw.constant 10 : i6
%midBits = hw.array_slice %bits[%idx] : (!hw.array<64xi1>) -> !hw.array<40xi1>
@ -115,7 +115,7 @@ hw.module @StructDecls() {
%reg2 = sv.reg : !hw.inout<array<8xstruct<a: i1, b: i1>>>
}
hw.module @UniformArrayCreate() -> (arr: !hw.array<5xi8>) {
hw.module @UniformArrayCreate(out arr: !hw.array<5xi8>) {
%c0_i8 = hw.constant 0 : i8
%arr = hw.array_create %c0_i8, %c0_i8, %c0_i8, %c0_i8, %c0_i8 : i8
hw.output %arr : !hw.array<5xi8>

13
integration_test/EmitVerilog/standards-verilator.mlir
View File

@ -16,12 +16,13 @@
// RUN: verilator --lint-only +1800-2012ext+sv %t1.2012.sv
// RUN: verilator --lint-only +1800-2017ext+sv %t1.2017.sv
hw.module @top(%clock : i1, %reset: i1,
%a: i4,
%s: !hw.struct<foo: i2, bar: i4>,
%parray: !hw.array<10xi4>,
%uarray: !hw.uarray<16xi8>)
-> (r0: i4, r1: i4) {
hw.module @top(in %clock : i1, in %reset: i1,
in %a: i4,
in %s: !hw.struct<foo: i2, bar: i4>,
in %parray: !hw.array<10xi4>,
in %uarray: !hw.uarray<16xi8>,
out r0: i4,
out r1: i4) {
%0 = comb.or %a, %a : i4
%1 = comb.and %a, %a : i4

2
integration_test/EmitVerilog/standards-vlog.mlir
View File

@ -16,7 +16,7 @@
// RUN: vlog -lint -sv -sv12compat %t1.2012.sv
// RUN: vlog -lint -sv -sv17compat %t1.2017.sv
hw.module @top(%clock : i1, %reset: i1,
hw.module @top(in %clock : i1, in %reset: i1,
%a: i4,
%s: !hw.struct<foo: i2, bar: i4>,
%parray: !hw.array<10xi4>,

4
integration_test/EmitVerilog/sv-interfaces.mlir
View File

@ -14,10 +14,10 @@ module {
// TODO: This ugly bit is because we don't yet have ExportVerilog support
// for modports as module port declarations.
hw.module.extern @Rcvr (%m: !sv.modport<@data_vr::@data_in>)
hw.module.extern @Rcvr (in %m: !sv.modport<@data_vr::@data_in>)
sv.verbatim "module Rcvr (data_vr.data_in m);\nendmodule"
hw.module @top (%clk: i1, %rst: i1) {
hw.module @top (in %clk: i1, in %rst: i1) {
%iface = sv.interface.instance : !sv.interface<@data_vr>
%ifaceInPort = sv.modport.get %iface @data_in :

2
integration_test/circt-lec/builtin.mlir
View File

@ -5,6 +5,6 @@
// RUN: circt-lec %s -v=false | FileCheck %s --check-prefix=BUILTIN_MODULE
// BUILTIN_MODULE: c1 == c2
hw.module @basic(%in: i1) -> (out: i1) {
hw.module @basic(in %in: i1, out out: i1) {
hw.output %in : i1
}

46
integration_test/circt-lec/comb.mlir
View File

@ -1,11 +1,11 @@
// These tests will be only enabled if circt-lec is built.
// REQUIRES: circt-lec
hw.module @basic(%in: i1) -> (out: i1) {
hw.module @basic(in %in: i1, out out: i1) {
hw.output %in : i1
}
hw.module @not(%in: i1) -> (out: i1) {
hw.module @not(in %in: i1, out out: i1) {
%true = hw.constant true
%out = comb.xor bin %in, %true : i1
hw.output %out : i1
@ -15,18 +15,18 @@ hw.module @not(%in: i1) -> (out: i1) {
// RUN: circt-lec %s -c1=adder -c2=completeAdder -v=false | FileCheck %s --check-prefix=COMB_ADD
// COMB_ADD: c1 == c2
hw.module @adder(%in1: i2, %in2: i2) -> (out: i2) {
hw.module @adder(in %in1: i2, in %in2: i2, out out: i2) {
%sum = comb.add bin %in1, %in2 : i2
hw.output %sum : i2
}
hw.module @halfAdder(%in1: i1, %in2: i1) -> (carry: i1, sum: i1) {
hw.module @halfAdder(in %in1: i1, in %in2: i1, out carry: i1, out sum: i1) {
%sum = comb.xor bin %in1, %in2 : i1
%carry = comb.and bin %in1, %in2 : i1
hw.output %carry, %sum: i1, i1
}
hw.module @completeAdder(%in1: i2, %in2 : i2) -> (out: i2) {
hw.module @completeAdder(in %in1: i2, in %in2 : i2, out out: i2) {
%in1_0 = comb.extract %in1 from 0 : (i2) -> i1
%in1_1 = comb.extract %in1 from 1 : (i2) -> i1
%in2_0 = comb.extract %in2 from 0 : (i2) -> i1
@ -42,12 +42,12 @@ hw.module @completeAdder(%in1: i2, %in2 : i2) -> (out: i2) {
// RUN: circt-lec %s -c1=and -c2=decomposedAnd -v=false | FileCheck %s --check-prefix=COMB_AND
// COMB_AND: c1 == c2
hw.module @and(%in1: i1, %in2: i1) -> (out: i1) {
hw.module @and(in %in1: i1, in %in2: i1, out out: i1) {
%out = comb.and bin %in1, %in2 : i1
hw.output %out : i1
}
hw.module @decomposedAnd(%in1: i1, %in2: i1) -> (out: i1) {
hw.module @decomposedAnd(in %in1: i1, in %in2: i1, out out: i1) {
%not_in1 = hw.instance "n_in1" @not(in: %in1: i1) -> (out: i1)
%not_in2 = hw.instance "n_in2" @not(in: %in2: i1) -> (out: i1)
%not_and = comb.or bin %not_in1, %not_in2 : i1
@ -80,13 +80,13 @@ hw.module @decomposedAnd(%in1: i1, %in2: i1) -> (out: i1) {
// RUN: circt-lec %s -c1=mulBy2 -c2=addTwice -v=false | FileCheck %s --check-prefix=COMB_MUL
// COMB_MUL: c1 == c2
hw.module @mulBy2(%in: i2) -> (out: i2) {
hw.module @mulBy2(in %in: i2, out out: i2) {
%two = hw.constant 2 : i2
%res = comb.mul bin %in, %two : i2
hw.output %res : i2
}
hw.module @addTwice(%in: i2) -> (out: i2) {
hw.module @addTwice(in %in: i2, out out: i2) {
%res = comb.add bin %in, %in : i2
hw.output %res : i2
}
@ -95,12 +95,12 @@ hw.module @addTwice(%in: i2) -> (out: i2) {
// RUN: circt-lec %s -c1=mux -c2=decomposedMux -v=false | FileCheck %s --check-prefix=COMB_MUX
// COMB_MUX: c1 == c2
hw.module @mux(%cond: i1, %tvalue: i8, %fvalue: i8) -> (out: i8) {
hw.module @mux(in %cond: i1, in %tvalue: i8, in %fvalue: i8, out out: i8) {
%res = comb.mux bin %cond, %tvalue, %fvalue : i8
hw.output %res : i8
}
hw.module @decomposedMux(%cond: i1, %tvalue: i8, %fvalue: i8) -> (out: i8) {
hw.module @decomposedMux(in %cond: i1, in %tvalue: i8, in %fvalue: i8, out out: i8) {
%cond_bar = hw.instance "n" @not(in: %cond: i1) -> (out: i1)
%lead_0 = hw.constant 0 : i7
%c_t = comb.concat %lead_0, %cond : i7, i1
@ -115,12 +115,12 @@ hw.module @decomposedMux(%cond: i1, %tvalue: i8, %fvalue: i8) -> (out: i8) {
// RUN: circt-lec %s -c1=or -c2=decomposedOr -v=false | FileCheck %s --check-prefix=COMB_OR
// COMB_OR: c1 == c2
hw.module @or(%in1: i1, %in2: i1) -> (out: i1) {
hw.module @or(in %in1: i1, in %in2: i1, out out: i1) {
%out = comb.or bin %in1, %in2 : i1
hw.output %out : i1
}
hw.module @decomposedOr(%in1: i1, %in2: i1) -> (out: i1) {
hw.module @decomposedOr(in %in1: i1, in %in2: i1, out out: i1) {
%not_in1 = hw.instance "n_in1" @not(in: %in1: i1) -> (out: i1)
%not_in2 = hw.instance "n_in2" @not(in: %in2: i1) -> (out: i1)
%not_or = comb.and bin %not_in1, %not_in2 : i1
@ -132,12 +132,12 @@ hw.module @decomposedOr(%in1: i1, %in2: i1) -> (out: i1) {
// RUN: circt-lec %s -c1=parity -c2=decomposedParity -v=false | FileCheck %s --check-prefix=COMB_PARITY
// COMB_PARITY: c1 == c2
hw.module @parity(%in: i8) -> (out: i1) {
hw.module @parity(in %in: i8, out out: i1) {
%res = comb.parity bin %in : i8
hw.output %res : i1
}
hw.module @decomposedParity(%in: i8) -> (out: i1) {
hw.module @decomposedParity(in %in: i8, out out: i1) {
%b0 = comb.extract %in from 0 : (i8) -> i1
%b1 = comb.extract %in from 1 : (i8) -> i1
%b2 = comb.extract %in from 2 : (i8) -> i1
@ -154,12 +154,12 @@ hw.module @decomposedParity(%in: i8) -> (out: i1) {
// RUN: circt-lec %s -c1=replicate -c2=decomposedReplicate -v=false | FileCheck %s --check-prefix=COMB_REPLICATE
// COMB_REPLICATE: c1 == c2
hw.module @replicate(%in: i2) -> (out: i8) {
hw.module @replicate(in %in: i2, out out: i8) {
%res = comb.replicate %in : (i2) -> i8
hw.output %res : i8
}
hw.module @decomposedReplicate(%in: i2) -> (out: i8) {
hw.module @decomposedReplicate(in %in: i2, out out: i8) {
%res = comb.concat %in, %in, %in, %in : i2, i2, i2, i2
hw.output %res : i8
}
@ -168,12 +168,12 @@ hw.module @decomposedReplicate(%in: i2) -> (out: i8) {
// RUN: circt-lec %s -c1=shl -c2=decomposedShl -v=false | FileCheck %s --check-prefix=COMB_SHL
// COMB_SHL: c1 == c2
hw.module @shl(%in1: i2, %in2: i2) -> (out: i2) {
hw.module @shl(in %in1: i2, in %in2: i2, out out: i2) {
%res = comb.shl bin %in1, %in2 : i2
hw.output %res : i2
}
hw.module @decomposedShl(%in1: i2, %in2: i2) -> (out: i2) {
hw.module @decomposedShl(in %in1: i2, in %in2: i2, out out: i2) {
%zero = hw.constant 0 : i2
%one = hw.constant 1 : i2
%two = hw.constant 2 : i2
@ -202,26 +202,26 @@ hw.module @decomposedShl(%in1: i2, %in2: i2) -> (out: i2) {
// RUN: circt-lec %s -c1=subtractor -c2=completeSubtractor -v=false | FileCheck %s --check-prefix=COMB_SUB
// COMB_SUB: c1 == c2
hw.module @subtractor(%in1: i8, %in2: i8) -> (out: i8) {
hw.module @subtractor(in %in1: i8, in %in2: i8, out out: i8) {
%diff = comb.sub bin %in1, %in2 : i8
hw.output %diff : i8
}
hw.module @halfSubtractor(%in1: i1, %in2: i1) -> (borrow: i1, diff: i1) {
hw.module @halfSubtractor(in %in1: i1, in %in2: i1, out borrow: i1, out diff: i1) {
%diff = comb.xor bin %in1, %in2 : i1
%not_in1 = hw.instance "n_in1" @not(in: %in1: i1) -> (out: i1)
%borrow = comb.and bin %not_in1, %in2 : i1
hw.output %borrow, %diff: i1, i1
}
hw.module @fullSubtractor(%in1: i1, %in2: i1, %b_in: i1) -> (borrow: i1, diff: i1) {
hw.module @fullSubtractor(in %in1: i1, in %in2: i1, in %b_in: i1, out borrow: i1, out diff: i1) {
%b1, %d1 = hw.instance "s1" @halfSubtractor(in1: %in1: i1, in2: %in2: i1) -> (borrow: i1, diff: i1)
%b2, %d_out = hw.instance "s2" @halfSubtractor(in1: %d1: i1, in2: %b_in: i1) -> (borrow: i1, diff: i1)
%b_out = comb.or bin %b1, %b2 : i1
hw.output %b_out, %d_out: i1, i1
}
hw.module @completeSubtractor(%in1: i8, %in2 : i8) -> (out: i8) {
hw.module @completeSubtractor(in %in1: i8, in %in2 : i8, out out: i8) {
%in1_0 = comb.extract %in1 from 0 : (i8) -> i1
%in1_1 = comb.extract %in1 from 1 : (i8) -> i1
%in1_2 = comb.extract %in1 from 2 : (i8) -> i1

4
integration_test/circt-lec/commandline.mlir
View File

@ -8,11 +8,11 @@
// CHECK: c1 == c2
//--- first.mlir
hw.module @basic(%in: i1) -> (out: i1) {
hw.module @basic(in %in: i1, out out: i1) {
hw.output %in : i1
}
//--- second.mlir
hw.module @basic(%in: i1) -> (out: i1) {
hw.module @basic(in %in: i1, out out: i1) {
hw.output %in : i1
}

18
integration_test/circt-lec/hw.mlir
View File

@ -1,7 +1,7 @@
// These tests will be only enabled if circt-lec is built.
// REQUIRES: circt-lec
hw.module @basic(%in: i1) -> (out: i1) {
hw.module @basic(in %in: i1, out out: i1) {
hw.output %in : i1
}
@ -9,14 +9,14 @@ hw.module @basic(%in: i1) -> (out: i1) {
// RUN: circt-lec %s -c1=basic -c2=notnot -v=false | FileCheck %s --check-prefix=HW_CONSTANT
// HW_CONSTANT: c1 == c2
hw.module @onePlusTwo() -> (out: i2) {
hw.module @onePlusTwo(out out: i2) {
%one = hw.constant 1 : i2
%two = hw.constant 2 : i2
%three = comb.add bin %one, %two : i2
hw.output %three : i2
}
hw.module @three() -> (out: i2) {
hw.module @three(out out: i2) {
%three = hw.constant 3 : i2
hw.output %three : i2
}
@ -25,13 +25,13 @@ hw.module @three() -> (out: i2) {
// RUN: circt-lec %s -c1=basic -c2=notnot -v=false | FileCheck %s --check-prefix=HW_INSTANCE
// HW_INSTANCE: c1 == c2
hw.module @not(%in: i1) -> (out: i1) {
hw.module @not(in %in: i1, out out: i1) {
%true = hw.constant true
%out = comb.xor bin %in, %true : i1
hw.output %out : i1
}
hw.module @notnot(%in: i1) -> (out: i1) {
hw.module @notnot(in %in: i1, out out: i1) {
%n = hw.instance "n" @not(in: %in: i1) -> (out: i1)
%nn = hw.instance "nn" @not(in: %n: i1) -> (out: i1)
hw.output %nn : i1
@ -41,17 +41,17 @@ hw.module @notnot(%in: i1) -> (out: i1) {
// RUN: circt-lec %s -c1=basic -c2=basic -v=false | FileCheck %s --check-prefix=HW_OUTPUT
// HW_OUTPUT: c1 == c2
hw.module @constZeroZero(%in: i1) -> (o1: i1, o2: i1) {
hw.module @constZeroZero(in %in: i1, out o1: i1, out o2: i1) {
%zero = hw.constant 0 : i1
hw.output %zero, %zero : i1, i1
}
hw.module @xorZeroZero(%in: i1) -> (o1: i1, o2: i1) {
hw.module @xorZeroZero(in %in: i1, out o1: i1, out o2: i1) {
%zero = comb.xor bin %in, %in : i1
hw.output %zero, %zero : i1, i1
}
hw.module @constZeroOne(%in: i1) -> (o1: i1, o2: i1) {
hw.module @constZeroOne(in %in: i1, out o1: i1, out o2: i1) {
%zero = hw.constant 0 : i1
%one = hw.constant 1 : i1
hw.output %zero, %one : i1, i1
@ -65,7 +65,7 @@ hw.module @constZeroOne(%in: i1) -> (o1: i1, o2: i1) {
// RUN: not circt-lec %s -c1=constZeroZero -c2=constZeroOne -v=false | FileCheck %s --check-prefix=TWOOUTPUTSFAIL
// TWOOUTPUTSFAIL: c1 != c2
hw.module @onePlusTwoNonSSA() -> (out: i2) {
hw.module @onePlusTwoNonSSA(out out: i2) {
%three = comb.add bin %one, %two : i2
%one = hw.constant 1 : i2
%two = hw.constant 2 : i2

22
lib/Bindings/Python/dialects/_hw_ops_ext.py
View File

@ -97,14 +97,10 @@ class InstanceBuilder(support.NamedValueOpView):
instance_of=self.module)
def operand_names(self):
arg_names = ArrayAttr(self.module.attributes["argNames"])
arg_name_attrs = map(StringAttr, arg_names)
return list(map(lambda s: s.value, arg_name_attrs))
return self.module.type.input_names
def result_names(self):
arg_names = ArrayAttr(self.module.attributes["resultNames"])
arg_name_attrs = map(StringAttr, arg_names)
return list(map(lambda s: s.value, arg_name_attrs))
return self.module.type.output_names
class ModuleLike:
@ -154,7 +150,6 @@ class ModuleLike:
module_ports.append(input_port)
input_names.append(input_name)
port_locs.append(unknownLoc)
attributes["argNames"] = ArrayAttr.get(input_names)
output_types = []
output_names = []
@ -165,8 +160,7 @@ class ModuleLike:
module_ports.append(output_port)
output_names.append(output_name)
port_locs.append(unknownLoc)
attributes["resultNames"] = ArrayAttr.get(output_names)
attributes["portLocs"] = ArrayAttr.get(port_locs)
attributes["port_locs"] = ArrayAttr.get(port_locs)
attributes["per_port_attrs"] = ArrayAttr.get([])
if len(parameters) > 0 or "parameters" not in attributes:
@ -329,10 +323,9 @@ class HWModuleOp(ModuleLike):
@property
def input_indices(self):
indices: dict[int, str] = {}
op_names = ArrayAttr(self.attributes["argNames"])
op_names = self.type.input_names
for idx, name in enumerate(op_names):
str_name = StringAttr(name).value
indices[str_name] = idx
indices[name] = idx
return indices
# Support attribute access to block arguments by name
@ -349,10 +342,7 @@ class HWModuleOp(ModuleLike):
return ret
def outputs(self) -> dict[str:Type]:
result_names = [
StringAttr(name).value
for name in ArrayAttr(self.attributes["resultNames"])
]
result_names = self.type.output_names
result_types = self.type.output_types
return dict(zip(result_names, result_types))

176
lib/Dialect/HW/HWOps.cpp
View File

@ -589,7 +589,7 @@ buildModule(OpBuilder &builder, OperationState &result, StringAttr name,
auto type = ModuleType::get(builder.getContext(), portTypes);
result.addAttribute(ModuleTy::getModuleTypeAttrName(result.name),
TypeAttr::get(type));
result.addAttribute("portLocs", builder.getArrayAttr(portLocs));
result.addAttribute("port_locs", builder.getArrayAttr(portLocs));
result.addAttribute("per_port_attrs",
arrayOrEmpty(builder.getContext(), portAttrs));
result.addAttribute("parameters", parameters);
@ -920,6 +920,35 @@ static void addArgAndResultAttrsHW(Builder &builder, OperationState &result,
addArgAndResultAttrsHW(builder, result, argAttrs, resultAttrs);
}
static void
addPortAttrsAndLocs(Builder &builder, OperationState &result,
SmallVectorImpl<module_like_impl::PortParse> &ports,
StringAttr portAttrsName, StringAttr portLocsName) {
auto unknownLoc = builder.getUnknownLoc();
auto nonEmptyAttrsFn = [](Attribute attr) {
return attr && !cast<DictionaryAttr>(attr).empty();
};
auto nonEmptyLocsFn = [unknownLoc](Attribute attr) {
return attr && cast<Location>(attr) != unknownLoc;
};
// Convert the specified array of dictionary attrs (which may have null
// entries) to an ArrayAttr of dictionaries.
SmallVector<Attribute> attrs;
SmallVector<Attribute> locs;
for (auto &port : ports) {
attrs.push_back(port.attrs ? port.attrs : builder.getDictionaryAttr({}));
locs.push_back(port.sourceLoc ? Location(*port.sourceLoc) : unknownLoc);
}
// Add the attributes to the ports.
if (llvm::any_of(attrs, nonEmptyAttrsFn))
result.addAttribute(portAttrsName, builder.getArrayAttr(attrs));
if (llvm::any_of(locs, nonEmptyLocsFn))
result.addAttribute(portLocsName, builder.getArrayAttr(locs));
}
template <typename ModuleTy>
static ParseResult parseHWModuleOp(OpAsmParser &parser, OperationState &result,
ExternModKind modKind = PlainMod) {
@ -950,51 +979,30 @@ static ParseResult parseHWModuleOp(OpAsmParser &parser, OperationState &result,
if (parseOptionalParameterList(parser, parameters))
return failure();
// Parse the function signature.
bool isVariadic = false;
SmallVector<OpAsmParser::Argument, 4> entryArgs;
SmallVector<Attribute> argNames;
SmallVector<Attribute> argLocs;
SmallVector<Attribute> resultNames;
SmallVector<DictionaryAttr> resultAttrs;
SmallVector<Attribute> resultLocs;
TypeAttr functionType;
if (failed(module_like_impl::parseModuleFunctionSignature(
parser, isVariadic, entryArgs, argNames, argLocs, resultNames,
resultAttrs, resultLocs, functionType)))
SmallVector<module_like_impl::PortParse> ports;
TypeAttr modType;
if (failed(module_like_impl::parseModuleSignature(parser, ports, modType)))
return failure();
// Parse the attribute dict.
if (failed(parser.parseOptionalAttrDictWithKeyword(result.attributes)))
return failure();
if (hasAttribute("resultNames", result.attributes) ||
hasAttribute("parameters", result.attributes)) {
parser.emitError(
loc, "explicit `resultNames` / `parameters` attributes not allowed");
if (hasAttribute("parameters", result.attributes)) {
parser.emitError(loc, "explicit `parameters` attributes not allowed");
return failure();
}
SmallVector<Attribute> portLocs;
portLocs.append(argLocs.begin(), argLocs.end());
portLocs.append(resultLocs.begin(), resultLocs.end());
auto *context = result.getContext();
// prefer the attribute over the ssa values
auto attr = getAttribute("argNames", result.attributes);
auto modType = detail::fnToMod(
cast<FunctionType>(functionType.getValue()),
attr ? cast<ArrayAttr>(attr).getValue() : argNames, resultNames);
result.attributes.erase("argNames");
result.addAttribute("portLocs", ArrayAttr::get(context, portLocs));
result.addAttribute("parameters", parameters);
if (!hasAttribute("comment", result.attributes))
result.addAttribute("comment", StringAttr::get(context, ""));
result.addAttribute(ModuleTy::getModuleTypeAttrName(result.name),
TypeAttr::get(modType));
result.addAttribute(ModuleTy::getModuleTypeAttrName(result.name), modType);
addPortAttrsAndLocs(parser.getBuilder(), result, ports,
ModuleTy::getPerPortAttrsAttrName(result.name),
ModuleTy::getPortLocsAttrName(result.name));
// Add the attributes to the function arguments.
addArgAndResultAttrsHW(parser.getBuilder(), result, entryArgs, resultAttrs);
SmallVector<OpAsmParser::Argument, 4> entryArgs;
for (auto &port : ports)
if (port.direction != ModulePort::Direction::Output)
entryArgs.push_back(port);
// Parse the optional function body.
auto *body = result.addRegion();
@ -1031,14 +1039,7 @@ FunctionType getHWModuleOpType(Operation *op) {
template <typename ModuleTy>
static void printModuleOp(OpAsmPrinter &p, ModuleTy mod) {
using namespace mlir::function_interface_impl;
FunctionType fnType = mod.getHWModuleType().getFuncType();
auto argTypes = fnType.getInputs();
auto resultTypes = fnType.getResults();
p << ' ';
// Print the visibility of the module.
StringRef visibilityAttrName = SymbolTable::getVisibilityAttrName();
if (auto visibility = mod.getOperation()->template getAttrOfType<StringAttr>(
@ -1053,40 +1054,25 @@ static void printModuleOp(OpAsmPrinter &p, ModuleTy mod) {
}
// Print the parameter list if present.
printOptionalParameterList(
p, mod.getOperation(),
mod.getOperation()->template getAttrOfType<ArrayAttr>("parameters"));
printOptionalParameterList(p, mod.getOperation(), mod.getParameters());
bool needArgNamesAttr = false;
module_like_impl::printModuleSignature(p, mod.getOperation(), argTypes,
/*isVariadic=*/false, resultTypes,
needArgNamesAttr);
module_like_impl::printModuleSignatureNew(p, mod.getOperation());
SmallVector<StringRef, 3> omittedAttrs;
if (isa<HWModuleGeneratedOp>(mod.getOperation()))
omittedAttrs.push_back("generatorKind");
if (!needArgNamesAttr)
omittedAttrs.push_back("argNames");
omittedAttrs.push_back("portLocs");
omittedAttrs.push_back(
ModuleTy::getModuleTypeAttrName(mod.getOperation()->getName()));
omittedAttrs.push_back("per_port_attrs");
omittedAttrs.push_back("resultNames");
omittedAttrs.push_back("parameters");
omittedAttrs.push_back(mod.getPortLocsAttrName());
omittedAttrs.push_back(mod.getModuleTypeAttrName());
omittedAttrs.push_back(mod.getPerPortAttrsAttrName());
omittedAttrs.push_back(mod.getParametersAttrName());
omittedAttrs.push_back(visibilityAttrName);
omittedAttrs.push_back(SymbolTable::getSymbolAttrName());
if (mod.getOperation()
->template getAttrOfType<StringAttr>("comment")
.getValue()
.empty())
omittedAttrs.push_back("comment");
// inject argNames
auto attrs = mod->getAttrs();
SmallVector<NamedAttribute> realAttrs(attrs.begin(), attrs.end());
realAttrs.push_back(
NamedAttribute(StringAttr::get(mod.getContext(), "argNames"),
ArrayAttr::get(mod.getContext(), mod.getInputNames())));
p.printOptionalAttrDictWithKeyword(realAttrs, omittedAttrs);
if (auto cmt =
mod.getOperation()->template getAttrOfType<StringAttr>("comment"))
if (cmt.getValue().empty())
omittedAttrs.push_back("comment");
mlir::function_interface_impl::printFunctionAttributes(p, mod.getOperation(),
omittedAttrs);
}
void HWModuleExternOp::print(OpAsmPrinter &p) { printModuleOp(p, *this); }
@ -1247,9 +1233,12 @@ template <typename ModTy>
static SmallVector<Location> getAllPortLocs(ModTy module) {
SmallVector<Location> retval;
auto locs = module.getPortLocs();
for (auto l : locs)
retval.push_back(cast<Location>(l));
assert(!locs.size() || locs.size() == module.getNumPorts());
if (locs) {
for (auto l : *locs)
retval.push_back(cast<Location>(l));
// Either we have a length of 0 or the correct length
assert(!locs->size() || locs->size() == module.getNumPorts());
}
return retval;
}
@ -1311,22 +1300,22 @@ void HWModuleGeneratedOp::setAllPortNames(ArrayRef<Attribute> names) {
SmallVector<Attribute> HWModuleOp::getAllPortAttrs() {
auto attrs = getPerPortAttrs();
if (attrs && !attrs.empty())
return {attrs.getValue().begin(), attrs.getValue().end()};
if (attrs && !attrs->empty())
return {attrs->getValue().begin(), attrs->getValue().end()};
return SmallVector<Attribute>(getNumPorts());
}
SmallVector<Attribute> HWModuleExternOp::getAllPortAttrs() {
auto attrs = getPerPortAttrs();
if (attrs && !attrs.empty())
return {attrs.getValue().begin(), attrs.getValue().end()};
if (attrs && !attrs->empty())
return {attrs->getValue().begin(), attrs->getValue().end()};
return SmallVector<Attribute>(getNumPorts());
}
SmallVector<Attribute> HWModuleGeneratedOp::getAllPortAttrs() {
auto attrs = getPerPortAttrs();
if (attrs && !attrs.empty())
return {attrs.getValue().begin(), attrs.getValue().end()};
if (attrs && !attrs->empty())
return {attrs->getValue().begin(), attrs->getValue().end()};
return SmallVector<Attribute>(getNumPorts());
}
@ -3214,35 +3203,6 @@ void TriggeredOp::build(OpBuilder &builder, OperationState &odsState,
// Temporary test module
//===----------------------------------------------------------------------===//
static void
addPortAttrsAndLocs(Builder &builder, OperationState &result,
SmallVectorImpl<module_like_impl::PortParse> &ports,
StringAttr portAttrsName, StringAttr portLocsName) {
auto unknownLoc = builder.getUnknownLoc();
auto nonEmptyAttrsFn = [](Attribute attr) {
return attr && !cast<DictionaryAttr>(attr).empty();
};
auto nonEmptyLocsFn = [unknownLoc](Attribute attr) {
return attr && cast<Location>(attr) != unknownLoc;
};
// Convert the specified array of dictionary attrs (which may have null
// entries) to an ArrayAttr of dictionaries.
SmallVector<Attribute> attrs;
SmallVector<Attribute> locs;
for (auto &port : ports) {
attrs.push_back(port.attrs ? port.attrs : builder.getDictionaryAttr({}));
locs.push_back(port.sourceLoc ? Location(*port.sourceLoc) : unknownLoc);
}
// Add the attributes to the ports.
if (llvm::any_of(attrs, nonEmptyAttrsFn))
result.addAttribute(portAttrsName, builder.getArrayAttr(attrs));
if (llvm::any_of(locs, nonEmptyLocsFn))
result.addAttribute(portLocsName, builder.getArrayAttr(locs));
}
void HWTestModuleOp::print(OpAsmPrinter &p) {
p << ' ';
// Print the visibility of the module.

130
lib/Dialect/HW/ModuleImplementation.cpp
View File

@ -241,13 +241,26 @@ ParseResult module_like_impl::parseModuleFunctionSignature(
// New Style
////////////////////////////////////////////////////////////////////////////////
/// Parse an optional keyword or string and set instance into 'result'.`
ParseResult parseOptionalKeywordOrOptionalString(OpAsmParser &p,
std::string *result) {
StringRef keyword;
if (succeeded(p.parseOptionalKeyword(&keyword))) {
*result = keyword.str();
return success();
}
p.parseOptionalString(result);
return success();
}
static ParseResult parseDirection(OpAsmParser &p, ModulePort::Direction &dir) {
StringRef key;
if (failed(p.parseKeyword(&key)))
return p.emitError(p.getCurrentLocation(), "expected port direction");
if (key == "input")
if (key == "in")
dir = ModulePort::Direction::Input;
else if (key == "output")
else if (key == "out")
dir = ModulePort::Direction::Output;
else if (key == "inout")
dir = ModulePort::Direction::InOut;
@ -257,22 +270,65 @@ static ParseResult parseDirection(OpAsmParser &p, ModulePort::Direction &dir) {
return success();
}
static ParseResult parseInputPort(OpAsmParser &parser,
module_like_impl::PortParse &result) {
if (parser.parseOperand(result.ssaName, /*allowResultNumber=*/false))
return failure();
NamedAttrList attrs;
// Parse the result name.
if (parseOptionalKeywordOrOptionalString(parser, &result.rawName))
return failure();
if (parser.parseColonType(result.type) ||
parser.parseOptionalAttrDict(attrs) ||
parser.parseOptionalLocationSpecifier(result.sourceLoc))
return failure();
result.attrs = attrs.getDictionary(parser.getContext());
return success();
}
static ParseResult parseOutputPort(OpAsmParser &parser,
module_like_impl::PortParse &result) {
// Stash the current location parser location.
auto irLoc = parser.getCurrentLocation();
// Parse the result name.
if (parser.parseKeywordOrString(&result.rawName))
return failure();
// Parse the results type.
if (parser.parseColonType(result.type))
return failure();
// Parse the result attributes.
NamedAttrList attrs;
if (failed(parser.parseOptionalAttrDict(attrs)))
return failure();
result.attrs = attrs.getDictionary(parser.getContext());
// Parse the result location.
std::optional<Location> maybeLoc;
if (failed(parser.parseOptionalLocationSpecifier(maybeLoc)))
return failure();
result.sourceLoc = maybeLoc ? *maybeLoc : parser.getEncodedSourceLoc(irLoc);
return success();
}
/// Parse a single argument with the following syntax:
///
/// direction `%ssaname : !type { optionalAttrDict} loc(optionalSourceLoc)`
/// output (id|string) : !type { optionalAttrDict} loc(optionalSourceLoc)`
/// (input|inout) %ssaname : !type { optionalAttrDict} loc(optionalSourceLoc)`
///
/// If `allowType` is false or `allowAttrs` are false then the respective
/// parts of the grammar are not parsed.
static ParseResult parsePort(OpAsmParser &p,
module_like_impl::PortParse &result) {
NamedAttrList attrs;
if (parseDirection(p, result.direction) ||
p.parseOperand(result.ssaName, /*allowResultNumber=*/false) ||
p.parseColonType(result.type) || p.parseOptionalAttrDict(attrs) ||
p.parseOptionalLocationSpecifier(result.sourceLoc))
if (parseDirection(p, result.direction))
return failure();
result.attrs = attrs.getDictionary(p.getContext());
return success();
if (result.direction == ModulePort::Direction::Output)
return parseOutputPort(p, result);
return parseInputPort(p, result);
}
static ParseResult
@ -297,8 +353,13 @@ ParseResult module_like_impl::parseModuleSignature(
// Process the ssa args for the information we're looking for.
SmallVector<ModulePort> ports;
for (auto &arg : args) {
ports.push_back({parsing_util::getNameFromSSA(context, arg.ssaName.name),
arg.type, arg.direction});
std::string name = arg.rawName;
if (arg.direction != ModulePort::Output)
name = parsing_util::getNameFromSSA(context, arg.ssaName.name).str();
ports.push_back({StringAttr::get(context, name), arg.type, arg.direction});
// rewrite type AFTER constructing ports. This will be used in block args.
if (arg.direction == ModulePort::InOut)
arg.type = InOutType::get(arg.type);
if (!arg.sourceLoc)
arg.sourceLoc = parser.getEncodedSourceLoc(arg.ssaName.location);
}
@ -309,9 +370,9 @@ ParseResult module_like_impl::parseModuleSignature(
static const char *directionAsString(ModulePort::Direction dir) {
if (dir == ModulePort::Direction::Input)
return "input";
return "in";
if (dir == ModulePort::Direction::Output)
return "output";
return "out";
if (dir == ModulePort::Direction::InOut)
return "inout";
assert(0 && "Unknown port direction");
@ -321,11 +382,15 @@ static const char *directionAsString(ModulePort::Direction dir) {
void module_like_impl::printModuleSignatureNew(OpAsmPrinter &p, Operation *op) {
Region &body = op->getRegion(0);
bool isExternal = body.empty();
SmallString<32> resultNameStr;
mlir::OpPrintingFlags flags;
unsigned curArg = 0;
auto typeAttr = op->getAttrOfType<TypeAttr>("module_type");
auto modType = cast<ModuleType>(typeAttr.getValue());
auto portAttrs = op->getAttrOfType<ArrayAttr>("port_attrs");
auto portAttrs = op->getAttrOfType<ArrayAttr>("per_port_attrs");
auto locAttrs = op->getAttrOfType<ArrayAttr>("port_locs");
p << '(';
@ -333,19 +398,40 @@ void module_like_impl::printModuleSignatureNew(OpAsmPrinter &p, Operation *op) {
if (i > 0)
p << ", ";
p.printKeywordOrString(directionAsString(port.dir));
p << " %";
p.printKeywordOrString(port.name);
if (port.dir == ModulePort::Direction::Output) {
p << " ";
p.printKeywordOrString(port.name);
} else {
if (!isExternal) {
// Get the printed format for the argument name.
resultNameStr.clear();
llvm::raw_svector_ostream tmpStream(resultNameStr);
p.printOperand(body.front().getArgument(curArg), tmpStream);
p << " " << tmpStream.str();
// If the name wasn't printable in a way that agreed with argName, make
// sure to print out an explicit argNames attribute.
if (tmpStream.str().drop_front() != port.name) {
p << " ";
p.printKeywordOrString(port.name);
}
} else {
p << " %" << port.name.getValue();
}
++curArg;
}
p << " : ";
p.printType(port.type);
if (auto attr = dyn_cast<DictionaryAttr>(portAttrs[i]))
p.printOptionalAttrDict(attr.getValue());
if (portAttrs && !portAttrs.empty())
if (auto attr = dyn_cast<DictionaryAttr>(portAttrs[i]))
p.printOptionalAttrDict(attr.getValue());
// TODO: `printOptionalLocationSpecifier` will emit aliases for locations,
// even if they are not printed. This will have to be fixed upstream. For
// now, use what was specified on the command line.
if (flags.shouldPrintDebugInfo())
if (flags.shouldPrintDebugInfo() && locAttrs)
if (auto loc = locAttrs[i])
p.printOptionalLocationSpecifier(cast<Location>(loc));
if (!isa<UnknownLoc>(loc))
p.printOptionalLocationSpecifier(cast<Location>(loc));
}
p << ')';

2
lib/Transforms/StripDebugInfoWithPred.cpp
View File

@ -89,7 +89,7 @@ void StripDebugInfoWithPred::runOnOperation() {
updateLocIfChanged(op, getStrippedLoc(op->getLoc()));
updateLocArray(op, "argLocs");
updateLocArray(op, "resultLocs");
updateLocArray(op, "portLocs");
updateLocArray(op, "port_locs");
// Strip block arguments debug info.
for (Region &region : op->getRegions())
for (Block &block : region.getBlocks())

2
llvm

@ -1 +1 @@
Subproject commit 56f7c7e52fe34fefda217b1194f681333159a809
Subproject commit a5e10e248efc72e7909e4067060e89c35a456a18

18
test/Analysis/infer-top-level.mlir
View File

@ -2,12 +2,12 @@
// CHECK: module attributes {test.top = ["baz"]}
module {
hw.module @bar() -> () {}
hw.module @foo() -> () {
hw.module @bar() {}
hw.module @foo() {
hw.instance "bar" @bar() -> ()
}
hw.module @baz() -> () {
hw.module @baz() {
hw.instance "foo" @foo() -> ()
}
}
@ -17,15 +17,15 @@ module {
// Test cycle through a component
// expected-error @+1 {{'builtin.module' op cannot deduce top level module - cycle detected in instance graph (bar->baz->foo->bar).}}
module {
hw.module @bar() -> () {
hw.module @bar() {
hw.instance "baz" @baz() -> ()
}
hw.module @foo() -> () {
hw.module @foo() {
hw.instance "bar" @bar() -> ()
}
hw.module @baz() -> () {
hw.module @baz() {
hw.instance "foo" @foo() -> ()
}
}
@ -35,13 +35,13 @@ module {
// test multiple candidate top components
// CHECK: module attributes {test.top = ["bar", "foo"]}
module {
hw.module @bar() -> () {
hw.module @bar() {
hw.instance "baz" @baz() -> ()
}
hw.module @foo() -> () {
hw.module @foo() {
hw.instance "baz" @baz() -> ()
}
hw.module @baz() -> () {}
hw.module @baz() {}
}

6
test/Conversion/CalyxToHW/primitives.mlir
View File

@ -1,6 +1,6 @@
// RUN: circt-opt --split-input-file -lower-calyx-to-hw %s | FileCheck %s
// CHECK: hw.module @main(%in0: i4, %clk: i1, %reset: i1, %go: i1) -> (out0: i8, done: i1) {
// CHECK: hw.module @main(in %in0 : i4, in %clk : i1, in %reset : i1, in %go : i1, out out0 : i8, out done : i1) {
// CHECK: %out0 = sv.wire : !hw.inout<i8>
// CHECK: %0 = sv.read_inout %out0 : !hw.inout<i8>
// CHECK: %done = sv.wire : !hw.inout<i1>
@ -33,7 +33,7 @@ module attributes {calyx.entrypoint = "main"} {
// -----
// CHECK: hw.module @main(%in0: i4, %clk: i1, %reset: i1, %go: i1) -> (out0: i8, done: i1) {
// CHECK: hw.module @main(in %in0 : i4, in %clk : i1, in %reset : i1, in %go : i1, out out0 : i8, out done : i1) {
// CHECK: %out0 = sv.wire : !hw.inout<i8>
// CHECK: %0 = sv.read_inout %out0 : !hw.inout<i8>
// CHECK: %done = sv.wire : !hw.inout<i1>
@ -67,7 +67,7 @@ module attributes {calyx.entrypoint = "main"} {
// -----
// CHECK: hw.module @main(%in0: i8, %in1: i8, %cond0: i1, %cond1: i1, %clk: i1, %reset: i1, %go: i1) -> (out: i8, done: i1) {
// CHECK: hw.module @main(in %in0 : i8, in %in1 : i8, in %cond0 : i1, in %cond1 : i1, in %clk : i1, in %reset : i1, in %go : i1, out out : i8, out done : i1) {
// CHECK: %out = sv.wire : !hw.inout<i8>
// CHECK: %0 = sv.read_inout %out : !hw.inout<i8>
// CHECK: %done = sv.wire : !hw.inout<i1>

2
test/Conversion/CombToArith/comb-to-arith.mlir
View File

@ -1,7 +1,7 @@
// RUN: circt-opt %s --convert-comb-to-arith | FileCheck %s
// CHECK-LABEL: @test
hw.module @test(%arg0: i32, %arg1: i32, %arg2: i32, %arg3: i32, %arg4: i1) -> () {
hw.module @test(in %arg0: i32, in %arg1: i32, in %arg2: i32, in %arg3: i32, in %arg4: i1) {
// CHECK-NEXT: %c42_i32 = arith.constant 42 : i32
%c42_i32 = hw.constant 42 : i32

28
test/Conversion/ConvertToArcs/convert-to-arcs.mlir
View File

@ -8,10 +8,10 @@ hw.module @Empty() {
// CHECK-LABEL: hw.module @Passthrough(
// CHECK-SAME: [[TMP:%.+]]: i4) -> (z: i4) {
// CHECK-SAME: in [[TMP:%.+]] : i4, out z : i4) {
// CHECK-NEXT: hw.output [[TMP]]
// CHECK-NEXT: }
hw.module @Passthrough(%a: i4) -> (z: i4) {
hw.module @Passthrough(in %a: i4, out z: i4) {
hw.output %a : i4
}
@ -25,7 +25,7 @@ hw.module @Passthrough(%a: i4) -> (z: i4) {
// CHECK-NEXT: }
// CHECK-LABEL: hw.module @CombOnly
hw.module @CombOnly(%i0: i4, %i1: i4) -> (z: i4) {
hw.module @CombOnly(in %i0: i4, in %i1: i4, out z: i4) {
// CHECK-NEXT: [[TMP:%.+]] = arc.state @CombOnly_arc(%i0, %i1) lat 0
// CHECK-NEXT: hw.output [[TMP]]
%0 = comb.add %i0, %i1 : i4
@ -43,7 +43,7 @@ hw.module @CombOnly(%i0: i4, %i1: i4) -> (z: i4) {
// CHECK-NEXT: }
// CHECK-LABEL: hw.module @SplitAtConstants
hw.module @SplitAtConstants() -> (z: i4) {
hw.module @SplitAtConstants(out z: i4) {
// CHECK-NEXT: %c1_i4 = hw.constant 1
// CHECK-NEXT: [[TMP:%.+]] = arc.state @SplitAtConstants_arc(%c1_i4) lat 0
// CHECK-NEXT: hw.output [[TMP]]
@ -70,7 +70,7 @@ hw.module @SplitAtConstants() -> (z: i4) {
// CHECK-NEXT: }
// CHECK-LABEL: hw.module @Pipeline
hw.module @Pipeline(%clock: !seq.clock, %i0: i4, %i1: i4) -> (z: i4) {
hw.module @Pipeline(in %clock: !seq.clock, in %i0: i4, in %i1: i4, out z: i4) {
// CHECK-NEXT: [[S0:%.+]] = arc.state @Pipeline_arc(%i0, %i1) clock %clock lat 1
// CHECK-NEXT: [[S1:%.+]] = arc.state @Pipeline_arc_0([[S0]], %i0) clock %clock lat 1
// CHECK-NEXT: [[S2:%.+]] = arc.state @Pipeline_arc_1([[S1]], %i1) lat 0
@ -94,7 +94,7 @@ hw.module @Pipeline(%clock: !seq.clock, %i0: i4, %i1: i4) -> (z: i4) {
// CHECK-NEXT: }
// CHECK-LABEL: hw.module @Reshuffling
hw.module @Reshuffling(%clockA: !seq.clock, %clockB: !seq.clock) -> (z0: i4, z1: i4, z2: i4, z3: i4) {
hw.module @Reshuffling(in %clockA: !seq.clock, in %clockB: !seq.clock, out z0: i4, out z1: i4, out z2: i4, out z3: i4) {
// CHECK-NEXT: hw.instance "x" @Reshuffling2()
// CHECK-NEXT: arc.state @Reshuffling_arc(%x.z0, %x.z1) clock %clockA lat 1
// CHECK-NEXT: arc.state @Reshuffling_arc_0(%x.z2, %x.z3) clock %clockB lat 1
@ -108,7 +108,7 @@ hw.module @Reshuffling(%clockA: !seq.clock, %clockB: !seq.clock) -> (z0: i4, z1:
}
// CHECK-NEXT: }
hw.module.extern private @Reshuffling2() -> (z0: i4, z1: i4, z2: i4, z3: i4)
hw.module.extern private @Reshuffling2(out z0: i4, out z1: i4, out z2: i4, out z3: i4)
// CHECK-LABEL: arc.define @FactorOutCommonOps_arc(
@ -127,7 +127,7 @@ hw.module.extern private @Reshuffling2() -> (z0: i4, z1: i4, z2: i4, z3: i4)
// CHECK-NEXT: }
// CHECK-LABEL: hw.module @FactorOutCommonOps
hw.module @FactorOutCommonOps(%clock: !seq.clock, %i0: i4, %i1: i4) -> (o0: i4, o1: i4) {
hw.module @FactorOutCommonOps(in %clock: !seq.clock, in %i0: i4, in %i1: i4, out o0: i4, out o1: i4) {
// CHECK-DAG: [[T0:%.+]] = arc.state @FactorOutCommonOps_arc_1(%i0, %i1) lat 0
%0 = comb.add %i0, %i1 : i4
// CHECK-DAG: [[T1:%.+]] = arc.state @FactorOutCommonOps_arc([[T0]], %i0) clock %clock lat 1
@ -153,7 +153,7 @@ hw.module @FactorOutCommonOps(%clock: !seq.clock, %i0: i4, %i1: i4) -> (o0: i4,
// CHECK-NEXT: }
// CHECK-LABEL: hw.module @SplitAtInstance(
hw.module @SplitAtInstance(%a: i4) -> (z: i4) {
hw.module @SplitAtInstance(in %a: i4, out z: i4) {
// CHECK-DAG: [[T0:%.+]] = arc.state @SplitAtInstance_arc(%a) lat 0
// CHECK-DAG: [[T1:%.+]] = hw.instance "x" @SplitAtInstance2(a: [[T0]]: i4)
// CHECK-DAG: [[T2:%.+]] = arc.state @SplitAtInstance_arc_0([[T1]]) lat 0
@ -165,11 +165,11 @@ hw.module @SplitAtInstance(%a: i4) -> (z: i4) {
}
// CHECK-NEXT: }
hw.module.extern private @SplitAtInstance2(%a: i4) -> (z: i4)
hw.module.extern private @SplitAtInstance2(in %a: i4, out z: i4)
// CHECK-LABEL: hw.module @AbsorbNames
hw.module @AbsorbNames(%clock: !seq.clock) -> () {
hw.module @AbsorbNames(in %clock: !seq.clock) {
// CHECK-NEXT: %x.z0, %x.z1 = hw.instance "x" @AbsorbNames2()
// CHECK-NEXT: arc.state @AbsorbNames_arc(%x.z0, %x.z1) clock %clock lat 1
// CHECK-SAME: {names = ["myRegA", "myRegB"]}
@ -180,14 +180,14 @@ hw.module @AbsorbNames(%clock: !seq.clock) -> () {
}
// CHECK-NEXT: }
hw.module.extern @AbsorbNames2() -> (z0: i4, z1: i4)
hw.module.extern @AbsorbNames2(out z0: i4, out z1: i4)
// CHECK: arc.define @[[TRIVIAL_ARC:.+]]([[ARG0:%.+]]: i4)
// CHECK-NEXT: arc.output [[ARG0]]
// CHECK-NEXT: }
// CHECK-LABEL: hw.module @Trivial(
hw.module @Trivial(%clock: !seq.clock, %i0: i4, %reset: i1) -> (out: i4) {
hw.module @Trivial(in %clock: !seq.clock, in %i0: i4, in %reset: i1, out out: i4) {
// CHECK: [[RES0:%.+]] = arc.state @[[TRIVIAL_ARC]](%i0) clock %clock reset %reset lat 1 {names = ["foo"]
// CHECK-NEXT: hw.output [[RES0:%.+]]
%0 = hw.constant 0 : i4
@ -205,7 +205,7 @@ hw.module @Trivial(%clock: !seq.clock, %i0: i4, %reset: i1) -> (out: i4) {
// CHECK-NEXT: }
// CHECK-LABEL: hw.module @NonTrivial(
hw.module @NonTrivial(%clock: !seq.clock, %i0: i4, %reset1: i1, %reset2: i1) -> (out1: i4, out2: i4) {
hw.module @NonTrivial(in %clock: !seq.clock, in %i0: i4, in %reset1: i1, in %reset2: i1, out out1: i4, out out2: i4) {
// CHECK: [[RES2:%.+]] = arc.state @[[NONTRIVIAL_ARC_0]](%i0) clock %clock reset %reset1 lat 1 {names = ["foo"]
// CHECK-NEXT: [[RES3:%.+]] = arc.state @[[NONTRIVIAL_ARC_1]](%i0) clock %clock reset %reset2 lat 1 {names = ["bar"]
// CHECK-NEXT: hw.output [[RES2]], [[RES3]]

47
test/Conversion/DCToHW/basic.mlir
View File

@ -1,37 +1,37 @@
// RUN: circt-opt --lower-dc-to-hw %s | FileCheck %s
// CHECK-LABEL: hw.module @simple(
// CHECK-SAME: %[[VAL_0:.*]]: !esi.channel<i0>, %[[VAL_1:.*]]: !esi.channel<i64>, %[[VAL_2:.*]]: i1, %[[VAL_3:.*]]: !esi.channel<i1>) -> (out0: !esi.channel<i0>, out1: !esi.channel<i64>, out2: i1, out3: !esi.channel<i1>) attributes {argNames = ["", "", "", ""]} {
// CHECK: in %[[VAL_0:.*]] "" : !esi.channel<i0>, in %[[VAL_1:.*]] "" : !esi.channel<i64>, in %[[VAL_2:.*]] "" : i1, in %[[VAL_3:.*]] "" : !esi.channel<i1>, out out0 : !esi.channel<i0>, out out1 : !esi.channel<i64>, out out2 : i1, out out3 : !esi.channel<i1>) {
// CHECK: hw.output %[[VAL_0]], %[[VAL_1]], %[[VAL_2]], %[[VAL_3]] : !esi.channel<i0>, !esi.channel<i64>, i1, !esi.channel<i1>
// CHECK: }
hw.module @simple(%0 : !dc.token, %1 : !dc.value<i64>, %2 : i1, %3 : !dc.value<i1>)
-> (out0: !dc.token, out1: !dc.value<i64>, out2: i1, out3: !dc.value<i1>) {
hw.module @simple(in %0 "" : !dc.token, in %1 "" : !dc.value<i64>, in %2 "" : i1, in %3 : !dc.value<i1>,
out out0: !dc.token, out out1: !dc.value<i64>, out out2: i1, out out3: !dc.value<i1>) {
hw.output %0, %1, %2, %3 : !dc.token, !dc.value<i64>, i1, !dc.value<i1>
}
// CHECK-LABEL: hw.module @pack(
// CHECK-SAME: %[[VAL_0:.*]]: !esi.channel<i0>, %[[VAL_1:.*]]: i64) -> (out0: !esi.channel<i64>) {
// CHECK: in %[[VAL_0:.*]] : !esi.channel<i0>, in %[[VAL_1:.*]] : i64, out out0 : !esi.channel<i64>) {
// CHECK: %[[VAL_2:.*]], %[[VAL_3:.*]] = esi.unwrap.vr %[[VAL_0]], %[[VAL_4:.*]] : i0
// CHECK: %[[VAL_5:.*]], %[[VAL_4]] = esi.wrap.vr %[[VAL_1]], %[[VAL_3]] : i64
// CHECK: hw.output %[[VAL_5]] : !esi.channel<i64>
hw.module @pack(%token : !dc.token, %v1 : i64) -> (out0: !dc.value<i64>) {
hw.module @pack(in %token : !dc.token, in %v1 : i64, out out0: !dc.value<i64>) {
%out = dc.pack %token, %v1 : i64
hw.output %out : !dc.value<i64>
}
// CHECK-LABEL: hw.module @unpack(
// CHECK-SAME: %[[VAL_0:.*]]: !esi.channel<i64>) -> (out0: !esi.channel<i0>, out1: i64) {
// CHECK: in %[[VAL_0:.*]] : !esi.channel<i64>, out out0 : !esi.channel<i0>, out out1 : i64) {
// CHECK: %[[VAL_1:.*]], %[[VAL_2:.*]] = esi.unwrap.vr %[[VAL_0]], %[[VAL_3:.*]] : i64
// CHECK: %[[VAL_4:.*]] = hw.constant 0 : i0
// CHECK: %[[VAL_5:.*]], %[[VAL_3]] = esi.wrap.vr %[[VAL_4]], %[[VAL_2]] : i0
// CHECK: hw.output %[[VAL_5]], %[[VAL_1]] : !esi.channel<i0>, i64
hw.module @unpack(%v : !dc.value<i64>) -> (out0: !dc.token, out1: i64) {
hw.module @unpack(in %v : !dc.value<i64>, out out0: !dc.token, out out1: i64) {
%out:2 = dc.unpack %v : !dc.value<i64>
hw.output %out#0, %out#1 : !dc.token, i64
}
// CHECK-LABEL: hw.module @join(
// CHECK-SAME: %[[VAL_0:.*]]: !esi.channel<i0>, %[[VAL_1:.*]]: !esi.channel<i0>) -> (out0: !esi.channel<i0>) {
// CHECK: in %[[VAL_0:.*]] : !esi.channel<i0>, in %[[VAL_1:.*]] : !esi.channel<i0>, out out0 : !esi.channel<i0>) {
// CHECK: %[[VAL_2:.*]], %[[VAL_3:.*]] = esi.unwrap.vr %[[VAL_0]], %[[VAL_4:.*]] : i0
// CHECK: %[[VAL_5:.*]], %[[VAL_6:.*]] = esi.unwrap.vr %[[VAL_1]], %[[VAL_4]] : i0
// CHECK: %[[VAL_7:.*]] = hw.constant 0 : i0
@ -40,13 +40,13 @@ hw.module @unpack(%v : !dc.value<i64>) -> (out0: !dc.token, out1: i64) {
// CHECK: %[[VAL_4]] = comb.and %[[VAL_9]], %[[VAL_10]] : i1
// CHECK: hw.output %[[VAL_8]] : !esi.channel<i0>
// CHECK: }
hw.module @join(%t1 : !dc.token, %t2 : !dc.token) -> (out0: !dc.token) {
hw.module @join(in %t1 : !dc.token, in %t2 : !dc.token, out out0: !dc.token) {
%out = dc.join %t1, %t2
hw.output %out : !dc.token
}
// CHECK-LABEL: hw.module @fork(
// CHECK-SAME: %[[VAL_0:.*]]: !esi.channel<i0>, %[[VAL_1:.*]]: !seq.clock {dc.clock}, %[[VAL_2:.*]]: i1 {dc.reset}) -> (out0: !esi.channel<i0>, out1: !esi.channel<i0>) {
// CHECK: in %[[VAL_0:.*]] : !esi.channel<i0>, in %[[VAL_1:.*]] : !seq.clock {dc.clock}, in %[[VAL_2:.*]] : i1 {dc.reset}, out out0 : !esi.channel<i0>, out out1 : !esi.channel<i0>) {
// CHECK: %[[VAL_3:.*]], %[[VAL_4:.*]] = esi.unwrap.vr %[[VAL_0]], %[[VAL_5:.*]] : i0
// CHECK: %[[VAL_6:.*]] = hw.constant 0 : i0
// CHECK: %[[VAL_7:.*]], %[[VAL_8:.*]] = esi.wrap.vr %[[VAL_6]], %[[VAL_9:.*]] : i0
@ -71,33 +71,36 @@ hw.module @join(%t1 : !dc.token, %t2 : !dc.token) -> (out0: !dc.token) {
// CHECK: %[[VAL_5]] = comb.and %[[VAL_18]], %[[VAL_24]] {sv.namehint = "allDone"} : i1
// CHECK: hw.output %[[VAL_7]], %[[VAL_11]] : !esi.channel<i0>, !esi.channel<i0>
// CHECK: }
hw.module @fork(%t : !dc.token, %clk : !seq.clock {"dc.clock"}, %rst : i1 {"dc.reset"}) -> (out0: !dc.token, out1: !dc.token) {
hw.module @fork(in %t : !dc.token, in %clk : !seq.clock {"dc.clock"}, in %rst : i1 {"dc.reset"}, out out0 : !dc.token, out out1 : !dc.token) {
%out:2 = dc.fork [2] %t
hw.output %out#0, %out#1 : !dc.token, !dc.token
}
// CHECK-LABEL: hw.module @bufferToken(
// CHECK-SAME: %[[VAL_0:.*]]: !esi.channel<i0>, %[[VAL_1:.*]]: !seq.clock {dc.clock}, %[[VAL_2:.*]]: i1 {dc.reset}) -> (out0: !esi.channel<i0>) {
// CHECK: in %[[VAL_0:.*]] : !esi.channel<i0>, in %[[VAL_1:.*]] : !seq.clock {dc.clock}, in %[[VAL_2:.*]] : i1 {dc.reset}, out out0 : !esi.channel<i0>) {
// CHECK: %[[VAL_3:.*]] = esi.buffer %[[VAL_1]], %[[VAL_2]], %[[VAL_0]] {stages = 2 : i64} : i0
// CHECK: hw.output %[[VAL_3]] : !esi.channel<i0>
// CHECK: }
hw.module @bufferToken(%t1 : !dc.token, %clk : !seq.clock {"dc.clock"}, %rst : i1 {"dc.reset"}) -> (out0: !dc.token) {
hw.module @bufferToken(in %t1 : !dc.token, in %clk : !seq.clock {"dc.clock"}, in %rst : i1 {"dc.reset"}, out out0: !dc.token) {
%out = dc.buffer [2] %t1 : !dc.token
hw.output %out : !dc.token
}
// CHECK-LABEL: hw.module @bufferValue(
// CHECK-SAME: %[[VAL_0:.*]]: !esi.channel<i64>, %[[VAL_1:.*]]: !seq.clock {dc.clock}, %[[VAL_2:.*]]: i1 {dc.reset}) -> (out0: !esi.channel<i64>) {
// CHECK-SAME: in %[[VAL_0:.*]] : !esi.channel<i64>,
// CHECK-SAME: in %[[VAL_1:.*]] : !seq.clock {dc.clock},
// CHECK-SAME: in %[[VAL_2:.*]] : i1 {dc.reset},
// CHECK-SAME: out out0 : !esi.channel<i64>) {
// CHECK: %[[VAL_3:.*]] = esi.buffer %[[VAL_1]], %[[VAL_2]], %[[VAL_0]] {stages = 2 : i64} : i64
// CHECK: hw.output %[[VAL_3]] : !esi.channel<i64>
// CHECK: }
hw.module @bufferValue(%v1 : !dc.value<i64>, %clk : !seq.clock {"dc.clock"}, %rst : i1 {"dc.reset"}) -> (out0: !dc.value<i64>) {
hw.module @bufferValue(in %v1 : !dc.value<i64>, in %clk : !seq.clock {"dc.clock"}, in %rst : i1 {"dc.reset"}, out out0: !dc.value<i64>) {
%out = dc.buffer [2] %v1 : !dc.value<i64>
hw.output %out : !dc.value<i64>
}
// CHECK-LABEL: hw.module @branch(
// CHECK-SAME: %[[VAL_0:.*]]: !esi.channel<i1>) -> (out0: !esi.channel<i0>, out1: !esi.channel<i0>) {
// CHECK: in %[[VAL_0:.*]] : !esi.channel<i1>, out out0 : !esi.channel<i0>, out out1 : !esi.channel<i0>) {
// CHECK: %[[VAL_1:.*]], %[[VAL_2:.*]] = esi.unwrap.vr %[[VAL_0]], %[[VAL_3:.*]] : i1
// CHECK: %[[VAL_4:.*]] = hw.constant 0 : i0
// CHECK: %[[VAL_5:.*]], %[[VAL_6:.*]] = esi.wrap.vr %[[VAL_4]], %[[VAL_7:.*]] : i0
@ -111,13 +114,13 @@ hw.module @bufferValue(%v1 : !dc.value<i64>, %clk : !seq.clock {"dc.clock"}, %rs
// CHECK: %[[VAL_3]] = comb.and %[[VAL_14]], %[[VAL_2]] : i1
// CHECK: hw.output %[[VAL_5]], %[[VAL_9]] : !esi.channel<i0>, !esi.channel<i0>
// CHECK: }
hw.module @branch(%sel : !dc.value<i1>) -> (out0: !dc.token, out1: !dc.token) {
hw.module @branch(in %sel : !dc.value<i1>, out out0: !dc.token, out out1: !dc.token) {
%true, %false = dc.branch %sel
hw.output %true, %false : !dc.token, !dc.token
}
// CHECK-LABEL: hw.module @select(
// CHECK-SAME: %[[VAL_0:.*]]: !esi.channel<i1>, %[[VAL_1:.*]]: !esi.channel<i0>, %[[VAL_2:.*]]: !esi.channel<i0>) -> (out0: !esi.channel<i0>) {
// CHECK: in %[[VAL_0:.*]] : !esi.channel<i1>, in %[[VAL_1:.*]] : !esi.channel<i0>, in %[[VAL_2:.*]] : !esi.channel<i0>, out out0 : !esi.channel<i0>) {
// CHECK: %[[VAL_3:.*]], %[[VAL_4:.*]] = esi.unwrap.vr %[[VAL_0]], %[[VAL_5:.*]] : i1
// CHECK: %[[VAL_6:.*]], %[[VAL_7:.*]] = esi.unwrap.vr %[[VAL_1]], %[[VAL_8:.*]] : i0
// CHECK: %[[VAL_9:.*]], %[[VAL_10:.*]] = esi.unwrap.vr %[[VAL_2]], %[[VAL_11:.*]] : i0
@ -136,17 +139,17 @@ hw.module @branch(%sel : !dc.value<i1>) -> (out0: !dc.token, out1: !dc.token) {
// CHECK: %[[VAL_11]] = comb.and %[[VAL_22]], %[[VAL_5]] : i1
// CHECK: hw.output %[[VAL_13]] : !esi.channel<i0>
// CHECK: }
hw.module @select(%sel : !dc.value<i1>, %true : !dc.token, %false : !dc.token) -> (out0: !dc.token) {
hw.module @select(in %sel : !dc.value<i1>, in %true : !dc.token, in %false : !dc.token, out out0: !dc.token) {
%0 = dc.select %sel, %true, %false
hw.output %0 : !dc.token
}
// CHECK-LABEL: hw.module @to_from_esi_noop(
// CHECK-SAME: %[[VAL_0:.*]]: !esi.channel<i0>, %[[VAL_1:.*]]: !esi.channel<i1>) -> (token: !esi.channel<i0>, value: !esi.channel<i1>) {
// CHECK: in %[[VAL_0:.*]] : !esi.channel<i0>, in %[[VAL_1:.*]] : !esi.channel<i1>, out token : !esi.channel<i0>, out value : !esi.channel<i1>) {
// CHECK-NEXT: hw.output %[[VAL_0]], %[[VAL_1]] : !esi.channel<i0>, !esi.channel<i1>
// CHECK-NEXT: }
hw.module @to_from_esi_noop(%token : !esi.channel<i0>, %value : !esi.channel<i1>) ->
(token : !esi.channel<i0>, value : !esi.channel<i1>) {
hw.module @to_from_esi_noop(in %token : !esi.channel<i0>, in %value : !esi.channel<i1>,
out token : !esi.channel<i0>, out value : !esi.channel<i1>) {
%token_dc = dc.from_esi %token : !esi.channel<i0>
%value_dc = dc.from_esi %value : !esi.channel<i1>
%token_esi = dc.to_esi %token_dc : !dc.token

2
test/Conversion/ExportVerilog/bugs.mlir
View File

@ -3,7 +3,7 @@
// Test bug in function type conversion
// CHECK-LABEL: InOutWire
module attributes {circt.loweringOptions = "disallowExpressionInliningInPorts"} {
hw.module.extern @Bar(%a: !hw.inout<i1>) -> (b: i1)
hw.module.extern @Bar(inout %a: i1, out b: i1)
hw.module private @InOutWire() {
// CHECK: wire a;
%a = sv.wire : !hw.inout<i1>

4
test/Conversion/ExportVerilog/complex-locations.mlir
View File

@ -6,7 +6,7 @@ module attributes {circt.loweringOptions = "locationInfoStyle=wrapInAtSquareBrac
// CHECK-SAME: // @[{'foo'(fooSource.x:10:8) <- {'bar'(barSource.x:20:8) <- 'baz'(bazSource.x:30:8)}}]
// Emulate a callstack-like location info.
hw.module @Callstack(%a: i1 loc("")) -> () {
hw.module @Callstack(in %a: i1 loc("")) {
hw.output
} loc(callsite(
"foo"("fooSource.x":10:8)
@ -17,7 +17,7 @@ hw.module @Callstack(%a: i1 loc("")) -> () {
// Check location merging logic.
// CHECK-LABEL: module MergedLocations(
hw.module @MergedLocations(%clock: i1, %flag1 : i1, %flag2: i1, %flag3: i1) {
hw.module @MergedLocations(in %clock: i1, in %flag1 : i1, in %flag2: i1, in %flag3: i1) {
%true = hw.constant 1 : i1 loc("")
%false = hw.constant 0 : i1
%r1 = sv.reg : !hw.inout<i1>

2
test/Conversion/ExportVerilog/debug-info.mlir
View File

@ -3,7 +3,7 @@
// CHECK-LABEL: module symbols
// CHECK-NEXT: input baz /* #hw<innerSym@bazSym> */
module attributes {circt.loweringOptions="printDebugInfo"} {
hw.module @symbols(%baz: i1 {hw.exportPort = #hw<innerSym@bazSym>}) -> () {
hw.module @symbols(in %baz: i1 {hw.exportPort = #hw<innerSym@bazSym>}) {
// CHECK: wire foo /* #hw<innerSym@fooSym> */;
%foo = sv.wire sym @fooSym : !hw.inout<i1>
// CHECK: reg bar /* #hw<innerSym@barSym> */;

16
test/Conversion/ExportVerilog/disallow-local-vars.mlir
View File

@ -6,7 +6,7 @@
// CHECK-LABEL: module side_effect_expr
// DISALLOW-LABEL: module side_effect_expr
hw.module @side_effect_expr(%clock: i1) -> (a: i1, a2: i1) {
hw.module @side_effect_expr(in %clock: i1, out a: i1, out a2: i1) {
// CHECK: `ifdef FOO_MACRO
// DISALLOW: `ifdef FOO_MACRO
@ -54,7 +54,7 @@ hw.module @side_effect_expr(%clock: i1) -> (a: i1, a2: i1) {
// CHECK-LABEL: module hoist_expressions
// DISALLOW-LABEL: module hoist_expressions
hw.module @hoist_expressions(%clock: i1, %x: i8, %y: i8, %z: i8) {
hw.module @hoist_expressions(in %clock: i1, in %x: i8, in %y: i8, in %z: i8) {
// DISALLOW: wire [7:0] [[ADD:[_A-Za-z0-9]+]] = x + y;
%fd = hw.constant 0x80000002 : i32
@ -102,7 +102,7 @@ hw.module @hoist_expressions(%clock: i1, %x: i8, %y: i8, %z: i8) {
// CHECK-LABEL: module always_inline_expr
// DISALLOW-LABEL: module always_inline_expr
// https://github.com/llvm/circt/issues/1705
hw.module @always_inline_expr(%ro_clock_0: i1, %ro_en_0: i1, %ro_addr_0: i1, %wo_clock_0: i1, %wo_en_0: i1, %wo_addr_0: i1, %wo_mask_0: i1, %wo_data_0: i5) -> (ro_data_0: i5) {
hw.module @always_inline_expr(in %ro_clock_0: i1, in %ro_en_0: i1, in %ro_addr_0: i1, in %wo_clock_0: i1, in %wo_en_0: i1, in %wo_addr_0: i1, in %wo_mask_0: i1, in %wo_data_0: i5, out ro_data_0: i5) {
%Memory = sv.reg : !hw.inout<uarray<2xi5>>
%0 = sv.array_index_inout %Memory[%ro_addr_0] : !hw.inout<uarray<2xi5>>, i1
%1 = sv.read_inout %0 : !hw.inout<i5>
@ -125,7 +125,7 @@ hw.module @always_inline_expr(%ro_clock_0: i1, %ro_en_0: i1, %ro_addr_0: i1, %wo
// CHECK-LABEL: module EmittedDespiteDisallowed
// DISALLOW-LABEL: module EmittedDespiteDisallowed
// https://github.com/llvm/circt/issues/2216
hw.module @EmittedDespiteDisallowed(%clock: i1, %reset: i1) {
hw.module @EmittedDespiteDisallowed(in %clock: i1, in %reset: i1) {
%tick_value_2 = sv.reg : !hw.inout<i1>
%counter_value = sv.reg : !hw.inout<i1>
@ -152,7 +152,7 @@ hw.module @EmittedDespiteDisallowed(%clock: i1, %reset: i1) {
}
// CHECK-LABEL: module ReadInoutAggregate(
hw.module @ReadInoutAggregate(%clock: i1) {
hw.module @ReadInoutAggregate(in %clock: i1) {
%register = sv.reg : !hw.inout<array<1xstruct<a: i32>>>
sv.always posedge %clock {
%c0_i16 = hw.constant 0 : i16
@ -179,7 +179,7 @@ hw.module @ReadInoutAggregate(%clock: i1) {
// DISALLOW-NEXT: if (a == b)
// DISALLOW-NEXT: $error("error")
hw.module @DefinedInDifferentBlock(%a: i1, %b: i1) {
hw.module @DefinedInDifferentBlock(in %a: i1, in %b: i1) {
sv.ifdef "DEF" {
%0 = comb.icmp eq %a, %b : i1
sv.initial {
@ -193,7 +193,7 @@ hw.module @DefinedInDifferentBlock(%a: i1, %b: i1) {
// CHECK-LABEL: module TemporaryWireAtDifferentBlock(
// DISALLOW-LABEL: module TemporaryWireAtDifferentBlock(
hw.module @TemporaryWireAtDifferentBlock(%a: i1) -> (b: i1) {
hw.module @TemporaryWireAtDifferentBlock(in %a: i1, out b: i1) {
// Check that %0 and %1 are not inlined.
// CHECK: wire [[GEN1:.+]];
// CHECK: wire [[GEN2:.+]] = [[GEN1]] + [[GEN1]];
@ -214,7 +214,7 @@ hw.module @TemporaryWireAtDifferentBlock(%a: i1) -> (b: i1) {
// CHECK-LABEL: module AggregateInline(
// DISALLOW-LABEL: module AggregateInline(
hw.module @AggregateInline(%clock: i1) {
hw.module @AggregateInline(in %clock: i1) {
%c0_i16 = hw.constant 0 : i16
%false = hw.constant false
// CHECK: wire [15:0]{{ *}}[[GEN:.+]];

2
test/Conversion/ExportVerilog/header-file.mlir
View File

@ -20,7 +20,7 @@ sv.verbatim "File2 should not include header" {output_file = #hw.output_file<"fi
// FOO: `include "circt_header.svh"
// FOO-NEXT: module Foo
hw.module @Foo() -> () {
hw.module @Foo() {
hw.output
}
}

231
test/Conversion/ExportVerilog/hw-dialect.mlir
View File

@ -1,26 +1,30 @@
// RUN: circt-opt %s --test-apply-lowering-options='options=emittedLineLength=100,emitBindComments' -export-verilog -verify-diagnostics -o %t.mlir | FileCheck %s
// CHECK-LABEL: // external module E
hw.module.extern @E(%a: i1, %b: i1, %c: i1)
hw.module.extern @Array(%a: !hw.array<2xi4>)
hw.module.extern @E(in %a: i1, in %b: i1, in %c: i1)
hw.module.extern @Array(in %a: !hw.array<2xi4>)
hw.module @TESTSIMPLE(%a: i4, %b: i4, %c: i2, %cond: i1,
%array2d: !hw.array<12 x array<10xi4>>,
%uarray: !hw.uarray<16xi8>,
%postUArray: i8,
%structA: !hw.struct<foo: i2, bar:i4>,
%arrOfStructA: !hw.array<5 x struct<foo: i2>>,
%array1: !hw.array<1xi1>
) -> (
r0: i4, r2: i4, r4: i4, r6: i4, r7: i4, r8: i4, r9: i4, r10: i4, r11: i4,
r12: i4, r13: i4, r14: i4, r15: i4, r16: i1, r17: i1, r18: i1, r19: i1,
r20: i1, r21: i1, r22: i1, r23: i1, r24: i1, r25: i1, r26: i1, r27: i1,
r28: i1, r29: i12, r30: i2, r31: i9, r33: i4, r34: i4, r35: !hw.array<3xi4>,
r36: !hw.array<6xi4>, r37: i4, r38: i12, r39: !hw.struct<a: i1, b: i1>,
r40: !hw.array<4xi2>, r41: !hw.uarray<1xi1>,
r42: !hw.struct<a: !hw.array<1xi1>>, r43: i4,
r44: !hw.struct<foo: i2, bar: i4>, r45: !hw.struct<foo: i2, bar: i4>,
r46: !hw.struct<foo: i2, bar: i4>, r47: i1
hw.module @TESTSIMPLE(in %a: i4, in %b: i4, in %c: i2, in %cond: i1,
in %array2d: !hw.array<12 x array<10xi4>>,
in %uarray: !hw.uarray<16xi8>,
in %postUArray: i8,
in %structA: !hw.struct<foo: i2, bar:i4>,
in %arrOfStructA: !hw.array<5 x struct<foo: i2>>,
in %array1: !hw.array<1xi1>,
out r0: i4, out r2: i4, out r4: i4, out r6: i4, out r7: i4,
out r8: i4, out r9: i4, out r10: i4, out r11: i4,
out r12: i4, out r13: i4, out r14: i4, out r15: i4,
out r16: i1, out r17: i1, out r18: i1, out r19: i1,
out r20: i1, out r21: i1, out r22: i1, out r23: i1,
out r24: i1, out r25: i1, out r26: i1, out r27: i1,
out r28: i1, out r29: i12, out r30: i2, out r31: i9,
out r33: i4, out r34: i4, out r35: !hw.array<3xi4>,
out r36: !hw.array<6xi4>, out r37: i4, out r38: i12,
out r39: !hw.struct<a: i1, b: i1>, out r40: !hw.array<4xi2>,
out r41: !hw.uarray<1xi1>, out r42: !hw.struct<a: !hw.array<1xi1>>,
out r43: i4, out r44: !hw.struct<foo: i2, bar: i4>,
out r45: !hw.struct<foo: i2, bar: i4>,
out r46: !hw.struct<foo: i2, bar: i4>, out r47: i1
) attributes {sv.attributes = [#sv.attribute<"svAttr">]} {
%0 = comb.add %a, %b : i4
@ -213,7 +217,7 @@ hw.module @i0Inst() {
%c0_i0 = hw.constant 0 : i0
hw.instance "i0" sym @i0Module @i0Module(arg1: %c0_i0: i0) -> ()
}
hw.module @i0Module(%arg1: i0) -> () {}
hw.module @i0Module(in %arg1: i0) {}
// CHECK-LABEL: module i0Inst();
// CHECK-NEXT: i0Module i0 (
// CHECK-NEXT: //.arg1 (/* Zero width */)
@ -225,7 +229,7 @@ hw.module @i0Module(%arg1: i0) -> () {}
// CHECK-EMPTY:
// CHECK-NEXT: endmodule
hw.module @B(%a: i1) -> (b: i1, c: i1) {
hw.module @B(in %a: i1, out b: i1, out c: i1) {
%0 = comb.or %a, %a : i1
%1 = comb.and %a, %a : i1
hw.output %0, %1 : i1, i1
@ -240,7 +244,7 @@ hw.module @B(%a: i1) -> (b: i1, c: i1) {
// CHECK-NEXT: assign c = a & a;
// CHECK-NEXT: endmodule
hw.module @A(%d: i1, %e: i1) -> (f: i1) {
hw.module @A(in %d: i1, in %e: i1, out f: i1) {
%1 = comb.mux %d, %d, %e : i1
hw.output %1 : i1
}
@ -253,7 +257,7 @@ hw.module @A(%d: i1, %e: i1) -> (f: i1) {
// CHECK-NEXT: assign f = d ? d : e;
// CHECK-NEXT: endmodule
hw.module @AAA(%d: i1, %e: i1) -> (f: i1) {
hw.module @AAA(in %d: i1, in %e: i1, out f: i1) {
%z = hw.constant 0 : i1
hw.output %z : i1
}
@ -269,13 +273,13 @@ hw.module @AAA(%d: i1, %e: i1) -> (f: i1) {
/// TODO: Specify parameter declarations.
hw.module.extern @EXT_W_PARAMS<DEFAULT: i64, DEPTH: f64, FORMAT: none,
WIDTH: i8>(%a: i1, %b: i0) -> (out: i1)
WIDTH: i8>(in %a: i1, in %b: i0, out out: i1)
attributes { verilogName="FooModule" }
hw.module.extern @EXT_W_PARAMS2<DEFAULT: i32>(%a: i2) -> (out: i1)
hw.module.extern @EXT_W_PARAMS2<DEFAULT: i32>(in %a: i2, out out: i1)
attributes { verilogName="FooModule" }
hw.module @AB(%w: i1, %x: i1, %i2: i2, %i3: i0) -> (y: i1, z: i1, p: i1, p2: i1) {
hw.module @AB(in %w: i1, in %x: i1, in %i2: i2, in %i3: i0, out y: i1, out z: i1, out p: i1, out p2: i1) {
%w2 = hw.instance "a1" @AAA(d: %w: i1, e: %w1: i1) -> (f: i1)
%w1, %y = hw.instance "b1" @B(a: %w2: i1) -> (b: i1, c: i1)
@ -332,7 +336,7 @@ hw.module @AB(%w: i1, %x: i1, %i2: i2, %i3: i0) -> (y: i1, z: i1, p: i1, p2: i1)
hw.module @shl(%a: i1) -> (b: i1) {
hw.module @shl(in %a: i1, out b: i1) {
%0 = comb.shl %a, %a : i1
hw.output %0 : i1
}
@ -345,7 +349,7 @@ hw.module @shl(%a: i1) -> (b: i1) {
// CHECK-NEXT: endmodule
hw.module @inout_0(%a: !hw.inout<i42>) -> (out: i42) {
hw.module @inout_0(inout %a: i42, out out: i42) {
%aget = sv.read_inout %a: !hw.inout<i42>
hw.output %aget : i42
}
@ -360,20 +364,20 @@ hw.module @inout_0(%a: !hw.inout<i42>) -> (out: i42) {
// https://github.com/llvm/circt/issues/316
// FIXME: The MLIR parser doesn't accept an i0 even though it is valid IR,
// this needs to be fixed upstream.
//hw.module @issue316(%inp_0: i0) {
//hw.module @issue316(in %inp_0: i0) {
// hw.output
//}
// https://github.com/llvm/circt/issues/318
// This shouldn't generate invalid Verilog
hw.module @extract_all(%tmp85: i1) -> (tmp106: i1) {
hw.module @extract_all(in %tmp85: i1, out tmp106: i1) {
%1 = comb.extract %tmp85 from 0 : (i1) -> i1
hw.output %1 : i1
}
// CHECK-LABEL: module extract_all
// CHECK: assign tmp106 = tmp85;
hw.module @wires(%in4: i4, %in8: i8) -> (a: i4, b: i8, c: i8) {
hw.module @wires(in %in4: i4, in %in8: i8, out a: i4, out b: i8, out c: i8) {
// CHECK-LABEL: module wires( //
// CHECK-NEXT: input [3:0] in4, //
// CHECK-NEXT: input [7:0] in8, //
@ -429,7 +433,7 @@ hw.module @wires(%in4: i4, %in8: i8) -> (a: i4, b: i8, c: i8) {
}
// CHECK-LABEL: module signs
hw.module @signs(%in1: i4, %in2: i4, %in3: i4, %in4: i4) {
hw.module @signs(in %in1: i4, in %in2: i4, in %in3: i4, in %in4: i4) {
%awire = sv.wire : !hw.inout<i4>
// CHECK: wire [3:0] awire;
@ -469,7 +473,7 @@ hw.module @signs(%in1: i4, %in2: i4, %in3: i4, %in4: i4) {
// CHECK-NEXT: output [6:0] r1,
// CHECK-NEXT: output [31:0] r2
// CHECK-NEXT: );
hw.module @casts(%in1: i7, %in2: !hw.array<8xi4>) -> (r1: !hw.array<7xi1>, r2: i32) {
hw.module @casts(in %in1: i7, in %in2: !hw.array<8xi4>, out r1: !hw.array<7xi1>, out r2: i32) {
// CHECK-EMPTY:
%r1 = hw.bitcast %in1 : (i7) -> !hw.array<7xi1>
%r2 = hw.bitcast %in2 : (!hw.array<8xi4>) -> i32
@ -488,8 +492,8 @@ hw.module @casts(%in1: i7, %in2: !hw.array<8xi4>) -> (r1: !hw.array<7xi1>, r2: i
// CHECK-NEXT: // output [2:0]/*Zero Width*/ arrZero_0
// CHECK-NEXT: );
// CHECK-EMPTY:
hw.module @TestZero(%a: i4, %zeroBit: i0, %arrZero: !hw.array<3xi0>)
-> (r0: i4, rZero: i0, arrZero_0: !hw.array<3xi0>) {
hw.module @TestZero(in %a: i4, in %zeroBit: i0, in %arrZero: !hw.array<3xi0>,
out r0: i4, out rZero: i0, out arrZero_0: !hw.array<3xi0>) {
%b = comb.add %a, %a : i4
hw.output %b, %zeroBit, %arrZero : i4, i0, !hw.array<3xi0>
@ -501,8 +505,8 @@ hw.module @TestZero(%a: i4, %zeroBit: i0, %arrZero: !hw.array<3xi0>)
}
// CHECK-LABEL: TestZeroInstance
hw.module @TestZeroInstance(%aa: i4, %azeroBit: i0, %aarrZero: !hw.array<3xi0>)
-> (r0: i4, rZero: i0, arrZero_0: !hw.array<3xi0>) {
hw.module @TestZeroInstance(in %aa: i4, in %azeroBit: i0, in %aarrZero: !hw.array<3xi0>,
out r0: i4, out rZero: i0, out arrZero_0: !hw.array<3xi0>) {
// CHECK: TestZero iii (
// CHECK-NEXT: .a (aa),
@ -525,8 +529,8 @@ hw.module @TestZeroInstance(%aa: i4, %azeroBit: i0, %aarrZero: !hw.array<3xi0>)
// CHECK-NEXT: // output /*Zero Width*/ structZero_0,
// CHECK-NEXT: // output /*Zero Width*/ structZeroNest_0
// CHECK-NEXT: );
hw.module @TestZeroStruct(%structZero: !hw.struct<>, %structZeroNest: !hw.struct<a: !hw.struct<>>)
-> (structZero_0: !hw.struct<>, structZeroNest_0: !hw.struct<a: !hw.struct<>>) {
hw.module @TestZeroStruct(in %structZero: !hw.struct<>, in %structZeroNest: !hw.struct<a: !hw.struct<>>,
out structZero_0: !hw.struct<>, out structZeroNest_0: !hw.struct<a: !hw.struct<>>) {
hw.output %structZero, %structZeroNest : !hw.struct<>, !hw.struct<a: !hw.struct<>>
// CHECK: // Zero width: assign structZero_0 = structZero;
@ -539,7 +543,7 @@ hw.module @TestZeroStruct(%structZero: !hw.struct<>, %structZeroNest: !hw.struct
// CHECK-NEXT: input [31:0] in1,
// CHECK-NEXT: output struct packed {/*z1: Zero Width;*/ logic [31:0] a; /*z2: Zero Width;*/ logic [31:0] b; /*c: Zero Width;*/ struct packed {logic [31:0] d1; /*z: Zero Width;*/ } d; } out0
// CHECK-NEXT: );
hw.module @zeroElements(%in0: i0, %in1: i32) -> (out0: !hw.struct<z1: i0, a: i32, z2: i0, b: i32, c: !hw.struct<z: i0>, d: !hw.struct<d1:i32, z:i0>>) {
hw.module @zeroElements(in %in0: i0, in %in1: i32, out out0: !hw.struct<z1: i0, a: i32, z2: i0, b: i32, c: !hw.struct<z: i0>, d: !hw.struct<d1:i32, z:i0>>) {
// CHECK: // Zero width: wire /*Zero Width*/
// CHECK-SAME: _GEN = '{};
// CHECK-NEXT: wire struct packed {logic [31:0] d1; /*z: Zero Width;*/ }
@ -556,8 +560,8 @@ hw.module @zeroElements(%in0: i0, %in1: i32) -> (out0: !hw.struct<z1: i0, a: i32
}
// CHECK-LABEL: TestZeroStructInstance
hw.module @TestZeroStructInstance(%structZero: !hw.struct<>, %structZeroNest: !hw.struct<a: !hw.struct<>>)
-> (structZero_0: !hw.struct<>, structZeroNest_0: !hw.struct<a: !hw.struct<>>) {
hw.module @TestZeroStructInstance(in %structZero: !hw.struct<>, in %structZeroNest: !hw.struct<a: !hw.struct<>>,
out structZero_0: !hw.struct<>, out structZeroNest_0: !hw.struct<a: !hw.struct<>>) {
// CHECK: TestZeroStruct iii (
// CHECK-NEXT: //.structZero (structZero)
@ -584,7 +588,7 @@ hw.module @TestZeroStructInstance(%structZero: !hw.struct<>, %structZeroNest: !h
// CHECK-NEXT: assign out1 = arg1[/*Zero width*/ 1'b0];
// CHECK-NEXT: // Zero width: assign out2 = arg0;
hw.module @testZeroArrayGet(%arg0: i0, %arg1 : !hw.array<1xi32>) -> (out: i32, out1: i32, out2: i0) {
hw.module @testZeroArrayGet(in %arg0: i0, in %arg1 : !hw.array<1xi32>, out out: i32, out out1: i32, out out2: i0) {
// Using an expression as index.
%idx = comb.add %arg0, %arg0 : i0
%0 = hw.array_get %arg1[%idx] : !hw.array<1xi32>, i0
@ -596,7 +600,7 @@ hw.module @testZeroArrayGet(%arg0: i0, %arg1 : !hw.array<1xi32>) -> (out: i32, o
// https://github.com/llvm/circt/issues/438
// CHECK-LABEL: module cyclic
hw.module @cyclic(%a: i1) -> (b: i1) {
hw.module @cyclic(in %a: i1, out b: i1) {
// CHECK: wire _GEN;
// CHECK: wire _GEN_0 = _GEN + _GEN;
@ -611,7 +615,7 @@ hw.module @cyclic(%a: i1) -> (b: i1) {
// https://github.com/llvm/circt/issues/668
// CHECK-LABEL: module longExpressions
hw.module @longExpressions(%a: i8, %a2: i8) -> (b: i8) {
hw.module @longExpressions(in %a: i8, in %a2: i8, out b: i8) {
// CHECK: assign b =
// CHECK-NEXT: (a + a + a + a + a + a + a + a + a + a + a + a + a + a + a + a + a + a + a + a + a + a + a)
// CHECK-NEXT: * (a + a + a + a + a + a + a + a + a + a + a + a + a + a + a + a + a + a + a + a + a + a + a)
@ -630,7 +634,7 @@ hw.module @longExpressions(%a: i8, %a2: i8) -> (b: i8) {
// https://github.com/llvm/circt/issues/668
// CHECK-LABEL: module longvariadic
hw.module @longvariadic(%a: i8) -> (b: i8) {
hw.module @longvariadic(in %a: i8, out b: i8) {
// CHECK: assign b =
// CHECK-NEXT: a + a + a + a + a + a + a + a + a + a + a + a + a + a + a + a + a + a + a + a + a + a + a + a
// CHECK-COUNT-9: + a + a + a + a + a + a + a + a + a + a + a + a + a + a + a + a + a + a + a + a + a + a + a + a
@ -666,7 +670,7 @@ hw.module @longvariadic(%a: i8) -> (b: i8) {
// CHECK-NEXT: );
// CHECK-EMPTY:
// CHECK-NEXT: assign r = a == c == (d == e);
hw.module @eqIssue(%a: i9, %c :i9, %d: i4, %e: i4) -> (r : i1){
hw.module @eqIssue(in %a: i9, in %c :i9, in %d: i4, in %e: i4, out r : i1){
%1 = comb.icmp eq %a, %c : i9
%2 = comb.icmp eq %d, %e : i4
%4 = comb.icmp eq %1, %2 : i1
@ -685,7 +689,7 @@ hw.module @longvariadic(%a: i8) -> (b: i8) {
// CHECK-NEXT: initial
// CHECK-NEXT: memory_r_en_pipe[1'h0] = 1'h0;
// CHECK-NEXT: endmodule
hw.module @ArrayLHS(%clock: i1) {
hw.module @ArrayLHS(in %clock: i1) {
%false = hw.constant false
%memory_r_en_pipe = sv.reg : !hw.inout<uarray<1xi1>>
%3 = sv.array_index_inout %memory_r_en_pipe[%false] : !hw.inout<uarray<1xi1>>, i1
@ -698,7 +702,7 @@ hw.module @ArrayLHS(%clock: i1) {
}
// CHECK-LABEL: module noTemporaryIfReadInOutIsAfterUse
hw.module @noTemporaryIfReadInOutIsAfterUse(%clock: i1, %x: i1) {
hw.module @noTemporaryIfReadInOutIsAfterUse(in %clock: i1, in %x: i1) {
// CHECK: wire aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa;
%0 = comb.and %1, %x : i1
@ -716,7 +720,7 @@ hw.module @noTemporaryIfReadInOutIsAfterUse(%clock: i1, %x: i1) {
}
// CHECK-LABEL: module largeConstant
hw.module @largeConstant(%a: i100000, %b: i16) -> (x: i100000, y: i16) {
hw.module @largeConstant(in %a: i100000, in %b: i16, out x: i100000, out y: i16) {
// Large constant is inlined on multiple lines.
// CHECK: assign x =
@ -740,7 +744,7 @@ hw.module @largeConstant(%a: i100000, %b: i16) -> (x: i100000, y: i16) {
hw.output %1, %2 : i100000, i16
}
// CHECK-LABEL: StructExtractExtract
hw.module @StructExtractExtract(%a: !hw.struct<b: i4>) -> (r: i2) {
hw.module @StructExtractExtract(in %a: !hw.struct<b: i4>, out r: i2) {
%0 = hw.struct_extract %a["b"] : !hw.struct<b: i4>
%1 = comb.extract %0 from 1 : (i4) -> i2
// CHECK: assign r = a.b[2:1];
@ -748,7 +752,7 @@ hw.module @StructExtractExtract(%a: !hw.struct<b: i4>) -> (r: i2) {
}
// CHECK-LABEL: StrurctExtractInline
hw.module @StrurctExtractInline(%a: !hw.struct<v: i1>) -> (b: i1, c: i1) {
hw.module @StrurctExtractInline(in %a: !hw.struct<v: i1>, out b: i1, out c: i1) {
%0 = hw.struct_extract %a["v"] : !hw.struct<v: i1>
// CHECK: assign b = a.v;
// CHECK-NEXT: assign c = a.v;
@ -756,17 +760,17 @@ hw.module @StrurctExtractInline(%a: !hw.struct<v: i1>) -> (b: i1, c: i1) {
}
// CHECK-LABEL: NoExtraTemporaryWireForAssign
hw.module @NoExtraTemporaryWireForAssign(%a: i2, %b: i4) {
hw.module @NoExtraTemporaryWireForAssign(in %a: i2, in %b: i4) {
// CHECK: wire struct packed {logic [1:0] foo; logic [3:0] bar; } _GEN = '{foo: a, bar: b};
%0 = hw.struct_create (%a, %b) : !hw.struct<foo: i2, bar: i4>
%1 = sv.wire : !hw.inout<!hw.struct<foo: i2, bar: i4>>
sv.assign %1, %0: !hw.struct<foo: i2, bar: i4>
}
hw.module.extern @DifferentResultMod() -> (out1: i1, out2: i2)
hw.module.extern @DifferentResultMod(out out1: i1, out out2: i2)
// CHECK-LABEL: module out_of_order_multi_result(
hw.module @out_of_order_multi_result() -> (b: i1, c: i2) {
hw.module @out_of_order_multi_result(out b: i1, out c: i2) {
// CHECK: wire _b1_out1;
// CHECK: wire [1:0] _b1_out2;
%b = comb.add %out1, %out1 : i1
@ -779,9 +783,9 @@ hw.module @out_of_order_multi_result() -> (b: i1, c: i2) {
hw.output %b, %c : i1, i2
}
hw.module.extern @single_result() -> (res: i3)
hw.module.extern @single_result(out res: i3)
// CHECK-LABEL: module instance_result_reuse_wires(
hw.module @instance_result_reuse_wires() -> (b: i3) {
hw.module @instance_result_reuse_wires(out b: i3) {
// CHECK: wire {{.*}} some_wire;
// CHECK: single_result b1 (
// CHECK-NEXT: .res (some_wire)
@ -796,10 +800,10 @@ hw.module @instance_result_reuse_wires() -> (b: i3) {
hw.output %read : i3
}
hw.module.extern @ExternDestMod(%a: i1, %b: i2) -> (c: i3, d: i4)
hw.module @InternalDestMod(%a: i1, %b: i3, %c: i1) {}
hw.module.extern @ExternDestMod(in %a: i1, in %b: i2, out c: i3, out d: i4)
hw.module @InternalDestMod(in %a: i1, in %b: i3, in %c: i1) {}
// CHECK-LABEL: module ABC
hw.module @ABC(%a: i1, %b: i2) -> (c: i4) {
hw.module @ABC(in %a: i1, in %b: i2, out c: i4) {
%0,%1 = hw.instance "whatever" sym @a1 @ExternDestMod(a: %a: i1, b: %b: i2) -> (c: i3, d: i4) {doNotPrint=1}
%2 = sv.xmr "whatever", "a" : !hw.inout<i1>
%3 = sv.read_inout %2: !hw.inout<i1>
@ -826,11 +830,11 @@ hw.module @ABC(%a: i1, %b: i2) -> (c: i4) {
// CHECK-NEXT: endmodule
hw.module.extern @Uwu() -> (uwu_output : i32)
hw.module.extern @Owo(%owo_in : i32) -> ()
hw.module.extern @Uwu(out uwu_output : i32)
hw.module.extern @Owo(in %owo_in : i32)
// CHECK-LABEL: module Nya(
hw.module @Nya() -> (nya_output : i32) {
hw.module @Nya(out nya_output : i32) {
%0 = hw.instance "uwu" @Uwu() -> (uwu_output: i32)
// CHECK: wire [31:0] _uwu_uwu_output;
// CHECK: Uwu uwu (
@ -848,7 +852,7 @@ hw.module @Nya() -> (nya_output : i32) {
}
// CHECK-LABEL: module Nya2(
hw.module @Nya2() -> (nya2_output : i32) {
hw.module @Nya2(out nya2_output : i32) {
%0 = hw.instance "uwu" @Uwu() -> (uwu_output: i32)
// CHECK: Uwu uwu (
// CHECK: .uwu_output (nya2_output)
@ -858,11 +862,11 @@ hw.module @Nya2() -> (nya2_output : i32) {
// CHECK: endmodule
}
hw.module.extern @Ni() -> (ni_output : i0)
hw.module.extern @San(%san_input : i0) -> ()
hw.module.extern @Ni(out ni_output : i0)
hw.module.extern @San(in %san_input : i0)
// CHECK-LABEL: module Ichi(
hw.module @Ichi() -> (Ichi_output : i0) {
hw.module @Ichi(out Ichi_output : i0) {
%0 = hw.instance "ni" @Ni() -> (ni_output: i0)
// CHECK: Ni ni (
// CHECK: //.ni_output (Ichi_output)
@ -873,7 +877,7 @@ hw.module @Ichi() -> (Ichi_output : i0) {
}
// CHECK-LABEL: module Chi(
hw.module @Chi() -> (Chi_output : i0) {
hw.module @Chi(out Chi_output : i0) {
%0 = hw.instance "ni" @Ni() -> (ni_output: i0)
// CHECK: Ni ni (
// CHECK: //.ni_output (_ni_ni_output)
@ -890,7 +894,7 @@ hw.module @Chi() -> (Chi_output : i0) {
}
// CHECK-LABEL: module Choochoo(
hw.module @Choochoo() -> (out : i0) {
hw.module @Choochoo(out out : i0) {
%0 = hw.constant 0 : i0
// CHECK: // Zero width: assign out = /*Zero width*/;
hw.output %0 : i0
@ -920,7 +924,7 @@ hw.module @Choochoo() -> (out : i0) {
>() attributes {verilogName = "RealBar"}
// CHECK-LABEL: module Issue1563(
hw.module @Issue1563(%a: i32) -> (out : i32) {
hw.module @Issue1563(in %a: i32, out out : i32) {
// CHECK: assign out = a + a;{{.*}}//{{.*}}XX.scala:123:19, YY.haskell:309:14, ZZ.swift:3:4
%0 = comb.add %a, %a : i32 loc(fused["XX.scala":123:19, "YY.haskell":309:14, "ZZ.swift":3:4])
hw.output %0 : i32
@ -929,7 +933,7 @@ hw.module @Issue1563(%a: i32) -> (out : i32) {
// CHECK-LABEL: module Foo1587
// Issue #1587: https://github.com/llvm/circt/issues/1587
hw.module @Foo1587(%idx: i2, %a_0: i4, %a_1: i4, %a_2: i4, %a_3: i4) -> (b: i4) {
hw.module @Foo1587(in %idx: i2, in %a_0: i4, in %a_1: i4, in %a_2: i4, in %a_3: i4, out b: i4) {
%0 = hw.array_create %a_0, %a_1, %a_2, %a_3 : i4
%1 = hw.array_get %0[%idx] : !hw.array<4xi4>, i2
hw.output %1 : i4
@ -939,7 +943,7 @@ hw.module @Foo1587(%idx: i2, %a_0: i4, %a_1: i4, %a_2: i4, %a_3: i4) -> (b: i4)
// CHECK-LABEL: module AddNegLiteral(
// Issue #1324: https://github.com/llvm/circt/issues/1324
hw.module @AddNegLiteral(%a: i8, %x: i8, %y: i8) -> (o1: i8, o2: i8) {
hw.module @AddNegLiteral(in %a: i8, in %x: i8, in %y: i8, out o1: i8, out o2: i8) {
// CHECK: assign o1 = a - 8'h4;
%c = hw.constant -4 : i8
@ -954,8 +958,8 @@ hw.module @AddNegLiteral(%a: i8, %x: i8, %y: i8) -> (o1: i8, o2: i8) {
// CHECK-LABEL: module ShiftAmountZext(
// Issue #1569: https://github.com/llvm/circt/issues/1569
hw.module @ShiftAmountZext(%a: i8, %b1: i4, %b2: i4, %b3: i4)
-> (o1: i8, o2: i8, o3: i8) {
hw.module @ShiftAmountZext(in %a: i8, in %b1: i4, in %b2: i4, in %b3: i4,
out o1: i8, out o2: i8, out o3: i8) {
%c = hw.constant 0 : i4
%B1 = comb.concat %c, %b1 : i4, i4
@ -981,7 +985,7 @@ hw.module @ModuleWithLocInfo() {
// CHECK-LABEL: module SignedshiftResultSign
// Issue #1681: https://github.com/llvm/circt/issues/1681
hw.module @SignedshiftResultSign(%a: i18) -> (b: i18) {
hw.module @SignedshiftResultSign(in %a: i18, out b: i18) {
// CHECK: assign b = $signed($signed(a) >>> a[6:0]) ^ 18'hB28;
%c2856_i18 = hw.constant 2856 : i18
%c0_i11 = hw.constant 0 : i11
@ -992,7 +996,7 @@ hw.module @SignedshiftResultSign(%a: i18) -> (b: i18) {
hw.output %3 : i18
}
// CHECK-LABEL: module SignedShiftRightPrecendence
hw.module @SignedShiftRightPrecendence(%p: i1, %x: i45) -> (o: i45) {
hw.module @SignedShiftRightPrecendence(in %p: i1, in %x: i45, out o: i45) {
// CHECK: assign o = $signed($signed(x) >>> (p ? 45'h5 : 45'h8))
%c5_i45 = hw.constant 5 : i45
%c8_i45 = hw.constant 8 : i45
@ -1002,7 +1006,7 @@ hw.module @SignedShiftRightPrecendence(%p: i1, %x: i45) -> (o: i45) {
}
// CHECK-LABEL: structExtractChain
hw.module @structExtractChain(%cond: i1, %a: !hw.struct<c: !hw.struct<d:i1>>) -> (out: i1) {
hw.module @structExtractChain(in %cond: i1, in %a: !hw.struct<c: !hw.struct<d:i1>>, out out: i1) {
%1 = hw.struct_extract %a["c"] : !hw.struct<c: !hw.struct<d:i1>>
%2 = hw.struct_extract %1["d"] : !hw.struct<d:i1>
// CHECK: assign out = a.c.d;
@ -1010,7 +1014,7 @@ hw.module @structExtractChain(%cond: i1, %a: !hw.struct<c: !hw.struct<d:i1>>) ->
}
// CHECK-LABEL: structExtractFromTemporary
hw.module @structExtractFromTemporary(%cond: i1, %a: !hw.struct<c: i1>, %b: !hw.struct<c: i1>) -> (out: i1) {
hw.module @structExtractFromTemporary(in %cond: i1, in %a: !hw.struct<c: i1>, in %b: !hw.struct<c: i1>, out out: i1) {
%0 = comb.mux %cond, %a, %b : !hw.struct<c: i1>
%1 = hw.struct_extract %0["c"] : !hw.struct<c: i1>
// CHECK: wire struct packed {logic c; } _GEN = cond ? a : b;
@ -1021,7 +1025,7 @@ hw.module @structExtractFromTemporary(%cond: i1, %a: !hw.struct<c: i1>, %b: !hw.
// CHECK-LABEL: module unionCreateNoPadding(
// CHECK-NEXT: input [1:0] in,
// CHECK-NEXT: output union packed { struct packed {logic a; logic [0:0] __post_padding_a;} a;logic [1:0] b;} out
hw.module @unionCreateNoPadding(%in: i2) -> (out: !hw.union<a: i1, b: i2>) {
hw.module @unionCreateNoPadding(in %in: i2, out out: !hw.union<a: i1, b: i2>) {
// CHECK: assign out = in + in;
%add = comb.add %in, %in : i2
%0 = hw.union_create "b", %add : !hw.union<a: i1, b: i2>
@ -1031,7 +1035,7 @@ hw.module @unionCreateNoPadding(%in: i2) -> (out: !hw.union<a: i1, b: i2>) {
// CHECK-LABEL: module unionCreatePadding(
// CHECK-NEXT: input in,
// CHECK-NEXT: output union packed { struct packed {logic a; logic [0:0] __post_padding_a;} a;logic [1:0] b;} out
hw.module @unionCreatePadding(%in: i1) -> (out: !hw.union<a: i1, b: i2>) {
hw.module @unionCreatePadding(in %in: i1, out out: !hw.union<a: i1, b: i2>) {
// CHECK: assign out = {in, 1'h0};
%0 = hw.union_create "a", %in : !hw.union<a: i1, b: i2>
hw.output %0 : !hw.union<a: i1, b: i2>
@ -1040,14 +1044,14 @@ hw.module @unionCreatePadding(%in: i1) -> (out: !hw.union<a: i1, b: i2>) {
// CHECK-LABEL: module unionCreateZeroWidthElement(
// CHECK-NEXT: // input /*Zero Width*/ in,
// CHECK-NEXT: output union packed {/*a: Zero Width;*/ logic [1:0] b;} out
hw.module @unionCreateZeroWidthElement(%in: i0) -> (out: !hw.union<a: i0, b: i2>) {
hw.module @unionCreateZeroWidthElement(in %in: i0, out out: !hw.union<a: i0, b: i2>) {
// CHECK: assign out = 2'h0;
%0 = hw.union_create "a", %in : !hw.union<a: i0, b: i2>
hw.output %0 : !hw.union<a: i0, b: i2>
}
// CHECK-LABEL: unionExtractFromTemporary
hw.module @unionExtractFromTemporary(%cond: i1, %a: !hw.union<c: i1>, %b: !hw.union<c: i1>) -> (out: i1) {
hw.module @unionExtractFromTemporary(in %cond: i1, in %a: !hw.union<c: i1>, in %b: !hw.union<c: i1>, out out: i1) {
%0 = comb.mux %cond, %a, %b : !hw.union<c: i1>
%1 = hw.union_extract %0["c"] : !hw.union<c: i1>
// CHECK: wire union packed {logic c;} _GEN = cond ? a : b;
@ -1056,7 +1060,7 @@ hw.module @unionExtractFromTemporary(%cond: i1, %a: !hw.union<c: i1>, %b: !hw.un
}
// CHECK-LABEL: structExplodeLowering
hw.module @structExplodeLowering(%a: !hw.struct<a: i1, b: i1>) -> (outA: i1, outB: i1) {
hw.module @structExplodeLowering(in %a: !hw.struct<a: i1, b: i1>, out outA: i1, out outB: i1) {
// CHECK: assign outA = a.a;
// CHECK: assign outB = a.b;
%0:2 = hw.struct_explode %a : !hw.struct<a: i1, b: i1>
@ -1069,7 +1073,7 @@ hw.module @structExplodeLowering(%a: !hw.struct<a: i1, b: i1>) -> (outA: i1, out
// CHECK-NEXT: input struct packed {logic repeat_0; logic repeat_0_0; } a,
// CHECK-NEXT: output struct packed {logic repeat_0; logic repeat_0_0; } r1
// CHECK-NEXT: );
hw.module @renameKeyword(%a: !hw.struct<repeat: i1, repeat_0: i1>) -> (r1: !hw.struct<repeat: i1, repeat_0: i1>){
hw.module @renameKeyword(in %a: !hw.struct<repeat: i1, repeat_0: i1>, out r1: !hw.struct<repeat: i1, repeat_0: i1>){
hw.output %a : !hw.struct<repeat: i1, repeat_0: i1>
}
@ -1080,7 +1084,7 @@ hw.module @renameKeyword(%a: !hw.struct<repeat: i1, repeat_0: i1>) -> (r1: !hw.s
// CHECK-NEXT: output struct packed {logic repeat_0; logic repeat_0_0; } r3,
// CHECK-NEXT: r4
// CHECK-NEXT: );
hw.module @useRenamedStruct(%a: !hw.inout<struct<repeat: i1, repeat_0: i1>>) -> (r1: i1, r2: i1, r3: !hw.struct<repeat: i1, repeat_0: i1>, r4: !hw.struct<repeat: i1, repeat_0: i1>) {
hw.module @useRenamedStruct(inout %a: !hw.struct<repeat: i1, repeat_0: i1>, out r1: i1, out r2: i1, out r3: !hw.struct<repeat: i1, repeat_0: i1>, out r4: !hw.struct<repeat: i1, repeat_0: i1>) {
%read = sv.read_inout %a : !hw.inout<struct<repeat: i1, repeat_0: i1>>
%i0 = hw.instance "inst1" @renameKeyword(a: %read: !hw.struct<repeat: i1, repeat_0: i1>) -> (r1: !hw.struct<repeat: i1, repeat_0: i1>)
@ -1102,7 +1106,7 @@ hw.module @useRenamedStruct(%a: !hw.inout<struct<repeat: i1, repeat_0: i1>>) ->
// CHECK-LABEL: module replicate
hw.module @replicate(%arg0: i7, %arg1: i1) -> (r1: i21, r2: i9, r3: i16, r4: i16) {
hw.module @replicate(in %arg0: i7, in %arg1: i1, out r1: i21, out r2: i9, out r3: i16, out r4: i16) {
// CHECK: assign r1 = {3{arg0}};
%r1 = comb.replicate %arg0 : (i7) -> i21
@ -1122,7 +1126,7 @@ hw.module @replicate(%arg0: i7, %arg1: i1) -> (r1: i21, r2: i9, r3: i16, r4: i16
}
// CHECK-LABEL: module addParenthesesToSuccessiveOperators
hw.module @addParenthesesToSuccessiveOperators(%a: i4, %b: i1, %c: i4) -> (o1:i1, o2:i1, o3:i1) {
hw.module @addParenthesesToSuccessiveOperators(in %a: i4, in %b: i1, in %c: i4, out o1:i1, out o2:i1, out o3:i1) {
%one4 = hw.constant -1 : i4
%zero4 = hw.constant 0 : i4
// CHECK: wire [[GEN:.+]] = &c;
@ -1150,7 +1154,7 @@ hw.module @addParenthesesToSuccessiveOperators(%a: i4, %b: i1, %c: i4) -> (o1:i1
// CHECK-NEXT: #(parameter [41:0] p1 = 42'd17
// CHECK-NEXT: parameter [0:0] p2) (
// CHECK-NEXT: input [7:0] arg0,
hw.module @parameters<p1: i42 = 17, p2: i1>(%arg0: i8) -> (out: i8) {
hw.module @parameters<p1: i42 = 17, p2: i1>(in %arg0: i8, out out: i8) {
// Local values should not conflict with output or parameter names.
// CHECK: wire [3:0] p1_0;
%p1 = sv.wire : !hw.inout<i4>
@ -1160,7 +1164,7 @@ hw.module @parameters<p1: i42 = 17, p2: i1>(%arg0: i8) -> (out: i8) {
hw.output %arg0 : i8
}
hw.module.extern @parameters2<p1: i42 = 17, p2: i1 = 0>(%arg0: i8) -> (out: i8)
hw.module.extern @parameters2<p1: i42 = 17, p2: i1 = 0>(in %arg0: i8, out out: i8)
// CHECK-LABEL: module parameters3
// CHECK-NEXT: #(parameter [41:0] p1 = 42'd17) (
@ -1168,12 +1172,12 @@ hw.module.extern @parameters2<p1: i42 = 17, p2: i1 = 0>(%arg0: i8) -> (out: i8)
// CHECK-NEXT: output [p1 - 1:0] out
// CHECK-NEXT: );
// CHECK: assign out = arg0;
hw.module @parameters3<p1: i42 = 17>(%arg0: !hw.int<#hw.param.decl.ref<"p1">>) -> (out: !hw.int<#hw.param.decl.ref<"p1">>) {
hw.module @parameters3<p1: i42 = 17>(in %arg0: !hw.int<#hw.param.decl.ref<"p1">>, out out: !hw.int<#hw.param.decl.ref<"p1">>) {
hw.output %arg0 : !hw.int<#hw.param.decl.ref<"p1">>
}
// CHECK-LABEL: module UseParameterized(
hw.module @UseParameterized(%a: i8) -> (ww: i8, xx: i8, yy: i8, zz: i8, qq: i8) {
hw.module @UseParameterized(in %a: i8, out ww: i8, out xx: i8, out yy: i8, out zz: i8, out qq: i8) {
// Two parameters.
// CHECK: parameters #(
// CHECK-NEXT: .p1(42'd4),
@ -1223,8 +1227,8 @@ hw.module @UseParameterized(%a: i8) -> (ww: i8, xx: i8, yy: i8, zz: i8, qq: i8)
}
// CHECK-LABEL: module UseParameterValue
hw.module @UseParameterValue<xx: i42>(%arg0: i8)
-> (out1: i8, out2: i8, out3: i8, out4: i42) {
hw.module @UseParameterValue<xx: i42>(in %arg0: i8,
out out1: i8, out out2: i8, out out3: i8, out out4: i42) {
// CHECK-NEXT: #(parameter [41:0] xx) (
// CHECK: parameters2 #(
@ -1258,8 +1262,7 @@ hw.module @UseParameterValue<xx: i42>(%arg0: i8)
// CHECK-LABEL: module VerilogCompatParameters
hw.module @VerilogCompatParameters<p1: i42, p2: i32, p3: f64 = 1.5,
p4: i32 = 4, p5: none = "foo",
p6: none>()
-> () {
p6: none>() {
// CHECK-NEXT: #(parameter [41:0] p1,
// CHECK-NEXT: parameter /*integer*/ p2,
// CHECK-NEXT: parameter p3 = 1.500000e+00,
@ -1275,11 +1278,11 @@ hw.module @VerilogCompatParameters<p1: i42, p2: i32, p3: f64 = 1.5,
// CHECK: parameter wire_0 = 2) (
hw.module @parameterizedTypes<param: i32 = 1, wire: i32 = 2>
// CHECK: input [16:0]{{ *}}a,
(%a: !hw.int<17>,
(in %a: !hw.int<17>,
// CHECK: input [param - 1:0]{{ *}}b
%b: !hw.int<#hw.param.decl.ref<"param">>,
in %b: !hw.int<#hw.param.decl.ref<"param">>,
// CHECK: input [$clog2($unsigned(param)) - 1:0]{{ *}}c
%c: !hw.int<#hw.param.expr.clog2<#hw.param.decl.ref<"param">>>) {
in %c: !hw.int<#hw.param.expr.clog2<#hw.param.decl.ref<"param">>>) {
// Check that the parameter name renamification propagates.
// CHECK: wire [wire_0 - 1:0] paramWire;
@ -1296,7 +1299,7 @@ hw.module @moduleWithComment()
// CHECK-LABEL: module Foo(
// https://github.com/llvm/circt/issues/2363
hw.module @Foo(%a: i1, %b: i1) -> (r1: i1, r2: i1) {
hw.module @Foo(in %a: i1, in %b: i1, out r1: i1, out r2: i1) {
// Make sure the temporary wire is indented correctly.
// CHECK: {{^ wire _GEN = a == b;}}
%0 = comb.icmp eq %a, %b : i1
@ -1311,9 +1314,9 @@ hw.module @Foo(%a: i1, %b: i1) -> (r1: i1, r2: i1) {
// CHECK-NEXT: output [N - 64'd1:0][param - 1:0] c
// CHECK-NEXT: );
hw.module @parameterizedArrays<param: i32, N: i32>
(%a: !hw.array<42x!hw.int<#hw.param.decl.ref<"param">>>,
%b: !hw.array<#hw.param.decl.ref<"N"> x !hw.int<#hw.param.decl.ref<"param">>>) ->
(c: !hw.array<#hw.param.decl.ref<"N"> x !hw.int<#hw.param.decl.ref<"param">>>) {
(in %a: !hw.array<42x!hw.int<#hw.param.decl.ref<"param">>>,
in %b: !hw.array<#hw.param.decl.ref<"N"> x !hw.int<#hw.param.decl.ref<"param">>>,
out c: !hw.array<#hw.param.decl.ref<"N"> x !hw.int<#hw.param.decl.ref<"param">>>) {
hw.output %b : !hw.array<#hw.param.decl.ref<"N"> x !hw.int<#hw.param.decl.ref<"param">>>
}
@ -1322,7 +1325,7 @@ hw.module @parameterizedArrays<param: i32, N: i32>
// CHECK-NEXT: input [23:0][11:0] b
// CHECK-NEXT: output [23:0][11:0] c
// CHECK-NEXT: );
hw.module @UseParameterizedArrays(%a: !hw.array<42xint<12>>, %b: !hw.array<24xint<12>>) -> (c: !hw.array<24xint<12>>) {
hw.module @UseParameterizedArrays(in %a: !hw.array<42xint<12>>, in %b: !hw.array<24xint<12>>, out c: !hw.array<24xint<12>>) {
// CHECK: parameterizedArrays #(
// CHECK-NEXT: .param(12),
// CHECK-NEXT: .N(24)
@ -1340,7 +1343,7 @@ hw.module @UseParameterizedArrays(%a: !hw.array<42xint<12>>, %b: !hw.array<24xin
// CHECK-LABEL: module NoneTypeParam
// CHECK: #(parameter p1) ();
// CHECK: endmodule
hw.module @NoneTypeParam<p1: none>() -> () {}
hw.module @NoneTypeParam<p1: none>() {}
// CHECK-LABEL: module ParamConcatInst
// CHECK: #(parameter name = "top") ();
@ -1348,12 +1351,12 @@ hw.module @NoneTypeParam<p1: none>() -> () {}
// CHECK: .p1({".", name, ".child"})
// CHECK: ) inst ();
// CHECK: endmodule
hw.module @ParamConcatInst<name: none = "top">() -> () {
hw.module @ParamConcatInst<name: none = "top">() {
hw.instance "inst" @NoneTypeParam<p1: none = #hw.param.expr.str.concat<".", #hw.param.decl.ref<"name">, ".", "child">>() -> ()
}
// CHECK-LABEL: module ParamsParensPrecedence
hw.module @ParamsParensPrecedence<param: i32>() -> (a:i32, b:i32, c:i32) {
hw.module @ParamsParensPrecedence<param: i32>(out a:i32, out b:i32, out c:i32) {
// CHECK: = $clog2($unsigned(param));
%1 = hw.param.value i32 = #hw.param.expr.clog2<#hw.param.decl.ref<"param">>
@ -1366,8 +1369,8 @@ hw.module @ParamsParensPrecedence<param: i32>() -> (a:i32, b:i32, c:i32) {
}
// CHECK-LABEL: module ArrayGetInline
hw.module @ArrayGetInline(%a: !hw.array<4xstruct<a: i32>>, %b: !hw.array<4xi1>, %idx: i2, %idx_port: !hw.inout<i2>)
-> (out: i32, out2: i1, out3: i1, out4: i1, out5: i1) {
hw.module @ArrayGetInline(in %a: !hw.array<4xstruct<a: i32>>, in %b: !hw.array<4xi1>, in %idx: i2, inout %idx_port: i2,
out out: i32, out out2: i1, out out3: i1, out out4: i1, out out5: i1) {
%c0_i2 = hw.constant 0 : i2
%x = hw.array_get %a[%c0_i2] : !hw.array<4xstruct<a: i32>>, i2
%y = hw.struct_extract %x["a"] : !hw.struct<a: i32>
@ -1383,7 +1386,7 @@ hw.module @ArrayGetInline(%a: !hw.array<4xstruct<a: i32>>, %b: !hw.array<4xi1>,
}
// CHECK-LABEL: module UniformArrayCreate
hw.module @UniformArrayCreate() -> (arr: !hw.array<5xi8>) {
hw.module @UniformArrayCreate(out arr: !hw.array<5xi8>) {
%c0_i8 = hw.constant 0 : i8
%arr = hw.array_create %c0_i8, %c0_i8, %c0_i8, %c0_i8, %c0_i8 : i8
// CHECK: assign arr = {5{8'h0}};
@ -1395,7 +1398,7 @@ hw.module @UniformArrayCreate() -> (arr: !hw.array<5xi8>) {
// CHECK-NEXT: );
// CHECK-EMPTY:
// CHECK-NEXT: endmodule
hw.module @Issue4485(%in: i4) {
hw.module @Issue4485(in %in: i4) {
%c0_i4 = hw.constant 0 : i4
%1 = comb.icmp eq %in, %c0_i4 : i4
%2 = sv.system.sampled %1 : i1
@ -1410,7 +1413,7 @@ hw.module @Issue4485(%in: i4) {
// CHECK-EMPTY:
// CHECK-NEXT: assign out = {in1, /*cast(bit[31:0])*/in2};
// CHECK-NEXT: endmodule
hw.module @inline_bitcast_in_concat(%in1: i7, %in2: !hw.array<8xi4>) -> (out: i39) {
hw.module @inline_bitcast_in_concat(in %in1: i7, in %in2: !hw.array<8xi4>, out out: i39) {
%r2 = hw.bitcast %in2 : (!hw.array<8xi4>) -> i32
%0 = comb.concat %in1, %r2: i7, i32
hw.output %0 : i39
@ -1422,7 +1425,7 @@ hw.module @inline_bitcast_in_concat(%in1: i7, %in2: !hw.array<8xi4>) -> (out: i3
// CHECK-NEXT: .a (_GEN)
// CHECK-NEXT: );
// CHECK-NEXT: endmodule
hw.module @DontInlineAggregateConstantIntoPorts() -> () {
hw.module @DontInlineAggregateConstantIntoPorts() {
%0 = hw.aggregate_constant [0 : i4, 1 : i4] : !hw.array<2xi4>
hw.instance "i0" @Array(a: %0: !hw.array<2xi4>) -> ()
}
@ -1437,7 +1440,7 @@ hw.module @DontInlineAggregateConstantIntoPorts() -> () {
// CHECK-NEXT: assign b = test.b.b;
// CHECK-NEXT: endmodule
!unionA = !hw.union<a: i16, b: i10>
hw.module @FooA(%test: !unionA) -> (a: i16, b: i10) {
hw.module @FooA(in %test: !unionA, out a: i16, out b: i10) {
%0 = hw.union_extract %test["a"] : !unionA
%1 = hw.union_extract %test["b"] : !unionA
hw.output %0, %1 : i16, i10
@ -1453,7 +1456,7 @@ hw.module @FooA(%test: !unionA) -> (a: i16, b: i10) {
// CHECK-NEXT: assign b = test.b.b;
// CHECK-NEXT: endmodule
!unionB = !hw.union<a: i16, b: i14 offset 2>
hw.module @FooB(%test: !unionB) -> (a: i16, b: i14) {
hw.module @FooB(in %test: !unionB, out a: i16, out b: i14) {
%0 = hw.union_extract %test["a"] : !unionB
%1 = hw.union_extract %test["b"] : !unionB
hw.output %0, %1 : i16, i14

8
test/Conversion/ExportVerilog/hw-enums.mlir
View File

@ -4,8 +4,8 @@
// CHECK: // typedef enum bit [0:0] {} enum1;
// CHECK: typedef enum bit [0:0] {enum2_U} enum2;
// CHECK-LABEL: module EnumCheck
hw.module @EnumCheck(%a : !hw.enum<T>, %b: !hw.enum<>, %c : !hw.enum<U>)
-> (d : !hw.enum<T>, e: !hw.enum<>, f: !hw.enum<U>) {
hw.module @EnumCheck(in %a : !hw.enum<T>, in %b: !hw.enum<>, in %c : !hw.enum<U>,
out d : !hw.enum<T>, out e: !hw.enum<>, out f: !hw.enum<U>) {
// CHECK: assign d = a;
// CHECK: // Zero width: assign e = b;
// CHECK: assign f = c;
@ -22,7 +22,7 @@ hw.module @EnumCheck(%a : !hw.enum<T>, %b: !hw.enum<>, %c : !hw.enum<U>)
// CHECK-EMPTY:
// CHECK-NEXT: assign result = test == enum0_A;
// CHECK-NEXT: endmodule
hw.module @EnumCmp(%test: !hw.enum<A, B>) -> (result: i1) {
hw.module @EnumCmp(in %test: !hw.enum<A, B>, out result: i1) {
%A = hw.enum.constant A : !hw.enum<A, B>
%0 = hw.enum.cmp %test, %A : !hw.enum<A, B>, !hw.enum<A, B>
hw.output %0 : i1
@ -78,7 +78,7 @@ hw.type_scope @__AnFSMTypedecl {
hw.typedecl @_state2 : !hw.enum<A, B>
}
hw.module @AnFSM(%clock : i1) {
hw.module @AnFSM(in %clock : i1) {
// Anonymous enum
%reg = sv.reg : !hw.inout<!hw.enum<A, B>>
%reg_read = sv.read_inout %reg : !hw.inout<!hw.enum<A, B>>

6
test/Conversion/ExportVerilog/hw-typedecls-errors.mlir
View File

@ -5,10 +5,10 @@ hw.type_scope @__hw_typedecls {
}
// expected-error @+1 {{unresolvable type reference}}
hw.module @testTypeAlias1(%arg0: !hw.typealias<@__hw_typedecls::@bar,i1>) {}
hw.module @testTypeAlias1(in %arg0 : !hw.typealias<@__hw_typedecls::@bar,i1>) {}
// expected-error @+1 {{unresolvable type reference}}
hw.module @testTypeAlias2(%arg0: !hw.typealias<@_other_scope::@foo,i1>) {}
hw.module @testTypeAlias2(in %arg0: !hw.typealias<@_other_scope::@foo,i1>) {}
// expected-error @+1 {{declared type did not match aliased type}}
hw.module @testTypeAlias3(%arg0: !hw.typealias<@__hw_typedecls::@foo,i2>) {}
hw.module @testTypeAlias3(in %arg0: !hw.typealias<@__hw_typedecls::@foo,i2>) {}

24
test/Conversion/ExportVerilog/hw-typedecls.mlir
View File

@ -48,25 +48,25 @@ sv.ifdef "__PYCDE_TYPES__" {
hw.module @testTypeAlias(
// CHECK: input foo arg0,
// CHECK: arg1
%arg0: !hw.typealias<@__hw_typedecls::@foo,i1>,
%arg1: !hw.typealias<@__hw_typedecls::@foo,i1>,
in %arg0: !hw.typealias<@__hw_typedecls::@foo,i1>,
in %arg1: !hw.typealias<@__hw_typedecls::@foo,i1>,
// CHECK: input foo[2:0] arg2
%arg2: !hw.array<3xtypealias<@__hw_typedecls::@foo,i1>>,
in %arg2: !hw.array<3xtypealias<@__hw_typedecls::@foo,i1>>,
// CHECK: input arr arrArg,
%arrArg: !hw.typealias<@__hw_typedecls::@arr,!hw.array<16xi8>>,
in %arrArg: !hw.typealias<@__hw_typedecls::@arr,!hw.array<16xi8>>,
// CHECK: input bar structArg,
%structArg: !hw.typealias<@__hw_typedecls::@bar,!hw.struct<a: i1, b: i1>>,
in %structArg: !hw.typealias<@__hw_typedecls::@bar,!hw.struct<a: i1, b: i1>>,
// CHECK: input myEnum enumArg,
%enumArg: !hw.typealias<@__hw_typedecls::@myEnum,!hw.enum<A, B, C>>) ->
in %enumArg: !hw.typealias<@__hw_typedecls::@myEnum,!hw.enum<A, B, C>>,
// CHECK: output foo out
(out: !hw.typealias<@__hw_typedecls::@foo, i1>) {
out out: !hw.typealias<@__hw_typedecls::@foo, i1>) {
// CHECK: out = arg0 + arg1
%0 = comb.add %arg0, %arg1 : !hw.typealias<@__hw_typedecls::@foo, i1>
hw.output %0 : !hw.typealias<@__hw_typedecls::@foo, i1>
}
// CHECK-LABEL: module testRegOp
hw.module @testRegOp() -> () {
hw.module @testRegOp() {
// CHECK: foo {{.+}};
%r1 = sv.reg : !hw.inout<!hw.typealias<@__hw_typedecls::@foo,i1>>
// CHECK: foo[2:0] {{.+}};
@ -74,7 +74,7 @@ hw.module @testRegOp() -> () {
}
// CHECK-LABEL: module testAggregateCreate
hw.module @testAggregateCreate(%i: i1) -> (out1: i1, out2: i1) {
hw.module @testAggregateCreate(in %i: i1, out out1: i1, out out2: i1) {
// CHECK: wire bar [[NAME:.+]] = {{.+}};
%0 = hw.struct_create(%i, %i) : !hw.typealias<@__hw_typedecls::@bar,!hw.struct<a: i1, b: i1>>
// CHECK: [[NAME]].a
@ -84,12 +84,12 @@ hw.module @testAggregateCreate(%i: i1) -> (out1: i1, out2: i1) {
hw.output %1, %2 : i1, i1
}
hw.module @testNestedAlias(%i: !hw.typealias<@__hw_typedecls::@nest2, !hw.typealias<@__hw_typedecls::@nest1, !hw.typealias<@__hw_typedecls::@bar, !hw.struct<a: i1, b: i1>>>>) -> () {
hw.module @testNestedAlias(in %i: !hw.typealias<@__hw_typedecls::@nest2, !hw.typealias<@__hw_typedecls::@nest1, !hw.typealias<@__hw_typedecls::@bar, !hw.struct<a: i1, b: i1>>>>) {
%0 = hw.struct_extract %i["a"] : !hw.typealias<@__hw_typedecls::@nest2, !hw.typealias<@__hw_typedecls::@nest1, !hw.typealias<@__hw_typedecls::@bar, !hw.struct<a: i1, b: i1>>>>
}
// CHECK-LABEL: module testAggregateInout
hw.module @testAggregateInout(%i: i1) -> (out1: i8, out2: i1) {
hw.module @testAggregateInout(in %i: i1, out out1: i8, out out2: i1) {
// CHECK: wire arr array;
// CHECK-NEXT: wire bar str;
// CHECK-NEXT: assign out1 = array[4'h0];
@ -105,7 +105,7 @@ hw.module @testAggregateInout(%i: i1) -> (out1: i8, out2: i1) {
}
// CHECK-LABEL: module testEnumOps
hw.module @testEnumOps() -> (out1: !hw.typealias<@__hw_typedecls::@myEnum,!hw.enum<A, B, C>>) {
hw.module @testEnumOps(out out1: !hw.typealias<@__hw_typedecls::@myEnum,!hw.enum<A, B, C>>) {
// CHECK: assign out1 = myEnum_A;
%0 = hw.enum.constant A : !hw.typealias<@__hw_typedecls::@myEnum,!hw.enum<A, B, C>>
hw.output %0 : !hw.typealias<@__hw_typedecls::@myEnum,!hw.enum<A, B, C>>

2
test/Conversion/ExportVerilog/line-length.mlir
View File

@ -4,7 +4,7 @@
// RUN: circt-opt --test-apply-lowering-options='options=emittedLineLength=40,maximumNumberOfTermsPerExpression=16' --export-verilog %s | FileCheck %s --check-prefixes=CHECK,LIMIT_SHORT
// RUN: circt-opt --test-apply-lowering-options='options=maximumNumberOfTermsPerExpression=32' --export-verilog %s | FileCheck %s --check-prefixes=CHECK,LIMIT_LONG
hw.module @longvariadic(%a: i8) -> (b: i8) {
hw.module @longvariadic(in %a: i8, out b: i8) {
%1 = comb.add %a, %a, %a, %a, %a, %a, %a, %a, %a, %a, %a, %a, %a, %a, %a, %a,
%a, %a, %a, %a, %a, %a, %a, %a, %a, %a, %a, %a, %a, %a, %a, %a,
%a, %a, %a, %a, %a, %a, %a, %a, %a, %a, %a, %a, %a, %a, %a, %a,

2
test/Conversion/ExportVerilog/load-dialect.mlir
View File

@ -7,7 +7,7 @@
// 2. the IR must trigger ExportVerilog to create a sv.wire
hw.module @cyclic(%a: i1) -> (b: i1) {
hw.module @cyclic(in %a: i1, out b: i1) {
// Check that a wire temporary is created by export verilog. This wire is
// for holding the value of %0. If this wire is not emitted then this test
// should either be deleted or find a different way to force IR generation.

6
test/Conversion/ExportVerilog/location-style.mlir
View File

@ -6,7 +6,7 @@ module attributes {circt.loweringOptions = "locationInfoStyle=wrapInAtSquareBrac
// CHECK-NEXT: input a
// CHECK-NOT: //
// CHECK: endmodule
hw.module @Foo(%a: i1 loc("")) -> () {
hw.module @Foo(in %a: i1 loc("")) {
hw.output
} loc("dummy":1:1)
}
@ -17,7 +17,7 @@ module attributes {circt.loweringOptions = "locationInfoStyle=plain"}{
// CHECK: module Foo();
// CHECK-SAME: // dummy:1:1
// CHECK-NEXT: endmodule
hw.module @Foo() -> () {
hw.module @Foo() {
hw.output
} loc("dummy":1:1)
}
@ -28,7 +28,7 @@ module attributes {circt.loweringOptions = "locationInfoStyle=none"}{
// CHECK: module Foo();
// CHECK-NOT: //
// CHECK-NEXT: endmodule
hw.module @Foo() -> () {
hw.module @Foo() {
hw.output
} loc("dummy":1:1)
}

6
test/Conversion/ExportVerilog/max-terms.mlir
View File

@ -1,7 +1,7 @@
// RUN: circt-opt -test-apply-lowering-options='options=maximumNumberOfTermsPerExpression=4,disallowLocalVariables' --export-verilog %s | FileCheck %s
// CHECK-LABEL: module large_use_in_procedural
hw.module @large_use_in_procedural(%clock: i1, %a: i1) {
hw.module @large_use_in_procedural(in %clock: i1, in %a: i1) {
// CHECK: wire [[GEN_1:long_concat]] = a + a + a + a + a;
// CHECK: always
@ -40,7 +40,7 @@ hw.module @large_use_in_procedural(%clock: i1, %a: i1) {
}
// CHECK-LABEL: module large_use_in_procedural_successive
hw.module @large_use_in_procedural_successive(%clock: i1, %a: i1) {
hw.module @large_use_in_procedural_successive(in %clock: i1, in %a: i1) {
sv.always posedge %clock {
%0 = comb.and %a, %a, %a, %a, %a : i1
%1 = comb.and %a, %a, %a, %a, %a : i1
@ -56,7 +56,7 @@ hw.module @large_use_in_procedural_successive(%clock: i1, %a: i1) {
}
// CHECK-LABEL: module dont_spill_to_procedural_regions
hw.module @dont_spill_to_procedural_regions(%z: i10) -> () {
hw.module @dont_spill_to_procedural_regions(in %z: i10) {
%r1 = sv.reg : !hw.inout<i1>
%r2 = sv.reg : !hw.inout<i10>
// CHECK: wire [9:0] _GEN = r2 + r2 + r2 + r2 + r2;

4
test/Conversion/ExportVerilog/misc-lowering-opts.mlir
View File

@ -8,7 +8,7 @@ module attributes {circt.loweringOptions="emitWireInPorts"} {
// CHECK-NEXT: input wire struct packed {logic [3:0] bar; } foo,
// CHECK-NEXT: output wire [2:0] x
// CHECK: endmodule
hw.module @Foo(%a: i1, %foo: !fooTy) -> (x: i3) {
hw.module @Foo(in %a: i1, in %foo: !fooTy, out x: i3) {
%c0_i3 = hw.constant 0 : i3
hw.output %c0_i3 : i3
}
@ -23,7 +23,7 @@ module attributes {circt.loweringOptions="caseInsensitiveKeywords"} {
// CHECK: input Module_0,
// CHECK-NEXT: output MoDuLe_0
// CHECK: assign MoDuLe_0 = Module_0;
hw.module @MODULE(%Module: i1) -> (MoDuLe: i1) {
hw.module @MODULE(in %Module: i1, out MoDuLe: i1) {
hw.output %Module : i1
}
}

6
test/Conversion/ExportVerilog/mitigate-vivado-array-index-const-prop-bug.mlir
View File

@ -3,7 +3,7 @@
// CHECK-LABEL: module Simple(
// FIXED-LABEL: module Simple(
hw.module @Simple(%a: !hw.array<16xi1>, %b : i4) -> (c: i1) {
hw.module @Simple(in %a : !hw.array<16xi1>, in %b : i4, out c: i1) {
// CHECK: assign c = a[b + 4'h1];
// FIXED: (* keep = "true" *)
@ -21,7 +21,7 @@ hw.module @Simple(%a: !hw.array<16xi1>, %b : i4) -> (c: i1) {
// CHECK-LABEL: module ExistingWire(
// FIXED-LABEL: module ExistingWire(
hw.module @ExistingWire(%a: !hw.array<16xi1>, %b : i4) -> (c: i1) {
hw.module @ExistingWire(in %a: !hw.array<16xi1>, in %b : i4, out c: i1) {
// CHECK: wire [3:0] existingWire = b + 4'h3;
// CHECK-NEXT: assign c = a[existingWire];
@ -43,7 +43,7 @@ hw.module @ExistingWire(%a: !hw.array<16xi1>, %b : i4) -> (c: i1) {
// CHECK-LABEL: module ProceduralRegion(
// FIXED-LABEL: module ProceduralRegion(
hw.module @ProceduralRegion(%a: !hw.array<16xi1>, %b : i4) {
hw.module @ProceduralRegion(in %a: !hw.array<16xi1>, in %b : i4) {
// CHECK: magic(a[b + 4'h1]);
// FIXED: initial begin

30
test/Conversion/ExportVerilog/name-legalize.mlir
View File

@ -4,19 +4,19 @@
// CHECK: input [3:0] casex_0,
// CHECK: output [3:0] if_0
// CHECK: );
hw.module @namechange(%casex: i4) -> (if: i4) {
hw.module @namechange(in %casex: i4, out if: i4) {
// CHECK: assign if_0 = casex_0;
hw.output %casex : i4
}
hw.module.extern @module_with_bool<bparam: i1>() -> ()
hw.module.extern @module_with_bool<bparam: i1>()
// CHECK-LABEL: module parametersNameConflict
// CHECK-NEXT: #(parameter [41:0] p2 = 42'd17,
// CHECK-NEXT: parameter [0:0] wire_0) (
// CHECK-NEXT: input [7:0] p1
// CHECK-NEXT: );
hw.module @parametersNameConflict<p2: i42 = 17, wire: i1>(%p1: i8) {
hw.module @parametersNameConflict<p2: i42 = 17, wire: i1>(in %p1: i8) {
%myWire = sv.wire : !hw.inout<i1>
// CHECK: `ifdef SOMEMACRO
@ -43,7 +43,7 @@ hw.module @parametersNameConflict<p2: i42 = 17, wire: i1>(%p1: i8) {
}
// CHECK-LABEL: module useParametersNameConflict(
hw.module @useParametersNameConflict(%xxx: i8) {
hw.module @useParametersNameConflict(in %xxx: i8) {
// CHECK: parametersNameConflict #(
// CHECK: .p2(42'd27),
// CHECK: .wire_0(0)
@ -65,13 +65,13 @@ hw.module @useParametersNameConflict(%xxx: i8) {
// CHECK: input inout_0,
// CHECK: output output_0
// CHECK: );
hw.module @inout(%inout: i1) -> (output: i1) {
hw.module @inout(in %inout: i1, out output: i1) {
// CHECK: assign output_0 = inout_0;
hw.output %inout : i1
}
// CHECK-LABEL: module inout_inst(
hw.module @inout_inst(%a: i1) {
hw.module @inout_inst(in %a: i1) {
// CHECK: inout_0 foo (
// CHECK: .inout_0 (a),
// CHECK: .output_0 (/* unused */)
@ -85,7 +85,7 @@ hw.module @inout_inst(%a: i1) {
// CHECK-NEXT: input inout_0,
// CHECK-NEXT: output output_0
// CHECK-NEXT: );
hw.module @reg(%inout: i1) -> (output: i1) {
hw.module @reg(in %inout: i1, out output: i1) {
// CHECK: assign output_0 = inout_0;
hw.output %inout : i1
}
@ -96,17 +96,17 @@ hw.module @reg(%inout: i1) -> (output: i1) {
// CHECK-NEXT: else_0,
// CHECK-NEXT: output [1:0] casex_0
// CHECK-NEXT: );
hw.module @issue525(%struct: i2, %else: i2) -> (casex: i2) {
hw.module @issue525(in %struct: i2, in %else: i2, out casex: i2) {
// CHECK: assign casex_0 = struct_0 + else_0;
%2 = comb.add %struct, %else : i2
hw.output %2 : i2
}
hw.module @B(%a: i1) -> () {
hw.module @B(in %a: i1) {
}
// CHECK-LABEL: module TestDupInstanceName(
hw.module @TestDupInstanceName(%a: i1) {
hw.module @TestDupInstanceName(in %a: i1) {
// CHECK: B name (
hw.instance "name" @B(a: %a: i1) -> ()
// CHECK: B name_0 (
@ -114,7 +114,7 @@ hw.module @TestDupInstanceName(%a: i1) {
}
// CHECK-LABEL: module TestEmptyInstanceName(
hw.module @TestEmptyInstanceName(%a: i1) {
hw.module @TestEmptyInstanceName(in %a: i1) {
// CHECK: B _GEN (
hw.instance "" @B(a: %a: i1) -> ()
// CHECK: B _GEN_0 (
@ -122,7 +122,7 @@ hw.module @TestEmptyInstanceName(%a: i1) {
}
// CHECK-LABEL: module TestInstanceNameValueConflict(
hw.module @TestInstanceNameValueConflict(%a: i1) {
hw.module @TestInstanceNameValueConflict(in %a: i1) {
// CHECK: wire name;
%name = sv.wire : !hw.inout<i1>
// CHECK: wire output_0;
@ -135,13 +135,13 @@ hw.module @TestInstanceNameValueConflict(%a: i1) {
// https://github.com/llvm/circt/issues/855
// CHECK-LABEL: module nameless_reg(
hw.module @nameless_reg(%a: i1) -> () {
hw.module @nameless_reg(in %a: i1) {
// CHECK: reg [3:0] _GEN;
%661 = sv.reg : !hw.inout<i4>
}
// CHECK-LABEL: module verif_renames(
hw.module @verif_renames(%cond: i1) {
hw.module @verif_renames(in %cond: i1) {
// CHECK: initial
sv.initial {
// CHECK: assert_0: assert(cond);
@ -150,7 +150,7 @@ hw.module @verif_renames(%cond: i1) {
}
// CHECK-LABEL: module verbatim_renames(
hw.module @verbatim_renames(%a: i1 {hw.exportPort = #hw<innerSym@asym>}) {
hw.module @verbatim_renames(in %a: i1 {hw.exportPort = #hw<innerSym@asym>}) {
// CHECK: // VERB Module : reg_0 inout_0
// CHECK: wire wire_0;
sv.verbatim "// VERB Module : {{0}} {{1}}" {symbols = [@reg, @inout]}

10
test/Conversion/ExportVerilog/no-wrap.mlir
View File

@ -5,7 +5,7 @@
// CHECK{LITERAL}: // {{
// CHECK-NEXT: endmodule
hw.module @VerbatimWrapping(%clock : i1, %cond : i1, %val : i8, %a : i3, %b : i3) {
hw.module @VerbatimWrapping(in %clock : i1, in %cond : i1, in %val : i8, in %a : i3, in %b : i3) {
%x = comb.add %a, %b : i3
%y = comb.xor %a, %b : i3
%arr = hw.array_create %x, %y, %x, %y, %x, %y, %x, %y, %x, %y, %x, %y : i3
@ -25,8 +25,8 @@ hw.module @VerbatimWrapping(%clock : i1, %cond : i1, %val : i8, %a : i3, %b : i3
// CHECK-NEXT: // Zero width: assign
// CHECK-SAME: ;
// CHECK-NEXT: endmodule
hw.module @TestZero(%a: i4, %zeroBitWithAVeryLongNameWhichMightSeemUnlikelyButHappensAllTheTime: i0, %arrZero: !hw.array<3xi0>)
-> (r0: i4, rZeroOutputWithAVeryLongName_YepThisToo_LongNamesAreTheWay_MoreText_GoGoGoGoGo: i0, arrZero_0: !hw.array<3xi0>) {
hw.module @TestZero(in %a: i4, in %zeroBitWithAVeryLongNameWhichMightSeemUnlikelyButHappensAllTheTime: i0, in %arrZero: !hw.array<3xi0>,
out r0: i4, out rZeroOutputWithAVeryLongName_YepThisToo_LongNamesAreTheWay_MoreText_GoGoGoGoGo: i0, out arrZero_0: !hw.array<3xi0>) {
%b = comb.add %a, %a : i4
%c = comb.add %zeroBitWithAVeryLongNameWhichMightSeemUnlikelyButHappensAllTheTime, %zeroBitWithAVeryLongNameWhichMightSeemUnlikelyButHappensAllTheTime : i0
@ -50,8 +50,8 @@ hw.module @TestZero(%a: i4, %zeroBitWithAVeryLongNameWhichMightSeemUnlikelyButHa
// CHECK: // Zero width: assign
// CHECK-SAME: ;
// CHECK-NEXT: endmodule
hw.module @TestZeroInstance(%aa: i4, %azeroBit: i0, %aarrZero: !hw.array<3xi0>)
-> (r0: i4, rZeroOutputWithAVeryLongNameYepThisToo: i0, arrZero_0: !hw.array<3xi0>) {
hw.module @TestZeroInstance(in %aa: i4, in %azeroBit: i0, in %aarrZero: !hw.array<3xi0>,
out r0: i4, out rZeroOutputWithAVeryLongNameYepThisToo: i0, out arrZero_0: !hw.array<3xi0>) {
%o1, %o2, %o3 = hw.instance "iii" @TestZero(a: %aa: i4, zeroBitWithAVeryLongNameWhichMightSeemUnlikelyButHappensAllTheTime: %azeroBit: i0, arrZero: %aarrZero: !hw.array<3xi0>) -> (r0: i4, rZeroOutputWithAVeryLongName_YepThisToo_LongNamesAreTheWay_MoreText_GoGoGoGoGo: i0, arrZero_0: !hw.array<3xi0>)

6
test/Conversion/ExportVerilog/output-file.mlir
View File

@ -5,7 +5,7 @@
#file1 = #hw.output_file<"dir1/file1.sv", includeReplicatedOps>
#filelist1 = #hw.output_filelist<"dir5/foo.f">
hw.module @foo1(%a: i1) -> (b: i1) attributes {output_file = #file1, output_filelist = #filelist1} {
hw.module @foo1(in %a: i1, out b: i1) attributes {output_file = #file1, output_filelist = #filelist1} {
hw.output %a : i1
}
// CHECK-LABEL: FILE "dir1{{[/\]}}file1.sv"
@ -16,7 +16,7 @@ hw.module @foo1(%a: i1) -> (b: i1) attributes {output_file = #file1, output_file
#file2 = #hw.output_file<"dir1/file2.sv">
#filelist2 = [#hw.output_filelist<"dir5/foo.f"> ,#hw.output_filelist<"dir5/bar.f">]
hw.module @foo2(%a: i1) -> (b: i1) attributes {output_file = #file2, output_filelist = #filelist2} {
hw.module @foo2(in %a: i1, out b: i1) attributes {output_file = #file2, output_filelist = #filelist2} {
hw.output %a : i1
}
// CHECK-LABEL: FILE "dir1{{[/\]}}file2.sv"
@ -26,7 +26,7 @@ hw.module @foo2(%a: i1) -> (b: i1) attributes {output_file = #file2, output_file
#file3 = #hw.output_file<"dir2/", includeReplicatedOps>
#filelist3 = [#hw.output_filelist<"dir5/bar.f">]
hw.module @foo3(%a: i1) -> (b: i1) attributes {output_file = #file3, output_filelist = #filelist3} {
hw.module @foo3(in %a: i1, out b: i1) attributes {output_file = #file3, output_filelist = #filelist3} {
hw.output %a : i1
}
// CHECK-LABEL: FILE "dir2{{[/\]}}foo3.sv"

12
test/Conversion/ExportVerilog/port-decl-sharing.mlir
View File

@ -7,7 +7,7 @@ module attributes {circt.loweringOptions = "disallowPortDeclSharing"}{
// CHECK-NEXT: output [1:0] a_0, // dummy:1:4
// CHECK-NEXT: output [1:0] b_0 // dummy:1:5
// CHECK-NEXT: );
hw.module @Foo(%a: i1 loc("dummy":1:2), %b: i1 loc("dummy":1:3)) -> (a: i2 loc("dummy":1:4), b: i2 loc("dummy":1:5)) {
hw.module @Foo(in %a: i1 loc("dummy":1:2), in %b: i1 loc("dummy":1:3), out a: i2 loc("dummy":1:4), out b: i2 loc("dummy":1:5)) {
%ao = comb.concat %a, %b: i1, i1
%bo = comb.concat %a, %a: i1, i1
hw.output %ao, %bo : i2, i2
@ -23,7 +23,7 @@ module {
// CHECK-NEXT: output [1:0] a_0, // dummy:1:4
// CHECK-NEXT: b_0 // dummy:1:5
// CHECK-NEXT: );
hw.module @Foo(%a: i1 loc("dummy":1:2), %b: i1 loc("dummy":1:3)) -> (a: i2 loc("dummy":1:4), b: i2 loc("dummy":1:5)) {
hw.module @Foo(in %a: i1 loc("dummy":1:2), in %b: i1 loc("dummy":1:3), out a: i2 loc("dummy":1:4), out b: i2 loc("dummy":1:5)) {
%ao = comb.concat %a, %b: i1, i1
%bo = comb.concat %a, %a: i1, i1
hw.output %ao, %bo : i2, i2
@ -38,7 +38,7 @@ hw.module @Foo(%a: i1 loc("dummy":1:2), %b: i1 loc("dummy":1:3)) -> (a: i2 loc("
// CHECK-NEXT: // output /*Zero Width*/ b_0 // dummy:1:5
// CHECK-NEXT: );
module attributes {circt.loweringOptions = "disallowPortDeclSharing"}{
hw.module @Foo(%a: i0 loc("dummy":1:2), %b: i0 loc("dummy":1:3)) -> (a: i0 loc("dummy":1:4), b: i0 loc("dummy":1:5)) {
hw.module @Foo(in %a: i0 loc("dummy":1:2), in %b: i0 loc("dummy":1:3), out a: i0 loc("dummy":1:4), out b: i0 loc("dummy":1:5)) {
hw.output %a, %b : i0, i0
} loc("dummy":1:1)
}
@ -52,7 +52,7 @@ module {
// CHECK-NEXT: // output /*Zero Width*/ a_0, // dummy:1:4
// CHECK-NEXT: // b_0 // dummy:1:5
// CHECK-NEXT: );
hw.module @Foo(%a: i0 loc("dummy":1:2), %b: i0 loc("dummy":1:3)) -> (a: i0 loc("dummy":1:4), b: i0 loc("dummy":1:5)) {
hw.module @Foo(in %a: i0 loc("dummy":1:2), in %b: i0 loc("dummy":1:3), out a: i0 loc("dummy":1:4), out b: i0 loc("dummy":1:5)) {
hw.output %a, %b : i0, i0
} loc("dummy":1:1)
}
@ -67,7 +67,7 @@ module attributes {circt.loweringOptions = "disallowPortDeclSharing"}{
// CHECK-NEXT: // output /*Zero Width*/ a_0, // dummy:1:4
// CHECK-NEXT: // output /*Zero Width*/ b_0 // dummy:1:5
// CHECK-NEXT: );
hw.module @Foo(%a: i0 loc("dummy":1:2), %b: i0 loc("dummy":1:3), %c : i100 loc("new":1:1)) -> (a: i0 loc("dummy":1:4), b: i0 loc("dummy":1:5)) {
hw.module @Foo(in %a: i0 loc("dummy":1:2), in %b: i0 loc("dummy":1:3), in %c : i100 loc("new":1:1), out a: i0 loc("dummy":1:4), out b: i0 loc("dummy":1:5)) {
hw.output %a, %b : i0, i0
} loc("dummy":1:1)
}
@ -82,7 +82,7 @@ module {
// CHECK-NEXT: // output /*Zero Width*/ a_0, // dummy:1:4
// CHECK-NEXT: // b_0 // dummy:1:5
// CHECK-NEXT: );
hw.module @Foo(%a: i0 loc("dummy":1:2), %b: i0 loc("dummy":1:3), %c : i100 loc("new":1:1)) -> (a: i0 loc("dummy":1:4), b: i0 loc("dummy":1:5)) {
hw.module @Foo(in %a: i0 loc("dummy":1:2), in %b: i0 loc("dummy":1:3), in %c : i100 loc("new":1:1), out a: i0 loc("dummy":1:4), out b: i0 loc("dummy":1:5)) {
hw.output %a, %b : i0, i0
} loc("dummy":1:1)
}

39
test/Conversion/ExportVerilog/prepare-for-emission.mlir
View File

@ -2,7 +2,7 @@
// RUN: circt-opt %s -export-verilog -split-input-file
// CHECK: @namehint_variadic
hw.module @namehint_variadic(%a: i3) -> (b: i3) {
hw.module @namehint_variadic(in %a: i3, out b: i3) {
// CHECK-NEXT: %0 = comb.add %a, %a : i3
// CHECK-NEXT: %1 = comb.add %a, %0 {sv.namehint = "bar"} : i3
// CHECK-NEXT: hw.output %1
@ -11,7 +11,7 @@ hw.module @namehint_variadic(%a: i3) -> (b: i3) {
}
// CHECK-LABEL: hw.module @outOfOrderInoutOperations
hw.module @outOfOrderInoutOperations(%a: i4) -> (c: i4) {
hw.module @outOfOrderInoutOperations(in %a: i4, out c: i4) {
// CHECK: %wire = sv.wire
// CHECK-NEXT: %0 = sv.array_index_inout %wire[%false]
// CHECK-NEXT: %1 = sv.array_index_inout %0[%false]
@ -27,7 +27,7 @@ hw.module @outOfOrderInoutOperations(%a: i4) -> (c: i4) {
}
// CHECK-LABEL: @twoState_variadic
hw.module @twoState_variadic(%a: i1, %b: i1, %c: i1) -> (d:i1){
hw.module @twoState_variadic(in %a: i1, in %b: i1, in %c: i1, out d:i1){
// CHECK: %0 = comb.or bin %b, %c : i1
// CHECK-NEXT: %1 = comb.or bin %a, %0 : i1
// CHECK-NEXT: hw.output %1 : i1
@ -36,7 +36,7 @@ hw.module @twoState_variadic(%a: i1, %b: i1, %c: i1) -> (d:i1){
}
// CHECK-LABEL: @carryOverWireAttrs
hw.module @carryOverWireAttrs(%a: i1) -> (b: i1){
hw.module @carryOverWireAttrs(in %a: i1, out b: i1){
// CHECK-NEXT: %foo = sv.wire {magic, sv.attributes = []} : !hw.inout<i1>
// CHECK-NEXT: sv.assign %foo, %a
// CHECK-NEXT: [[TMP:%.+]] = sv.read_inout %foo
@ -49,7 +49,7 @@ hw.module @carryOverWireAttrs(%a: i1) -> (b: i1){
module {
// CHECK-LABEL: hw.module @SpillTemporaryInProceduralRegion
hw.module @SpillTemporaryInProceduralRegion(%a: i4, %b: i4, %fd: i32) -> () {
hw.module @SpillTemporaryInProceduralRegion(in %a: i4, in %b: i4, in %fd: i32) {
// CHECK-NEXT: %r = sv.reg
// CHECK-NEXT: sv.initial {
// CHECK-NEXT: %0 = sv.logic
@ -73,7 +73,7 @@ module {
module attributes {circt.loweringOptions = "disallowLocalVariables"} {
// CHECK: @test_hoist
hw.module @test_hoist(%a: i3) -> () {
hw.module @test_hoist(in %a: i3) {
// CHECK-NEXT: %reg = sv.reg
%reg = sv.reg : !hw.inout<i3>
// CHECK-NEXT: %0 = comb.add
@ -85,7 +85,7 @@ module attributes {circt.loweringOptions = "disallowLocalVariables"} {
}
// CHECK-LABEL: hw.module @SpillTemporary
hw.module @SpillTemporary(%a: i4, %b: i4) -> (c: i1) {
hw.module @SpillTemporary(in %a: i4, in %b: i4, out c: i1) {
// CHECK-NEXT: %0 = comb.add %a, %b
// CHECK-NEXT: %[[GEN:.+]] = sv.wire
// CHECK-NEXT: sv.assign %1, %[[GEN:.+]]
@ -98,7 +98,7 @@ module attributes {circt.loweringOptions = "disallowLocalVariables"} {
}
// CHECK-LABEL: hw.module @SpillTemporaryInProceduralRegion
hw.module @SpillTemporaryInProceduralRegion(%a: i4, %b: i4, %fd: i32) -> () {
hw.module @SpillTemporaryInProceduralRegion(in %a: i4, in %b: i4, in %fd: i32) {
// CHECK-NEXT: %r = sv.reg
// CHECK-NEXT: %[[VAL:.+]] = comb.add %a, %b
// CHECK-NEXT: %[[GEN:.+]] = sv.wire
@ -118,7 +118,7 @@ module attributes {circt.loweringOptions = "disallowLocalVariables"} {
}
// CHECK-LABEL: @SpillTemporaryWireForMultipleUseExpression
hw.module @SpillTemporaryWireForMultipleUseExpression(%a: i4, %b: i4) -> (c: i4, d: i4) {
hw.module @SpillTemporaryWireForMultipleUseExpression(in %a: i4, in %b: i4, out c: i4, out d: i4) {
// CHECK-NEXT: %[[VAL:.+]] = comb.add %a, %b
// CHECK-NEXT: %[[GEN:bar]] = sv.wire
// CHECK-NEXT: sv.assign %[[GEN]], %[[VAL]]
@ -133,9 +133,9 @@ module attributes {circt.loweringOptions = "disallowLocalVariables"} {
// -----
module attributes {circt.loweringOptions = "disallowExpressionInliningInPorts"} {
hw.module.extern @MyExtModule(%in: i8)
hw.module.extern @MyExtModule(in %in: i8)
// CHECK-LABEL: @MoveInstances
hw.module @MoveInstances(%a_in: i8) -> (){
hw.module @MoveInstances(in %a_in: i8){
// CHECK-NEXT: %_xyz3_in = sv.wire
// CHECK-NEXT: %0 = comb.add %a_in, %a_in
// CHECK-NEXT: %1 = sv.read_inout %_xyz3_in
@ -150,7 +150,7 @@ module attributes {circt.loweringOptions = "disallowExpressionInliningInPorts"}
module attributes {circt.loweringOptions =
"wireSpillingHeuristic=spillLargeTermsWithNamehints,wireSpillingNamehintTermLimit=3"} {
// CHECK-LABEL: namehints
hw.module @namehints(%a: i8) -> (b: i8) {
hw.module @namehints(in %a: i8, out b: i8) {
// "foo" should be spilled because it has a meaningful name.
// CHECK: %foo = sv.wire
%0 = comb.add %a, %a {sv.namehint = "foo" } : i8
@ -169,7 +169,7 @@ module attributes {circt.loweringOptions =
module attributes {circt.loweringOptions =
"disallowMuxInlining"} {
// CHECK-LABEL: mux
hw.module @mux(%c: i1, %b: i8, %a: i8) -> (d: i8, e: i8) {
hw.module @mux(in %c: i1, in %b: i8, in %a: i8, out d: i8, out e: i8) {
// CHECK: %use_for_mux = sv.wire
// CHECK-NEXT: sv.assign %use_for_mux, %0 : i8
// CHECK-NEXT: %[[read:.+]] = sv.read_inout %use_for_mux : !hw.inout<i8>
@ -189,7 +189,7 @@ module attributes {circt.loweringOptions =
// CHECK: "wireSpillingHeuristic=spillLargeTermsWithNamehints,disallowMuxInlining"
module attributes {circt.loweringOptions =
"wireSpillingHeuristic=spillLargeTermsWithNamehints,disallowMuxInlining"} {
hw.module @combine(%c: i1, %b: i8, %a: i8) -> (d: i8) {
hw.module @combine(in %c: i1, in %b: i8, in %a: i8, out d: i8) {
// Meaningful names should be spilled
// CHECK: %foo = sv.wire
// Mux should be spilled
@ -204,7 +204,7 @@ module attributes {circt.loweringOptions =
// -----
module attributes {circt.loweringOptions = "maximumNumberOfTermsPerExpression=2"} {
// CHECK-NOT: sv.wire
hw.module @Foo(%in_0: i4, %in_1: i4, %in_2: i4, %in_3: i4) -> (out: !hw.array<4xi4>) {
hw.module @Foo(in %in_0: i4, in %in_1: i4, in %in_2: i4, in %in_3: i4, out out: !hw.array<4xi4>) {
%0 = comb.concat %in_0, %in_1, %in_2, %in_3 : i4, i4, i4, i4
%1 = hw.bitcast %0 : (i16) -> !hw.array<4xi4>
hw.output %1 : !hw.array<4xi4>
@ -213,8 +213,7 @@ module attributes {circt.loweringOptions = "maximumNumberOfTermsPerExpression=2"
// -----
// CHECK-LABEL: hw.module @packed_struct_assignment(
// CHECK-SAME: %[[VAL_0:.*]]: i32) -> (out: !hw.struct<a: i32>, out2: !hw.struct<a: i32>, out3: !hw.struct<a: i32>) {
// CHECK: hw.module @packed_struct_assignment(in %[[VAL_0:.*]] : i32, out out : !hw.struct<a: i32>, out out2 : !hw.struct<a: i32>, out out3 : !hw.struct<a: i32>) {
// CHECK: %[[VAL_1:.*]] = sv.wire
// CHECK-NEXT: %[[VAL_2:.*]] = sv.struct_field_inout %[[VAL_1]]["a"]
// CHECK-NEXT: sv.assign %[[VAL_2]], %[[VAL_0]]
@ -228,7 +227,7 @@ module attributes {circt.loweringOptions = "maximumNumberOfTermsPerExpression=2"
// CHECK: }
!T = !hw.struct<a: i32>
module attributes { circt.loweringOptions = "disallowPackedStructAssignments"} {
hw.module @packed_struct_assignment(%in : i32) -> (out: !T, out2: !T, out3: !T) {
hw.module @packed_struct_assignment(in %in : i32, out out: !T, out out2: !T, out out3: !T) {
%0 = hw.struct_create (%in) : !T
%1 = hw.aggregate_constant [1: i32] : !T
hw.output %0, %0, %1 : !T, !T, !T
@ -240,7 +239,7 @@ module attributes { circt.loweringOptions = "disallowPackedStructAssignments"} {
// wires, where they crash the PrepareForEmission pass. They are always emitted
// inline, so no need to restructure the IR.
// CHECK-LABEL: hw.module @Issue5613
hw.module @Issue5613(%a: i1, %b: i1) {
hw.module @Issue5613(in %a: i1, in %b: i1) {
verif.assert %2 : !ltl.sequence
%0 = ltl.implication %2, %1 : !ltl.sequence, !ltl.property
%1 = ltl.or %b, %3 : i1, !ltl.property
@ -258,7 +257,7 @@ hw.module @Issue5613(%a: i1, %b: i1) {
//
// See: https://github.com/llvm/circt/issues/5605
// CHECK-LABEL: hw.module @Issue5605
hw.module @Issue5605(%a: i1, %b: i1, %clock: i1, %reset: i1) {
hw.module @Issue5605(in %a: i1, in %b: i1, in %clock: i1, in %reset: i1) {
%0 = comb.concat %a, %b : i1, i1
// CHECK: %1 = sv.wire
// CHECK-NEXT: sv.assign %1, %0

10
test/Conversion/ExportVerilog/pretty.mlir
View File

@ -23,7 +23,7 @@ sv.interface @IValidReady_Struct {
// CHECK-NEXT: _GEN_1,
// CHECK-NEXT: _GEN_0,
// CHECK-NEXT: _GEN_0})};{{.*}}
hw.module @structs(%clk: i1, %rstn: i1) {
hw.module @structs(in %clk: i1, in %rstn: i1) {
%0 = sv.interface.instance name "iface" : !sv.interface<@IValidReady_Struct>
sv.interface.signal.assign %0(@IValidReady_Struct::@data) = %s : !hw.struct<foo: !hw.array<72xi1>, bar: !hw.array<128xi1>, baz: !hw.array<224xi1>>
%c0 = hw.constant 0 : i8
@ -40,8 +40,8 @@ hw.module @structs(%clk: i1, %rstn: i1) {
// CHECK-LABEL:module CoverAssert({{.*}}
hw.module @CoverAssert(
%clock: i1, %reset: i1,
%eeeeee_fffff_gggggg_hhh_i_jjjjj_kkkkkkkkk_lllllll_mmmmmmmmm_nnnnnnnn_0: i4) {
in %clock: i1, in %reset: i1,
in %eeeeee_fffff_gggggg_hhh_i_jjjjj_kkkkkkkkk_lllllll_mmmmmmmmm_nnnnnnnn_0: i4) {
%c0_i4 = hw.constant 0 : i4
%true = hw.constant true
@ -67,7 +67,7 @@ hw.module @CoverAssert(
sv.assert.concurrent posedge %clock, %5 label "assert__label" message "assert failed"
}
hw.module @MuxChain(%a_0: i1, %a_1: i1, %a_2: i1, %c_0: i1, %c_1: i1, %c_2: i1) -> (out: i1) {
hw.module @MuxChain(in %a_0: i1, in %a_1: i1, in %a_2: i1, in %c_0: i1, in %c_1: i1, in %c_2: i1, out out: i1) {
%0 = comb.mux bin %a_1, %c_1, %c_0 : i1
%1 = comb.mux bin %a_0, %0, %c_2 : i1
%2 = comb.mux bin %a_2, %1, %c_1 : i1
@ -240,7 +240,7 @@ hw.module @svattrs() {
sv.macro.decl @RANDOM
// CHECK-LABEL:module ForStatement{{.*}}
hw.module @ForStatement(%aaaaaaaaaaa: i5, %xxxxxxxxxxxxxxx : i2, %yyyyyyyyyyyyyyy : i2, %zzzzzzzzzzzzzzz : i2) -> () {
hw.module @ForStatement(in %aaaaaaaaaaa: i5, in %xxxxxxxxxxxxxxx : i2, in %yyyyyyyyyyyyyyy : i2, in %zzzzzzzzzzzzzzz : i2) {
%_RANDOM = sv.logic : !hw.inout<uarray<3xi32>>
sv.initial {
%x_and_y = comb.and %xxxxxxxxxxxxxxx, %yyyyyyyyyyyyyyy : i2

10
test/Conversion/ExportVerilog/pruning.mlir
View File

@ -3,7 +3,7 @@
// CHECK-LABEL: module zeroWidthPAssign(
// CHECK: always_ff @(posedge clk) begin
// CHECK-NEXT: end
hw.module @zeroWidthPAssign(%arg0: i0, %clk: i1) -> (out: i0) {
hw.module @zeroWidthPAssign(in %arg0 : i0, in %clk: i1, out out: i0) {
%0 = sv.reg {hw.verilogName = "_GEN"} : !hw.inout<i0>
sv.alwaysff(posedge %clk) {
sv.passign %0, %arg0 : i0
@ -13,7 +13,7 @@ hw.module @zeroWidthPAssign(%arg0: i0, %clk: i1) -> (out: i0) {
}
// CHECK-LABEL: module zeroWidthLogic(
// CHECK-NOT: reg
hw.module @zeroWidthLogic(%arg0: i0, %sel : i1, %clk: i1) -> (out: i0) {
hw.module @zeroWidthLogic(in %arg0 : i0, in %sel : i1, in %clk : i1, out out : i0) {
%r = sv.reg : !hw.inout<i0>
%rr = sv.read_inout %r : !hw.inout<i0>
%2 = comb.mux %sel, %rr, %arg0 : i0
@ -21,14 +21,14 @@ hw.module @zeroWidthLogic(%arg0: i0, %sel : i1, %clk: i1) -> (out: i0) {
}
// CHECK-LABEL: module Concat(
hw.module @Concat(%arg0: i0, %arg1: i1, %clk: i1) -> (out: i2) {
hw.module @Concat(in %arg0 : i0, in %arg1 : i1, in %clk : i1, out out: i2) {
// CHECK: assign out = {arg1, clk};
%1 = comb.concat %arg0, %arg1, %clk : i0, i1, i1
hw.output %1 : i2
}
// CHECK-LABEL: module icmp(
hw.module @icmp(%a: i0) -> (y: i1) {
hw.module @icmp(in %a : i0, out y: i1) {
// CHECK: assign y = 1'h1;
%0 = comb.icmp eq %a, %a : i0
hw.output %0 : i1
@ -36,7 +36,7 @@ hw.module @icmp(%a: i0) -> (y: i1) {
// CHECK-LABEL: module parity(
hw.module @parity(%arg0: i0) -> (out: i1) {
hw.module @parity(in %arg0 : i0, out out: i1) {
// CHECK: assign out = 1'h0;
%0 = comb.parity %arg0 : i0
hw.output %0 : i1

4
test/Conversion/ExportVerilog/sv-always-wire.mlir
View File

@ -2,7 +2,7 @@
// RUN: circt-opt %s -test-apply-lowering-options='options=exprInEventControl' -prettify-verilog -export-verilog | FileCheck %s --check-prefix=INLINE
// CHECK-LABEL: module AlwaysSpill(
hw.module @AlwaysSpill(%port: i1) {
hw.module @AlwaysSpill(in %port: i1) {
%false = hw.constant false
%true = hw.constant true
%awire = sv.wire : !hw.inout<i1>
@ -33,7 +33,7 @@ hw.module @AlwaysSpill(%port: i1) {
// CHECK-LABEL: module Foo
// INLINE-LABEL: module Foo
hw.module @Foo(%reset0: i1, %reset1: i1) -> () {
hw.module @Foo(in %reset0: i1, in %reset1: i1) {
%0 = comb.or %reset0, %reset1 : i1
// CHECK: wire [[TMP0:.*]] = reset0 | reset1;
// CHECK-NEXT: always @(posedge [[TMP0]])

132
test/Conversion/ExportVerilog/sv-dialect.mlir
View File

@ -2,7 +2,7 @@
// CHECK-LABEL: module M1
// CHECK-NEXT: #(parameter [41:0] param1) (
hw.module @M1<param1: i42>(%clock : i1, %cond : i1, %val : i8) {
hw.module @M1<param1: i42>(in %clock : i1, in %cond : i1, in %val : i8) {
%wire42 = sv.reg : !hw.inout<i42>
%forceWire = sv.wire sym @wire1 : !hw.inout<i1>
%partSelectReg = sv.reg : !hw.inout<i42>
@ -462,8 +462,7 @@ hw.module @M1<param1: i42>(%clock : i1, %cond : i1, %val : i8) {
// CHECK-NEXT: b, //
// CHECK-NEXT: c //
// CHECK-NEXT: );
hw.module @Aliasing(%a : !hw.inout<i42>, %b : !hw.inout<i42>,
%c : !hw.inout<i42>) {
hw.module @Aliasing(inout %a : i42, inout %b : i42, inout %c : i42) {
// CHECK: alias a = b;
sv.alias %a, %b : !hw.inout<i42>, !hw.inout<i42>
@ -471,7 +470,7 @@ hw.module @Aliasing(%a : !hw.inout<i42>, %b : !hw.inout<i42>,
sv.alias %a, %b, %c : !hw.inout<i42>, !hw.inout<i42>, !hw.inout<i42>
}
hw.module @reg_0(%in4: i4, %in8: i8) -> (a: i8, b: i8) {
hw.module @reg_0(in %in4: i4, in %in8: i8, out a: i8, out b: i8) {
// CHECK-LABEL: module reg_0(
// CHECK-NEXT: input [3:0] in4, //
// CHECK-NEXT: input [7:0] in8, //
@ -513,7 +512,7 @@ hw.module @reg_0(%in4: i4, %in8: i8) -> (a: i8, b: i8) {
hw.output %regout, %memout : i8, i8
}
hw.module @reg_1(%in4: i4, %in8: i8) -> (a : i3, b : i5) {
hw.module @reg_1(in %in4: i4, in %in8: i8, out a : i3, out b : i5) {
// CHECK-LABEL: module reg_1(
// CHECK: reg [17:0] myReg2
@ -539,7 +538,7 @@ hw.module @reg_1(%in4: i4, %in8: i8) -> (a : i3, b : i5) {
// CHECK-LABEL: module regWithInit(
// CHECK: reg reg1 = 1'h0;
// CHECK: reg [31:0] reg2 = 32'(arg + arg);
hw.module @regWithInit(%arg : i32) {
hw.module @regWithInit(in %arg : i32) {
%c0_i1 = hw.constant 0 : i1
%reg1 = sv.reg init %c0_i1 : !hw.inout<i1>
@ -550,7 +549,7 @@ hw.module @regWithInit(%arg : i32) {
// CHECK-LABEL: module struct_field_inout1(
// CHECK-NEXT: inout struct packed {logic b; } a
// CHECK-NEXT: );
hw.module @struct_field_inout1(%a : !hw.inout<struct<b: i1>>) {
hw.module @struct_field_inout1(inout %a : !hw.struct<b: i1>) {
// CHECK: assign a.b = 1'h1;
%true = hw.constant true
%0 = sv.struct_field_inout %a["b"] : !hw.inout<struct<b: i1>>
@ -560,7 +559,7 @@ hw.module @struct_field_inout1(%a : !hw.inout<struct<b: i1>>) {
// CHECK-LABEL: module struct_field_inout2(
// CHECK-NEXT: inout struct packed {struct packed {logic c; } b; } a
// CHECK-NEXT: );
hw.module @struct_field_inout2(%a: !hw.inout<struct<b: !hw.struct<c: i1>>>) {
hw.module @struct_field_inout2(inout %a: !hw.struct<b: !hw.struct<c: i1>>) {
// CHECK: assign a.b.c = 1'h1;
%true = hw.constant true
%0 = sv.struct_field_inout %a["b"] : !hw.inout<struct<b: !hw.struct<c: i1>>>
@ -569,7 +568,7 @@ hw.module @struct_field_inout2(%a: !hw.inout<struct<b: !hw.struct<c: i1>>>) {
}
// CHECK-LABEL: module PartSelectInoutInline(
hw.module @PartSelectInoutInline(%v:i40) {
hw.module @PartSelectInoutInline(in %v:i40) {
%r = sv.reg : !hw.inout<i42>
%c2_i3 = hw.constant 2 : i3
%a = sv.indexed_part_select_inout %r[%c2_i3 : 40] : !hw.inout<i42>, i3
@ -581,8 +580,8 @@ hw.module @PartSelectInoutInline(%v:i40) {
}
// CHECK-LABEL: module AggregateConstantXZ(
hw.module @AggregateConstantXZ() -> (res1: !hw.struct<foo: i2, bar: !hw.array<3xi4>>,
res2: !hw.struct<foo: i2, bar: !hw.array<3xi4>>) {
hw.module @AggregateConstantXZ(out res1: !hw.struct<foo: i2, bar: !hw.array<3xi4>>,
out res2 : !hw.struct<foo: i2, bar: !hw.array<3xi4>>) {
%0 = sv.constantX : !hw.struct<foo: i2, bar: !hw.array<3xi4>>
%1 = sv.constantZ : !hw.struct<foo: i2, bar: !hw.array<3xi4>>
// CHECK: assign res1 = 14'bx
@ -591,7 +590,7 @@ hw.module @AggregateConstantXZ() -> (res1: !hw.struct<foo: i2, bar: !hw.array<3x
}
// CHECK-LABEL: module AggregateVerbatim(
hw.module @AggregateVerbatim() -> (res1: !hw.struct<a: i1>, res2: !hw.array<1xi1>, res3: !hw.array<1xi1>) {
hw.module @AggregateVerbatim(out res1: !hw.struct<a: i1>, out res2: !hw.array<1xi1>, out res3: !hw.array<1xi1>) {
%a = sv.verbatim.expr "STRUCT_A_" : () -> !hw.struct<a: i1>
%b = sv.verbatim.expr "ARRAY_" : () -> !hw.array<1xi1>
%c = sv.verbatim.expr "MACRO({{0}}, {{1}})" (%a, %b) : (!hw.struct<a: i1>, !hw.array<1xi1>) -> !hw.array<1xi1>
@ -603,7 +602,7 @@ hw.module @AggregateVerbatim() -> (res1: !hw.struct<a: i1>, res2: !hw.array<1xi1
// CHECK-LABEL: issue508
// https://github.com/llvm/circt/issues/508
hw.module @issue508(%in1: i1, %in2: i1) {
hw.module @issue508(in %in1: i1, in %in2: i1) {
// CHECK: wire _GEN = in1 | in2;
%clock = comb.or %in1, %in2 : i1
@ -615,7 +614,7 @@ hw.module @issue508(%in1: i1, %in2: i1) {
// CHECK-LABEL: exprInlineTestIssue439
// https://github.com/llvm/circt/issues/439
hw.module @exprInlineTestIssue439(%clk: i1) {
hw.module @exprInlineTestIssue439(in %clk: i1) {
%fd = hw.constant 0x80000002 : i32
// CHECK: always @(posedge clk) begin
@ -633,7 +632,7 @@ hw.module @exprInlineTestIssue439(%clk: i1) {
// https://github.com/llvm/circt/issues/595
// CHECK-LABEL: module issue595
hw.module @issue595(%arr: !hw.array<128xi1>) {
hw.module @issue595(in %arr: !hw.array<128xi1>) {
// CHECK: wire [31:0] [[TEMP1:.+]];
%c0_i32 = hw.constant 0 : i32
%c0_i7 = hw.constant 0 : i7
@ -655,7 +654,7 @@ hw.module @issue595(%arr: !hw.array<128xi1>) {
// CHECK-LABEL: module issue595_variant1
hw.module @issue595_variant1(%arr: !hw.array<128xi1>) {
hw.module @issue595_variant1(in %arr: !hw.array<128xi1>) {
// CHECK: wire [31:0] [[TEMP1:.+]];
%c0_i32 = hw.constant 0 : i32
%c0_i7 = hw.constant 0 : i7
@ -676,7 +675,7 @@ hw.module @issue595_variant1(%arr: !hw.array<128xi1>) {
}
// CHECK-LABEL: module issue595_variant2_checkRedunctionAnd
hw.module @issue595_variant2_checkRedunctionAnd(%arr: !hw.array<128xi1>) {
hw.module @issue595_variant2_checkRedunctionAnd(in %arr: !hw.array<128xi1>) {
// CHECK: wire [31:0] [[TEMP1:.+]];
%c0_i32 = hw.constant -1 : i32
%c0_i7 = hw.constant 0 : i7
@ -697,8 +696,8 @@ hw.module @issue595_variant2_checkRedunctionAnd(%arr: !hw.array<128xi1>) {
}
// CHECK-LABEL: module slice_inline_ports
hw.module @slice_inline_ports(%arr: !hw.array<128xi1>, %x: i3, %y: i7)
-> (o1: !hw.array<2xi3>, o2: !hw.array<64xi1>, o3: !hw.array<64xi1>) {
hw.module @slice_inline_ports(in %arr: !hw.array<128xi1>, in %x: i3, in %y: i7,
out o1: !hw.array<2xi3>, out o2: !hw.array<64xi1>, out o3: !hw.array<64xi1>) {
// array_create cannot be inlined into the slice.
%c1_i2 = hw.constant 1 : i2
@ -723,7 +722,7 @@ hw.module @slice_inline_ports(%arr: !hw.array<128xi1>, %x: i3, %y: i7)
// CHECK-LABEL: if_multi_line_expr1
hw.module @if_multi_line_expr1(%clock: i1, %reset: i1, %really_long_port: i11) {
hw.module @if_multi_line_expr1(in %clock: i1, in %reset: i1, in %really_long_port: i11) {
%tmp6 = sv.reg : !hw.inout<i25>
// CHECK: if (reset)
@ -746,7 +745,7 @@ hw.module @if_multi_line_expr1(%clock: i1, %reset: i1, %really_long_port: i11) {
}
// CHECK-LABEL: if_multi_line_expr2
hw.module @if_multi_line_expr2(%clock: i1, %reset: i1, %really_long_port: i11) {
hw.module @if_multi_line_expr2(in %clock: i1, in %reset: i1, in %really_long_port: i11) {
%tmp6 = sv.reg : !hw.inout<i25>
%c12345_i25 = hw.constant 12345 : i25
@ -770,7 +769,7 @@ hw.module @if_multi_line_expr2(%clock: i1, %reset: i1, %really_long_port: i11) {
// https://github.com/llvm/circt/issues/720
// CHECK-LABEL: module issue720(
hw.module @issue720(%clock: i1, %arg1: i1, %arg2: i1, %arg3: i1) {
hw.module @issue720(in %clock: i1, in %arg1: i1, in %arg2: i1, in %arg3: i1) {
// CHECK: always @(posedge clock) begin
sv.always posedge %clock {
@ -803,7 +802,7 @@ hw.module @issue720(%clock: i1, %arg1: i1, %arg2: i1, %arg3: i1) {
}
// CHECK-LABEL: module issue720ifdef(
hw.module @issue720ifdef(%clock: i1, %arg1: i1, %arg2: i1, %arg3: i1) {
hw.module @issue720ifdef(in %clock: i1, in %arg1: i1, in %arg2: i1, in %arg3: i1) {
// CHECK: always @(posedge clock) begin
sv.always posedge %clock {
// The variable for the ifdef block needs to be emitted at the top of the
@ -842,7 +841,7 @@ hw.module @issue720ifdef(%clock: i1, %arg1: i1, %arg2: i1, %arg3: i1) {
// https://github.com/llvm/circt/issues/728
// CHECK-LABEL: module issue728(
hw.module @issue728(%clock: i1, %asdfasdfasdfasdfafa: i1, %gasfdasafwjhijjafija: i1) {
hw.module @issue728(in %clock: i1, in %asdfasdfasdfasdfafa: i1, in %gasfdasafwjhijjafija: i1) {
%fd = hw.constant 0x80000002 : i32
// CHECK: always @(posedge clock) begin
@ -862,7 +861,7 @@ hw.module @issue728(%clock: i1, %asdfasdfasdfasdfafa: i1, %gasfdasafwjhijjafija:
}
// CHECK-LABEL: module issue728ifdef(
hw.module @issue728ifdef(%clock: i1, %asdfasdfasdfasdfafa: i1, %gasfdasafwjhijjafija: i1) {
hw.module @issue728ifdef(in %clock: i1, in %asdfasdfasdfasdfafa: i1, in %gasfdasafwjhijjafija: i1) {
%fd = hw.constant 0x80000002 : i32
// CHECK: always @(posedge clock) begin
@ -885,7 +884,7 @@ hw.module @issue728ifdef(%clock: i1, %asdfasdfasdfasdfafa: i1, %gasfdasafwjhijja
}
// CHECK-LABEL: module alwayscombTest(
hw.module @alwayscombTest(%a: i1) -> (x: i1) {
hw.module @alwayscombTest(in %a: i1, out x: i1) {
// CHECK: reg combWire;
%combWire = sv.reg : !hw.inout<i1>
// CHECK: always_comb
@ -902,7 +901,7 @@ hw.module @alwayscombTest(%a: i1) -> (x: i1) {
// https://github.com/llvm/circt/issues/838
// CHECK-LABEL: module inlineProceduralWiresWithLongNames(
hw.module @inlineProceduralWiresWithLongNames(%clock: i1, %in: i1) {
hw.module @inlineProceduralWiresWithLongNames(in %clock: i1, in %in: i1) {
%aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa = sv.wire : !hw.inout<i1>
%0 = sv.read_inout %aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa : !hw.inout<i1>
%bbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbb = sv.wire : !hw.inout<i1>
@ -922,7 +921,7 @@ hw.module @inlineProceduralWiresWithLongNames(%clock: i1, %in: i1) {
// https://github.com/llvm/circt/issues/859
// CHECK-LABEL: module oooReg(
hw.module @oooReg(%in: i1) -> (result: i1) {
hw.module @oooReg(in %in: i1, out result: i1) {
// CHECK: wire abc = in;
%0 = sv.read_inout %abc : !hw.inout<i1>
@ -935,7 +934,7 @@ hw.module @oooReg(%in: i1) -> (result: i1) {
// https://github.com/llvm/circt/issues/865
// CHECK-LABEL: module ifdef_beginend(
hw.module @ifdef_beginend(%clock: i1, %cond: i1, %val: i8) {
hw.module @ifdef_beginend(in %clock: i1, in %cond: i1, in %val: i8) {
// CHECK: always @(posedge clock) begin
sv.always posedge %clock {
// CHECK-NEXT: `ifndef SYNTHESIS
@ -946,7 +945,7 @@ hw.module @ifdef_beginend(%clock: i1, %cond: i1, %val: i8) {
// https://github.com/llvm/circt/issues/884
// CHECK-LABEL: module ConstResetValueMustBeInlined(
hw.module @ConstResetValueMustBeInlined(%clock: i1, %reset: i1, %d: i42) -> (q: i42) {
hw.module @ConstResetValueMustBeInlined(in %clock: i1, in %reset: i1, in %d: i42, out q: i42) {
%c0_i42 = hw.constant 0 : i42
%tmp = sv.reg : !hw.inout<i42>
// CHECK: always_ff @(posedge clock or posedge reset) begin
@ -1044,7 +1043,7 @@ hw.module @RegisterOfStructOrArrayOfStruct() {
// CHECK-LABEL: module MultiUseReadInOut(
// Issue #1564
hw.module @MultiUseReadInOut(%auto_in_ar_bits_id : i2) -> (aa: i3, bb: i3){
hw.module @MultiUseReadInOut(in %auto_in_ar_bits_id : i2, out aa: i3, out bb: i3){
%a = sv.reg : !hw.inout<i3>
%b = sv.reg : !hw.inout<i3>
%c = sv.reg : !hw.inout<i3>
@ -1094,9 +1093,9 @@ hw.module @DontDuplicateSideEffectingVerbatim() {
}
hw.generator.schema @verbatim_schema, "Simple", ["ports", "write_latency", "read_latency"]
hw.module.extern @verbatim_inout_2 () -> ()
hw.module.extern @verbatim_inout_2 ()
// CHECK-LABEL: module verbatim_M1(
hw.module @verbatim_M1(%clock : i1, %cond : i1, %val : i8) {
hw.module @verbatim_M1(in %clock : i1, in %cond : i1, in %val : i8) {
%c42 = hw.constant 42 : i8
%reg1 = sv.reg sym @verbatim_reg1: !hw.inout<i8>
%reg2 = sv.reg sym @verbatim_reg2: !hw.inout<i8>
@ -1117,7 +1116,7 @@ hw.module @verbatim_M1(%clock : i1, %cond : i1, %val : i8) {
}
// CHECK-LABEL: module verbatim_M2(
hw.module @verbatim_M2(%clock : i1, %cond : i1, %val : i8) {
hw.module @verbatim_M2(in %clock : i1, in %cond : i1, in %val : i8) {
%c42 = hw.constant 42 : i8
%add = comb.add %val, %c42 : i8
%c42_2 = hw.constant 42 : i8
@ -1130,7 +1129,7 @@ hw.module @verbatim_M2(%clock : i1, %cond : i1, %val : i8) {
// CHECK-LABEL: module InlineAutomaticLogicInit(
// Issue #1567: https://github.com/llvm/circt/issues/1567
hw.module @InlineAutomaticLogicInit(%a : i42, %b: i42, %really_really_long_port: i11) {
hw.module @InlineAutomaticLogicInit(in %a : i42, in %b: i42, in %really_really_long_port: i11) {
%regValue = sv.reg : !hw.inout<i42>
// CHECK: initial begin
sv.initial {
@ -1232,7 +1231,7 @@ hw.module @InlineAutomaticLogicInit(%a : i42, %b: i42, %really_really_long_port:
// Issue #2335: https://github.com/llvm/circt/issues/2335
// CHECK-LABEL: module AggregateTemporay(
hw.module @AggregateTemporay(%clock: i1, %foo: i1, %bar: i25) {
hw.module @AggregateTemporay(in %clock: i1, in %foo: i1, in %bar: i25) {
%temp1 = sv.reg : !hw.inout<!hw.struct<b: i1>>
%temp2 = sv.reg : !hw.inout<!hw.array<5x!hw.array<5x!hw.struct<b: i1>>>>
sv.always posedge %clock {
@ -1250,7 +1249,7 @@ hw.module @AggregateTemporay(%clock: i1, %foo: i1, %bar: i25) {
//CHECK-LABEL: module XMR_src
//CHECK: assign $root.a.b.c = a;
//CHECK-NEXT: assign aa = d.e.f;
hw.module @XMR_src(%a : i23) -> (aa: i3) {
hw.module @XMR_src(in %a : i23, out aa: i3) {
%xmr1 = sv.xmr isRooted a,b,c : !hw.inout<i23>
%xmr2 = sv.xmr "d",e,f : !hw.inout<i3>
%r = sv.read_inout %xmr2 : !hw.inout<i3>
@ -1268,8 +1267,8 @@ hw.hierpath private @ref2 [@wait_order::@baz]
hw.module @XMRRef_Bar() {
%new = sv.wire sym @new : !hw.inout<i2>
}
hw.module.extern @XMRRef_Baz(%a: i2, %b: i1)
hw.module.extern @XMRRef_Qux(%a: i2, %b: i1)
hw.module.extern @XMRRef_Baz(in %a: i2, in %b: i1)
hw.module.extern @XMRRef_Qux(in %a: i2, in %b: i1)
// CHECK-LABEL: module wait_order
hw.module @wait_order() {
hw.instance "bar" sym @bar @XMRRef_Bar() -> ()
@ -1293,12 +1292,12 @@ hw.module @wait_order() {
hw.instance "qux" sym @qux @XMRRef_Qux(a: %xmrRead: i2, b: %xmr2Read: i1) -> ()
}
hw.module.extern @MyExtModule(%in: i8)
hw.module.extern @ExtModule(%in: i8) -> (out: i8)
hw.module.extern @MyExtModule(in %in: i8)
hw.module.extern @ExtModule(in %in: i8, out out: i8)
// CHECK-LABEL: module InlineBind
// CHEC: output wire_0
hw.module @InlineBind(%a_in: i8) -> (wire: i8){
hw.module @InlineBind(in %a_in: i8, out wire: i8){
// CHECK: wire [7:0] _ext1_out;
// CHECK-NEXT: wire [7:0] _GEN;
// CHECK-NEXT: /* This instance is elsewhere emitted as a bind statement.
@ -1322,7 +1321,7 @@ hw.module @InlineBind(%a_in: i8) -> (wire: i8){
}
// CHECK-LABEL: module MoveInstances
hw.module @MoveInstances(%a_in: i8) -> (outc : i8){
hw.module @MoveInstances(in %a_in: i8, out outc : i8){
// CHECK: MyExtModule xyz3 (
// CHECK: .in (8'(a_in + a_in))
// CHECK: );
@ -1337,17 +1336,17 @@ hw.module @MoveInstances(%a_in: i8) -> (outc : i8){
}
// CHECK-LABEL: module extInst
hw.module.extern @extInst(%_h: i1, %_i: i1, %_j: i1, %_k: i1, %_z :i0) -> ()
hw.module.extern @extInst(in %_h: i1, in %_i: i1, in %_j: i1, in %_k: i1, in %_z :i0)
// CHECK-LABEL: module extInst2
// CHECK-NEXT: input signed_0,
// CHECK-NEXT: _i,
// CHECK-NEXT: _j,
// CHECK-NEXT: _k
hw.module @extInst2(%signed: i1, %_i: i1, %_j: i1, %_k: i1, %_z :i0) -> () {}
hw.module @extInst2(in %signed: i1, in %_i: i1, in %_j: i1, in %_k: i1, in %_z :i0) {}
// CHECK-LABEL: module zeroWidthArrayIndex
hw.module @zeroWidthArrayIndex(%clock : i1, %data : i64) -> () {
hw.module @zeroWidthArrayIndex(in %clock : i1, in %data : i64) {
%reg = sv.reg : !hw.inout<uarray<1xi64>>
sv.alwaysff(posedge %clock) {
%c0_i0_1 = hw.constant 0 : i0
@ -1358,7 +1357,7 @@ hw.module @zeroWidthArrayIndex(%clock : i1, %data : i64) -> () {
}
// CHECK-LABEL: module remoteInstDut
hw.module @remoteInstDut(%i: i1, %j: i1, %z: i0) -> () {
hw.module @remoteInstDut(in %i: i1, in %j: i1, in %z: i0) {
%mywire = sv.wire : !hw.inout<i1>
%mywire_rd = sv.read_inout %mywire : !hw.inout<i1>
%myreg = sv.reg : !hw.inout<i1>
@ -1392,7 +1391,7 @@ hw.module @remoteInstDut(%i: i1, %j: i1, %z: i0) -> () {
// CHECK-NEXT: if (flag4)
// CHECK: end
// CHECK: else
hw.module @SimplyNestedElseIf(%clock: i1, %flag1 : i1, %flag2: i1, %flag3: i1, %flag4: i1) {
hw.module @SimplyNestedElseIf(in %clock: i1, in %flag1 : i1, in %flag2: i1, in %flag3: i1, in %flag4: i1) {
%fd = hw.constant 0x80000002 : i32
sv.always posedge %clock {
@ -1423,7 +1422,7 @@ hw.module @SimplyNestedElseIf(%clock: i1, %flag1 : i1, %flag2: i1, %flag3: i1, %
// CHECK: if (flag2)
// CHECK: else
// CHECK: end
hw.module @DoNotChainElseIf(%clock: i1, %flag1 : i1, %flag2: i1) {
hw.module @DoNotChainElseIf(in %clock: i1, in %flag1 : i1, in %flag2: i1) {
%wire = sv.reg : !hw.inout<i32>
%fd = hw.constant 0x80000002 : i32
@ -1448,7 +1447,7 @@ hw.module @DoNotChainElseIf(%clock: i1, %flag1 : i1, %flag2: i1) {
// CHECK: else begin
// CHECK: automatic logic _GEN;
// CHECK: _GEN = flag2 & flag4;
hw.module @NestedElseIfHoist(%clock: i1, %flag1 : i1, %flag2: i1, %flag3: i1, %flag4 : i1, %arg0: i32, %arg1: i32, %arg2: i32) {
hw.module @NestedElseIfHoist(in %clock: i1, in %flag1 : i1, in %flag2: i1, in %flag3: i1, in %flag4 : i1, in %arg0: i32, in %arg1: i32, in %arg2: i32) {
%fd = hw.constant 0x80000002 : i32
sv.always posedge %clock {
@ -1483,7 +1482,7 @@ hw.module @NestedElseIfHoist(%clock: i1, %flag1 : i1, %flag2: i1, %flag3: i1, %f
// CHECK-SAME: // Flag:3:3, If:3:3
// CHECK: else
// CHECK-SAME: // If:3:3
hw.module @ElseIfLocations(%clock: i1, %flag1 : i1, %flag2: i1, %flag3: i1) {
hw.module @ElseIfLocations(in %clock: i1, in %flag1 : i1, in %flag2: i1, in %flag3: i1) {
%fd = hw.constant 0x80000002 : i32
%true = hw.constant 1 : i1
@ -1514,7 +1513,7 @@ hw.module @ElseIfLocations(%clock: i1, %flag1 : i1, %flag2: i1, %flag3: i1) {
// CHECK: [[INPUT:[:alnum:]+]], //
// CHECK: output [[OUTPUT:.+]] //
// CHECK: );
hw.module @ReuseExistingInOut(%clock: i1, %a: i1) -> (out1: i1) {
hw.module @ReuseExistingInOut(in %clock: i1, in %a: i1, out out1: i1) {
%expr1 = comb.or %a, %a : i1
%expr2 = comb.and %a, %a : i1
@ -1543,7 +1542,7 @@ hw.module @ReuseExistingInOut(%clock: i1, %a: i1) -> (out1: i1) {
}
// CHECK-LABEL: ProhibitReuseOfExistingInOut
hw.module @ProhibitReuseOfExistingInOut(%a: i1) -> (out1: i1) {
hw.module @ProhibitReuseOfExistingInOut(in %a: i1, out out1: i1) {
// CHECK-DAG: wire [[GEN:.+]] = a | a;
// CHECK-DAG: wire mywire;
// CHECK: `ifdef FOO
@ -1567,9 +1566,10 @@ hw.module @ProhibitReuseOfExistingInOut(%a: i1) -> (out1: i1) {
// CHECK: assign out = {[[GEN0]], [[GEN1]]}
hw.module @Verilator3405(
%0: i1, %1: i1, %2: i1, %3: i1, %4: i1, %5: i1, %6: i1, %7: i1, %8: i1,
%9: i1, %10: i1, %11: i1, %12: i1, %13: i1, %14: i1, %15: i1, %16: i1,
%17: i1, %18: i1, %19: i1, %20: i1, %21: i1, %22: i1) -> (out: i2) {
in %0: i1, in %1: i1, in %2: i1, in %3: i1, in %4: i1, in %5: i1, in %6: i1, in %7: i1, in %8: i1,
in %9: i1, in %10: i1, in %11: i1, in %12: i1, in %13: i1, in %14: i1, in %15: i1, in %16: i1,
in %17: i1, in %18: i1, in %19: i1, in %20: i1, in %21: i1, in %22: i1,
out out: i2) {
%lhs = comb.or %0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10 : i1
%rhs = comb.or %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21 : i1
@ -1579,7 +1579,7 @@ hw.module @Verilator3405(
hw.output %out : i2
}
hw.module @prohiditInline(%a:i4, %b:i1, %c:i1, %d: i4) {
hw.module @prohiditInline(in %a:i4, in %b:i1, in %c:i1, in %d: i4) {
%0 = sv.reg : !hw.inout<i4>
%1 = sv.reg : !hw.inout<i4>
%2 = sv.reg : !hw.inout<i2>
@ -1596,7 +1596,7 @@ hw.module @prohiditInline(%a:i4, %b:i1, %c:i1, %d: i4) {
}
// CHECK-LABEL: module CollectNamesOrder
hw.module @CollectNamesOrder(%in: i1) -> (out: i1) {
hw.module @CollectNamesOrder(in %in: i1, out out: i1) {
// CHECK: wire _GEN_0 = in | in;
// CHECK: wire _GEN;
%0 = comb.or %in, %in : i1
@ -1606,7 +1606,7 @@ hw.module @CollectNamesOrder(%in: i1) -> (out: i1) {
}
// CHECK-LABEL: module InlineReadInout
hw.module private @InlineReadInout() -> () {
hw.module private @InlineReadInout() {
%c0_i32 = hw.constant 0 : i32
%false = hw.constant false
%r1 = sv.reg : !hw.inout<i2>
@ -1626,7 +1626,7 @@ hw.module private @InlineReadInout() -> () {
}
// CHECK-LABEL: module Dollar
hw.module private @Dollar(%cond: i1) -> () {
hw.module private @Dollar(in %cond: i1) {
sv.initial {
// CHECK: _$a:
// CHECK-NEXT: a$:
@ -1636,7 +1636,7 @@ hw.module private @Dollar(%cond: i1) -> () {
}
// CHECK-LABEL: IndexPartSelectInoutArray
hw.module @IndexPartSelectInoutArray(%a: !hw.array<2xi1>, %c: i1, %d: i1) {
hw.module @IndexPartSelectInoutArray(in %a: !hw.array<2xi1>, in %c: i1, in %d: i1) {
%c0_i2 = hw.constant 0 : i2
%r1 = sv.reg : !hw.inout<array<3xi1>>
sv.always posedge %d {
@ -1647,7 +1647,7 @@ hw.module @IndexPartSelectInoutArray(%a: !hw.array<2xi1>, %c: i1, %d: i1) {
hw.output
}
hw.module @IndexPartSelect() -> (a : i3) {
hw.module @IndexPartSelect(out a : i3) {
// CHECK-LABEL: module IndexPartSelect(
// CHECK: wire [17:0] _GEN = 18'h3;
// CHECK-NEXT: assign a = _GEN[4'h3 +: 3];
@ -1675,7 +1675,7 @@ sv.macro.decl @RANDOM
sv.macro.decl @PRINTF_COND_
// CHECK-LABEL: module ForStatement
hw.module @ForStatement(%a: i5) -> () {
hw.module @ForStatement(in %a: i5) {
%_RANDOM = sv.logic : !hw.inout<uarray<3xi32>>
sv.initial {
%c-2_i2 = hw.constant -2 : i2
@ -1694,7 +1694,7 @@ hw.module @ForStatement(%a: i5) -> () {
}
// CHECK-LABEL: module intrinsic
hw.module @intrinsic(%clk: i1) -> (io1: i1, io2: i1, io3: i1, io4: i5) {
hw.module @intrinsic(in %clk: i1, out io1: i1, out io2: i1, out io3: i1, out io4: i5) {
// CHECK: wire [4:0] [[tmp:.*]];
%x_i1 = sv.constantX : i1
@ -1756,7 +1756,7 @@ hw.module @NastyPortParent() {
%false = hw.constant false
%0 = hw.instance "foo" sym @foo @NastyPort(".lots$of.dots": %false: i1) -> (".more.dots": i1) {doNotPrint = true}
}
hw.module @NastyPort(%.lots$of.dots: i1) -> (".more.dots": i1) {
hw.module @NastyPort(in %.lots$of.dots: i1, out ".more.dots": i1) {
%false = hw.constant false
hw.output %false : i1
}
@ -1781,7 +1781,7 @@ sv.bind #hw.innerNameRef<@InlineBind::@foo2>
// CHECK: sv.wire {hw.verilogName = "_GEN"} : !hw.inout<i32>
// CHECK-LABEL: hw.module @extInst2
// CHECK-SAME: (%signed: i1 {hw.verilogName = "signed_0"}
// CHECK-SAME: (in %signed : i1 {hw.verilogName = "signed_0"}
// CHECK-LABEL: hw.module @remoteInstDut
// CHECK: %signed = sv.wire {hw.verilogName = "signed_0"} : !hw.inout<i1>

2
test/Conversion/ExportVerilog/sv-fwrite.mlir
View File

@ -1,6 +1,6 @@
// RUN: circt-opt %s -export-verilog -verify-diagnostics | FileCheck %s --strict-whitespace
hw.module @top(%clock : i1, %reset: i1) -> () {
hw.module @top(in %clock : i1, in %reset: i1) {
sv.alwaysff(posedge %clock) {
%0 = hw.constant 0x80000001 : i32
%1 = hw.constant 0x80000002 : i32

10
test/Conversion/ExportVerilog/sv-interfaces.mlir
View File

@ -46,10 +46,10 @@ module {
sv.interface.modport @data_out (output @data, output @valid, input @ready)
}
hw.module.extern @Rcvr (%m: !sv.modport<@data_vr::@data_in>)
hw.module.extern @Rcvr (in %m: !sv.modport<@data_vr::@data_in>)
// CHECK-LABEL: module Top
hw.module @Top (%clk: i1) {
hw.module @Top (in %clk: i1) {
// CHECK: data_vr [[IFACE:.+]]();
%iface = sv.interface.instance : !sv.interface<@data_vr>
// CHECK: MACRO-Interface:data_vr
@ -97,9 +97,9 @@ module {
// NOTE(fschuiki): Extern modules should trigger an error diagnostic if they
// would cause a rename, but since the user supplies the module externally we
// can't just rename it.
hw.module.extern @regStuff (%m: !sv.modport<@data_vr::@data_in>)
hw.module.extern @regStuff (in %m: !sv.modport<@data_vr::@data_in>)
// CHECK-LABEL: module Top2
hw.module @Top2 (%clk: i1) {
hw.module @Top2 (in %clk: i1) {
// CHECK: data_vr [[IFACE:.+]]();{{.*}}//{{.+}}
%iface = sv.interface.instance : !sv.interface<@data_vr>
@ -125,7 +125,7 @@ module {
// CHECK-NOT: wire [383:0] _tmp =
// CHECK: wire struct packed {logic [383:0] foo; } _GEN
// CHECK: endmodule
hw.module @structs(%clk: i1, %rstn: i1) {
hw.module @structs(in %clk: i1, in %rstn: i1) {
%0 = sv.interface.instance name "iface" : !sv.interface<@IValidReady_Struct>
sv.interface.signal.assign %0(@IValidReady_Struct::@data) = %s : !hw.struct<foo: !hw.array<384xi1>>
%c0 = hw.constant 0 : i8

2
test/Conversion/ExportVerilog/sv-verifLabels.mlir
View File

@ -1,7 +1,7 @@
// RUN: circt-opt --export-verilog %s | FileCheck %s --check-prefix=CHECK-OFF
// RUN: circt-opt --test-apply-lowering-options='options=verifLabels' --export-verilog %s | FileCheck %s --check-prefix=CHECK-ON
hw.module @foo(%clock: i1, %cond: i1) {
hw.module @foo(in %clock: i1, in %cond: i1) {
sv.initial {
// CHECK-OFF: assert(
// CHECK-OFF: assume(

10
test/Conversion/ExportVerilog/variadic-operand-splitting.mlir
View File

@ -2,11 +2,11 @@
// RUN: circt-opt -test-apply-lowering-options='options=maximumNumberOfTermsPerExpression=2' -export-verilog %s | FileCheck %s -check-prefixes=CHECK,MAX_4
hw.module @Baz(
%a0: i1, %a1: i1, %a2: i1, %a3: i1,
%a4: i1, %a5: i1, %a6: i1, %a7: i1,
%b0: i1, %b1: i1, %b2: i1, %b3: i1,
%b4: i1, %b5: i1, %b6: i1, %b7: i1
) -> (c: i1) {
in %a0: i1, in %a1: i1, in %a2: i1, in %a3: i1,
in %a4: i1, in %a5: i1, in %a6: i1, in %a7: i1,
in %b0: i1, in %b1: i1, in %b2: i1, in %b3: i1,
in %b4: i1, in %b5: i1, in %b6: i1, in %b7: i1,
out c: i1) {
%0 = comb.and %a0, %b0 : i1
%1 = comb.and %a1, %b1 : i1
%2 = comb.and %a2, %b2 : i1

18
test/Conversion/ExportVerilog/verif.mlir
View File

@ -1,7 +1,7 @@
// RUN: circt-opt %s --test-apply-lowering-options="options=emittedLineLength=9001,verifLabels" --export-verilog --verify-diagnostics | FileCheck %s
// CHECK-LABEL: module Labels
hw.module @Labels(%a: i1) {
hw.module @Labels(in %a: i1) {
// CHECK: foo1: assert property (a);
// CHECK: foo2: assume property (a);
// CHECK: foo3: cover property (a);
@ -16,7 +16,7 @@ hw.module @Labels(%a: i1) {
}
// CHECK-LABEL: module BasicEmissionNonTemporal
hw.module @BasicEmissionNonTemporal(%a: i1, %b: i1) {
hw.module @BasicEmissionNonTemporal(in %a: i1, in %b: i1) {
%0 = comb.and %a, %b : i1
%1 = comb.or %a, %b : i1
// CHECK: assert property (a);
@ -40,7 +40,7 @@ hw.module @BasicEmissionNonTemporal(%a: i1, %b: i1) {
}
// CHECK-LABEL: module BasicEmissionTemporal
hw.module @BasicEmissionTemporal(%a: i1) {
hw.module @BasicEmissionTemporal(in %a: i1) {
%p = ltl.not %a : i1
// CHECK: assert property (not a);
// CHECK: assume property (not a);
@ -61,7 +61,7 @@ hw.module @BasicEmissionTemporal(%a: i1) {
}
// CHECK-LABEL: module Sequences
hw.module @Sequences(%clk: i1, %a: i1, %b: i1) {
hw.module @Sequences(in %clk: i1, in %a: i1, in %b: i1) {
// CHECK: assert property (##0 a);
// CHECK: assert property (##4 a);
// CHECK: assert property (##[5:6] a);
@ -125,7 +125,7 @@ hw.module @Sequences(%clk: i1, %a: i1, %b: i1) {
}
// CHECK-LABEL: module Properties
hw.module @Properties(%clk: i1, %a: i1, %b: i1) {
hw.module @Properties(in %clk: i1, in %a: i1, in %b: i1) {
%true = hw.constant true
// CHECK: assert property (not a);
@ -170,7 +170,7 @@ hw.module @Properties(%clk: i1, %a: i1, %b: i1) {
}
// CHECK-LABEL: module Precedence
hw.module @Precedence(%a: i1, %b: i1) {
hw.module @Precedence(in %a: i1, in %b: i1) {
// CHECK: assert property ((a or b) and b);
%a0 = ltl.or %a, %b : i1, i1
%a1 = ltl.and %a0, %b : !ltl.sequence, i1
@ -199,7 +199,7 @@ hw.module @Precedence(%a: i1, %b: i1) {
}
// CHECK-LABEL: module SystemVerilogSpecExamples
hw.module @SystemVerilogSpecExamples(%clk: i1, %a: i1, %b: i1, %c: i1, %d: i1, %e: i1) {
hw.module @SystemVerilogSpecExamples(in %clk: i1, in %a: i1, in %b: i1, in %c: i1, in %d: i1, in %e: i1) {
// Section 16.7 "Sequences"
// CHECK: assert property (a ##1 b ##0 c ##1 d);
@ -233,7 +233,7 @@ hw.module @SystemVerilogSpecExamples(%clk: i1, %a: i1, %b: i1, %c: i1, %d: i1, %
}
// CHECK-LABEL: module LivenessExample
hw.module @LivenessExample(%clock: i1, %reset: i1, %isLive: i1) {
hw.module @LivenessExample(in %clock: i1, in %reset: i1, in %isLive: i1) {
%true = hw.constant true
// CHECK: wire _GEN = ~isLive;
@ -262,7 +262,7 @@ hw.module @LivenessExample(%clock: i1, %reset: i1, %isLive: i1) {
// https://github.com/llvm/circt/issues/5763
// CHECK-LABEL: module Issue5763
hw.module @Issue5763(%a: i3) {
hw.module @Issue5763(in %a: i3) {
// CHECK: assert property ((&a) & a[0]);
%c-1_i3 = hw.constant -1 : i3
%0 = comb.extract %a from 0 : (i3) -> i1

84
test/Conversion/ExportVerilog/verilog-basic.mlir
View File

@ -1,10 +1,10 @@
// RUN: circt-opt %s -test-apply-lowering-options='options=emitBindComments' -export-verilog -verify-diagnostics | FileCheck %s --strict-whitespace
hw.testmodule @NewStyle (input %a : i3,
output %b : i3,
input %c : i4,
output %d : i4,
hw.testmodule @NewStyle (in %a : i3,
out b : i3,
in %c : i4,
out d : i4,
inout %e : i64 {hw.exportPort = #hw<innerSym@symA>}) {
hw.output %a, %c : i3, i4
}
@ -13,7 +13,7 @@ hw.testmodule @NewStyle (input %a : i3,
// CHECK-NEXT: input a,{{.*}}
// CHECK-NEXT: b
// CHECK-NEXT: );
hw.module @inputs_only(%a: i1, %b: i1) {
hw.module @inputs_only(in %a: i1, in %b: i1) {
hw.output
}
@ -40,9 +40,11 @@ hw.module @no_ports() {
// CHECK-NEXT: output [1:0] orvout
// CHECK-NEXT: );
hw.module @Expressions(%in4: i4, %clock: i1) ->
(out1a: i1, out1b: i1, out1c: i1, out1d: i1, out1e: i1, out1f: i1, out1g: i1,
out4: i4, out4s: i4, out16: i16, out16s: i16, sext17: i17, orvout: i2) {
hw.module @Expressions(in %in4: i4, in %clock: i1,
out out1a: i1, out out1b: i1, out out1c: i1,
out out1d: i1, out out1e: i1, out out1f: i1, out out1g: i1,
out out4: i4, out out4s: i4, out out16: i16, out out16s: i16,
out sext17: i17, out orvout: i2) {
%c1_i4 = hw.constant 1 : i4
%c2_i4 = hw.constant 2 : i4
%c3_i4 = hw.constant 3 : i4
@ -157,7 +159,7 @@ hw.module @Expressions(%in4: i4, %clock: i1) ->
}
// CHECK-LABEL: module Precedence(
hw.module @Precedence(%a: i4, %b: i4, %c: i4) -> (out1: i1, out: i10) {
hw.module @Precedence(in %a: i4, in %b: i4, in %c: i4, out out1: i1, out out: i10) {
%false = hw.constant false
%c0_i2 = hw.constant 0 : i2
%c0_i4 = hw.constant 0 : i4
@ -256,9 +258,11 @@ hw.module @Precedence(%a: i4, %b: i4, %c: i4) -> (out1: i1, out: i10) {
}
// CHECK-LABEL: module CmpSign(
hw.module @CmpSign(%a: i4, %b: i4, %c: i4, %d: i4) ->
(o0: i1, o1: i1, o2: i1, o3: i1, o4: i1, o5: i1, o6: i1, o7: i1,
o8: i1, o9: i1, o10: i1, o11: i1, o12: i1, o13: i1, o14: i1, o15: i1) {
hw.module @CmpSign(in %a: i4, in %b: i4, in %c: i4, in %d: i4,
out o0: i1, out o1: i1, out o2: i1, out o3: i1,
out o4: i1, out o5: i1, out o6: i1, out o7: i1,
out o8: i1, out o9: i1, out o10: i1, out o11: i1,
out o12: i1, out o13: i1, out o14: i1, out o15: i1) {
// CHECK: assign o0 = a < b;
%0 = comb.icmp ult %a, %b : i4
// CHECK-NEXT: assign o1 = $signed(c) < $signed(d);
@ -297,7 +301,7 @@ hw.module @CmpSign(%a: i4, %b: i4, %c: i4, %d: i4) ->
// CHECK-LABEL: module Wires(
hw.hierpath @myWirePath [@Wires::@myWire]
hw.module @Wires(%a: i4) -> (x: i4, y: i4) {
hw.module @Wires(in %a: i4, out x: i4, out y: i4) {
// CHECK-DAG: wire [3:0] wire1 = a;
// CHECK-DAG: assign x = wire1;
%wire1 = hw.wire %a : i4
@ -333,7 +337,7 @@ hw.module @Wires(%a: i4) -> (x: i4, y: i4) {
}
// CHECK-LABEL: module MultiUseExpr
hw.module @MultiUseExpr(%a: i4) -> (b0: i1, b1: i1, b2: i1, b3: i1, b4: i2) {
hw.module @MultiUseExpr(in %a: i4, out b0: i1, out b1: i1, out b2: i1, out b3: i1, out b4: i2) {
%false = hw.constant false
%c1_i5 = hw.constant 1 : i5
%c-1_i5 = hw.constant -1 : i5
@ -366,7 +370,7 @@ hw.module @MultiUseExpr(%a: i4) -> (b0: i1, b1: i1, b2: i1, b3: i1, b4: i2) {
// CHECK: wire [3:0] w = 4'h1;
// CHECK: assign out4 = in4 + 4'h1;
// CHECK-NEXT: endmodule
hw.module @SimpleConstPrint(%in4: i4) -> (out4: i4) {
hw.module @SimpleConstPrint(in %in4: i4, out out4: i4) {
%w = sv.wire : !hw.inout<i4>
%c1_i4 = hw.constant 1 : i4
sv.assign %w, %c1_i4 : i4
@ -377,7 +381,7 @@ hw.module @SimpleConstPrint(%in4: i4) -> (out4: i4) {
// Use constants, don't fold them into wires
// CHECK-LABEL: module SimpleConstPrintReset(
// CHECK: q <= 4'h1;
hw.module @SimpleConstPrintReset(%clock: i1, %reset: i1, %in4: i4) -> () {
hw.module @SimpleConstPrintReset(in %clock: i1, in %reset: i1, in %in4: i4) {
%w = sv.wire : !hw.inout<i4>
%q = sv.reg : !hw.inout<i4>
%c1_i4 = hw.constant 1 : i4
@ -394,7 +398,7 @@ hw.module @SimpleConstPrintReset(%clock: i1, %reset: i1, %in4: i4) -> () {
}
// CHECK-LABEL: module InlineDeclAssignment
hw.module @InlineDeclAssignment(%a: i1) {
hw.module @InlineDeclAssignment(in %a: i1) {
// CHECK: wire b = a;
%b = sv.wire : !hw.inout<i1>
sv.assign %b, %a : i1
@ -409,7 +413,7 @@ hw.module @InlineDeclAssignment(%a: i1) {
// CHECK-NEXT: input a
// CHECK-NEXT: );
// CHECK-EMPTY:
hw.module @ordered_region(%a: i1) {
hw.module @ordered_region(in %a: i1) {
sv.ordered {
// CHECK-NEXT: `ifdef foo
sv.ifdef "foo" {
@ -429,11 +433,11 @@ hw.module @ordered_region(%a: i1) {
}
hw.module.extern @MyExtModule(%in: i8) -> (out: i1) attributes {verilogName = "FooExtModule"}
hw.module.extern @AParameterizedExtModule<CFG: none>(%in: i8) -> (out: i1)
hw.module.extern @MyExtModule(in %in: i8, out out: i1) attributes {verilogName = "FooExtModule"}
hw.module.extern @AParameterizedExtModule<CFG: none>(in %in: i8, out out: i1)
// CHECK-LABEL: module ExternMods
hw.module @ExternMods(%a_in: i8) {
hw.module @ExternMods(in %a_in: i8) {
// CHECK: AParameterizedExtModule #(
// CHECK: .CFG(FOO)
// CHECK: ) xyz2
@ -445,10 +449,10 @@ hw.module @ExternMods(%a_in: i8) {
}
hw.module.extern @MyParameterizedExtModule<DEFAULT: i32, DEPTH: f64, FORMAT: none,
WIDTH: i8>(%in: i8) -> (out: i1)
WIDTH: i8>(in %in: i8, out out: i1)
// CHECK-LABEL: module UseInstances
hw.module @UseInstances(%a_in: i8) -> (a_out1: i1, a_out2: i1) {
hw.module @UseInstances(in %a_in: i8, out a_out1: i1, out a_out2: i1) {
// CHECK: FooExtModule xyz (
// CHECK: .in (a_in),
// CHECK: .out (a_out1)
@ -472,10 +476,10 @@ hw.module @UseInstances(%a_in: i8) -> (a_out1: i1, a_out2: i1) {
// Instantiate a parametric module using parameters from its parent module
hw.module.extern @ExternParametricWidth<width: i32>
(%in: !hw.int<#hw.param.decl.ref<"width">>) -> (out: !hw.int<#hw.param.decl.ref<"width">>)
(in %in: !hw.int<#hw.param.decl.ref<"width">>, out out: !hw.int<#hw.param.decl.ref<"width">>)
// CHECK-LABEL: module NestedParameterUsage
hw.module @NestedParameterUsage<param: i32>(
%in: !hw.int<#hw.param.decl.ref<"param">>) -> (out: !hw.int<#hw.param.decl.ref<"param">>) {
in %in: !hw.int<#hw.param.decl.ref<"param">>, out out: !hw.int<#hw.param.decl.ref<"param">>) {
// CHECK: #(parameter /*integer*/ param) (
// CHECK: input [param - 1:0] in,
// CHECK: output [param - 1:0] out
@ -494,7 +498,7 @@ hw.module @NestedParameterUsage<param: i32>(
}
// CHECK-LABEL: module Stop(
hw.module @Stop(%clock: i1, %reset: i1) {
hw.module @Stop(in %clock: i1, in %reset: i1) {
// CHECK: always @(posedge clock) begin
// CHECK: `ifndef SYNTHESIS
// CHECK: if (`STOP_COND_ & reset)
@ -517,7 +521,7 @@ hw.module @Stop(%clock: i1, %reset: i1) {
sv.macro.decl @PRINTF_COND_
// CHECK-LABEL: module Print
hw.module @Print(%clock: i1, %reset: i1, %a: i4, %b: i4) {
hw.module @Print(in %clock: i1, in %reset: i1, in %a: i4, in %b: i4) {
%fd = hw.constant 0x80000002 : i32
%false = hw.constant false
%c1_i5 = hw.constant 1 : i5
@ -581,7 +585,7 @@ hw.module @ReadMemXMRHierPath() {
sv.verbatim "// VERB: hierpath {{0:|}}" {symbols = [@ReadMem_path]}
// CHECK-LABEL: module UninitReg1(
hw.module @UninitReg1(%clock: i1, %reset: i1, %cond: i1, %value: i2) {
hw.module @UninitReg1(in %clock: i1, in %reset: i1, in %cond: i1, in %value: i2) {
%c-1_i2 = hw.constant -1 : i2
%count = sv.reg : !hw.inout<i2>
@ -601,7 +605,7 @@ hw.module @UninitReg1(%clock: i1, %reset: i1, %cond: i1, %value: i2) {
// https://github.com/llvm/circt/issues/2168
// CHECK-LABEL: module shrs_parens(
hw.module @shrs_parens(%a: i18, %b: i18, %c: i1) -> (o: i18) {
hw.module @shrs_parens(in %a: i18, in %b: i18, in %c: i1, out o: i18) {
// CHECK: assign o = a + $signed($signed(b) >>> c);
%c0_i17 = hw.constant 0 : i17
%0 = comb.concat %c0_i17, %c : i17, i1
@ -613,7 +617,7 @@ hw.module @shrs_parens(%a: i18, %b: i18, %c: i1) -> (o: i18) {
// https://github.com/llvm/circt/issues/755
// CHECK-LABEL: module UnaryParensIssue755(
// CHECK: assign b = |(~a);
hw.module @UnaryParensIssue755(%a: i8) -> (b: i1) {
hw.module @UnaryParensIssue755(in %a: i8, out b: i1) {
%c-1_i8 = hw.constant -1 : i8
%c0_i8 = hw.constant 0 : i8
%0 = comb.xor %a, %c-1_i8 : i8
@ -623,11 +627,11 @@ hw.module @UnaryParensIssue755(%a: i8) -> (b: i1) {
// Inner name references to ports which are renamed to avoid collisions with
// reserved Verilog keywords.
hw.module.extern @VerbatimModuleExtern(%foo: i1 {hw.exportPort = #hw<innerSym@symA>}) -> (bar: i1 {hw.exportPort = #hw<innerSym@symB>})
hw.module.extern @VerbatimModuleExtern(in %foo: i1 {hw.exportPort = #hw<innerSym@symA>}, out bar: i1 {hw.exportPort = #hw<innerSym@symB>})
// CHECK-LABEL: module VerbatimModule(
// CHECK-NEXT: input signed_0
// CHECK-NEXT: output unsigned_0
hw.module @VerbatimModule(%signed: i1 {hw.exportPort = #hw<innerSym@symA>}) -> (unsigned: i1 {hw.exportPort = #hw<innerSym@symB>}) {
hw.module @VerbatimModule(in %signed: i1 {hw.exportPort = #hw<innerSym@symA>}, out unsigned: i1 {hw.exportPort = #hw<innerSym@symB>}) {
%parameter = sv.wire sym @symC : !hw.inout<i4>
%localparam = sv.reg sym @symD : !hw.inout<i4>
%shortint = sv.interface.instance sym @symE : !sv.interface<@Interface>
@ -665,7 +669,7 @@ hw.module @BindEmissionInstance() {
hw.output
}
// CHECK-LABEL: module BindEmission()
hw.module @BindEmission() -> () {
hw.module @BindEmission() {
// CHECK-NEXT: /* This instance is elsewhere emitted as a bind statement
// CHECK-NEXT: BindEmissionInstance BindEmissionInstance ();
// CHECK-NEXT: */
@ -676,7 +680,7 @@ hw.module @BindEmission() -> () {
// Check for instance name matching module name
sv.bind #hw.innerNameRef<@BindEmission2::@BindEmissionInstance> {output_file = #hw.output_file<"BindTest/BindEmissionInstance2.sv", excludeFromFileList>}
// CHECK-LABEL: module BindEmission2()
hw.module @BindEmission2() -> () {
hw.module @BindEmission2() {
// CHECK-NEXT: /* This instance is elsewhere emitted as a bind statement
// CHECK-NEXT: BindEmissionInstance BindEmissionInstance ();
// CHECK-NEXT: */
@ -684,7 +688,7 @@ hw.module @BindEmission2() -> () {
hw.output
}
hw.module @rename_port(%r: i1 {hw.verilogName = "w"}) {
hw.module @rename_port(in %r: i1 {hw.verilogName = "w"}) {
// CHECK-LABEL: module rename_port
// CHECK: input w
// CHECK: wire [3:0] w_0;
@ -692,7 +696,7 @@ hw.module @rename_port(%r: i1 {hw.verilogName = "w"}) {
hw.output
}
hw.module @bind_rename_port(%.io_req_ready.output: i1, %reset: i1 { hw.verilogName = "resetSignalName" }, %clock: i1) {
hw.module @bind_rename_port(in %.io_req_ready.output: i1, in %reset: i1 { hw.verilogName = "resetSignalName" }, in %clock: i1) {
// CHECK-LABEL: module bind_rename_port
// CHECK-NEXT: input _io_req_ready_output,
// CHECK-NEXT: resetSignalName,
@ -701,7 +705,7 @@ hw.module @bind_rename_port(%.io_req_ready.output: i1, %reset: i1 { hw.verilogNa
}
// CHECK-LABEL: module SiFive_MulDiv
hw.module @SiFive_MulDiv(%clock: i1, %reset: i1) -> (io_req_ready: i1) {
hw.module @SiFive_MulDiv(in %clock: i1, in %reset: i1, out io_req_ready: i1) {
%false = hw.constant false
hw.instance "InvisibleBind_assert" sym @__ETC_SiFive_MulDiv_assert @bind_rename_port(".io_req_ready.output": %false: i1, reset: %reset: i1, clock: %clock: i1) -> () {doNotPrint = true}
hw.output %false : i1
@ -718,8 +722,8 @@ sv.interface @Interface {
sv.interface.signal @b : i1
}
hw.module.extern @W422_Bar() -> (clock: i1, reset: i1)
hw.module.extern @W422_Baz() -> (q: i1)
hw.module.extern @W422_Bar(out clock: i1, out reset: i1)
hw.module.extern @W422_Baz(out q: i1)
// CHECK-LABEL: module W422_Foo
// CHECK-NOT: GEN
hw.module @W422_Foo() {
@ -737,7 +741,7 @@ sv.interface @Interface {
hw.output
}
hw.module @BindInterface() -> () {
hw.module @BindInterface() {
%bar = sv.interface.instance sym @__Interface__ {doNotPrint = true} : !sv.interface<@Interface>
hw.output
}

2
test/Conversion/ExportVerilog/verilog-errors.mlir
View File

@ -1,7 +1,7 @@
// RUN: circt-opt -export-verilog -verify-diagnostics --split-input-file -mlir-print-op-on-diagnostic=false %s
// expected-error @+1 {{value has an unsupported verilog type 'f32'}}
hw.module @Top(%out: f32) {
hw.module @Top(in %out: f32) {
}
// -----

10
test/Conversion/ExportVerilog/verilog-locations.mlir
View File

@ -1,7 +1,7 @@
// RUN: circt-opt %s -export-verilog -verify-diagnostics --mlir-print-debuginfo --split-input-file | FileCheck %s --strict-whitespace
module attributes {circt.loweringOptions = "emitVerilogLocations"} {
hw.module @MultiUseExpr(%a: i4) -> (b0: i1) {
hw.module @MultiUseExpr(in %a: i4, out b0: i1) {
%0 = comb.parity %a : i4
hw.output %0 : i1
}
@ -14,10 +14,10 @@ hw.module @MultiUseExpr(%a: i4) -> (b0: i1) {
// assign b0 = ^a;
// endmodule
// CHECK: hw.module @MultiUseExpr
// CHECK-LABEL: hw.module @MultiUseExpr
// CHECK: %[[v0:.+]] = comb.parity %a : i4 loc(#loc19)
// CHECK: hw.output %[[v0]] : i1 loc(#loc20)
// CHECK: } loc(#loc18)
// CHECK: } loc(#loc)
// CHECK: #loc = loc("{{.+}}verilog-locations.mlir{{.*}})
// CHECK: #loc1 = loc("{{.+}}verilog-locations.mlir{{.*}})
// CHECK: #loc2 = loc("":2:0)
@ -41,7 +41,7 @@ hw.module @MultiUseExpr(%a: i4) -> (b0: i1) {
// -----
module attributes {circt.loweringOptions = "locationInfoStyle=none,emitVerilogLocations"} {
hw.module @SimpleConstPrintReset(%clock: i1, %reset: i1, %in4: i4) -> () {
hw.module @SimpleConstPrintReset(in %clock: i1, in %reset: i1, in %in4: i4) {
%w = sv.wire : !hw.inout<i4>
%q = sv.reg : !hw.inout<i4>
%c1_i4 = hw.constant 1 : i4
@ -143,7 +143,7 @@ hw.module @SimpleConstPrintReset(%clock: i1, %reset: i1, %in4: i4) -> () {
// -----
module attributes {circt.loweringOptions = "emitVerilogLocations"} {
hw.module @InlineDeclAssignment(%a: i1) {
hw.module @InlineDeclAssignment(in %a: i1) {
%b = sv.wire : !hw.inout<i1>
sv.assign %b, %a : i1

4
test/Conversion/ExportVerilog/version-comment.mlir
View File

@ -3,7 +3,7 @@
module {
// CHECK-LABEL: Generated
// CHECK-NEXT: module Foo(
hw.module @Foo(%a: i1 loc("")) -> () {
hw.module @Foo(in %a: i1 loc("")) {
hw.output
}
}
@ -13,7 +13,7 @@ hw.module @Foo(%a: i1 loc("")) -> () {
module attributes {circt.loweringOptions = "omitVersionComment"}{
// CHECK-NOT: Generated
// CHECK-LABEL: module Bar(
hw.module @Bar() -> () {
hw.module @Bar() {
hw.output
}
}

30
test/Conversion/FIRRTLToHW/lower-to-hw-module.mlir
View File

@ -11,7 +11,7 @@ firrtl.circuit "Simple" {
// CHECK-LABEL: hw.module.extern private @MyParameterizedExtModule
// CHECK-SAME: <DEFAULT: i64, DEPTH: f64, FORMAT: none, WIDTH: i8>
// CHECK-SAME: (%in: i1) -> (out: i8)
// CHECK-SAME: (in %in : i1, out out : i8)
// CHECK: attributes {verilogName = "name_thing"}
firrtl.extmodule private @MyParameterizedExtModule
<DEFAULT: i64 = 0,
@ -21,7 +21,7 @@ firrtl.circuit "Simple" {
(in in: !firrtl.uint<1>, out out: !firrtl.uint<8>)
attributes {defname = "name_thing"}
// CHECK-LABEL: hw.module @Simple(%in1: i4, %in2: i2, %in3: i8) -> (out4: i4)
// CHECK-LABEL: hw.module @Simple(in %in1 : i4, in %in2 : i2, in %in3 : i8, out out4 : i4)
firrtl.module @Simple(in %in1: !firrtl.uint<4>,
in %in2: !firrtl.uint<2>,
in %in3: !firrtl.sint<8>,
@ -80,7 +80,7 @@ firrtl.circuit "Simple" {
firrtl.printf %clock, %reset, "Something interesting! %x"(%myext#1) : !firrtl.clock, !firrtl.uint<1>, !firrtl.uint<8>
}
// CHECK-LABEL: hw.module private @OutputFirst(%in1: i1, %in4: i4) -> (out4: i4) {
// CHECK-LABEL: hw.module private @OutputFirst(in %in1 : i1, in %in4 : i4, out out4 : i4) {
firrtl.module private @OutputFirst(out %out4: !firrtl.uint<4>,
in %in1: !firrtl.uint<1>,
in %in4: !firrtl.uint<4>) {
@ -90,8 +90,8 @@ firrtl.circuit "Simple" {
}
// CHECK-LABEL: hw.module private @PortMadness(
// CHECK: %inA: i4, %inB: i4, %inC: i4, %inE: i3)
// CHECK: -> (outA: i4, outB: i4, outC: i4, outD: i4, outE: i4) {
// CHECK: in %inA : i4, in %inB : i4, in %inC : i4, in %inE : i3,
// CHECK: out outA : i4, out outB : i4, out outC : i4, out outD : i4, out outE : i4) {
firrtl.module private @PortMadness(in %inA: !firrtl.uint<4>,
in %inB: !firrtl.uint<4>,
in %inC: !firrtl.uint<4>,
@ -135,7 +135,7 @@ firrtl.circuit "Simple" {
firrtl.connect %ip1_in, %in : !firrtl.uint<1>, !firrtl.uint<1>
}
// CHECK-LABEL: hw.module private @Analog(%a1: !hw.inout<i1>) -> (outClock: !seq.clock) {
// CHECK-LABEL: hw.module private @Analog(inout %a1 : i1, out outClock : !seq.clock) {
// CHECK-NEXT: [[READ:%.+]] = sv.read_inout %a1 : !hw.inout<i1>
// CHECK-NEXT: [[CLK:%.+]] = seq.to_clock [[READ]]
// CHECK-NEXT: hw.output [[CLK]] : !seq.clock
@ -184,7 +184,7 @@ firrtl.circuit "Simple" {
firrtl.connect %myext#0, %11 : !firrtl.uint<1>, !firrtl.uint<1>
}
// CHECK-LABEL: hw.module private @ZeroWidthPorts(%inA: i4) -> (outa: i4) {
// CHECK-LABEL: hw.module private @ZeroWidthPorts(in %inA : i4, out outa : i4) {
firrtl.module private @ZeroWidthPorts(in %inA: !firrtl.uint<4>,
in %inB: !firrtl.uint<0>,
in %inC: !firrtl.analog<0>,
@ -236,7 +236,7 @@ firrtl.circuit "Simple" {
// CHECK: hw.output %myinst.outa
}
// CHECK-LABEL: hw.module private @SimpleStruct(%source: !hw.struct<valid: i1, ready: i1, data: i64>) -> (sink: !hw.struct<valid: i1, ready: i1, data: i64>) {
// CHECK-LABEL: hw.module private @SimpleStruct(in %source : !hw.struct<valid: i1, ready: i1, data: i64>, out sink : !hw.struct<valid: i1, ready: i1, data: i64>) {
// CHECK-NEXT: hw.output %source : !hw.struct<valid: i1, ready: i1, data: i64>
firrtl.module private @SimpleStruct(in %source: !firrtl.bundle<valid: uint<1>, ready: uint<1>, data: uint<64>>,
out %sink: !firrtl.bundle<valid: uint<1>, ready: uint<1>, data: uint<64>>) {
@ -244,7 +244,7 @@ firrtl.circuit "Simple" {
}
// https://github.com/llvm/circt/issues/690
// CHECK-LABEL: hw.module private @bar690(%led_0: !hw.inout<i1>) {
// CHECK-LABEL: hw.module private @bar690(inout %led_0 : i1) {
firrtl.module private @bar690(in %led_0: !firrtl.analog<1>) {
}
// CHECK-LABEL: hw.module private @foo690()
@ -253,14 +253,14 @@ firrtl.circuit "Simple" {
// CHECK: hw.instance "fpga" @bar690(led_0: %.led_0.wire: !hw.inout<i1>) -> ()
%result = firrtl.instance fpga @bar690(in led_0: !firrtl.analog<1>)
}
// CHECK-LABEL: hw.module private @foo690a(%a: !hw.inout<i1>) {
// CHECK-LABEL: hw.module private @foo690a(inout %a : i1) {
firrtl.module private @foo690a(in %a: !firrtl.analog<1>) {
%result = firrtl.instance fpga @bar690(in led_0: !firrtl.analog<1>)
firrtl.attach %result, %a: !firrtl.analog<1>, !firrtl.analog<1>
}
// https://github.com/llvm/circt/issues/740
// CHECK-LABEL: hw.module private @foo740(%led_0: !hw.inout<i1>) {
// CHECK-LABEL: hw.module private @foo740(inout %led_0 : i1) {
// CHECK-NEXT: hw.instance "fpga" @bar740(led_0: %led_0: !hw.inout<i1>) -> ()
firrtl.extmodule private @bar740(in led_0: !firrtl.analog<1>)
firrtl.module private @foo740(in %led_0: !firrtl.analog<1>) {
@ -270,14 +270,14 @@ firrtl.circuit "Simple" {
firrtl.extmodule private @UIntToAnalog_8(out a: !firrtl.analog<8>, out b: !firrtl.analog<8>)
firrtl.module @Example(out %port: !firrtl.analog<8>) {
// CHECK-LABEL: hw.module @Example(%port: !hw.inout<i8>)
// CHECK-LABEL: hw.module @Example(inout %port : i8)
// CHECK-NEXT: hw.instance "a2b" @UIntToAnalog_8(a: %port: !hw.inout<i8>, b: %port: !hw.inout<i8>)
%a2b_a, %a2b_b = firrtl.instance a2b @UIntToAnalog_8(out a: !firrtl.analog<8>, out b: !firrtl.analog<8>)
firrtl.attach %port, %a2b_b, %a2b_a : !firrtl.analog<8>, !firrtl.analog<8>, !firrtl.analog<8>
}
// Memory modules are lowered to plain external modules.
// CHECK: hw.module.extern @MRead_ext(%R0_addr: i4, %R0_en: i1, %R0_clk: i1) -> (R0_data: i42) attributes {verilogName = "MRead_ext"}
// CHECK: hw.module.extern @MRead_ext(in %R0_addr : i4, in %R0_en : i1, in %R0_clk : i1, out R0_data : i42) attributes {verilogName = "MRead_ext"}
firrtl.memmodule @MRead_ext(in R0_addr: !firrtl.uint<4>, in R0_en: !firrtl.uint<1>, in R0_clk: !firrtl.uint<1>, out R0_data: !firrtl.uint<42>) attributes {dataWidth = 42 : ui32, depth = 12 : ui64, extraPorts = [], maskBits = 0 : ui32, numReadPorts = 1 : ui32, numReadWritePorts = 0 : ui32, numWritePorts = 0 : ui32, readLatency = 0 : ui32, writeLatency = 1 : ui32}
// The following operations should be passed through without an error.
@ -286,8 +286,8 @@ firrtl.circuit "Simple" {
// DontTouch on ports becomes symbol.
// CHECK-LABEL: hw.module.extern private @PortDT
// CHECK-SAME: (%a: i1 {hw.exportPort = #hw<innerSym@__PortDT__a>}, %hassym: i1 {hw.exportPort = #hw<innerSym@hassym>})
// CHECK-SAME: -> (b: i2 {hw.exportPort = #hw<innerSym@__PortDT__b>})
// CHECK-SAME: (in %a : i1 {hw.exportPort = #hw<innerSym@__PortDT__a>}, in %hassym : i1 {hw.exportPort = #hw<innerSym@hassym>},
// CHECK-SAME: out b : i2 {hw.exportPort = #hw<innerSym@__PortDT__b>})
firrtl.extmodule private @PortDT(
in a: !firrtl.uint<1> [{class = "firrtl.transforms.DontTouchAnnotation"}],
in hassym: !firrtl.uint<1> sym @hassym [{class = "firrtl.transforms.DontTouchAnnotation"}],

72
test/Conversion/FIRRTLToHW/lower-to-hw.mlir
View File

@ -593,7 +593,7 @@ firrtl.circuit "Simple" attributes {annotations = [{class =
// CHECK-NOT: output_file
// CHECK-NEXT: sv.bind <@bindTest::@[[quxSymbol:.+]]> {
// CHECK-SAME: output_file = #hw.output_file<"bindings.sv", excludeFromFileList>
// CHECK-NEXT: hw.module private @bindTest(%dummy: i1)
// CHECK-NEXT: hw.module private @bindTest(in %dummy : i1)
firrtl.module private @bindTest(in %dummy: !firrtl.uint<1>) {
// CHECK: hw.instance "baz" sym @[[bazSymbol]] @bar
%baz = firrtl.instance baz {lowerToBind} @bar(in io_cpu_flush: !firrtl.uint<1>)
@ -635,8 +635,8 @@ firrtl.circuit "Simple" attributes {annotations = [{class =
firrtl.connect %out, %2 : !firrtl.uint<1>, !firrtl.uint<1>
}
// CHECK-LABEL: hw.module private @Analog(%a1: !hw.inout<i1>, %b1: !hw.inout<i1>,
// CHECK: %c1: !hw.inout<i1>) -> (outClock: !seq.clock) {
// CHECK-LABEL: hw.module private @Analog(inout %a1 : i1, inout %b1 : i1,
// CHECK: inout %c1 : i1, out outClock : !seq.clock) {
// CHECK-NEXT: %0 = sv.read_inout %c1 : !hw.inout<i1>
// CHECK-NEXT: %1 = sv.read_inout %b1 : !hw.inout<i1>
// CHECK-NEXT: %2 = sv.read_inout %a1 : !hw.inout<i1>
@ -664,7 +664,7 @@ firrtl.circuit "Simple" attributes {annotations = [{class =
firrtl.connect %outClock, %1 : !firrtl.clock, !firrtl.clock
}
// CHECK-LABEL: hw.module private @top_modx() -> (tmp27: i23) {
// CHECK-LABEL: hw.module private @top_modx(out tmp27 : i23) {
// CHECK-NEXT: %c0_i23 = hw.constant 0 : i23
// CHECK-NEXT: %c42_i23 = hw.constant 42 : i23
// CHECK-NEXT: hw.output %c0_i23 : i23
@ -679,7 +679,7 @@ firrtl.circuit "Simple" attributes {annotations = [{class =
firrtl.connect %tmp27, %3 : !firrtl.uint<23>, !firrtl.uint<23>
}
// CHECK-LABEL: hw.module private @SimpleStruct(%source: !hw.struct<valid: i1, ready: i1, data: i64>) -> (fldout: i64) {
// CHECK-LABEL: hw.module private @SimpleStruct(in %source : !hw.struct<valid: i1, ready: i1, data: i64>, out fldout : i64) {
// CHECK-NEXT: %data = hw.struct_extract %source["data"] : !hw.struct<valid: i1, ready: i1, data: i64>
// CHECK-NEXT: hw.output %data : i64
// CHECK-NEXT: }
@ -689,7 +689,7 @@ firrtl.circuit "Simple" attributes {annotations = [{class =
firrtl.connect %fldout, %2 : !firrtl.uint<64>, !firrtl.uint<64>
}
// CHECK-LABEL: hw.module private @SimpleEnum(%source: !hw.enum<valid, ready, data>) -> (sink: !hw.enum<valid, ready, data>) {
// CHECK-LABEL: hw.module private @SimpleEnum(in %source : !hw.enum<valid, ready, data>, out sink : !hw.enum<valid, ready, data>) {
// CHECK-NEXT: %valid = hw.enum.constant valid : !hw.enum<valid, ready, data
// CHECK-NEXT: %0 = hw.enum.cmp %source, %valid : !hw.enum<valid, ready, data>, !hw.enum<valid, ready, data>
// CHECK-NEXT: hw.output %source : !hw.enum<valid, ready, data>
@ -701,7 +701,7 @@ firrtl.circuit "Simple" attributes {annotations = [{class =
firrtl.strictconnect %sink, %source : !firrtl.enum<valid: uint<0>, ready: uint<0>, data: uint<0>>
}
// CHECK-LABEL: hw.module private @SimpleEnumCreate() -> (sink: !hw.enum<a, b, c>) {
// CHECK-LABEL: hw.module private @SimpleEnumCreate(out sink : !hw.enum<a, b, c>) {
// CHECK-NEXT: %a = hw.enum.constant a : !hw.enum<a, b, c>
// CHECK-NEXT: hw.output %a : !hw.enum<a, b, c>
// CHECK-NEXT: }
@ -711,7 +711,7 @@ firrtl.circuit "Simple" attributes {annotations = [{class =
firrtl.strictconnect %sink, %0 : !firrtl.enum<a: uint<0>, b: uint<0>, c: uint<0>>
}
// CHECK-LABEL: hw.module private @DataEnum(%source: !hw.struct<tag: !hw.enum<a, b, c>, body: !hw.union<a: i2, b: i1, c: i32>>) -> (sink: !hw.struct<tag: !hw.enum<a, b, c>, body: !hw.union<a: i2, b: i1, c: i32>>) {
// CHECK-LABEL: hw.module private @DataEnum(in %source : !hw.struct<tag: !hw.enum<a, b, c>, body: !hw.union<a: i2, b: i1, c: i32>>, out sink : !hw.struct<tag: !hw.enum<a, b, c>, body: !hw.union<a: i2, b: i1, c: i32>>) {
// CHECK-NEXT: %tag = hw.struct_extract %source["tag"] : !hw.struct<tag: !hw.enum<a, b, c>, body: !hw.union<a: i2, b: i1, c: i32>>
// CHECK-NEXT: %a = hw.enum.constant a : !hw.enum<a, b, c>
// CHECK-NEXT: %0 = hw.enum.cmp %tag, %a : !hw.enum<a, b, c>, !hw.enum<a, b, c>
@ -726,7 +726,7 @@ firrtl.circuit "Simple" attributes {annotations = [{class =
firrtl.strictconnect %sink, %source : !firrtl.enum<a: uint<2>, b: uint<1>, c: uint<32>>
}
// CHECK-LABEL: hw.module private @DataEnumCreate(%input: i2) -> (sink: !hw.struct<tag: !hw.enum<a, b, c>, body: !hw.union<a: i2, b: i1, c: i32>>) {
// CHECK-LABEL: hw.module private @DataEnumCreate(in %input : i2, out sink : !hw.struct<tag: !hw.enum<a, b, c>, body: !hw.union<a: i2, b: i1, c: i32>>) {
// CHECK-NEXT: %a = hw.enum.constant a : !hw.enum<a, b, c>
// CHECK-NEXT: %0 = hw.union_create "a", %input : !hw.union<a: i2, b: i1, c: i32>
// CHECK-NEXT: %1 = hw.struct_create (%a, %0) : !hw.struct<tag: !hw.enum<a, b, c>, body: !hw.union<a: i2, b: i1, c: i32>>
@ -775,7 +775,7 @@ firrtl.circuit "Simple" attributes {annotations = [{class =
%widx_widx_bin = firrtl.regreset %clock, %reset, %c0_ui1 {name = "widx_widx_bin"} : !firrtl.clock, !firrtl.asyncreset, !firrtl.uint<1>, !firrtl.uint<4>
}
// CHECK-LABEL: hw.module private @Struct0bits(%source: !hw.struct<valid: i1, ready: i1, data: i0>) {
// CHECK-LABEL: hw.module private @Struct0bits(in %source : !hw.struct<valid: i1, ready: i1, data: i0>) {
// CHECK-NEXT: hw.output
// CHECK-NEXT: }
firrtl.module private @Struct0bits(in %source: !firrtl.bundle<valid: uint<1>, ready: uint<1>, data: uint<0>>) {
@ -809,21 +809,18 @@ firrtl.circuit "Simple" attributes {annotations = [{class =
firrtl.extmodule @chkcoverAnno(in clock: !firrtl.clock) attributes {annotations = [{class = "freechips.rocketchip.annotations.InternalVerifBlackBoxAnnotation"}]}
// chckcoverAnno is extracted because it is instantiated inside the DUT.
// CHECK-LABEL: hw.module.extern @chkcoverAnno(%clock: !seq.clock)
// CHECK-LABEL: hw.module.extern @chkcoverAnno(in %clock : !seq.clock)
// CHECK-SAME: attributes {firrtl.extract.cover.extra}
firrtl.extmodule @chkcoverAnno2(in clock: !firrtl.clock) attributes {annotations = [{class = "freechips.rocketchip.annotations.InternalVerifBlackBoxAnnotation"}]}
// checkcoverAnno2 is NOT extracted because it is not instantiated under the
// DUT.
// CHECK-LABEL: hw.module.extern @chkcoverAnno2(%clock: !seq.clock)
// CHECK-LABEL: hw.module.extern @chkcoverAnno2(in %clock : !seq.clock)
// CHECK-NOT: attributes {firrtl.extract.cover.extra}
// CHECK-LABEL: hw.module.extern @InnerNamesExt
// CHECK-SAME: (
// CHECK-SAME: clockIn: !seq.clock {hw.exportPort = #hw<innerSym@extClockInSym>}
// CHECK-SAME: ) -> (
// CHECK-SAME: clockOut: !seq.clock {hw.exportPort = #hw<innerSym@extClockOutSym>}
// CHECK-SAME: )
// CHECK: in %clockIn : !seq.clock {hw.exportPort = #hw<innerSym@extClockInSym>}
// CHECK: out clockOut : !seq.clock {hw.exportPort = #hw<innerSym@extClockOutSym>}
firrtl.extmodule @InnerNamesExt(
in clockIn: !firrtl.clock sym @extClockInSym,
out clockOut: !firrtl.clock sym @extClockOutSym
@ -885,11 +882,10 @@ firrtl.circuit "Simple" attributes {annotations = [{class =
// CHECK-LABEL: hw.module private @InnerNames
// CHECK-SAME: (
// CHECK-SAME: %value: i42 {hw.exportPort = #hw<innerSym@portValueSym>}
// CHECK-SAME: %clock: !seq.clock {hw.exportPort = #hw<innerSym@portClockSym>}
// CHECK-SAME: %reset: i1 {hw.exportPort = #hw<innerSym@portResetSym>}
// CHECK-SAME: ) -> (
// CHECK-SAME: out: i1 {hw.exportPort = #hw<innerSym@portOutSym>}
// CHECK-SAME: in %value : i42 {hw.exportPort = #hw<innerSym@portValueSym>}
// CHECK-SAME: in %clock : !seq.clock {hw.exportPort = #hw<innerSym@portClockSym>}
// CHECK-SAME: in %reset : i1 {hw.exportPort = #hw<innerSym@portResetSym>}
// CHECK-SAME: out out : i1 {hw.exportPort = #hw<innerSym@portOutSym>}
// CHECK-SAME: )
firrtl.module private @InnerNames(
in %value: !firrtl.uint<42> sym @portValueSym,
@ -1059,7 +1055,7 @@ firrtl.circuit "Simple" attributes {annotations = [{class =
%bar = firrtl.dshl %a, %b {name = "anothername"} : (!firrtl.uint<1>, !firrtl.uint<1>) -> !firrtl.uint<2>
}
// CHECK-LABEL: hw.module private @MultibitMux(%source_0: i1, %source_1: i1, %source_2: i1, %index: i2) -> (sink: i1) {
// CHECK-LABEL: hw.module private @MultibitMux(in %source_0 : i1, in %source_1 : i1, in %source_2 : i1, in %index : i2, out sink : i1) {
firrtl.module private @MultibitMux(in %source_0: !firrtl.uint<1>, in %source_1: !firrtl.uint<1>, in %source_2: !firrtl.uint<1>, out %sink: !firrtl.uint<1>, in %index: !firrtl.uint<2>) {
%0 = firrtl.multibit_mux %index, %source_2, %source_1, %source_0 : !firrtl.uint<2>, !firrtl.uint<1>
firrtl.connect %sink, %0 : !firrtl.uint<1>, !firrtl.uint<1>
@ -1132,7 +1128,7 @@ firrtl.circuit "Simple" attributes {annotations = [{class =
firrtl.strictconnect %out, %b_inst : !firrtl.uint<1>
}
// CHECK-LABEL: hw.module @LowerToFirReg(%clock: !seq.clock, %reset: i1, %value: i2)
// CHECK-LABEL: hw.module @LowerToFirReg(in %clock : !seq.clock, in %reset : i1, in %value : i2)
firrtl.module @LowerToFirReg(
in %clock: !firrtl.clock,
in %reset: !firrtl.uint<1>,
@ -1146,7 +1142,7 @@ firrtl.circuit "Simple" attributes {annotations = [{class =
// CHECK-NEXT: %regB = seq.firreg %value clock %clock reset sync %reset, %value : i2
}
// CHECK-LABEL: hw.module @SyncReset(%clock: !seq.clock, %reset: i1, %value: i2) -> (result: i2)
// CHECK-LABEL: hw.module @SyncReset(in %clock : !seq.clock, in %reset : i1, in %value : i2, out result : i2)
firrtl.module @SyncReset(in %clock: !firrtl.clock,
in %reset: !firrtl.uint<1>,
in %value: !firrtl.uint<2>,
@ -1159,7 +1155,7 @@ firrtl.circuit "Simple" attributes {annotations = [{class =
firrtl.strictconnect %result, %count : !firrtl.uint<2>
}
// CHECK-LABEL: hw.module @AsyncReset(%clock: !seq.clock, %reset: i1, %value: i2) -> (result: i2)
// CHECK-LABEL: hw.module @AsyncReset(in %clock : !seq.clock, in %reset : i1, in %value : i2, out result : i2)
firrtl.module @AsyncReset(in %clock: !firrtl.clock,
in %reset: !firrtl.asyncreset,
in %value: !firrtl.uint<2>,
@ -1173,7 +1169,7 @@ firrtl.circuit "Simple" attributes {annotations = [{class =
firrtl.strictconnect %result, %count : !firrtl.uint<2>
}
// CHECK-LABEL: hw.module @NoConnect(%clock: !seq.clock, %reset: i1) -> (result: i2)
// CHECK-LABEL: hw.module @NoConnect(in %clock : !seq.clock, in %reset : i1, out result : i2)
firrtl.module @NoConnect(in %clock: !firrtl.clock,
in %reset: !firrtl.uint<1>,
out %result: !firrtl.uint<2>) {
@ -1185,13 +1181,13 @@ firrtl.circuit "Simple" attributes {annotations = [{class =
// CHECK: hw.output %count : i2
}
// CHECK-LABEL: hw.module @passThroughForeignTypes
// CHECK-SAME: (%inOpaque: index) -> (outOpaque: index) {
// CHECK-SAME: (in %inOpaque : index, out outOpaque : index) {
// CHECK-NEXT: %sub2.bar = hw.instance "sub2" @moreForeignTypes(foo: %sub1.bar: index) -> (bar: index)
// CHECK-NEXT: %sub1.bar = hw.instance "sub1" @moreForeignTypes(foo: %inOpaque: index) -> (bar: index)
// CHECK-NEXT: hw.output %sub2.bar : index
// CHECK-NEXT: }
// CHECK-LABEL: hw.module @moreForeignTypes
// CHECK-SAME: (%foo: index) -> (bar: index) {
// CHECK-SAME: (in %foo : index, out bar : index) {
// CHECK-NEXT: hw.output %foo : index
// CHECK-NEXT: }
firrtl.module @passThroughForeignTypes(in %inOpaque: index, out %outOpaque: index) {
@ -1207,7 +1203,7 @@ firrtl.circuit "Simple" attributes {annotations = [{class =
}
// CHECK-LABEL: hw.module @foreignOpsOnForeignTypes
// CHECK-SAME: (%x: f32) -> (y: f32) {
// CHECK-SAME: (in %x : f32, out y : f32) {
// CHECK-NEXT: [[TMP:%.+]] = arith.addf %x, %x : f32
// CHECK-NEXT: hw.output [[TMP]] : f32
// CHECK-NEXT: }
@ -1217,7 +1213,7 @@ firrtl.circuit "Simple" attributes {annotations = [{class =
}
// CHECK-LABEL: hw.module @wiresWithForeignTypes
// CHECK-SAME: (%in: f32) -> (out: f32) {
// CHECK-SAME: (in %in : f32, out out : f32) {
// CHECK-NEXT: [[ADD1:%.+]] = arith.addf [[ADD2:%.+]], [[ADD2]] : f32
// CHECK-NEXT: [[ADD2]] = arith.addf %in, [[ADD2]] : f32
// CHECK-NEXT: hw.output [[ADD1]] : f32
@ -1312,7 +1308,7 @@ firrtl.circuit "Simple" attributes {annotations = [{class =
%result_iOut = firrtl.instance iOut @AnalogOutModA(out a: !firrtl.analog<8>)
firrtl.attach %a, %result_iIn, %result_iOut : !firrtl.analog<8>, !firrtl.analog<8>, !firrtl.analog<8>
}
// CHECK-LABEL: hw.module @AnalogMergeTwoWithPort(%a: !hw.inout<i8>) {
// CHECK-LABEL: hw.module @AnalogMergeTwoWithPort(inout %a : i8) {
// CHECK-NEXT: hw.instance "iIn" @AnalogInModA(a: %a: !hw.inout<i8>) -> ()
// CHECK-NEXT: hw.instance "iOut" @AnalogOutModA(a: %a: !hw.inout<i8>) -> ()
// CHECK-NEXT: hw.output
@ -1451,10 +1447,10 @@ firrtl.circuit "TypeAlias" {
// CHECK: hw.typedecl @bar_0 : i64
// CHECK: }
// CHECK: hw.module @TypeAlias(
// CHECK-SAME: %in: !hw.typealias<@TypeAlias__TYPESCOPE_::@A, i1>
// CHECK-SAME: %const: !hw.typealias<@TypeAlias__TYPESCOPE_::@B, i1>
// CHECK-SAME: out: !hw.typealias<@TypeAlias__TYPESCOPE_::@C, !hw.typealias<@TypeAlias__TYPESCOPE_::@baz, i1>>
// CHECK-SAME: out2: !hw.typealias<@TypeAlias__TYPESCOPE_::@D, i1>)
// CHECK-SAME: in %in : !hw.typealias<@TypeAlias__TYPESCOPE_::@A, i1>
// CHECK-SAME: in %const : !hw.typealias<@TypeAlias__TYPESCOPE_::@B, i1>
// CHECK-SAME: out out : !hw.typealias<@TypeAlias__TYPESCOPE_::@C, !hw.typealias<@TypeAlias__TYPESCOPE_::@baz, i1>>
// CHECK-SAME: out out2 : !hw.typealias<@TypeAlias__TYPESCOPE_::@D, i1>)
// CHECK: %wire = hw.wire %0 : !hw.typealias<@TypeAlias__TYPESCOPE_::@baz, i1>
// CHECK: %0 = hw.bitcast %in : (!hw.typealias<@TypeAlias__TYPESCOPE_::@A, i1>) -> !hw.typealias<@TypeAlias__TYPESCOPE_::@baz, i1>
// CHECK: %wire2 = hw.wire %1 : !hw.typealias<@TypeAlias__TYPESCOPE_::@baf, i1>
@ -1465,8 +1461,8 @@ firrtl.circuit "TypeAlias" {
// CHECK: }
// CHECK: hw.module private @SimpleStruct(
// CHECK-SAME: %source: !hw.typealias<@TypeAlias__TYPESCOPE_::@bar, !hw.struct<valid: i1, ready: i1, data: i64>>
// CHECK-SAME: fldout: !hw.typealias<@TypeAlias__TYPESCOPE_::@bar_0, i64>
// CHECK-SAME: in %source : !hw.typealias<@TypeAlias__TYPESCOPE_::@bar, !hw.struct<valid: i1, ready: i1, data: i64>>
// CHECK-SAME: out fldout : !hw.typealias<@TypeAlias__TYPESCOPE_::@bar_0, i64>
// CHECK: %wire = hw.wire %0 : !hw.struct<valid: i1, ready: i1, data: i64>
// CHECK: %0 = hw.bitcast %source : (!hw.typealias<@TypeAlias__TYPESCOPE_::@bar, !hw.struct<valid: i1, ready: i1, data: i64>>) -> !hw.struct<valid: i1, ready: i1, data: i64>
// CHECK: %data = hw.struct_extract %wire["data"] : !hw.struct<valid: i1, ready: i1, data: i64>

6
test/Conversion/FSMToSV/test_basic.mlir
View File

@ -15,11 +15,11 @@ fsm.machine @FSM(%arg0: i1, %arg1: i1) -> (i8) attributes {initialState = "A"} {
}
}
// CHECK: hw.module @top(%arg0: i1, %arg1: i1, %clk: !seq.clock, %rst: i1) -> (out: i8) {
// CHECK: hw.module @top(in %arg0 : i1, in %arg1 : i1, in %clk : !seq.clock, in %rst : i1, out out : i8) {
// CHECK: %fsm_inst.out0 = hw.instance "fsm_inst" @FSM(in0: %arg0: i1, in1: %arg1: i1, clk: %clk: !seq.clock, rst: %rst: i1) -> (out0: i8)
// CHECK: hw.output %fsm_inst.out0 : i8
// CHECK: }
hw.module @top(%arg0: i1, %arg1: i1, %clk : !seq.clock, %rst : i1) -> (out: i8) {
hw.module @top(in %arg0: i1, in %arg1: i1, in %clk : !seq.clock, in %rst : i1, out out: i8) {
%out = fsm.hw_instance "fsm_inst" @FSM(%arg0, %arg1), clock %clk, reset %rst : (i1, i1) -> (i8)
hw.output %out : i8
}
@ -30,7 +30,7 @@ hw.module @top(%arg0: i1, %arg1: i1, %clk : !seq.clock, %rst : i1) -> (out: i8)
// CHECK-NEXT: hw.typedecl @top_state_t : !hw.enum<A, B>
// CHECK-NEXT: }
// CHECK-LABEL: hw.module @top(%a0: i1, %a1: i1, %clk: !seq.clock, %rst: i1) -> (r0: i8, r1: i8) {
// CHECK-LABEL: hw.module @top(in %a0 : i1, in %a1 : i1, in %clk : !seq.clock, in %rst : i1, out r0 : i8, out r1 : i8) {
// CHECK-NEXT: %A = hw.enum.constant A : !hw.typealias<@fsm_enum_typedecls::@top_state_t, !hw.enum<A, B>>
// CHECK-NEXT: %to_A = sv.reg sym @A : !hw.inout<typealias<@fsm_enum_typedecls::@top_state_t, !hw.enum<A, B>>>
// CHECK-NEXT: sv.assign %to_A, %A : !hw.typealias<@fsm_enum_typedecls::@top_state_t, !hw.enum<A, B>>

42
test/Conversion/HWArithToHW/test_basic.mlir
View File

@ -1,10 +1,10 @@
// RUN: circt-opt -split-input-file -lower-hwarith-to-hw %s | FileCheck %s
// CHECK: hw.module @constant() -> (out: i32) {
// CHECK: hw.module @constant(out out : i32) {
// CHECK: %c0_i32 = hw.constant 0 : i32
// CHECK: hw.output %c0_i32 : i32
hw.module @constant() -> (out: i32) {
hw.module @constant(out out: i32) {
%0 = hwarith.constant 0 : si32
%out = hwarith.cast %0 : (si32) -> i32
hw.output %out : i32
@ -12,8 +12,8 @@ hw.module @constant() -> (out: i32) {
// -----
// CHECK: hw.module @add(%op0: i32, %op1: i32) -> (sisi: i32, siui: i32, uisi: i32, uiui: i32) {
hw.module @add(%op0: i32, %op1: i32) -> (sisi: i32, siui: i32, uisi: i32, uiui: i32) {
// CHECK: hw.module @add(in %op0 : i32, in %op1 : i32, out sisi : i32, out siui : i32, out uisi : i32, out uiui : i32) {
hw.module @add(in %op0 : i32, in %op1 : i32, out sisi : i32, out siui : i32, out uisi : i32, out uiui : i32) {
%op0Signed = hwarith.cast %op0 : (i32) -> si32
%op0Unsigned = hwarith.cast %op0 : (i32) -> ui32
%op1Signed = hwarith.cast %op1 : (i32) -> si32
@ -64,8 +64,8 @@ hw.module @add(%op0: i32, %op1: i32) -> (sisi: i32, siui: i32, uisi: i32, uiui:
// -----
// CHECK: hw.module @sub(%op0: i32, %op1: i32) -> (sisi: i32, siui: i32, uisi: i32, uiui: i32) {
hw.module @sub(%op0: i32, %op1: i32) -> (sisi: i32, siui: i32, uisi: i32, uiui: i32) {
// CHECK: hw.module @sub(in %op0 : i32, in %op1 : i32, out sisi : i32, out siui : i32, out uisi : i32, out uiui : i32) {
hw.module @sub(in %op0: i32, in %op1: i32, out sisi: i32, out siui: i32, out uisi: i32, out uiui: i32) {
%op0Signed = hwarith.cast %op0 : (i32) -> si32
%op0Unsigned = hwarith.cast %op0 : (i32) -> ui32
%op1Signed = hwarith.cast %op1 : (i32) -> si32
@ -116,8 +116,8 @@ hw.module @sub(%op0: i32, %op1: i32) -> (sisi: i32, siui: i32, uisi: i32, uiui:
// -----
// CHECK: hw.module @mul(%op0: i32, %op1: i32) -> (sisi: i32, siui: i32, uisi: i32, uiui: i32) {
hw.module @mul(%op0: i32, %op1: i32) -> (sisi: i32, siui: i32, uisi: i32, uiui: i32) {
// CHECK: hw.module @mul(in %op0 : i32, in %op1 : i32, out sisi : i32, out siui : i32, out uisi : i32, out uiui : i32) {
hw.module @mul(in %op0: i32, in %op1: i32, out sisi: i32, out siui: i32, out uisi: i32, out uiui: i32) {
%op0Signed = hwarith.cast %op0 : (i32) -> si32
%op0Unsigned = hwarith.cast %op0 : (i32) -> ui32
@ -171,8 +171,8 @@ hw.module @mul(%op0: i32, %op1: i32) -> (sisi: i32, siui: i32, uisi: i32, uiui:
// -----
// CHECK: hw.module @div(%op0: i32, %op1: i32) -> (sisi: i32, siui: i32, uisi: i32, uiui: i32) {
hw.module @div(%op0: i32, %op1: i32) -> (sisi: i32, siui: i32, uisi: i32, uiui: i32) {
// CHECK: hw.module @div(in %op0 : i32, in %op1 : i32, out sisi : i32, out siui : i32, out uisi : i32, out uiui : i32) {
hw.module @div(in %op0: i32, in %op1: i32, out sisi: i32, out siui: i32, out uisi: i32, out uiui: i32) {
%op0Signed = hwarith.cast %op0 : (i32) -> si32
%op0Unsigned = hwarith.cast %op0 : (i32) -> ui32
%op1Signed = hwarith.cast %op1 : (i32) -> si32
@ -216,8 +216,8 @@ hw.module @div(%op0: i32, %op1: i32) -> (sisi: i32, siui: i32, uisi: i32, uiui:
// -----
// CHECK: hw.module @icmp(%op0: i32, %op1: i32) -> (sisi: i1, siui: i1, uisi: i1, uiui: i1) {
hw.module @icmp(%op0: i32, %op1: i32) -> (sisi: i1, siui: i1, uisi: i1, uiui: i1) {
// CHECK: hw.module @icmp(in %op0 : i32, in %op1 : i32, out sisi : i1, out siui : i1, out uisi : i1, out uiui : i1) {
hw.module @icmp(in %op0: i32, in %op1: i32, out sisi: i1, out siui: i1, out uisi: i1, out uiui: i1) {
%op0Signed = hwarith.cast %op0 : (i32) -> si32
%op0Unsigned = hwarith.cast %op0 : (i32) -> ui32
%op1Signed = hwarith.cast %op1 : (i32) -> si32
@ -254,8 +254,8 @@ hw.module @icmp(%op0: i32, %op1: i32) -> (sisi: i1, siui: i1, uisi: i1, uiui: i1
// -----
// CHECK: hw.module @icmp_mixed_width(%op0: i5, %op1: i7) -> (sisi: i1, siui: i1, uisi: i1, uiui: i1) {
hw.module @icmp_mixed_width(%op0: i5, %op1: i7) -> (sisi: i1, siui: i1, uisi: i1, uiui: i1) {
// CHECK: hw.module @icmp_mixed_width(in %op0 : i5, in %op1 : i7, out sisi : i1, out siui : i1, out uisi : i1, out uiui : i1) {
hw.module @icmp_mixed_width(in %op0: i5, in %op1: i7, out sisi: i1, out siui: i1, out uisi: i1, out uiui: i1) {
%op0Signed = hwarith.cast %op0 : (i5) -> si5
%op0Unsigned = hwarith.cast %op0 : (i5) -> ui5
%op1Signed = hwarith.cast %op1 : (i7) -> si7
@ -297,12 +297,12 @@ hw.module @icmp_mixed_width(%op0: i5, %op1: i7) -> (sisi: i1, siui: i1, uisi: i1
// -----
// Signature conversion and other-dialect operations using signedness values.
// CHECK: hw.module @sigAndOps(%a: i8, %b: i8, %cond: i1, %clk: !seq.clock) -> (out: i8) {
// CHECK: hw.module @sigAndOps(in %a : i8, in %b : i8, in %cond : i1, in %clk : !seq.clock, out out : i8) {
// CHECK-NEXT: %[[MUX_OUT:.*]] = comb.mux %cond, %a, %b : i8
// CHECK-NEXT: %[[REG_OUT:.*]] = seq.compreg %[[MUX_OUT]], %clk : i8
// CHECK-NEXT: hw.output %[[REG_OUT]] : i8
// CHECK-NEXT: }
hw.module @sigAndOps(%a: ui8, %b: ui8, %cond: i1, %clk : !seq.clock) -> (out: ui8) {
hw.module @sigAndOps(in %a: ui8, in %b: ui8, in %cond: i1, in %clk : !seq.clock, out out: ui8) {
%0 = comb.mux %cond, %a, %b : ui8
%1 = seq.compreg %0, %clk: ui8
hw.output %1 : ui8
@ -311,12 +311,12 @@ hw.module @sigAndOps(%a: ui8, %b: ui8, %cond: i1, %clk : !seq.clock) -> (out: ui
// -----
// Type conversions of struct and array ops.
// CHECK: hw.module @structAndArrays(%a: i8, %b: i8) -> (out: !hw.struct<foo: !hw.array<2xi8>>) {
// CHECK: hw.module @structAndArrays(in %a : i8, in %b : i8, out out : !hw.struct<foo: !hw.array<2xi8>>) {
// CHECK-NEXT: %[[ARRAY:.*]] = hw.array_create %a, %b : i8
// CHECK-NEXT: %[[STRUCT:.*]] = hw.struct_create (%[[ARRAY]]) : !hw.struct<foo: !hw.array<2xi8>>
// CHECK-NEXT: hw.output %[[STRUCT]] : !hw.struct<foo: !hw.array<2xi8>>
// CHECK-NEXT: }
hw.module @structAndArrays(%a: ui8, %b: ui8) -> (out: !hw.struct<foo: !hw.array<2xui8>>) {
hw.module @structAndArrays(in %a: ui8, in %b: ui8, out out: !hw.struct<foo: !hw.array<2xui8>>) {
%2 = hw.array_create %a, %b : ui8
%3 = hw.struct_create (%2) : !hw.struct<foo: !hw.array<2xui8>>
hw.output %3 : !hw.struct<foo: !hw.array<2xui8>>
@ -324,8 +324,8 @@ hw.module @structAndArrays(%a: ui8, %b: ui8) -> (out: !hw.struct<foo: !hw.array<
// -----
// CHECK: hw.module.extern @externHWModule(%a: i8, %b: i8) -> (out: !hw.struct<foo: !hw.array<2xi8>>)
hw.module.extern @externHWModule(%a: ui8, %b: ui8) -> (out: !hw.struct<foo: !hw.array<2xui8>>)
// CHECK: hw.module.extern @externHWModule(in %a : i8, in %b : i8, out out : !hw.struct<foo: !hw.array<2xi8>>)
hw.module.extern @externHWModule(in %a: ui8, in %b: ui8, out out: !hw.struct<foo: !hw.array<2xui8>>)
// -----
@ -357,7 +357,7 @@ hw.module @backedges() {
// CHECK: sv.assign %[[VAL_1]], %[[VAL_5]] : i2
// CHECK: hw.output
// CHECK: }
hw.module @wires () -> () {
hw.module @wires () {
%r52 = sv.wire : !hw.inout<ui2>
%r53 = sv.reg : !hw.inout<ui2>
%0 = sv.read_inout %r52 : !hw.inout<ui2>

4
test/Conversion/HWToLLHD/errors.mlir
View File

@ -3,10 +3,10 @@
module {
// Since HW-to-LLHD needs to construct a zero value for temporary signals,
// we don't support non-IntegerType arguments to instances.
hw.module @sub(%in: f16) -> (out: f16) {
hw.module @sub(in %in: f16, out out: f16) {
hw.output %in: f16
}
hw.module @test(%in: f16) -> (out: f16) {
hw.module @test(in %in: f16, out out: f16) {
// expected-error @+1 {{failed to legalize operation 'hw.instance'}}
%0 = hw.instance "sub1" @sub (in: %in: f16) -> (out: f16)
hw.output %0: f16

14
test/Conversion/HWToLLHD/structure.mlir
View File

@ -4,7 +4,7 @@ module {
// CHECK-LABEL: llhd.entity @FeedThrough
// CHECK-SAME: (%[[IN:.+]] : !llhd.sig<i1>) ->
// CHECK-SAME: (%[[OUT:.+]] : !llhd.sig<i1>)
hw.module @FeedThrough(%in: i1) -> (out: i1) {
hw.module @FeedThrough(in %in: i1, out out: i1) {
// CHECK: llhd.con %[[OUT]], %[[IN]]
hw.output %in: i1
}
@ -12,7 +12,7 @@ module {
// CHECK-LABEL: llhd.entity @CombOp
// CHECK-SAME: (%[[IN:.+]] : !llhd.sig<i1>) ->
// CHECK-SAME: (%[[OUT:.+]] : !llhd.sig<i1>)
hw.module @CombOp(%in: i1) -> (out: i1) {
hw.module @CombOp(in %in : i1, out out: i1) {
// CHECK: %[[PRB:.+]] = llhd.prb %[[IN]]
// CHECK: %[[ADD:.+]] = comb.add %[[PRB]], %[[PRB]]
// CHECK: llhd.drv %[[OUT]], %[[ADD]]
@ -23,14 +23,14 @@ module {
// CHECK-LABEL: llhd.entity @sub
// CHECK-SAME: ({{.+}} : !llhd.sig<i1>) ->
// CHECK-SAME: ({{.+}} : !llhd.sig<i1>)
hw.module @sub(%in: i1) -> (out: i1) {
hw.module @sub(in %in: i1, out out: i1) {
hw.output %in : i1
}
// CHECK-LABEL: llhd.entity @SimpleInstance
// CHECK-SAME: (%[[IN:.+]] : !llhd.sig<i1>) ->
// CHECK-SAME: (%[[OUT:.+]] : !llhd.sig<i1>)
hw.module @SimpleInstance(%in: i1) -> (out: i1) {
hw.module @SimpleInstance(in %in: i1, out out: i1) {
// CHECK: llhd.inst "sub1" @sub(%[[IN]]) -> (%[[OUT]]) : (!llhd.sig<i1>) -> !llhd.sig<i1>
%0 = hw.instance "sub1" @sub (in: %in: i1) -> (out: i1)
hw.output %0 : i1
@ -39,7 +39,7 @@ module {
// CHECK-LABEL: llhd.entity @InstanceWithLocalOps
// CHECK-SAME: (%[[IN:.+]] : !llhd.sig<i1>) ->
// CHECK-SAME: (%[[OUT:.+]] : !llhd.sig<i1>)
hw.module @InstanceWithLocalOps(%in: i1) -> (out: i1) {
hw.module @InstanceWithLocalOps(in %in: i1, out out: i1) {
// CHECK: %[[PRB:.+]] = llhd.prb %[[IN]]
// CHECK: %[[ADD1:.+]] = comb.add %[[PRB]], %[[PRB]]
// CHECK: llhd.drv %[[ARG_SIG:.+]], %[[ADD1]]
@ -58,7 +58,7 @@ module {
// CHECK-SAME: (%[[IN:.+]] : !llhd.sig<i1>) -> (
// CHECK-SAME: %[[OUT1:.+]] : !llhd.sig<i1>,
// CHECK-SAME: %[[OUT2:.+]] : !llhd.sig<i1>)
hw.module @InstanceDirectlyDrivingMultipleOutputs(%in: i1) -> (out1: i1, out2: i1) {
hw.module @InstanceDirectlyDrivingMultipleOutputs(in %in: i1, out out1: i1, out out2: i1) {
// CHECK: llhd.inst "sub1" @sub(%[[IN]]) -> (%[[OUT2]]) : (!llhd.sig<i1>) -> !llhd.sig<i1>
// CHECK: llhd.con %[[OUT1]], %[[OUT2]]
%0 = hw.instance "sub1" @sub (in: %in: i1) -> (out: i1)
@ -69,7 +69,7 @@ module {
// CHECK-SAME: (%[[IN:.+]] : !llhd.sig<i1>) -> (
// CHECK-SAME: %[[OUT1:.+]] : !llhd.sig<i1>,
// CHECK-SAME: %[[OUT2:.+]] : !llhd.sig<i1>)
hw.module @InstanceIndirectlyDrivingMultipleOutputs(%in: i1) -> (out1: i1, out2: i1) {
hw.module @InstanceIndirectlyDrivingMultipleOutputs(in %in: i1, out out1: i1, out out2: i1) {
// CHECK: %[[RES_SIG:.+]] = llhd.sig
// CHECK: %[[RES:.+]] = llhd.prb %[[RES_SIG]]
// CHECK: llhd.inst "sub1" @sub(%[[IN]]) -> (%[[RES_SIG]]) : (!llhd.sig<i1>) -> !llhd.sig<i1>

2
test/Conversion/HWToSV/test_trigger.mlir
View File

@ -1,6 +1,6 @@
// RUN: circt-opt --lower-hw-to-sv --allow-unregistered-dialect %s | FileCheck %s
hw.module @foo(%trigger : i1, %in : i32) {
hw.module @foo(in %trigger : i1, in %in : i32) {
// CHECK: sv.always posedge %trigger {
// CHECK-NEXT: "some.user"(%in) : (i32) -> ()
// CHECK-NEXT: }

6
test/Conversion/HWToSystemC/errors.mlir
View File

@ -2,17 +2,17 @@
// expected-error @+2 {{module parameters not supported yet}}
// expected-error @+1 {{failed to legalize operation 'hw.module'}}
hw.module @someModule<p1: i42 = 17, p2: i1>() -> () {}
hw.module @someModule<p1: i42 = 17, p2: i1>() {}
// -----
// expected-error @+2 {{inout arguments not supported yet}}
// expected-error @+1 {{failed to legalize operation 'hw.module'}}
hw.module @someModule(%in0: !hw.inout<i32>) -> () {}
hw.module @someModule(inout %in0: i32) {}
// -----
hw.module @graphRegionToSSACFG(%in0: i32) -> () {
hw.module @graphRegionToSSACFG(in %in0: i32) {
// expected-error @+1 {{operand #1 does not dominate this use}}
%0 = comb.add %in0, %1 : i32
// expected-note @+1 {{operand defined here (op in the same block)}}

34
test/Conversion/HWToSystemC/structure.mlir
View File

@ -3,13 +3,13 @@
// CHECK: emitc.include <"systemc.h">
// CHECK-LABEL: systemc.module @emptyModule ()
hw.module @emptyModule () -> () {}
hw.module @emptyModule () {}
// CHECK-LABEL: systemc.module @onlyInputs (%a: !systemc.in<!systemc.uint<32>>, %b: !systemc.in<!systemc.biguint<256>>, %c: !systemc.in<!systemc.bv<1024>>, %d: !systemc.in<i1>)
hw.module @onlyInputs (%a: i32, %b: i256, %c: i1024, %d: i1) -> () {}
hw.module @onlyInputs (in %a: i32, in %b: i256, in %c: i1024, in %d: i1) {}
// CHECK-LABEL: systemc.module @onlyOutputs (%sum: !systemc.out<!systemc.uint<32>>)
hw.module @onlyOutputs () -> (sum: i32) {
hw.module @onlyOutputs (out sum: i32) {
// CHECK-NEXT: systemc.ctor {
// CHECK-NEXT: systemc.method %innerLogic
// CHECK-NEXT: }
@ -23,7 +23,7 @@ hw.module @onlyOutputs () -> (sum: i32) {
}
// CHECK-LABEL: systemc.module @adder (%a: !systemc.in<!systemc.uint<32>>, %b: !systemc.in<!systemc.uint<32>>, %sum: !systemc.out<!systemc.uint<32>>)
hw.module @adder (%a: i32, %b: i32) -> (sum: i32) {
hw.module @adder (in %a: i32, in %b: i32, out sum: i32) {
// CHECK-NEXT: systemc.ctor {
// CHECK-NEXT: systemc.method %innerLogic
// CHECK-NEXT: systemc.sensitive %a, %b : !systemc.in<!systemc.uint<32>>, !systemc.in<!systemc.uint<32>>
@ -43,28 +43,28 @@ hw.module @adder (%a: i32, %b: i32) -> (sum: i32) {
}
// CHECK-LABEL: systemc.module private @moduleVisibility
hw.module private @moduleVisibility () -> () {}
hw.module private @moduleVisibility () {}
// CHECK-LABEL: systemc.module @argAttrs (%port0: !systemc.in<!systemc.uint<32>> {hw.attrname = "sometext"}, %port1: !systemc.in<!systemc.uint<32>>, %out0: !systemc.out<!systemc.uint<32>>)
hw.module @argAttrs (%port0: i32 {hw.attrname = "sometext"}, %port1: i32) -> (out0: i32) {
hw.module @argAttrs (in %port0: i32 {hw.attrname = "sometext"}, in %port1: i32, out out0: i32) {
%0 = hw.constant 0 : i32
hw.output %0 : i32
}
// CHECK-LABEL: systemc.module @resultAttrs (%port0: !systemc.in<!systemc.uint<32>>, %out0: !systemc.out<!systemc.uint<32>> {hw.attrname = "sometext"})
hw.module @resultAttrs (%port0: i32) -> (out0: i32 {hw.attrname = "sometext"}) {
hw.module @resultAttrs (in %port0: i32, out out0: i32 {hw.attrname = "sometext"}) {
%0 = hw.constant 0 : i32
hw.output %0 : i32
}
// CHECK-LABEL: systemc.module @submodule
hw.module @submodule (%in0: i16, %in1: i32) -> (out0: i16, out1: i32, out2: i64) {
hw.module @submodule (in %in0: i16, in %in1: i32, out out0: i16, out out1: i32, out out2: i64) {
%0 = hw.constant 0 : i64
hw.output %in0, %in1, %0 : i16, i32, i64
}
// CHECK-LABEL: systemc.module @instanceLowering (%port0: !systemc.in<!systemc.uint<32>>, %out0: !systemc.out<!systemc.uint<16>>, %out1: !systemc.out<!systemc.uint<32>>, %out2: !systemc.out<!systemc.uint<64>>) {
hw.module @instanceLowering (%port0: i32) -> (out0: i16, out1: i32, out2: i64) {
hw.module @instanceLowering (in %port0: i32, out out0: i16, out out1: i32, out out2: i64) {
// CHECK-NEXT: %inst1 = systemc.instance.decl @submodule : !systemc.module<submodule(in0: !systemc.in<!systemc.uint<16>>, in1: !systemc.in<!systemc.uint<32>>, out0: !systemc.out<!systemc.uint<16>>, out1: !systemc.out<!systemc.uint<32>>, out2: !systemc.out<!systemc.uint<64>>)>
// CHECK-NEXT: %inst1_in0 = systemc.signal : !systemc.signal<!systemc.uint<16>>
// CHECK-NEXT: %inst1_in1 = systemc.signal : !systemc.signal<!systemc.uint<32>>
@ -118,7 +118,7 @@ hw.module @instanceLowering (%port0: i32) -> (out0: i16, out1: i32, out2: i64) {
}
// CHECK-LABEL: systemc.module @instanceLowering2
hw.module @instanceLowering2 () -> () {
hw.module @instanceLowering2 () {
// CHECK-NEXT: %inst1 = systemc.instance.decl @emptyModule : !systemc.module<emptyModule()>
// CHECK-NEXT: systemc.ctor {
// CHECK-NEXT: systemc.method %
@ -130,10 +130,10 @@ hw.module @instanceLowering2 () -> () {
}
// CHECK-LABEL: systemc.module @systemCTypes (%p0: !systemc.in<!systemc.int<32>>, %p1: !systemc.in<!systemc.int_base>, %p2: !systemc.in<!systemc.uint<32>>, %p3: !systemc.in<!systemc.uint_base>, %p4: !systemc.in<!systemc.bigint<32>>, %p5: !systemc.in<!systemc.signed>, %p6: !systemc.in<!systemc.biguint<32>>, %p7: !systemc.in<!systemc.unsigned>, %p8: !systemc.in<!systemc.bv<32>>, %p9: !systemc.in<!systemc.bv_base>, %p10: !systemc.in<!systemc.lv<32>>, %p11: !systemc.in<!systemc.lv_base>, %p12: !systemc.in<!systemc.logic>)
hw.module @systemCTypes (%p0: !systemc.int<32>, %p1: !systemc.int_base,
%p2: !systemc.uint<32>, %p3: !systemc.uint_base,
%p4: !systemc.bigint<32>, %p5: !systemc.signed,
%p6: !systemc.biguint<32>, %p7: !systemc.unsigned,
%p8: !systemc.bv<32>, %p9: !systemc.bv_base,
%p10: !systemc.lv<32>, %p11: !systemc.lv_base,
%p12: !systemc.logic) -> () {}
hw.module @systemCTypes (in %p0: !systemc.int<32>, in %p1: !systemc.int_base,
in %p2: !systemc.uint<32>, in %p3: !systemc.uint_base,
in %p4: !systemc.bigint<32>, in %p5: !systemc.signed,
in %p6: !systemc.biguint<32>, in %p7: !systemc.unsigned,
in %p8: !systemc.bv<32>, in %p9: !systemc.bv_base,
in %p10: !systemc.lv<32>, in %p11: !systemc.lv_base,
in %p12: !systemc.logic) {}

33
test/Conversion/HandshakeToDC/basic.mlir
View File

@ -1,7 +1,6 @@
// RUN: circt-opt %s --lower-handshake-to-dc | FileCheck %s
// CHECK-LABEL: hw.module @test_fork(
// CHECK-SAME: %[[VAL_0:.*]]: !dc.token) -> (out0: !dc.token, out1: !dc.token) {
// CHECK: hw.module @test_fork(in %[[VAL_0:.*]] : !dc.token, out out0 : !dc.token, out out1 : !dc.token) {
// CHECK: %[[VAL_1:.*]]:2 = dc.fork [2] %[[VAL_0]]
// CHECK: hw.output %[[VAL_1]]#0, %[[VAL_1]]#1 : !dc.token, !dc.token
// CHECK: }
@ -10,8 +9,7 @@ handshake.func @test_fork(%arg0: none) -> (none, none) {
return %0#0, %0#1 : none, none
}
// CHECK-LABEL: hw.module @test_fork_data(
// CHECK-SAME: %[[VAL_0:.*]]: !dc.value<i32>) -> (out0: !dc.value<i32>) {
// CHECK: hw.module @test_fork_data(in %[[VAL_0:.*]] : !dc.value<i32>, out out0 : !dc.value<i32>) {
// CHECK: %[[VAL_1:.*]], %[[VAL_2:.*]] = dc.unpack %[[VAL_0]] : !dc.value<i32>
// CHECK: %[[VAL_3:.*]]:2 = dc.fork [2] %[[VAL_1]]
// CHECK: %[[VAL_4:.*]] = dc.pack %[[VAL_3]]#0, %[[VAL_2]] : i32
@ -29,8 +27,7 @@ handshake.func @test_fork_data(%arg0: i32) -> (i32) {
return %1 : i32
}
// CHECK-LABEL: hw.module @top(
// CHECK-SAME: %[[VAL_0:.*]]: !dc.value<i64>, %[[VAL_1:.*]]: !dc.value<i64>, %[[VAL_2:.*]]: !dc.token) -> (out0: !dc.value<i64>, out1: !dc.token) {
// CHECK: hw.module @top(in %[[VAL_0:.*]] : !dc.value<i64>, in %[[VAL_1:.*]] : !dc.value<i64>, in %[[VAL_2:.*]] : !dc.token, out out0 : !dc.value<i64>, out out1 : !dc.token) {
// CHECK: %[[VAL_3:.*]], %[[VAL_4:.*]] = dc.unpack %[[VAL_0]] : !dc.value<i64>
// CHECK: %[[VAL_5:.*]], %[[VAL_6:.*]] = dc.unpack %[[VAL_1]] : !dc.value<i64>
// CHECK: %[[VAL_7:.*]] = dc.join %[[VAL_3]], %[[VAL_5]]
@ -50,8 +47,7 @@ handshake.func @top(%arg0: i64, %arg1: i64, %arg8: none, ...) -> (i64, none) {
return %1, %arg8 : i64, none
}
// CHECK-LABEL: hw.module @mux(
// CHECK-SAME: %[[VAL_0:.*]]: !dc.value<i1>, %[[VAL_1:.*]]: !dc.value<i64>, %[[VAL_2:.*]]: !dc.value<i64>) -> (out0: !dc.value<i64>) {
// CHECK: hw.module @mux(in %[[VAL_0:.*]] : !dc.value<i1>, in %[[VAL_1:.*]] : !dc.value<i64>, in %[[VAL_2:.*]] : !dc.value<i64>, out out0 : !dc.value<i64>) {
// CHECK: %[[VAL_3:.*]], %[[VAL_4:.*]] = dc.unpack %[[VAL_0]] : !dc.value<i1>
// CHECK: %[[VAL_5:.*]], %[[VAL_6:.*]] = dc.unpack %[[VAL_1]] : !dc.value<i64>
// CHECK: %[[VAL_7:.*]], %[[VAL_8:.*]] = dc.unpack %[[VAL_2]] : !dc.value<i64>
@ -68,8 +64,7 @@ handshake.func @mux(%select : i1, %a : i64, %b : i64) -> i64{
return %0 : i64
}
// CHECK-LABEL: hw.module @mux4(
// CHECK-SAME: %[[VAL_0:.*]]: !dc.value<i2>, %[[VAL_1:.*]]: !dc.value<i64>, %[[VAL_2:.*]]: !dc.value<i64>, %[[VAL_3:.*]]: !dc.value<i64>, %[[VAL_4:.*]]: !dc.value<i64>) -> (out0: !dc.value<i64>) {
// CHECK: hw.module @mux4(in %[[VAL_0:.*]] : !dc.value<i2>, in %[[VAL_1:.*]] : !dc.value<i64>, in %[[VAL_2:.*]] : !dc.value<i64>, in %[[VAL_3:.*]] : !dc.value<i64>, in %[[VAL_4:.*]] : !dc.value<i64>, out out0 : !dc.value<i64>) {
// CHECK: %[[VAL_5:.*]], %[[VAL_6:.*]] = dc.unpack %[[VAL_0]] : !dc.value<i2>
// CHECK: %[[VAL_7:.*]], %[[VAL_8:.*]] = dc.unpack %[[VAL_1]] : !dc.value<i64>
// CHECK: %[[VAL_9:.*]], %[[VAL_10:.*]] = dc.unpack %[[VAL_2]] : !dc.value<i64>
@ -98,8 +93,7 @@ handshake.func @mux4(%select : i2, %a : i64, %b : i64, %c : i64, %d : i64) -> i6
return %0 : i64
}
// CHECK-LABEL: hw.module @test_conditional_branch(
// CHECK-SAME: %[[VAL_0:.*]]: !dc.value<i1>, %[[VAL_1:.*]]: !dc.value<index>, %[[VAL_2:.*]]: !dc.token) -> (out0: !dc.value<index>, out1: !dc.value<index>, out2: !dc.token) {
// CHECK: hw.module @test_conditional_branch(in %[[VAL_0:.*]] : !dc.value<i1>, in %[[VAL_1:.*]] : !dc.value<index>, in %[[VAL_2:.*]] : !dc.token, out out0 : !dc.value<index>, out out1 : !dc.value<index>, out out2 : !dc.token) {
// CHECK: %[[VAL_3:.*]], %[[VAL_4:.*]] = dc.unpack %[[VAL_0]] : !dc.value<i1>
// CHECK: %[[VAL_5:.*]], %[[VAL_6:.*]] = dc.unpack %[[VAL_1]] : !dc.value<index>
// CHECK: %[[VAL_7:.*]] = dc.join %[[VAL_3]], %[[VAL_5]]
@ -114,8 +108,7 @@ handshake.func @test_conditional_branch(%arg0: i1, %arg1: index, %arg2: none, ..
return %0#0, %0#1, %arg2 : index, index, none
}
// CHECK-LABEL: hw.module @test_conditional_branch_none(
// CHECK-SAME: %[[VAL_0:.*]]: !dc.value<i1>, %[[VAL_1:.*]]: !dc.token) -> (out0: !dc.token, out1: !dc.token) {
// CHECK: hw.module @test_conditional_branch_none(in %[[VAL_0:.*]] : !dc.value<i1>, in %[[VAL_1:.*]] : !dc.token, out out0 : !dc.token, out out1 : !dc.token) {
// CHECK: %[[VAL_2:.*]], %[[VAL_3:.*]] = dc.unpack %[[VAL_0]] : !dc.value<i1>
// CHECK: %[[VAL_4:.*]] = dc.join %[[VAL_2]], %[[VAL_1]]
// CHECK: %[[VAL_5:.*]] = dc.pack %[[VAL_4]], %[[VAL_3]] : i1
@ -127,8 +120,7 @@ handshake.func @test_conditional_branch_none(%arg0: i1, %arg1: none) -> (none, n
return %0#0, %0#1 : none, none
}
// CHECK-LABEL: hw.module @test_constant(
// CHECK-SAME: %[[VAL_0:.*]]: !dc.token) -> (out0: !dc.value<i32>) {
// CHECK: hw.module @test_constant(in %[[VAL_0:.*]] : !dc.token, out out0 : !dc.value<i32>) {
// CHECK: %[[VAL_1:.*]] = dc.source
// CHECK: %[[VAL_2:.*]] = arith.constant 42 : i32
// CHECK: %[[VAL_3:.*]] = dc.pack %[[VAL_1]], %[[VAL_2]] : i32
@ -139,8 +131,7 @@ handshake.func @test_constant(%arg0: none) -> (i32) {
return %1: i32
}
// CHECK-LABEL: hw.module @test_control_merge(
// CHECK-SAME: %[[VAL_0:.*]]: !dc.token, %[[VAL_1:.*]]: !dc.token) -> (out0: !dc.token, out1: !dc.value<index>) {
// CHECK: hw.module @test_control_merge(in %[[VAL_0:.*]] : !dc.token, in %[[VAL_1:.*]] : !dc.token, out out0 : !dc.token, out out1 : !dc.value<index>) {
// CHECK: %[[VAL_2:.*]] = dc.merge %[[VAL_0]], %[[VAL_1]]
// CHECK: %[[VAL_3:.*]], %[[VAL_4:.*]] = dc.unpack %[[VAL_2]] : !dc.value<i1>
// CHECK: %[[VAL_5:.*]], %[[VAL_6:.*]] = dc.unpack %[[VAL_2]] : !dc.value<i1>
@ -153,8 +144,7 @@ handshake.func @test_control_merge(%arg0 : none, %arg1 : none) -> (none, index)
return %out, %idx : none, index
}
// CHECK-LABEL: hw.module @test_control_merge_data(
// CHECK-SAME: %[[VAL_0:.*]]: !dc.value<i2>, %[[VAL_1:.*]]: !dc.value<i2>) -> (out0: !dc.value<i2>, out1: !dc.value<index>) {
// CHECK: hw.module @test_control_merge_data(in %[[VAL_0:.*]] : !dc.value<i2>, in %[[VAL_1:.*]] : !dc.value<i2>, out out0 : !dc.value<i2>, out out1 : !dc.value<index>) {
// CHECK: %[[VAL_2:.*]], %[[VAL_3:.*]] = dc.unpack %[[VAL_0]] : !dc.value<i2>
// CHECK: %[[VAL_4:.*]], %[[VAL_5:.*]] = dc.unpack %[[VAL_1]] : !dc.value<i2>
// CHECK: %[[VAL_6:.*]] = dc.merge %[[VAL_2]], %[[VAL_4]]
@ -170,8 +160,7 @@ handshake.func @test_control_merge_data(%arg0 : i2, %arg1 : i2) -> (i2, index) {
return %out, %idx : i2, index
}
// CHECK-LABEL: hw.module @branch_and_merge(
// CHECK-SAME: %[[VAL_0:.*]]: !dc.value<i1>, %[[VAL_1:.*]]: !dc.token) -> (out0: !dc.token, out1: !dc.value<index>) {
// CHECK: hw.module @branch_and_merge(in %[[VAL_0:.*]] : !dc.value<i1>, in %[[VAL_1:.*]] : !dc.token, out out0 : !dc.token, out out1 : !dc.value<index>) {
// CHECK: %[[VAL_2:.*]] = dc.merge %[[VAL_3:.*]], %[[VAL_4:.*]]
// CHECK: %[[VAL_5:.*]], %[[VAL_6:.*]] = dc.unpack %[[VAL_2]] : !dc.value<i1>
// CHECK: %[[VAL_7:.*]], %[[VAL_8:.*]] = dc.unpack %[[VAL_2]] : !dc.value<i1>

19
test/Conversion/HandshakeToHW/test_buffer.mlir
View File

@ -1,7 +1,11 @@
// RUN: circt-opt -lower-handshake-to-hw --split-input-file %s | FileCheck %s
// CHECK-LABEL: hw.module @handshake_buffer_3slots_seq_1ins_1outs_ctrl(
// CHECK-SAME: %[[VAL_0:.*]]: !esi.channel<i0>, %[[CLOCK:.*]]: !seq.clock, %[[VAL_2:.*]]: i1) -> (out0: !esi.channel<i0>) {
// CHECK-SAME: in %[[VAL_0:.*]] : !esi.channel<i0>,
// CHECK-SAME: in %[[CLOCK:.*]] : !seq.clock,
// CHECK-SAME: in %[[VAL_2:.*]] : i1,
// CHECK-SAME: out out0 : !esi.channel<i0>
// CHECK-SAME: ) {
// CHECK: %[[VAL_3:.*]], %[[VAL_4:.*]] = esi.unwrap.vr %[[VAL_0]], %[[VAL_5:.*]] : i0
// CHECK: %[[VAL_6:.*]], %[[VAL_7:.*]] = esi.wrap.vr %[[VAL_8:.*]], %[[VAL_9:.*]] : i0
// CHECK: %[[VAL_10:.*]] = hw.constant 0 : i0
@ -74,7 +78,11 @@ handshake.func @test_buffer_none(%arg0: none, %arg1: none, ...) -> (none, none)
// -----
// CHECK-LABEL: hw.module @handshake_buffer_in_ui64_out_ui64_2slots_seq(
// CHECK-SAME: %[[VAL_0:.*]]: !esi.channel<i64>, %[[CLOCK:.*]]: !seq.clock, %[[VAL_2:.*]]: i1) -> (out0: !esi.channel<i64>) {
// CHECK-SAME: in %[[VAL_0:.*]] : !esi.channel<i64>,
// CHECK-SAME: in %[[CLOCK:.*]] : !seq.clock,
// CHECK-SAME: in %[[VAL_2:.*]] : i1,
// CHECK-SAME: out out0 : !esi.channel<i64>
// CHECK-SAME: ) {
// CHECK: %[[VAL_3:.*]], %[[VAL_4:.*]] = esi.unwrap.vr %[[VAL_0]], %[[VAL_5:.*]] : i64
// CHECK: %[[VAL_6:.*]], %[[VAL_7:.*]] = esi.wrap.vr %[[VAL_8:.*]], %[[VAL_9:.*]] : i64
// CHECK: %[[VAL_10:.*]] = hw.constant 0 : i64
@ -126,7 +134,12 @@ handshake.func @test_buffer_data(%arg0: index, %arg1: none, ...) -> (index, none
// -----
// CHECK-LABEL: hw.module @handshake_buffer_in_tuple_ui32_ui32_out_tuple_ui32_ui32_2slots_seq(%in0: !esi.channel<!hw.struct<field0: i32, field1: i32>>, %clock: !seq.clock, %reset: i1) -> (out0: !esi.channel<!hw.struct<field0: i32, field1: i32>>) {
// CHECK-LABEL: hw.module @handshake_buffer_in_tuple_ui32_ui32_out_tuple_ui32_ui32_2slots_seq(
// CHECK-SAME: in %in0 : !esi.channel<!hw.struct<field0: i32, field1: i32>>,
// CHECK-SAME: in %clock : !seq.clock,
// CHECK-SAME: in %reset : i1,
// CHECK-SAME: out out0 : !esi.channel<!hw.struct<field0: i32, field1: i32>>
// CHECK-SAME: ) {
// CHECK: %[[CZERO:.*]] = hw.struct_create (%c0_i32, %c0_i32) : !hw.struct<field0: i32, field1: i32>
// CHECK: %data0_reg = seq.compreg %4, %clock, %reset, %[[CZERO]] : !hw.struct<field0: i32, field1: i32>

6
test/Conversion/HandshakeToHW/test_cmerge.mlir
View File

@ -2,8 +2,7 @@
// Test a control merge that is control only.
// CHECK-LABEL: hw.module @handshake_control_merge_out_ui64_2ins_2outs_ctrl(
// CHECK-SAME: %[[VAL_0:.*]]: !esi.channel<i0>, %[[VAL_1:.*]]: !esi.channel<i0>, %[[CLOCK:.*]]: !seq.clock, %[[VAL_3:.*]]: i1) -> (dataOut: !esi.channel<i0>, index: !esi.channel<i64>) {
// CHECK: hw.module @handshake_control_merge_out_ui64_2ins_2outs_ctrl(in %[[VAL_0:.*]] : !esi.channel<i0>, in %[[VAL_1:.*]] : !esi.channel<i0>, in %[[CLOCK:.*]] : !seq.clock, in %[[VAL_3:.*]] : i1, out dataOut : !esi.channel<i0>, out index : !esi.channel<i64>) {
// CHECK: %[[VAL_4:.*]], %[[VAL_5:.*]] = esi.unwrap.vr %[[VAL_0]], %[[VAL_6:.*]] : i0
// CHECK: %[[VAL_7:.*]], %[[VAL_8:.*]] = esi.unwrap.vr %[[VAL_1]], %[[VAL_9:.*]] : i0
// CHECK: %[[VAL_10:.*]], %[[VAL_11:.*]] = esi.wrap.vr %[[VAL_12:.*]], %[[VAL_13:.*]] : i0
@ -59,8 +58,7 @@ handshake.func @test_cmerge(%arg0: none, %arg1: none, %arg2: none, ...) -> (none
// Test a control merge that also outputs the selected input's data.
// CHECK-LABEL: hw.module @handshake_control_merge_in_ui64_ui64_ui64_out_ui64_ui64(
// CHECK-SAME: %[[VAL_0:.*]]: !esi.channel<i64>, %[[VAL_1:.*]]: !esi.channel<i64>, %[[VAL_2:.*]]: !esi.channel<i64>, %[[CLOCK:.*]]: !seq.clock, %[[VAL_4:.*]]: i1) -> (dataOut: !esi.channel<i64>, index: !esi.channel<i64>) {
// CHECK: hw.module @handshake_control_merge_in_ui64_ui64_ui64_out_ui64_ui64(in %[[VAL_0:.*]] : !esi.channel<i64>, in %[[VAL_1:.*]] : !esi.channel<i64>, in %[[VAL_2:.*]] : !esi.channel<i64>, in %[[CLOCK:.*]] : !seq.clock, in %[[VAL_4:.*]] : i1, out dataOut : !esi.channel<i64>, out index : !esi.channel<i64>) {
// CHECK: %[[VAL_5:.*]], %[[VAL_6:.*]] = esi.unwrap.vr %[[VAL_0]], %[[VAL_7:.*]] : i64
// CHECK: %[[VAL_8:.*]], %[[VAL_9:.*]] = esi.unwrap.vr %[[VAL_1]], %[[VAL_10:.*]] : i64
// CHECK: %[[VAL_11:.*]], %[[VAL_12:.*]] = esi.unwrap.vr %[[VAL_2]], %[[VAL_13:.*]] : i64

6
test/Conversion/HandshakeToHW/test_cond_br.mlir
View File

@ -1,7 +1,6 @@
// RUN: circt-opt -split-input-file -lower-handshake-to-hw %s | FileCheck %s
// CHECK-LABEL: hw.module @handshake_cond_br_in_ui1_ui64_out_ui64_ui64(
// CHECK-SAME: %[[VAL_0:.*]]: !esi.channel<i1>, %[[VAL_1:.*]]: !esi.channel<i64>) -> (outTrue: !esi.channel<i64>, outFalse: !esi.channel<i64>) {
// CHECK: hw.module @handshake_cond_br_in_ui1_ui64_out_ui64_ui64(in %[[VAL_0:.*]] : !esi.channel<i1>, in %[[VAL_1:.*]] : !esi.channel<i64>, out outTrue : !esi.channel<i64>, out outFalse : !esi.channel<i64>) {
// CHECK: %[[VAL_2:.*]], %[[VAL_3:.*]] = esi.unwrap.vr %[[VAL_0]], %[[VAL_4:.*]] : i1
// CHECK: %[[VAL_5:.*]], %[[VAL_6:.*]] = esi.unwrap.vr %[[VAL_1]], %[[VAL_4]] : i64
// CHECK: %[[VAL_7:.*]], %[[VAL_8:.*]] = esi.wrap.vr %[[VAL_5]], %[[VAL_9:.*]] : i64
@ -23,8 +22,7 @@ handshake.func @test_conditional_branch(%arg0: i1, %arg1: index) -> (index, inde
// -----
// CHECK-LABEL: hw.module @handshake_cond_br_in_ui1_2ins_2outs_ctrl(
// CHECK-SAME: %[[VAL_0:.*]]: !esi.channel<i1>, %[[VAL_1:.*]]: !esi.channel<i0>) -> (outTrue: !esi.channel<i0>, outFalse: !esi.channel<i0>) {
// CHECK: hw.module @handshake_cond_br_in_ui1_2ins_2outs_ctrl(in %[[VAL_0:.*]] : !esi.channel<i1>, in %[[VAL_1:.*]] : !esi.channel<i0>, out outTrue : !esi.channel<i0>, out outFalse : !esi.channel<i0>) {
// CHECK: %[[VAL_2:.*]], %[[VAL_3:.*]] = esi.unwrap.vr %[[VAL_0]], %[[VAL_4:.*]] : i1
// CHECK: %[[VAL_5:.*]], %[[VAL_6:.*]] = esi.unwrap.vr %[[VAL_1]], %[[VAL_4]] : i0
// CHECK: %[[VAL_7:.*]], %[[VAL_8:.*]] = esi.wrap.vr %[[VAL_5]], %[[VAL_9:.*]] : i0

6
test/Conversion/HandshakeToHW/test_constant.mlir
View File

@ -1,15 +1,13 @@
// RUN: circt-opt -lower-handshake-to-hw -split-input-file %s | FileCheck %s
// CHECK-LABEL: hw.module @handshake_constant_c42_out_ui64(
// CHECK-SAME: %[[VAL_0:.*]]: !esi.channel<i0>) -> (out0: !esi.channel<i64>) {
// CHECK: hw.module @handshake_constant_c42_out_ui64(in %[[VAL_0:.*]] : !esi.channel<i0>, out out0 : !esi.channel<i64>) {
// CHECK: %[[VAL_1:.*]], %[[VAL_2:.*]] = esi.unwrap.vr %[[VAL_0]], %[[VAL_3:.*]] : i0
// CHECK: %[[VAL_4:.*]], %[[VAL_3]] = esi.wrap.vr %[[VAL_5:.*]], %[[VAL_2]] : i64
// CHECK: %[[VAL_5]] = hw.constant 42 : i64
// CHECK: hw.output %[[VAL_4]] : !esi.channel<i64>
// CHECK: }
// CHECK-LABEL: hw.module @handshake_constant_c42_out_ui32(
// CHECK-SAME: %[[VAL_0:.*]]: !esi.channel<i0>) -> (out0: !esi.channel<i32>) {
// CHECK: hw.module @handshake_constant_c42_out_ui32(in %[[VAL_0:.*]] : !esi.channel<i0>, out out0 : !esi.channel<i32>) {
// CHECK: %[[VAL_1:.*]], %[[VAL_2:.*]] = esi.unwrap.vr %[[VAL_0]], %[[VAL_3:.*]] : i0
// CHECK: %[[VAL_4:.*]], %[[VAL_3]] = esi.wrap.vr %[[VAL_5:.*]], %[[VAL_2]] : i32
// CHECK: %[[VAL_5]] = hw.constant 42 : i32

6
test/Conversion/HandshakeToHW/test_fork.mlir
View File

@ -1,7 +1,6 @@
// RUN: circt-opt -lower-handshake-to-hw -split-input-file %s | FileCheck %s
// CHECK-LABEL: hw.module @handshake_fork_1ins_2outs_ctrl(
// CHECK-SAME: %[[VAL_0:.*]]: !esi.channel<i0>, %[[CLOCK:.*]]: !seq.clock, %[[VAL_2:.*]]: i1) -> (out0: !esi.channel<i0>, out1: !esi.channel<i0>) {
// CHECK: hw.module @handshake_fork_1ins_2outs_ctrl(in %[[VAL_0:.*]] : !esi.channel<i0>, in %[[CLOCK:.*]] : !seq.clock, in %[[VAL_2:.*]] : i1, out out0 : !esi.channel<i0>, out out1 : !esi.channel<i0>) {
// CHECK: %[[VAL_3:.*]], %[[VAL_4:.*]] = esi.unwrap.vr %[[VAL_0]], %[[VAL_5:.*]] : i0
// CHECK: %[[VAL_6:.*]], %[[VAL_7:.*]] = esi.wrap.vr %[[VAL_3]], %[[VAL_8:.*]] : i0
// CHECK: %[[VAL_9:.*]], %[[VAL_10:.*]] = esi.wrap.vr %[[VAL_3]], %[[VAL_11:.*]] : i0
@ -32,8 +31,7 @@ handshake.func @test_fork(%arg0: none, %arg1: none, ...) -> (none, none, none) {
// -----
// CHECK-LABEL: hw.module @handshake_fork_in_ui64_out_ui64_ui64(
// CHECK-SAME: %[[VAL_0:.*]]: !esi.channel<i64>, %[[CLOCK:.*]]: !seq.clock, %[[VAL_2:.*]]: i1) -> (out0: !esi.channel<i64>, out1: !esi.channel<i64>) {
// CHECK: hw.module @handshake_fork_in_ui64_out_ui64_ui64(in %[[VAL_0:.*]] : !esi.channel<i64>, in %[[CLOCK:.*]] : !seq.clock, in %[[VAL_2:.*]] : i1, out out0 : !esi.channel<i64>, out out1 : !esi.channel<i64>) {
// CHECK: %[[VAL_3:.*]], %[[VAL_4:.*]] = esi.unwrap.vr %[[VAL_0]], %[[VAL_5:.*]] : i64
// CHECK: %[[VAL_6:.*]], %[[VAL_7:.*]] = esi.wrap.vr %[[VAL_3]], %[[VAL_8:.*]] : i64
// CHECK: %[[VAL_9:.*]], %[[VAL_10:.*]] = esi.wrap.vr %[[VAL_3]], %[[VAL_11:.*]] : i64

18
test/Conversion/HandshakeToHW/test_instance.mlir
View File

@ -1,16 +1,13 @@
// RUN: circt-opt -lower-handshake-to-hw -split-input-file %s | FileCheck %s
// CHECK-LABEL: hw.module @foo(
// CHECK-SAME: %[[VAL_0:.*]]: !esi.channel<i32>,
// CHECK-SAME: %[[CLOCK:.*]]: !seq.clock,
// CHECK-SAME: %[[VAL_2:.*]]: i1) -> (out0: !esi.channel<i32>) {
// CHECK-SAME: in %[[VAL_0:.*]] : !esi.channel<i32>,
// CHECK-SAME: in %[[CLOCK:.*]] : !seq.clock,
// CHECK-SAME: in %[[VAL_2:.*]] : i1, out out0 : !esi.channel<i32>) {
// CHECK: hw.output %[[VAL_0]] : !esi.channel<i32>
// CHECK: }
// CHECK-LABEL: hw.module @bar(
// CHECK-SAME: %[[VAL_0:.*]]: !esi.channel<i32>,
// CHECK-SAME: %[[CLOCK:.*]]: !seq.clock,
// CHECK-SAME: %[[VAL_2:.*]]: i1) -> (out0: !esi.channel<i32>) {
// CHECK: hw.module @bar(in %[[VAL_0:.*]] : !esi.channel<i32>, in %[[CLOCK:.*]] : !seq.clock, in %[[VAL_2:.*]] : i1, out out0 : !esi.channel<i32>) {
// CHECK: %[[VAL_3:.*]] = hw.instance "foo0" @foo(in: %[[VAL_0]]: !esi.channel<i32>, clock: %[[CLOCK]]: !seq.clock, reset: %[[VAL_2]]: i1) -> (out0: !esi.channel<i32>)
// CHECK: hw.output %[[VAL_3]] : !esi.channel<i32>
// CHECK: }
@ -25,12 +22,9 @@ handshake.func @bar(%in : i32) -> (i32) {
// -----
// CHECK: hw.module.extern @foo(%[[VAL_4:.*]]: !esi.channel<i32>, %[[CLOCK:.*]]: !seq.clock, %[[VAL_6:.*]]: i1) -> (out0: !esi.channel<i32>)
// CHECK: hw.module.extern @foo(in %[[VAL_4:.*]] : !esi.channel<i32>, in %[[CLOCK:.*]] : !seq.clock, in %[[VAL_6:.*]] : i1, out out0 : !esi.channel<i32>)
// CHECK-LABEL: hw.module @bar(
// CHECK-SAME: %[[VAL_4]]: !esi.channel<i32>,
// CHECK-SAME: %[[CLOCK]]: !seq.clock,
// CHECK-SAME: %[[VAL_6]]: i1) -> (out0: !esi.channel<i32>) {
// CHECK: hw.module @bar(in %[[VAL_4]] : !esi.channel<i32>, in %[[CLOCK]] : !seq.clock, in %[[VAL_6]] : i1, out out0 : !esi.channel<i32>) {
// CHECK: %[[VAL_0:.*]] = hw.instance "foo0" @foo(in: %[[VAL_4]]: !esi.channel<i32>, clock: %[[CLOCK]]: !seq.clock, reset: %[[VAL_6]]: i1) -> (out0: !esi.channel<i32>)
// CHECK: hw.output %[[VAL_0]] : !esi.channel<i32>
// CHECK: }

9
test/Conversion/HandshakeToHW/test_join.mlir
View File

@ -1,8 +1,6 @@
// RUN: circt-opt -lower-handshake-to-hw -split-input-file %s | FileCheck %s
// CHECK-LABEL: hw.module @handshake_join_2ins_1outs_ctrl(
// CHECK-SAME: %[[VAL_0:.*]]: !esi.channel<i0>,
// CHECK-SAME: %[[VAL_1:.*]]: !esi.channel<i0>) -> (out0: !esi.channel<i0>) {
// CHECK: hw.module @handshake_join_2ins_1outs_ctrl(in %[[VAL_0:.*]] : !esi.channel<i0>, in %[[VAL_1:.*]] : !esi.channel<i0>, out out0 : !esi.channel<i0>) {
// CHECK: %[[VAL_2:.*]], %[[VAL_3:.*]] = esi.unwrap.vr %[[VAL_0]], %[[VAL_4:.*]] : i0
// CHECK: %[[VAL_5:.*]], %[[VAL_6:.*]] = esi.unwrap.vr %[[VAL_1]], %[[VAL_4]] : i0
// CHECK: %[[VAL_7:.*]], %[[VAL_8:.*]] = esi.wrap.vr %[[VAL_9:.*]], %[[VAL_10:.*]] : i0
@ -19,10 +17,7 @@ handshake.func @test_join(%arg0: none, %arg1: none, %arg2: none, ...) -> (none,
// -----
// CHECK-LABEL: hw.module @handshake_join_in_ui32_ui1_3ins_1outs_ctrl(
// CHECK-SAME: %[[VAL_0:.*]]: !esi.channel<i32>,
// CHECK-SAME: %[[VAL_1:.*]]: !esi.channel<i1>,
// CHECK-SAME: %[[VAL_2:.*]]: !esi.channel<i0>) -> (out0: !esi.channel<i0>) {
// CHECK: hw.module @handshake_join_in_ui32_ui1_3ins_1outs_ctrl(in %[[VAL_0:.*]] : !esi.channel<i32>, in %[[VAL_1:.*]] : !esi.channel<i1>, in %[[VAL_2:.*]] : !esi.channel<i0>, out out0 : !esi.channel<i0>) {
// CHECK: %[[VAL_3:.*]], %[[VAL_4:.*]] = esi.unwrap.vr %[[VAL_0]], %[[VAL_5:.*]] : i32
// CHECK: %[[VAL_6:.*]], %[[VAL_7:.*]] = esi.unwrap.vr %[[VAL_1]], %[[VAL_5]] : i1
// CHECK: %[[VAL_8:.*]], %[[VAL_9:.*]] = esi.unwrap.vr %[[VAL_2]], %[[VAL_5]] : i0

6
test/Conversion/HandshakeToHW/test_mux.mlir
View File

@ -1,7 +1,6 @@
// RUN: circt-opt -lower-handshake-to-hw -split-input-file %s | FileCheck %s
// CHECK-LABEL: hw.module @handshake_mux_in_ui64_ui64_ui64_out_ui64(
// CHECK-SAME: %[[VAL_0:.*]]: !esi.channel<i64>, %[[VAL_1:.*]]: !esi.channel<i64>, %[[VAL_2:.*]]: !esi.channel<i64>) -> (out0: !esi.channel<i64>) {
// CHECK: hw.module @handshake_mux_in_ui64_ui64_ui64_out_ui64(in %[[VAL_0:.*]] : !esi.channel<i64>, in %[[VAL_1:.*]] : !esi.channel<i64>, in %[[VAL_2:.*]] : !esi.channel<i64>, out out0 : !esi.channel<i64>) {
// CHECK: %[[VAL_3:.*]], %[[VAL_4:.*]] = esi.unwrap.vr %[[VAL_0]], %[[VAL_5:.*]] : i64
// CHECK: %[[VAL_6:.*]], %[[VAL_7:.*]] = esi.unwrap.vr %[[VAL_1]], %[[VAL_8:.*]] : i64
// CHECK: %[[VAL_9:.*]], %[[VAL_10:.*]] = esi.unwrap.vr %[[VAL_2]], %[[VAL_11:.*]] : i64
@ -29,8 +28,7 @@ handshake.func @test_mux(%arg0: index, %arg1: index, %arg2: index, %arg3: none,
// -----
// CHECK-LABEL: hw.module @handshake_mux_in_ui64_ui64_ui64_ui64_out_ui64(
// CHECK-SAME: %[[VAL_0:.*]]: !esi.channel<i64>, %[[VAL_1:.*]]: !esi.channel<i64>, %[[VAL_2:.*]]: !esi.channel<i64>, %[[VAL_3:.*]]: !esi.channel<i64>) -> (out0: !esi.channel<i64>) {
// CHECK: hw.module @handshake_mux_in_ui64_ui64_ui64_ui64_out_ui64(in %[[VAL_0:.*]] : !esi.channel<i64>, in %[[VAL_1:.*]] : !esi.channel<i64>, in %[[VAL_2:.*]] : !esi.channel<i64>, in %[[VAL_3:.*]] : !esi.channel<i64>, out out0 : !esi.channel<i64>) {
// CHECK: %[[VAL_4:.*]], %[[VAL_5:.*]] = esi.unwrap.vr %[[VAL_0]], %[[VAL_6:.*]] : i64
// CHECK: %[[VAL_7:.*]], %[[VAL_8:.*]] = esi.unwrap.vr %[[VAL_1]], %[[VAL_9:.*]] : i64
// CHECK: %[[VAL_10:.*]], %[[VAL_11:.*]] = esi.unwrap.vr %[[VAL_2]], %[[VAL_12:.*]] : i64

13
test/Conversion/HandshakeToHW/test_pack_unpack.mlir
View File

@ -1,8 +1,9 @@
// RUN: circt-opt -lower-handshake-to-hw -split-input-file %s | FileCheck %s
// CHECK-LABEL: hw.module @handshake_pack_in_ui64_ui32_out_tuple_ui64_ui32(
// CHECK-SAME: %[[VAL_0:.*]]: !esi.channel<i64>,
// CHECK-SAME: %[[VAL_1:.*]]: !esi.channel<i32>) -> (out0: !esi.channel<!hw.struct<field0: i64, field1: i32>>) {
// CHECK-SAME: in %[[VAL_0:.*]] : !esi.channel<i64>,
// CHECK-SAME: in %[[VAL_1:.*]] : !esi.channel<i32>,
// CHECK-SAME: out out0 : !esi.channel<!hw.struct<field0: i64, field1: i32>>) {
// CHECK: %[[VAL_2:.*]], %[[VAL_3:.*]] = esi.unwrap.vr %[[VAL_0]], %[[VAL_4:.*]] : i64
// CHECK: %[[VAL_5:.*]], %[[VAL_6:.*]] = esi.unwrap.vr %[[VAL_1]], %[[VAL_4]] : i32
// CHECK: %[[VAL_7:.*]], %[[VAL_8:.*]] = esi.wrap.vr %[[VAL_9:.*]], %[[VAL_10:.*]] : !hw.struct<field0: i64, field1: i32>
@ -20,9 +21,11 @@ handshake.func @test_pack(%arg0: i64, %arg1: i32, %ctrl: none, ...) -> (tuple<i6
// -----
// CHECK-LABEL: hw.module @handshake_unpack_in_tuple_ui64_ui32_out_ui64_ui32(
// CHECK-SAME: %[[VAL_0:.*]]: !esi.channel<!hw.struct<field0: i64, field1: i32>>,
// CHECK-SAME: %[[CLOCK:.*]]: !seq.clock,
// CHECK-SAME: %[[VAL_2:.*]]: i1) -> (out0: !esi.channel<i64>, out1: !esi.channel<i32>) {
// CHECK-SAME: in %[[VAL_0:.*]] : !esi.channel<!hw.struct<field0: i64, field1: i32>>,
// CHECK-SAME: in %[[CLOCK:.*]] : !seq.clock,
// CHECK-SAME: in %[[VAL_2:.*]] : i1,
// CHECK-SAME: out out0 : !esi.channel<i64>,
// CHECK-SAME: out out1 : !esi.channel<i32>) {
// CHECK: %[[VAL_3:.*]], %[[VAL_4:.*]] = esi.unwrap.vr %[[VAL_0]], %[[VAL_5:.*]] : !hw.struct<field0: i64, field1: i32>
// CHECK: %[[VAL_6:.*]], %[[VAL_7:.*]] = esi.wrap.vr %[[VAL_8:.*]], %[[VAL_9:.*]] : i64
// CHECK: %[[VAL_10:.*]], %[[VAL_11:.*]] = esi.wrap.vr %[[VAL_12:.*]], %[[VAL_13:.*]] : i32

7
test/Conversion/HandshakeToHW/test_select.mlir
View File

@ -1,12 +1,9 @@
// RUN: circt-opt -lower-handshake-to-hw -split-input-file %s | FileCheck %s
// CHECK-LABEL: hw.module @arith_select_in_ui1_ui32_ui32_out_ui32(
// CHECK-SAME: %[[VAL_0:.*]]: !esi.channel<i1>,
// CHECK-SAME: %[[VAL_1:.*]]: !esi.channel<i32>,
// CHECK-SAME: %[[VAL_2:.*]]: !esi.channel<i32>) -> (out0: !esi.channel<i32>) {
// CHECK: hw.module @arith_select_in_ui1_ui32_ui32_out_ui32(in %[[VAL_0:.*]] : !esi.channel<i1>, in %[[VAL_1:.*]] : !esi.channel<i32>, in %[[VAL_2:.*]] : !esi.channel<i32>, out out0 : !esi.channel<i32>) {
// CHECK: %[[VAL_3:.*]], %[[VAL_4:.*]] = esi.unwrap.vr %[[VAL_0]], %[[VAL_5:.*]] : i1
// CHECK: %[[VAL_6:.*]], %[[VAL_7:.*]] = esi.unwrap.vr %[[VAL_1]], %[[VAL_5]] : i32
// CHECK: %[[VAL_8:.*]], %[[VAL_9:.*]] = esi.unwrap.vr %[[VAL_2]], %[[VAL_5]] : i32
// CHECK: %[[VAL_8:.*]], %[[VAL_9:.*]] = esi.unwrap.vr %[[VAL_2]], %[[VAL_5]] : i32
// CHECK: %[[VAL_10:.*]], %[[VAL_11:.*]] = esi.wrap.vr %[[VAL_12:.*]], %[[VAL_13:.*]] : i32
// CHECK: %[[VAL_13]] = comb.and %[[VAL_4]], %[[VAL_7]], %[[VAL_9]] : i1
// CHECK: %[[VAL_5]] = comb.and %[[VAL_11]], %[[VAL_13]] : i1

5
test/Conversion/HandshakeToHW/test_simple_loop.mlir
View File

@ -1,9 +1,6 @@
// RUN: circt-opt -lower-handshake-to-hw -split-input-file %s | FileCheck %s
// CHECK-LABEL: hw.module @main(
// CHECK-SAME: %[[VAL_0:.*]]: !esi.channel<i0>,
// CHECK-SAME: %[[CLOCK:.*]]: !seq.clock,
// CHECK-SAME: %[[VAL_2:.*]]: i1) -> (out0: !esi.channel<i64>, outCtrl: !esi.channel<i0>) {
// CHECK: hw.module @main(in %[[VAL_0:.*]] : !esi.channel<i0>, in %[[CLOCK:.*]] : !seq.clock, in %[[VAL_2:.*]] : i1, out out0 : !esi.channel<i64>, out outCtrl : !esi.channel<i0>) {
// CHECK: %[[VAL_3:.*]], %[[VAL_4:.*]], %[[VAL_5:.*]], %[[VAL_6:.*]] = hw.instance "handshake_fork0" @handshake_fork_1ins_4outs_ctrl(in0: %[[VAL_0]]: !esi.channel<i0>, clock: %[[CLOCK]]: !seq.clock, reset: %[[VAL_2]]: i1) -> (out0: !esi.channel<i0>, out1: !esi.channel<i0>, out2: !esi.channel<i0>, out3: !esi.channel<i0>)
// CHECK: %[[VAL_7:.*]] = hw.instance "handshake_constant0" @handshake_constant_c1_out_ui64(ctrl: %[[VAL_5]]: !esi.channel<i0>) -> (out0: !esi.channel<i64>)
// CHECK: %[[VAL_8:.*]] = hw.instance "handshake_constant1" @handshake_constant_c42_out_ui64(ctrl: %[[VAL_4]]: !esi.channel<i0>) -> (out0: !esi.channel<i64>)

5
test/Conversion/HandshakeToHW/test_sink.mlir
View File

@ -1,13 +1,12 @@
// RUN: circt-opt -lower-handshake-to-hw %s | FileCheck %s
// CHECK-LABEL: hw.module @handshake_sink_in_ui64(
// CHECK-SAME: %[[VAL_0:.*]]: !esi.channel<i64>) {
// CHECK: hw.module @handshake_sink_in_ui64(in %[[VAL_0:.*]] : !esi.channel<i64>) {
// CHECK: %[[VAL_1:.*]], %[[VAL_2:.*]] = esi.unwrap.vr %[[VAL_0]], %[[VAL_3:.*]] : i64
// CHECK: %[[VAL_3]] = hw.constant true
// CHECK: hw.output
// CHECK: }
handshake.func @test_sink(%arg0: index) -> () {
handshake.func @test_sink(%arg0: index) {
sink %arg0 : index
return
}

2
test/Conversion/HandshakeToHW/test_source.mlir
View File

@ -1,6 +1,6 @@
// RUN: circt-opt -lower-handshake-to-hw %s | FileCheck %s
// CHECK-LABEL: hw.module @handshake_source_0ins_1outs_ctrl() -> (out0: !esi.channel<i0>) {
// CHECK-LABEL: hw.module @handshake_source_0ins_1outs_ctrl(out out0 : !esi.channel<i0>) {
// CHECK: %[[VAL_0:.*]], %[[VAL_1:.*]] = esi.wrap.vr %[[VAL_2:.*]], %[[VAL_3:.*]] : i0
// CHECK: %[[VAL_3]] = hw.constant true
// CHECK: %[[VAL_2]] = hw.constant 0 : i0

2
test/Conversion/HandshakeToHW/test_struct_create.mlir
View File

@ -1,7 +1,7 @@
// RUN: circt-opt -lower-handshake-to-hw %s | FileCheck %s
// CHECK-LABEL: hw.module @hw_struct_create_in_ui4_ui32_out_struct_address_ui4_data_ui32(
// CHECK-SAME: %[[VAL_0:.*]]: !esi.channel<i4>, %[[VAL_1:.*]]: !esi.channel<i32>) -> (out0: !esi.channel<!hw.struct<address: i4, data: i32>>) {
// CHECK-SAME: in %[[VAL_0:.*]] : !esi.channel<i4>, in %[[VAL_1:.*]] : !esi.channel<i32>, out out0 : !esi.channel<!hw.struct<address: i4, data: i32>>) {
// CHECK: %[[VAL_2:.*]], %[[VAL_3:.*]] = esi.unwrap.vr %[[VAL_0]], %[[VAL_4:.*]] : i4
// CHECK: %[[VAL_5:.*]], %[[VAL_6:.*]] = esi.unwrap.vr %[[VAL_1]], %[[VAL_4]] : i32
// CHECK: %[[VAL_7:.*]], %[[VAL_8:.*]] = esi.wrap.vr %[[VAL_9:.*]], %[[VAL_10:.*]] : !hw.struct<address: i4, data: i32>

3
test/Conversion/HandshakeToHW/test_sync.mlir
View File

@ -1,7 +1,6 @@
// RUN: circt-opt -lower-handshake-to-hw -split-input-file %s | FileCheck %s
// CHECK-LABEL: hw.module @handshake_sync_in_ui32_out_ui32(
// CHECK-SAME: %[[VAL_0:.*]]: !esi.channel<i0>, %[[VAL_1:.*]]: !esi.channel<i32>, %[[CLOCK:.*]]: !seq.clock, %[[VAL_3:.*]]: i1) -> (out0: !esi.channel<i0>, out1: !esi.channel<i32>) {
// CHECK: hw.module @handshake_sync_in_ui32_out_ui32(in %[[VAL_0:.*]] : !esi.channel<i0>, in %[[VAL_1:.*]] : !esi.channel<i32>, in %[[CLOCK:.*]] : !seq.clock, in %[[VAL_3:.*]] : i1, out out0 : !esi.channel<i0>, out out1 : !esi.channel<i32>) {
// CHECK: %[[VAL_4:.*]], %[[VAL_5:.*]] = esi.unwrap.vr %[[VAL_0]], %[[VAL_6:.*]] : i0
// CHECK: %[[VAL_7:.*]], %[[VAL_8:.*]] = esi.unwrap.vr %[[VAL_1]], %[[VAL_6]] : i32
// CHECK: %[[VAL_9:.*]], %[[VAL_10:.*]] = esi.wrap.vr %[[VAL_4]], %[[VAL_11:.*]] : i0

40
test/Conversion/PipelineToHW/test_basic.mlir
View File

@ -1,18 +1,16 @@
// RUN: circt-opt --lower-pipeline-to-hw %s | FileCheck %s
// CHECK-LABEL: hw.module @testBasic(
// CHECK-SAME: %[[VAL_0:.*]]: i1, %[[CLOCK:.*]]: !seq.clock, %[[VAL_2:.*]]: i1) -> (out: i1) {
// CHECK: hw.module @testBasic(in %[[VAL_0:.*]] : i1, in %[[CLOCK:.*]] : !seq.clock, in %[[VAL_2:.*]] : i1, out out : i1) {
// CHECK: hw.output %[[VAL_0]] : i1
// CHECK: }
hw.module @testBasic(%arg0: i1, %clk: !seq.clock, %rst: i1) -> (out: i1) {
hw.module @testBasic(in %arg0: i1, in %clk: !seq.clock, in %rst: i1, out out : i1) {
%0:2 = pipeline.scheduled(%a0 : i1 = %arg0) clock(%clk) reset(%rst) go(%arg0) entryEn(%s0_enable) -> (out : i1) {
pipeline.return %a0 : i1
}
hw.output %0#0 : i1
}
// CHECK-LABEL: hw.module @testLatency1(
// CHECK-SAME: %[[VAL_0:.*]]: i32, %[[VAL_1:.*]]: i32, %[[VAL_2:.*]]: i1, %[[CLOCK:.*]]: !seq.clock, %[[VAL_4:.*]]: i1) -> (out: i32, done: i1) {
// CHECK: hw.module @testLatency1(in %[[VAL_0:.*]] : i32, in %[[VAL_1:.*]] : i32, in %[[VAL_2:.*]] : i1, in %[[CLOCK:.*]] : !seq.clock, in %[[VAL_4:.*]] : i1, out out : i32, out done : i1) {
// CHECK: %[[VAL_5:.*]] = comb.add %[[VAL_0]], %[[VAL_0]] : i32
// CHECK: %[[VAL_6:.*]] = hw.constant false
// CHECK: %[[VAL_7:.*]] = seq.compreg sym @p0_stage1_enable %[[VAL_2]], %[[CLOCK]], %[[VAL_4]], %[[VAL_6]] : i1
@ -26,7 +24,7 @@ hw.module @testBasic(%arg0: i1, %clk: !seq.clock, %rst: i1) -> (out: i1) {
// CHECK: %[[VAL_15:.*]] = seq.compreg sym @p0_stage4_enable %[[VAL_12]], %[[CLOCK]], %[[VAL_4]], %[[VAL_14]] : i1
// CHECK: hw.output %[[VAL_13]], %[[VAL_15]] : i32, i1
// CHECK: }
hw.module @testLatency1(%arg0: i32, %arg1: i32, %go: i1, %clk: !seq.clock, %rst: i1) -> (out: i32, done: i1) {
hw.module @testLatency1(in %arg0: i32, in %arg1: i32, in %go: i1, in %clk: !seq.clock, in %rst: i1, out out: i32, out done: i1) {
%out, %done = pipeline.scheduled(%a0 : i32 = %arg0) clock(%clk) reset(%rst) go(%go) entryEn(%s0_enable) -> (out: i32) {
%1 = pipeline.latency 2 -> (i32) {
%6 = comb.add %a0, %a0 : i32
@ -45,8 +43,7 @@ hw.module @testLatency1(%arg0: i32, %arg1: i32, %go: i1, %clk: !seq.clock, %rst:
hw.output %out, %done : i32, i1
}
// CHECK-LABEL: hw.module @testSingle(
// CHECK-SAME: %[[VAL_0:.*]]: i32, %[[VAL_1:.*]]: i32, %[[VAL_2:.*]]: i1, %[[CLOCK:.*]]: !seq.clock, %[[VAL_4:.*]]: i1) -> (out0: i32, out1: i1) {
// CHECK: hw.module @testSingle(in %[[VAL_0:.*]] : i32, in %[[VAL_1:.*]] : i32, in %[[VAL_2:.*]] : i1, in %[[CLOCK:.*]] : !seq.clock, in %[[VAL_4:.*]] : i1, out out0 : i32, out out1 : i1) {
// CHECK: %[[VAL_5:.*]] = comb.sub %[[VAL_0]], %[[VAL_1]] : i32
// CHECK: %[[VAL_6:.*]] = seq.compreg sym @p0_stage0_reg0 %[[VAL_5]], %[[CLOCK]] : i32
// CHECK: %[[VAL_7:.*]] = seq.compreg sym @p0_stage0_reg1 %[[VAL_0]], %[[CLOCK]] : i32
@ -55,7 +52,7 @@ hw.module @testLatency1(%arg0: i32, %arg1: i32, %go: i1, %clk: !seq.clock, %rst:
// CHECK: %[[VAL_10:.*]] = comb.add %[[VAL_6]], %[[VAL_7]] : i32
// CHECK: hw.output %[[VAL_10]], %[[VAL_9]] : i32, i1
// CHECK: }
hw.module @testSingle(%arg0: i32, %arg1: i32, %go: i1, %clk: !seq.clock, %rst: i1) -> (out0: i32, out1: i1) {
hw.module @testSingle(in %arg0: i32, in %arg1: i32, in %go: i1, in %clk: !seq.clock, in %rst: i1, out out0: i32, out out1: i1) {
%0:2 = pipeline.scheduled(%a0 : i32 = %arg0, %a1 : i32 = %arg1) clock(%clk) reset(%rst) go(%go) entryEn(%s0_enable) -> (out: i32){
%1 = comb.sub %a0,%a1 : i32
pipeline.stage ^bb1 regs(%1 : i32, %a0 : i32)
@ -66,8 +63,7 @@ hw.module @testSingle(%arg0: i32, %arg1: i32, %go: i1, %clk: !seq.clock, %rst: i
hw.output %0#0, %0#1 : i32, i1
}
// CHECK-LABEL: hw.module @testMultiple(
// CHECK-SAME: %[[VAL_0:.*]]: i32, %[[VAL_1:.*]]: i32, %[[VAL_2:.*]]: i1, %[[CLOCK:.*]]: !seq.clock, %[[VAL_4:.*]]: i1) -> (out0: i32, out1: i1) {
// CHECK: hw.module @testMultiple(in %[[VAL_0:.*]] : i32, in %[[VAL_1:.*]] : i32, in %[[VAL_2:.*]] : i1, in %[[CLOCK:.*]] : !seq.clock, in %[[VAL_4:.*]] : i1, out out0 : i32, out out1 : i1) {
// CHECK: %[[VAL_5:.*]] = comb.sub %[[VAL_0]], %[[VAL_1]] : i32
// CHECK: %[[VAL_6:.*]] = seq.compreg sym @p0_stage0_reg0 %[[VAL_5]], %[[CLOCK]] : i32
// CHECK: %[[VAL_7:.*]] = seq.compreg sym @p0_stage0_reg1 %[[VAL_0]], %[[CLOCK]] : i32
@ -92,7 +88,7 @@ hw.module @testSingle(%arg0: i32, %arg1: i32, %go: i1, %clk: !seq.clock, %rst: i
// CHECK: %[[VAL_26:.*]] = comb.mul %[[VAL_22]], %[[VAL_23]] : i32
// CHECK: hw.output %[[VAL_15]], %[[VAL_14]] : i32, i1
// CHECK: }
hw.module @testMultiple(%arg0: i32, %arg1: i32, %go: i1, %clk: !seq.clock, %rst: i1) -> (out0: i32, out1: i1) {
hw.module @testMultiple(in %arg0: i32, in %arg1: i32, in %go: i1, in %clk: !seq.clock, in %rst: i1, out out0: i32, out out1: i1) {
%0:2 = pipeline.scheduled(%a0 : i32 = %arg0, %a1 : i32 = %arg1) clock(%clk) reset(%rst) go(%go) entryEn(%s0_enable) -> (out: i32){
%1 = comb.sub %a0,%a1 : i32
pipeline.stage ^bb1 regs(%1 : i32, %a0 : i32)
@ -118,8 +114,7 @@ hw.module @testMultiple(%arg0: i32, %arg1: i32, %go: i1, %clk: !seq.clock, %rst:
hw.output %0#0, %0#1 : i32, i1
}
// CHECK-LABEL: hw.module @testSingleWithExt(
// CHECK-SAME: %[[VAL_0:.*]]: i32, %[[VAL_1:.*]]: i32, %[[VAL_2:.*]]: i1, %[[CLOCK:.*]]: !seq.clock, %[[VAL_4:.*]]: i1) -> (out0: i32, out1: i32) {
// CHECK: hw.module @testSingleWithExt(in %[[VAL_0:.*]] : i32, in %[[VAL_1:.*]] : i32, in %[[VAL_2:.*]] : i1, in %[[CLOCK:.*]] : !seq.clock, in %[[VAL_4:.*]] : i1, out out0 : i32, out out1 : i32) {
// CHECK: %[[VAL_5:.*]] = hw.constant true
// CHECK: %[[VAL_6:.*]] = comb.sub %[[VAL_0]], %[[VAL_0]] : i32
// CHECK: %[[VAL_7:.*]] = seq.compreg sym @p0_stage0_reg0 %[[VAL_6]], %[[CLOCK]] : i32
@ -131,7 +126,7 @@ hw.module @testMultiple(%arg0: i32, %arg1: i32, %go: i1, %clk: !seq.clock, %rst:
// CHECK: %[[VAL_13:.*]] = seq.compreg sym @p0_stage2_enable %[[VAL_9]], %[[CLOCK]], %[[VAL_4]], %[[VAL_12]] : i1
// CHECK: hw.output %[[VAL_11]], %[[VAL_1]] : i32, i32
// CHECK: }
hw.module @testSingleWithExt(%arg0: i32, %ext1: i32, %go : i1, %clk: !seq.clock, %rst: i1) -> (out0: i32, out1: i32) {
hw.module @testSingleWithExt(in %arg0: i32, in %ext1: i32, in %go : i1, in %clk: !seq.clock, in %rst: i1, out out0: i32, out out1: i32) {
%0:3 = pipeline.scheduled(%a0 : i32 = %arg0, %a1 : i32 = %arg0) clock(%clk) reset(%rst) go(%go) entryEn(%s0_enable) -> (out0: i32, out1: i32) {
%true = hw.constant true
%1 = comb.sub %a0, %a0 : i32
@ -149,8 +144,7 @@ hw.module @testSingleWithExt(%arg0: i32, %ext1: i32, %go : i1, %clk: !seq.clock,
hw.output %0#0, %0#1 : i32, i32
}
// CHECK-LABEL: hw.module @testControlUsage(
// CHECK-SAME: %[[VAL_0:.*]]: i32, %[[VAL_1:.*]]: i1, %[[CLOCK:.*]]: !seq.clock, %[[VAL_3:.*]]: i1) -> (out0: i32) {
// CHECK: hw.module @testControlUsage(in %[[VAL_0:.*]] : i32, in %[[VAL_1:.*]] : i1, in %[[CLOCK:.*]] : !seq.clock, in %[[VAL_3:.*]] : i1, out out0 : i32) {
// CHECK: %[[VAL_4:.*]] = hw.constant 0 : i32
// CHECK: %[[VAL_5:.*]] = sv.wire : !hw.inout<i32>
// CHECK: %[[VAL_6:.*]] = sv.read_inout %[[VAL_5]] : !hw.inout<i32>
@ -175,7 +169,7 @@ hw.module @testSingleWithExt(%arg0: i32, %ext1: i32, %go : i1, %clk: !seq.clock,
// CHECK: sv.assign %[[VAL_19]], %[[VAL_22]] : i32
// CHECK: hw.output %[[VAL_22]] : i32
// CHECK: }
hw.module @testControlUsage(%arg0: i32, %go : i1, %clk: !seq.clock, %rst: i1) -> (out0: i32) {
hw.module @testControlUsage(in %arg0: i32, in %go : i1, in %clk: !seq.clock, in %rst: i1, out out0: i32) {
%0:2 = pipeline.scheduled(%a0 : i32 = %arg0) clock(%clk) reset(%rst) go(%go) entryEn(%s0_enable) -> (out: i32) {
%zero = hw.constant 0 : i32
%reg_out_wire = sv.wire : !hw.inout<i32>
@ -207,8 +201,7 @@ hw.module @testControlUsage(%arg0: i32, %go : i1, %clk: !seq.clock, %rst: i1) ->
// -----
// CHECK-LABEL: hw.module @testWithStall(
// CHECK-SAME: %[[VAL_0:.*]]: i32, %[[VAL_1:.*]]: i1, %[[VAL_2:.*]]: i1, %[[CLOCK:.*]]: !seq.clock, %[[VAL_4:.*]]: i1) -> (out0: i32, out1: i1) {
// CHECK: hw.module @testWithStall(in %[[VAL_0:.*]] : i32, in %[[VAL_1:.*]] : i1, in %[[VAL_2:.*]] : i1, in %[[CLOCK:.*]] : !seq.clock, in %[[VAL_4:.*]] : i1, out out0 : i32, out out1 : i1) {
// CHECK: %[[VAL_5:.*]] = hw.constant true
// CHECK: %[[VAL_6:.*]] = comb.xor %[[VAL_2]], %[[VAL_5]] : i1
// CHECK: %[[VAL_7:.*]] = comb.and %[[VAL_1]], %[[VAL_6]]
@ -222,7 +215,7 @@ hw.module @testControlUsage(%arg0: i32, %go : i1, %clk: !seq.clock, %rst: i1) ->
// CHECK: %[[VAL_15:.*]] = comb.and %[[VAL_12]], %[[VAL_14]]
// CHECK: hw.output %[[VAL_8]], %[[VAL_15]] : i32, i1
// CHECK: }
hw.module @testWithStall(%arg0: i32, %go: i1, %stall : i1, %clk: !seq.clock, %rst: i1) -> (out0: i32, out1: i1) {
hw.module @testWithStall(in %arg0: i32, in %go: i1, in %stall : i1, in %clk: !seq.clock, in %rst: i1, out out0: i32, out out1: i1) {
%0:2 = pipeline.scheduled(%a0 : i32 = %arg0) stall(%stall) clock(%clk) reset(%rst) go(%go) entryEn(%s0_enable) -> (out: i32) {
pipeline.stage ^bb1 regs(%a0 : i32)
^bb1(%1: i32, %s1_enable : i1): // pred: ^bb1
@ -233,8 +226,7 @@ hw.module @testWithStall(%arg0: i32, %go: i1, %stall : i1, %clk: !seq.clock, %rs
// -----
// CHECK-LABEL: hw.module @testStallability(
// CHECK-SAME: %[[VAL_0:.*]]: i32, %[[VAL_1:.*]]: i1, %[[CLOCK:.*]]: !seq.clock, %[[VAL_3:.*]]: i1, %[[VAL_4:.*]]: i1) -> (out: i32) {
// CHECK: hw.module @testStallability(in %[[VAL_0:.*]] : i32, in %[[VAL_1:.*]] : i1, in %[[CLOCK:.*]] : !seq.clock, in %[[VAL_3:.*]] : i1, in %[[VAL_4:.*]] : i1, out out : i32) {
// CHECK: %[[VAL_5:.*]] = hw.constant true
// CHECK: %[[VAL_6:.*]] = comb.xor %[[VAL_4]], %[[VAL_5]] : i1
// CHECK: %[[VAL_7:.*]] = comb.and %[[VAL_1]], %[[VAL_6]]
@ -264,7 +256,7 @@ hw.module @testWithStall(%arg0: i32, %go: i1, %stall : i1, %clk: !seq.clock, %rs
// CHECK: hw.output %[[VAL_21]] : i32
// CHECK: }
hw.module @testStallability(%arg0: i32, %go: i1, %clk: !seq.clock, %rst: i1, %stall: i1) -> (out: i32) {
hw.module @testStallability(in %arg0: i32, in %go: i1, in %clk: !seq.clock, in %rst: i1, in %stall: i1, out out: i32) {
%out, %done = pipeline.scheduled "MyPipeline"(%a0 : i32 = %arg0)
stall(%stall) clock(%clk) reset(%rst) go(%go) entryEn(%s0_enable)
{stallability = [true, false, true]} -> (out : i32) {

5
test/Conversion/PipelineToHW/test_ce.mlir
View File

@ -1,8 +1,7 @@
// RUN: circt-opt --lower-pipeline-to-hw="clock-gate-regs" %s | FileCheck %s
// CHECK-LABEL: hw.module @testSingle(
// CHECK-SAME: %[[VAL_0:.*]]: i32, %[[VAL_1:.*]]: i32, %[[VAL_2:.*]]: i1, %[[CLOCK:.*]]: !seq.clock, %[[VAL_4:.*]]: i1) -> (out0: i32, out1: i1) {
// CHECK: hw.module @testSingle(in %[[VAL_0:.*]] : i32, in %[[VAL_1:.*]] : i32, in %[[VAL_2:.*]] : i1, in %[[CLOCK:.*]] : !seq.clock, in %[[VAL_4:.*]] : i1, out out0 : i32, out out1 : i1) {
// CHECK: %[[VAL_5:.*]] = comb.sub %[[VAL_0]], %[[VAL_1]] : i32
// CHECK: %[[VAL_6:.*]] = seq.clock_gate %[[CLOCK]], %[[VAL_2]]
// CHECK: %[[VAL_7:.*]] = seq.compreg sym @p0_stage0_reg0 %[[VAL_5]], %[[VAL_6]] : i32
@ -13,7 +12,7 @@
// CHECK: hw.output %[[VAL_11]], %[[VAL_10]] : i32, i1
// CHECK: }
hw.module @testSingle(%arg0: i32, %arg1: i32, %go: i1, %clk: !seq.clock, %rst: i1) -> (out0: i32, out1: i1) {
hw.module @testSingle(in %arg0: i32, in %arg1: i32, in %go: i1, in %clk: !seq.clock, in %rst: i1, out out0: i32, out out1: i1) {
%0:2 = pipeline.scheduled(%a0 : i32 = %arg0, %a1 : i32 = %arg1) clock(%clk) reset(%rst) go(%go) entryEn(%s0_enable) -> (out: i32){
%1 = comb.sub %a0,%a1 : i32
pipeline.stage ^bb1 regs(%1 : i32, %a0 : i32)

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