[MSFT] Remove ChannelOp

This was unused. Fixes #6660.
This commit is contained in:
John Demme 2024-02-08 17:32:55 +00:00
parent d6ec48c09a
commit 28cdbbcccd
3 changed files with 0 additions and 67 deletions

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@ -45,30 +45,6 @@ def PEOutputOp: MSFTOp<"pe.output", [Terminator]> {
let assemblyFormat = "$output attr-dict `:` type($output)";
}
def ChannelOp: MSFTOp<"constructs.channel",
[Pure, Symbol,
AllTypesMatch<["input", "output"]>]> {
let summary = "A pipeline-able connection";
let description = [{
A logical, feed-forward connection between a producer and consumer. Can be
pipelined with a number of stages (cycle delay) on a per-instance basis.
`defaultStages` is used when `stages` isn't specified by a
`DynamicInstance`. Non-resettable, for now.
Per-instance specification is not yet supported, so the default pipelining
is always used.
}];
let arguments = (ins AnyType:$input, ClockType:$clk, StrAttr:$sym_name,
UI64Attr:$defaultStages);
let results = (outs AnyType:$output);
let assemblyFormat = [{
$input $clk $sym_name `(` $defaultStages `)` attr-dict `:` type($input)
}];
}
// Linear, pipelineable datapath.
def LinearOp : MSFTOp<"hlc.linear", [
SingleBlockImplicitTerminator<"OutputOp">

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@ -157,35 +157,6 @@ public:
};
} // anonymous namespace
namespace {
/// Lower MSFT's ChannelOp to a set of registers.
struct ChannelOpLowering : public OpConversionPattern<ChannelOp> {
public:
ChannelOpLowering(MLIRContext *ctxt, LowerConstructsPass &pass)
: OpConversionPattern(ctxt), pass(pass) {}
LogicalResult
matchAndRewrite(ChannelOp chan, OpAdaptor adaptor,
ConversionPatternRewriter &rewriter) const final {
Location loc = chan.getLoc();
Operation *mod = chan->getParentOfType<hw::HWModuleLike>();
assert(mod && "ChannelOp must be contained by module");
Namespace &ns = pass.getNamespaceFor(mod);
Value clk = chan.getClk();
Value v = chan.getInput();
for (uint64_t stageNum = 0, e = chan.getDefaultStages(); stageNum < e;
++stageNum)
v = rewriter.create<seq::CompRegOp>(loc, v, clk,
ns.newName(chan.getSymName()));
rewriter.replaceOp(chan, {v});
return success();
}
protected:
LowerConstructsPass &pass;
};
} // namespace
void LowerConstructsPass::runOnOperation() {
auto top = getOperation();
auto *ctxt = &getContext();
@ -196,8 +167,6 @@ void LowerConstructsPass::runOnOperation() {
RewritePatternSet patterns(ctxt);
patterns.insert<SystolicArrayOpLowering>(ctxt);
target.addIllegalOp<SystolicArrayOp>();
patterns.insert<ChannelOpLowering>(ctxt, *this);
target.addIllegalOp<ChannelOp>();
if (failed(mlir::applyPartialConversion(top, target, std::move(patterns))))
signalPassFailure();

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@ -50,18 +50,6 @@ hw.module @PE(in %clk: !seq.clock, in %a: i8, in %b: i8, out sum: i8) {
hw.output %sumDelay1 : i8
}
// CHECK-LABEL: hw.module @ChannelExample(in %clk : !seq.clock, in %a : i8, out out : i8) {
// CHECK: [[REG0:%.+]] = msft.constructs.channel %a %clk "chEx"(2) : i8
// CHECK: hw.output [[REG0]] : i8
// LOWER-LABEL: hw.module @ChannelExample(in %clk : !seq.clock, in %a : i8, out out : i8) {
// LOWER: %chEx_0 = seq.compreg sym @chEx_0 %a, %clk : i8
// LOWER: %chEx_1 = seq.compreg sym @chEx_1 %chEx_0, %clk : i8
// LOWER: hw.output %chEx_1 : i8
hw.module @ChannelExample (in %clk: !seq.clock, in %a : i8, out out: i8) {
%out = msft.constructs.channel %a %clk "chEx" (2) : i8
hw.output %out : i8
}
// CHECK-LABEL: hw.module @foo(in %in0 : i32, in %in1 : i32, in %in2 : i32, in %clk : !seq.clock, out out : i32) {
// CHECK: %0 = msft.hlc.linear clock %clk : i32 {
// CHECK: %1 = comb.mul %in0, %in1 : i32