mirror of https://github.com/llvm/circt.git
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commit
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@ -45,30 +45,6 @@ def PEOutputOp: MSFTOp<"pe.output", [Terminator]> {
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let assemblyFormat = "$output attr-dict `:` type($output)";
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}
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def ChannelOp: MSFTOp<"constructs.channel",
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[Pure, Symbol,
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AllTypesMatch<["input", "output"]>]> {
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let summary = "A pipeline-able connection";
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let description = [{
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A logical, feed-forward connection between a producer and consumer. Can be
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pipelined with a number of stages (cycle delay) on a per-instance basis.
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`defaultStages` is used when `stages` isn't specified by a
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`DynamicInstance`. Non-resettable, for now.
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Per-instance specification is not yet supported, so the default pipelining
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is always used.
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}];
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let arguments = (ins AnyType:$input, ClockType:$clk, StrAttr:$sym_name,
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UI64Attr:$defaultStages);
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let results = (outs AnyType:$output);
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let assemblyFormat = [{
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$input $clk $sym_name `(` $defaultStages `)` attr-dict `:` type($input)
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}];
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}
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// Linear, pipelineable datapath.
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def LinearOp : MSFTOp<"hlc.linear", [
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SingleBlockImplicitTerminator<"OutputOp">
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@ -157,35 +157,6 @@ public:
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};
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} // anonymous namespace
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namespace {
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/// Lower MSFT's ChannelOp to a set of registers.
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struct ChannelOpLowering : public OpConversionPattern<ChannelOp> {
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public:
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ChannelOpLowering(MLIRContext *ctxt, LowerConstructsPass &pass)
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: OpConversionPattern(ctxt), pass(pass) {}
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LogicalResult
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matchAndRewrite(ChannelOp chan, OpAdaptor adaptor,
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ConversionPatternRewriter &rewriter) const final {
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Location loc = chan.getLoc();
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Operation *mod = chan->getParentOfType<hw::HWModuleLike>();
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assert(mod && "ChannelOp must be contained by module");
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Namespace &ns = pass.getNamespaceFor(mod);
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Value clk = chan.getClk();
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Value v = chan.getInput();
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for (uint64_t stageNum = 0, e = chan.getDefaultStages(); stageNum < e;
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++stageNum)
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v = rewriter.create<seq::CompRegOp>(loc, v, clk,
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ns.newName(chan.getSymName()));
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rewriter.replaceOp(chan, {v});
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return success();
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}
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protected:
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LowerConstructsPass &pass;
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};
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} // namespace
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void LowerConstructsPass::runOnOperation() {
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auto top = getOperation();
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auto *ctxt = &getContext();
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@ -196,8 +167,6 @@ void LowerConstructsPass::runOnOperation() {
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RewritePatternSet patterns(ctxt);
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patterns.insert<SystolicArrayOpLowering>(ctxt);
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target.addIllegalOp<SystolicArrayOp>();
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patterns.insert<ChannelOpLowering>(ctxt, *this);
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target.addIllegalOp<ChannelOp>();
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if (failed(mlir::applyPartialConversion(top, target, std::move(patterns))))
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signalPassFailure();
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@ -50,18 +50,6 @@ hw.module @PE(in %clk: !seq.clock, in %a: i8, in %b: i8, out sum: i8) {
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hw.output %sumDelay1 : i8
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}
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// CHECK-LABEL: hw.module @ChannelExample(in %clk : !seq.clock, in %a : i8, out out : i8) {
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// CHECK: [[REG0:%.+]] = msft.constructs.channel %a %clk "chEx"(2) : i8
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// CHECK: hw.output [[REG0]] : i8
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// LOWER-LABEL: hw.module @ChannelExample(in %clk : !seq.clock, in %a : i8, out out : i8) {
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// LOWER: %chEx_0 = seq.compreg sym @chEx_0 %a, %clk : i8
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// LOWER: %chEx_1 = seq.compreg sym @chEx_1 %chEx_0, %clk : i8
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// LOWER: hw.output %chEx_1 : i8
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hw.module @ChannelExample (in %clk: !seq.clock, in %a : i8, out out: i8) {
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%out = msft.constructs.channel %a %clk "chEx" (2) : i8
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hw.output %out : i8
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}
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// CHECK-LABEL: hw.module @foo(in %in0 : i32, in %in1 : i32, in %in2 : i32, in %clk : !seq.clock, out out : i32) {
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// CHECK: %0 = msft.hlc.linear clock %clk : i32 {
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// CHECK: %1 = comb.mul %in0, %in1 : i32
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