mirror of https://github.com/llvm/circt.git
[ESI] Wrap modules exposing latency insensitive signals to expose ESI channels (#828)
Add two functions which are intended to be exposed over an API: - A function to heuristically locate signal port triplets with ready valid on an RTL module. - A function which takes an RTL module and a list of those port triplets and build a 'shell' around that module which 'uplifts' the port triplets to ESI channels. Adds an 'esi-tester' binary to execute these two functions.
This commit is contained in:
John Demme
GitHub
parent
4fdba7023e
commit
31d19839f0
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@ -19,8 +19,11 @@
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#ifndef CIRCT_DIALECT_ESI_ESIDIALECT_H
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#define CIRCT_DIALECT_ESI_ESIDIALECT_H
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#include "circt/Dialect/RTL/RTLOps.h"
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#include "circt/Support/LLVM.h"
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#include "mlir/IR/BuiltinAttributes.h"
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#include "mlir/IR/Dialect.h"
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namespace circt {
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namespace esi {
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@ -46,6 +49,23 @@ private:
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void registerESIPasses();
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void registerESITranslations();
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/// A triple of signals which represent a latency insensitive interface with
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/// valid/ready semantics.
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struct ESIPortValidReadyMapping {
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rtl::ModulePortInfo data, valid, ready;
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};
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/// Find all the port triples on a module which fit the
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/// <name>/<name>_valid/<name>_ready pattern. Ready must be the opposite
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/// direction of the other two.
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void findValidReadySignals(Operation *modOp,
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SmallVectorImpl<ESIPortValidReadyMapping> &names);
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/// Build an ESI module wrapper, converting the wires with latency-insensitive
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/// semantics to ESI channels and passing through the rest.
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Operation *buildESIWrapper(OpBuilder &b, Operation *mod,
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ArrayRef<ESIPortValidReadyMapping> esiPortNames);
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} // namespace esi
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} // namespace circt
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@ -13,12 +13,19 @@
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#include "circt/Dialect/ESI/ESIDialect.h"
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#include "circt/Dialect/ESI/ESIOps.h"
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#include "circt/Dialect/ESI/ESITypes.h"
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#include "circt/Dialect/RTL/RTLOps.h"
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#include "circt/Support/BackedgeBuilder.h"
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#include "circt/Support/ImplicitLocOpBuilder.h"
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#include "circt/Support/LLVM.h"
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#include "mlir/IR/Builders.h"
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#include "mlir/IR/DialectImplementation.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/StringMap.h"
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#include "llvm/ADT/StringSet.h"
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#include "llvm/Support/FormatVariadic.h"
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namespace circt {
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namespace esi {
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using namespace circt;
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using namespace circt::esi;
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ESIDialect::ESIDialect(MLIRContext *context)
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: Dialect("esi", context, TypeID::get<ESIDialect>()) {
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@ -30,7 +37,238 @@ ESIDialect::ESIDialect(MLIRContext *context)
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#include "circt/Dialect/ESI/ESI.cpp.inc"
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>();
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}
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} // namespace esi
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} // namespace circt
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/// Find all the port triples on a module which fit the
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/// <name>/<name>_valid/<name>_ready pattern. Ready must be the opposite
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/// direction of the other two.
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void circt::esi::findValidReadySignals(
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Operation *modOp, SmallVectorImpl<ESIPortValidReadyMapping> &names) {
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SmallVector<rtl::ModulePortInfo, 64> ports;
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rtl::getModulePortInfo(modOp, ports);
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llvm::StringMap<rtl::ModulePortInfo> nameMap(ports.size());
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for (auto port : ports)
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nameMap[port.getName()] = port;
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for (auto port : ports) {
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if (port.direction == rtl::PortDirection::INOUT)
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continue;
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StringRef portDataName = port.getName();
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if (portDataName.endswith("_data")) // Detect both `foo` and `foo_data`.
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portDataName = portDataName.substr(0, portDataName.size() - 5);
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// Try to find a corresponding 'valid' port.
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SmallString<64> portName = portDataName;
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portName.append("_valid");
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auto valid = nameMap.find(portName);
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if (valid == nameMap.end() || valid->second.direction != port.direction ||
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!valid->second.type.isSignlessInteger(1))
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continue;
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// Try to find a corresponding 'ready' port.
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portName = portDataName;
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portName.append("_ready");
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rtl::PortDirection readyDir = port.direction == rtl::PortDirection::INPUT
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? rtl::PortDirection::OUTPUT
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: rtl::PortDirection::INPUT;
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auto ready = nameMap.find(portName);
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if (ready == nameMap.end() || ready->second.direction != readyDir ||
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!valid->second.type.isSignlessInteger(1))
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continue;
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// Found one.
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names.push_back(ESIPortValidReadyMapping{
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.data = port, .valid = valid->second, .ready = ready->second});
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}
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}
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/// Build an ESI module wrapper, converting the wires with latency-insensitive
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/// semantics to ESI channels and passing through the rest.
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Operation *
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circt::esi::buildESIWrapper(OpBuilder &b, Operation *pearl,
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ArrayRef<ESIPortValidReadyMapping> portsToConvert) {
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// In order to avoid the similar sounding and looking "wrapped" and "wrapper"
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// names or the ambiguous "module", we use "pearl" for the module _being
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// wrapped_ and "shell" for the _wrapper_ modules which is being created
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// (terms typically used in latency insensitive design papers).
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auto *ctxt = b.getContext();
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Location loc = pearl->getLoc();
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FunctionType modType = rtl::getModuleType(pearl);
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SmallVector<rtl::ModulePortInfo, 64> pearlPorts;
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rtl::getModulePortInfo(pearl, pearlPorts);
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// -----
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// First, build up a set of data structures to use throughout this function.
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StringSet<> controlPorts; // Memoize the list of ready/valid ports to ignore.
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llvm::StringMap<ESIPortValidReadyMapping>
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dataPortMap; // Store a lookup table of ports to convert indexed on the
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// data port name.
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// Validate input and assemble lookup structures.
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for (const auto &esiPort : portsToConvert) {
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if (esiPort.data.direction == rtl::PortDirection::INOUT) {
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pearl->emitError("Data signal '")
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<< esiPort.data.name << "' must not be INOUT";
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return nullptr;
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}
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dataPortMap[esiPort.data.name.getValue()] = esiPort;
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if (esiPort.valid.direction != esiPort.data.direction) {
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pearl->emitError("Valid port '")
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<< esiPort.valid.name << "' direction must match data port.";
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return nullptr;
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}
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if (esiPort.valid.type != b.getI1Type()) {
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pearl->emitError("Valid signal '")
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<< esiPort.valid.name << "' must be i1 type";
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return nullptr;
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}
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controlPorts.insert(esiPort.valid.name.getValue());
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if (esiPort.ready.direction != (esiPort.data.isOutput()
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? rtl::PortDirection::INPUT
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: rtl::PortDirection::OUTPUT)) {
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pearl->emitError("Ready port '")
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<< esiPort.ready.name
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<< "' must be opposite direction to data signal.";
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return nullptr;
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}
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if (esiPort.ready.type != b.getI1Type()) {
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pearl->emitError("Ready signal '")
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<< esiPort.ready.name << "' must be i1 type";
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return nullptr;
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}
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controlPorts.insert(esiPort.ready.name.getValue());
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}
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// -----
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// Second, build a list of ports for the shell module, skipping the
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// valid/ready, and converting the ESI data ports to the ESI channel port
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// type. Store some bookkeeping information.
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SmallVector<rtl::ModulePortInfo, 64> shellPorts;
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// Map the shell operand to the pearl port.
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SmallVector<rtl::ModulePortInfo, 64> inputPortMap;
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// Map the shell result to the pearl port.
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SmallVector<rtl::ModulePortInfo, 64> outputPortMap;
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for (const auto port : pearlPorts) {
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if (controlPorts.contains(port.name.getValue()))
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continue;
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rtl::ModulePortInfo newPort = port;
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if (dataPortMap.find(port.name.getValue()) != dataPortMap.end())
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newPort.type = esi::ChannelPort::get(ctxt, port.type);
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if (port.isOutput()) {
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newPort.argNum = outputPortMap.size();
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outputPortMap.push_back(port);
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} else {
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newPort.argNum = inputPortMap.size();
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inputPortMap.push_back(port);
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}
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shellPorts.push_back(newPort);
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}
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// -----
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// Third, create the shell module and also some builders for the inside.
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SmallString<64> shellNameBuf;
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StringAttr shellName = b.getStringAttr(
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(SymbolTable::getSymbolName(pearl) + "_esi").toStringRef(shellNameBuf));
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auto shell = b.create<rtl::RTLModuleOp>(loc, shellName, shellPorts);
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shell.getBodyBlock()->clear(); // Erase the terminator.
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auto modBuilder =
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ImplicitLocOpBuilder::atBlockBegin(loc, shell.getBodyBlock());
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BackedgeBuilder bb(modBuilder, modBuilder.getLoc());
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// Hold the operands for `rtl.output` here.
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SmallVector<Value, 64> outputs(shell.getNumResults());
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// -----
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// Fourth, assemble the inputs for the pearl module AND build all the ESI wrap
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// and unwrap ops for both the input and output channels.
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SmallVector<Value, 64> pearlOperands(modType.getNumInputs());
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// Since we build all the ESI wrap and unwrap operations before pearl
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// instantiation, we only need backedges from the pearl instance result. Index
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// the backedges by the pearl modules result number.
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llvm::DenseMap<size_t, Backedge> backedges;
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// Go through the shell input ports, either tunneling them through or
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// unwrapping the ESI channels. We'll need backedges for the ready signals
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// since they are results from the upcoming pearl instance.
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for (const auto port : shellPorts) {
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if (port.isOutput())
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continue;
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Value arg = shell.getArgument(port.argNum);
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auto esiPort = dataPortMap.find(port.name.getValue());
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if (esiPort == dataPortMap.end()) {
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// If it's just a regular port, it just gets passed through.
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size_t pearlOpNum = inputPortMap[port.argNum].argNum;
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pearlOperands[pearlOpNum] = arg;
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continue;
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}
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Backedge ready = bb.get(modBuilder.getI1Type());
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backedges.insert(std::make_pair(esiPort->second.ready.argNum, ready));
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auto unwrap = modBuilder.create<UnwrapValidReady>(arg, ready);
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pearlOperands[esiPort->second.data.argNum] = unwrap.rawOutput();
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pearlOperands[esiPort->second.valid.argNum] = unwrap.valid();
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}
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// Iterate through the shell output ports, identify the ESI channels, and
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// build ESI wrapper ops for signals being output from the pearl. The data and
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// valid for these wrap ops will need to be backedges.
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for (const auto port : shellPorts) {
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if (!port.isOutput())
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continue;
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auto esiPort = dataPortMap.find(port.name.getValue());
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if (esiPort == dataPortMap.end())
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continue;
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Backedge data = bb.get(esiPort->second.data.type);
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Backedge valid = bb.get(modBuilder.getI1Type());
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auto wrap = modBuilder.create<WrapValidReady>(data, valid);
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backedges.insert(std::make_pair(esiPort->second.data.argNum, data));
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backedges.insert(std::make_pair(esiPort->second.valid.argNum, valid));
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outputs[port.argNum] = wrap.chanOutput();
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pearlOperands[esiPort->second.ready.argNum] = wrap.ready();
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}
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// -----
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// Fifth, instantiate the pearl module.
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auto pearlInst = modBuilder.create<rtl::InstanceOp>(
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modType.getResults(), "pearl", SymbolTable::getSymbolName(pearl),
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pearlOperands, DictionaryAttr());
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// Hookup all the backedges.
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for (size_t i = 0, e = pearlInst.getNumResults(); i < e; ++i) {
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auto backedge = backedges.find(i);
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if (backedge != backedges.end())
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backedge->second.setValue(pearlInst.getResult(i));
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}
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// -----
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// Finally, find all the regular outputs and either tunnel them through.
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for (const auto port : shellPorts) {
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if (!port.isOutput())
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continue;
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auto esiPort = dataPortMap.find(port.name.getValue());
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if (esiPort != dataPortMap.end())
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continue;
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size_t pearlResNum = outputPortMap[port.argNum].argNum;
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outputs[port.argNum] = pearlInst.getResult(pearlResNum);
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}
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modBuilder.create<rtl::OutputOp>(outputs);
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return shell;
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}
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#include "circt/Dialect/ESI/ESIAttrs.cpp.inc"
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@ -1,4 +1,5 @@
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add_subdirectory(CAPI)
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add_subdirectory(Dialect)
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configure_lit_site_cfg(
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${CMAKE_CURRENT_SOURCE_DIR}/lit.site.cfg.py.in
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@ -12,6 +13,7 @@ set(CIRCT_TEST_DEPENDS
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circt-capi-ir-test
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circt-opt
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circt-translate
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esi-tester
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handshake-runner
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firtool
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llhd-sim
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@ -0,0 +1,9 @@
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##===- CMakeLists.txt - ---------------------------------------*- cmake -*-===//
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##
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## Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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## See https://llvm.org/LICENSE.txt for license information.
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## SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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##
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##===----------------------------------------------------------------------===//
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add_subdirectory(ESI)
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@ -0,0 +1,30 @@
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##===- CMakeLists.txt - ---------------------------------------*- cmake -*-===//
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##
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## Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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## See https://llvm.org/LICENSE.txt for license information.
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## SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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##
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##===----------------------------------------------------------------------===//
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set(LLVM_LINK_COMPONENTS
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Support
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)
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add_llvm_tool(esi-tester
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esi-tester.cpp
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)
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llvm_update_compile_flags(esi-tester)
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target_link_libraries(esi-tester
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PRIVATE
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CIRCTESI
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CIRCTRTL
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CIRCTSV
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MLIRParser
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MLIRSupport
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MLIRIR
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MLIROptLib
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MLIRStandard
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MLIRTransforms
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MLIRLLVMIR
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)
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@ -0,0 +1,52 @@
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//===- esi-tester.cpp - The ESI test driver -------------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This program exercises some ESI functionality which is intended to be for API
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// use only.
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//
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//===----------------------------------------------------------------------===//
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#include "circt/InitAllDialects.h"
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#include "circt/InitAllPasses.h"
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#include "mlir/Dialect/StandardOps/IR/Ops.h"
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#include "mlir/Pass/Pass.h"
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#include "mlir/Support/MlirOptMain.h"
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#include "mlir/Transforms/Passes.h"
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using namespace circt;
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using namespace circt::esi;
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/// This is a test pass for verifying FuncOp's eraseResult method.
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struct TestESIModWrap
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: public mlir::PassWrapper<TestESIModWrap, OperationPass<mlir::ModuleOp>> {
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void runOnOperation() override {
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auto mlirMod = getOperation();
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auto b = mlir::OpBuilder::atBlockEnd(mlirMod.getBody());
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SmallVector<rtl::RTLModuleOp, 8> mods;
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for (Operation *mod : mlirMod.getOps<rtl::RTLModuleExternOp>()) {
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SmallVector<ESIPortValidReadyMapping, 32> liPorts;
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findValidReadySignals(mod, liPorts);
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if (!liPorts.empty())
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if (!buildESIWrapper(b, mod, liPorts))
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signalPassFailure();
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}
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}
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};
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int main(int argc, char **argv) {
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mlir::DialectRegistry registry;
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registry.insert<comb::CombDialect, esi::ESIDialect, rtl::RTLDialect>();
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mlir::PassRegistration<TestESIModWrap>(
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"test-mod-wrap", "Test the ESI find and wrap functionality");
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return mlir::failed(
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mlir::MlirOptMain(argc, argv, "CIRCT modular optimizer driver", registry,
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/*preloadDialectsInContext=*/true));
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}
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@ -0,0 +1,24 @@
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// RUN: esi-tester %s --test-mod-wrap | FileCheck %s
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rtl.module.extern @OutputChannel(%clk: i1, %bar_ready: i1) -> (%bar: i42, %bar_valid: i1)
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// CHECK-LABEL: rtl.module @OutputChannel_esi(%clk: i1) -> (%bar: !esi.channel<i42>) {
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// CHECK: %chanOutput, %ready = esi.wrap.vr %pearl.bar, %pearl.bar_valid : i42
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// CHECK: %pearl.bar, %pearl.bar_valid = rtl.instance "pearl" @OutputChannel(%clk, %ready) : (i1, i1) -> (i42, i1)
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// CHECK: rtl.output %chanOutput : !esi.channel<i42>
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rtl.module.extern @InputChannel(%clk: i1, %foo_data: i23, %foo_valid: i1) -> (%foo_ready: i1, %rawOut: i99)
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// CHECK-LABEL: rtl.module @InputChannel_esi(%clk: i1, %foo_data: !esi.channel<i23>) -> (%rawOut: i99) {
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// CHECK: %rawOutput, %valid = esi.unwrap.vr %foo_data, %pearl.foo_ready : i23
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// CHECK: %pearl.foo_ready, %pearl.rawOut = rtl.instance "pearl" @InputChannel(%clk, %rawOutput, %valid) : (i1, i23, i1) -> (i1, i99)
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// CHECK: rtl.output %pearl.rawOut : i99
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rtl.module.extern @Mixed(%clk: i1, %foo: i23, %foo_valid: i1, %bar_ready: i1) ->
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(%bar: i42, %bar_valid: i1, %foo_ready: i1, %rawOut: i99)
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// CHECK-LABEL: rtl.module @Mixed_esi(%clk: i1, %foo: !esi.channel<i23>) -> (%bar: !esi.channel<i42>, %rawOut: i99) {
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||||
// CHECK: %rawOutput, %valid = esi.unwrap.vr %foo, %pearl.foo_ready : i23
|
||||
// CHECK: %chanOutput, %ready = esi.wrap.vr %pearl.bar, %pearl.bar_valid : i42
|
||||
// CHECK: %pearl.bar, %pearl.bar_valid, %pearl.foo_ready, %pearl.rawOut = rtl.instance "pearl" @Mixed(%clk, %rawOutput, %valid, %ready) : (i1, i23, i1, i1) -> (i42, i1, i1, i99)
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||||
// CHECK: rtl.output %chanOutput, %pearl.rawOut : !esi.channel<i42>, i99
|
||||
|
|
@ -61,6 +61,7 @@ tools = [
|
|||
'circt-opt',
|
||||
'circt-translate',
|
||||
'circt-capi-ir-test',
|
||||
'esi-tester',
|
||||
'llhd-sim'
|
||||
]
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue