[ImportVerilog] Support for String Types, String Literals (#7403)

Co-authored-by: itaras20 <ian.taras20@gmail.com>

include/circt/Dialect/Moore/MooreOps.td

@@ -454,6 +454,21 @@ def NamedConstantOp : MooreOp<"named_constant", [
   }];
 }
 
+def StringConstantOp : MooreOp<"string_constant", [Pure, ConstantLike]> {
+  let summary = "Produce a constant string value";
+  let description = [{
+    Produces a constant value of string type.
+
+    Example:
+    ```mlir
+    %0 = moore.string "hello world"
+    ```
+  }];
+  let arguments = (ins StrAttr:$value);
+  let results = (outs IntType:$result);
+  let assemblyFormat = "$value attr-dict `:` type($result)";
+}
+
 def ConversionOp : MooreOp<"conversion", [Pure]> {
   let summary = "A type conversion";
   let description = [{

lib/Conversion/ImportVerilog/Expressions.cpp

@@ -712,6 +712,12 @@ struct RvalueExprVisitor {
     return {};
   }
 
+  /// Handle string literals.
+  Value visit(const slang::ast::StringLiteral &expr) {
+    auto type = context.convertType(*expr.type);
+    return builder.create<moore::StringConstantOp>(loc, type, expr.getValue());
+  }
+
   /// Emit an error for all other expressions.
   template <typename T>
   Value visit(T &&node) {

lib/Conversion/ImportVerilog/Types.cpp

@@ -147,6 +147,10 @@ struct TypeVisitor {
     return moore::UnpackedUnionType::get(context.getContext(), members);
   }
 
+  Type visit(const slang::ast::StringType &type) {
+    return moore::StringType::get(context.getContext());
+  }
+
   /// Emit an error for all other types.
   template <typename T>
   Type visit(T &&node) {

test/Conversion/ImportVerilog/basic.sv

@@ -201,6 +201,19 @@ module Basic;
   // CHECK: %ev2 = moore.variable [[VARIANT_B]]
   MyEnum ev1 = VariantA;
   MyEnum ev2 = VariantB;
+
+  // CHECK: [[STR_WELCOME:%.+]] = moore.string_constant "Welcome to Moore" : i128
+  // CHECK: [[CONV_WELCOME:%.+]] = moore.conversion [[STR_WELCOME]] : !moore.i128 -> !moore.string
+  // CHECK: [[VAR_S:%.+]] = moore.variable [[CONV_WELCOME]] : <string>
+  string s = "Welcome to Moore";
+
+  // CHECK: [[VAR_S1:%.+]] = moore.variable : <string>
+  // CHECK: [[STR_HELLO:%.+]] = moore.string_constant "Hello World" : i88
+  // CHECK: [[CONV_HELLO:%.+]] = moore.conversion [[STR_HELLO]] : !moore.i88 -> !moore.string
+  // CHECK: moore.assign [[VAR_S1]], [[CONV_HELLO]] : string
+  string s1; 
+  assign s1 = "Hello World";
+
 endmodule
 
 // CHECK-LABEL: moore.module @Statements

test/Conversion/ImportVerilog/types.sv

@@ -146,3 +146,9 @@ module Typedefs;
   myType1 v0;
   myType2 v1;
 endmodule
+
+// CHECK-LABEL: moore.module @String
+module String;
+  // CHECK-NEXT: %s = moore.variable : <string>
+  string s;
+endmodule