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[ImportVerilog] Fix root op ordering 

Use `upper_bound` to pick an insertion point for modules. This ensures
that multiple parametrizations of a module appear in the order in which
they were instantiated, instead of the reverse order.
This commit is contained in:
Fabian Schuiki 2024-07-17 12:39:12 -07:00
parent 9845589129
commit 419de21c45
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1 changed files with 1 additions and 1 deletions
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lib/Conversion/ImportVerilog/Structure.cpp
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@ -534,7 +534,7 @@ Context::convertModuleHeader(const slang::ast::InstanceBodySymbol *module) {
// Pick an insertion point for this module according to the source file
// location.
auto it = orderedRootOps.lower_bound(module->location);
auto it = orderedRootOps.upper_bound(module->location);
if (it == orderedRootOps.end())
builder.setInsertionPointToEnd(intoModuleOp.getBody());
else