mirror of https://github.com/llvm/circt.git
[RTG][CAPI] Expose getter for bag and set element type (#8227)
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@ -21,7 +21,7 @@ class Test:
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sig = inspect.signature(test_func)
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assert len(sig.parameters) == 0, "test arguments not supported yet"
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self.type = rtg.DictType.get(None, [])
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self.type = rtg.DictType.get([])
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@property
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def name(self) -> str:
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@ -58,12 +58,18 @@ MLIR_CAPI_EXPORTED bool rtgTypeIsASet(MlirType type);
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/// Creates an RTG set type in the context.
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MLIR_CAPI_EXPORTED MlirType rtgSetTypeGet(MlirType elementType);
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/// Return the element type of the RTG set.
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MLIR_CAPI_EXPORTED MlirType rtgSetTypeGetElementType(MlirType type);
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/// If the type is an RTG bag.
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MLIR_CAPI_EXPORTED bool rtgTypeIsABag(MlirType type);
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/// Creates an RTG bag type in the context.
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MLIR_CAPI_EXPORTED MlirType rtgBagTypeGet(MlirType elementType);
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/// Return the element type of the RTG bag.
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MLIR_CAPI_EXPORTED MlirType rtgBagTypeGetElementType(MlirType type);
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/// If the type is an RTG dict.
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MLIR_CAPI_EXPORTED bool rtgTypeIsADict(MlirType type);
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@ -13,8 +13,8 @@ with Context() as ctx, Location.unknown():
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m = Module.create()
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with InsertionPoint(m.body):
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cpuTy = rtgtest.CPUType.get()
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dictTy = rtg.DictType.get(ctx, [(StringAttr.get('cpu0'), cpuTy),
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(StringAttr.get('cpu1'), cpuTy)])
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dictTy = rtg.DictType.get([(StringAttr.get('cpu0'), cpuTy),
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(StringAttr.get('cpu1'), cpuTy)], ctx)
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target = rtg.TargetOp('target_name', TypeAttr.get(dictTy))
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targetBlock = Block.create_at_start(target.bodyRegion, [])
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@ -44,6 +44,9 @@ with Context() as ctx, Location.unknown():
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seq = rtg.SequenceOp('seq', TypeAttr.get(rtg.SequenceType.get([setTy])))
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seqBlock = Block.create_at_start(seq.bodyRegion, [setTy])
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# CHECK: !rtg.sequence{{$}}
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print(setTy.element_type)
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# CHECK: rtg.sequence @seq(%{{.*}}: !rtg.set<!rtg.sequence>) {
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# CHECK: }
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print(m)
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@ -100,6 +103,9 @@ with Context() as ctx, Location.unknown():
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seq.bodyRegion,
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[sequenceTy, labelTy, setTy, bagTy, ireg, randomizedSequenceTy])
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# CHECK: index{{$}}
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print(bagTy.element_type)
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# CHECK: rtg.sequence @seq(%{{.*}}: !rtg.sequence, %{{.*}}: !rtg.label, %{{.*}}: !rtg.set<index>, %{{.*}}: !rtg.bag<index>, %{{.*}}: !rtgtest.ireg, %{{.*}}: !rtg.randomized_sequence)
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print(m)
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@ -62,7 +62,10 @@ void circt::python::populateDialectRTGSubmodule(nb::module_ &m) {
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[](nb::object cls, MlirType elementType) {
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return cls(rtgSetTypeGet(elementType));
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},
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nb::arg("self"), nb::arg("element_type"));
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nb::arg("self"), nb::arg("element_type"))
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.def_property_readonly("element_type", [](MlirType self) {
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return rtgSetTypeGetElementType(self);
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});
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mlir_type_subclass(m, "BagType", rtgTypeIsABag)
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.def_classmethod(
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@ -70,13 +73,17 @@ void circt::python::populateDialectRTGSubmodule(nb::module_ &m) {
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[](nb::object cls, MlirType elementType) {
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return cls(rtgBagTypeGet(elementType));
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},
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nb::arg("self"), nb::arg("element_type"));
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nb::arg("self"), nb::arg("element_type"))
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.def_property_readonly("element_type", [](MlirType self) {
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return rtgBagTypeGetElementType(self);
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});
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mlir_type_subclass(m, "DictType", rtgTypeIsADict)
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.def_classmethod(
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"get",
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[](nb::object cls, MlirContext ctxt,
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const std::vector<std::pair<MlirAttribute, MlirType>> &entries) {
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[](nb::object cls,
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const std::vector<std::pair<MlirAttribute, MlirType>> &entries,
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MlirContext ctxt) {
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std::vector<MlirAttribute> names;
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std::vector<MlirType> types;
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for (auto entry : entries) {
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@ -86,9 +93,10 @@ void circt::python::populateDialectRTGSubmodule(nb::module_ &m) {
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return cls(
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rtgDictTypeGet(ctxt, types.size(), names.data(), types.data()));
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},
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nb::arg("self"), nb::arg("ctxt") = nullptr,
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nb::arg("self"),
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nb::arg("entries") =
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std::vector<std::pair<MlirAttribute, MlirType>>());
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std::vector<std::pair<MlirAttribute, MlirType>>(),
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nb::arg("ctxt") = nullptr);
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nb::enum_<RTGLabelVisibility>(m, "LabelVisibility")
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.value("LOCAL", RTG_LABEL_VISIBILITY_LOCAL)
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@ -88,7 +88,7 @@ def type_to_pytype(t) -> ir.Type:
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if t.__class__ != ir.Type:
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return t
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from .dialects import esi, hw, seq
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from .dialects import esi, hw, seq, rtg
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try:
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return ir.IntegerType(t)
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except ValueError:
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@ -129,6 +129,30 @@ def type_to_pytype(t) -> ir.Type:
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return esi.BundleType(t)
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except ValueError:
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pass
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try:
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return rtg.LabelType(t)
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except ValueError:
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pass
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try:
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return rtg.SetType(t)
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except ValueError:
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pass
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try:
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return rtg.BagType(t)
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except ValueError:
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pass
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try:
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return rtg.SequenceType(t)
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except ValueError:
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pass
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try:
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return rtg.RandomizedSequenceType(t)
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except ValueError:
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pass
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try:
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return rtg.DictType(t)
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except ValueError:
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pass
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raise TypeError(f"Cannot convert {repr(t)} to python type")
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@ -79,6 +79,10 @@ MlirType rtgSetTypeGet(MlirType elementType) {
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return wrap(SetType::get(ty.getContext(), ty));
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}
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MlirType rtgSetTypeGetElementType(MlirType type) {
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return wrap(cast<SetType>(unwrap(type)).getElementType());
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}
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// BagType
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//===----------------------------------------------------------------------===//
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@ -89,6 +93,10 @@ MlirType rtgBagTypeGet(MlirType elementType) {
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return wrap(BagType::get(ty.getContext(), ty));
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}
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MlirType rtgBagTypeGetElementType(MlirType type) {
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return wrap(cast<BagType>(unwrap(type)).getElementType());
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}
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// DictType
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//===----------------------------------------------------------------------===//
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@ -64,6 +64,8 @@ static void testSetType(MlirContext ctx) {
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fprintf(stderr, rtgTypeIsASet(setTy) ? "is_set\n" : "isnot_set\n");
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// CHECK: !rtg.set<i32>
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mlirTypeDump(setTy);
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// CHECK: i32{{$}}
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mlirTypeDump(rtgSetTypeGetElementType(setTy));
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}
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static void testBagType(MlirContext ctx) {
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@ -74,6 +76,8 @@ static void testBagType(MlirContext ctx) {
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fprintf(stderr, rtgTypeIsABag(bagTy) ? "is_bag\n" : "isnot_bag\n");
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// CHECK: !rtg.bag<i32>
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mlirTypeDump(bagTy);
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// CHECK: i32{{$}}
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mlirTypeDump(rtgBagTypeGetElementType(bagTy));
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}
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static void testDictType(MlirContext ctx) {
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