mirror of https://github.com/llvm/circt.git
[Seq] Add a pass to convert an array seq.firreg to seq.firmem (#8716)
This commit introduces a new transformation pass `RegOfVecToMem` that converts register arrays following memory access patterns into `seq.firmem` operations. When a valid pattern is detected, the pass replaces the register array with a `seq.firmem` operation and corresponding read/write ports. This is required for the `circt-verilog` tool, to identify memories, such that other `circt` transformations/analysis can be run in the `seq` dialect on the `mlir` parsed from verilog.
This commit is contained in:
Prithayan Barua
GitHub
parent
640daf0c92
commit
4ce45d581f
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@ -31,6 +31,7 @@ std::unique_ptr<mlir::Pass> createLowerSeqFIFOPass();
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std::unique_ptr<mlir::Pass>
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createHWMemSimImplPass(const HWMemSimImplOptions &options = {});
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std::unique_ptr<mlir::Pass> createLowerSeqShiftRegPass();
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std::unique_ptr<mlir::Pass> createRegOfVecToMem();
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/// Generate the code for registering passes.
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#define GEN_PASS_REGISTRATION
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@ -111,4 +111,16 @@ def LowerSeqShiftReg : Pass<"lower-seq-shiftreg", "hw::HWModuleOp"> {
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let dependentDialects = ["circt::hw::HWDialect"];
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}
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def RegOfVecToMem : Pass<"seq-reg-of-vec-to-mem", "hw::HWModuleOp"> {
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let summary = "Convert register arrays to FIRRTL memories";
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let description = [{
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This pass identifies register arrays that follow memory access patterns
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and converts them to seq.firmem operations. It looks for patterns where:
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1. A register array is updated via array_inject operations
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2. The array is read via array_get operations
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3. Updates are controlled by enable signals through mux operations
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4. Read and write operations use the same clock
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}];
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}
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#endif // CIRCT_DIALECT_SEQ_SEQPASSES
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@ -1,6 +1,7 @@
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add_circt_dialect_library(CIRCTSeqTransforms
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ExternalizeClockGate.cpp
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HWMemSimImpl.cpp
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RegOfVecToMem.cpp
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LowerSeqHLMem.cpp
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LowerSeqFIFO.cpp
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LowerSeqShiftReg.cpp
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@ -0,0 +1,261 @@
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//===- RegOfVecToMem.cpp - Convert Register Arrays to Memories -----------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This transformation pass converts register arrays that follow memory access
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// patterns to seq.firmem operations.
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//
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//===----------------------------------------------------------------------===//
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#include "circt/Dialect/Comb/CombOps.h"
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#include "circt/Dialect/HW/HWOps.h"
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#include "circt/Dialect/Seq/SeqOps.h"
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#include "circt/Dialect/Seq/SeqPasses.h"
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#include "mlir/IR/ImplicitLocOpBuilder.h"
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#include "mlir/Pass/Pass.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/Support/Debug.h"
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#define DEBUG_TYPE "reg-of-vec-to-mem"
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using namespace circt;
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using namespace seq;
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using namespace hw;
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namespace circt {
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namespace seq {
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#define GEN_PASS_DEF_REGOFVECTOMEM
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#include "circt/Dialect/Seq/SeqPasses.h.inc"
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} // namespace seq
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} // namespace circt
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namespace {
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struct MemoryPattern {
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FirRegOp memReg; // The register array representing memory
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FirRegOp outputReg; // Optional output register
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Value clock; // Clock signal
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Value readAddr; // Read address
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Value writeAddr; // Write address
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Value writeData; // Write data
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Value writeEnable; // Write enable
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Value readEnable; // Read enable (optional)
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comb::MuxOp writeMux; // Mux selecting between old/new memory state
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comb::MuxOp readMux; // Mux for read data
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hw::ArrayGetOp readAccess; // Array read operation
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hw::ArrayInjectOp writeAccess; // Array write operation
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};
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class RegOfVecToMemPass : public impl::RegOfVecToMemBase<RegOfVecToMemPass> {
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public:
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void runOnOperation() override;
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private:
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bool analyzeMemoryPattern(FirRegOp reg, MemoryPattern &pattern);
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bool createFirMemory(MemoryPattern &pattern);
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bool isArrayType(Type type);
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std::optional<std::pair<uint64_t, uint64_t>> getArrayDimensions(Type type);
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SmallVector<Operation *> opsToErase;
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};
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} // end anonymous namespace
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bool RegOfVecToMemPass::isArrayType(Type type) {
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return isa<hw::ArrayType, hw::UnpackedArrayType>(type);
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}
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std::optional<std::pair<uint64_t, uint64_t>>
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RegOfVecToMemPass::getArrayDimensions(Type type) {
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if (auto arrayType = dyn_cast<hw::ArrayType>(type)) {
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auto elemType = arrayType.getElementType();
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if (auto intType = dyn_cast<IntegerType>(elemType)) {
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return std::make_pair(arrayType.getNumElements(), intType.getWidth());
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}
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}
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return std::nullopt;
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}
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bool RegOfVecToMemPass::analyzeMemoryPattern(FirRegOp reg,
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MemoryPattern &pattern) {
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LLVM_DEBUG(llvm::dbgs() << "Analyzing register: " << reg << "\n");
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// Check if register has array type
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if (!isArrayType(reg.getType()))
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return false;
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ArrayGetOp readAccess;
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ArrayInjectOp writeAccess;
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comb::MuxOp writeMux;
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for (auto *user : reg.getResult().getUsers()) {
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LLVM_DEBUG(llvm::dbgs() << " Register user: " << *user << "\n");
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if (auto arrayGet = dyn_cast<hw::ArrayGetOp>(user); !readAccess && arrayGet)
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readAccess = arrayGet;
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else if (auto arrayInject = dyn_cast<hw::ArrayInjectOp>(user);
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!writeAccess && arrayInject)
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writeAccess = arrayInject;
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else if (auto mux = dyn_cast<comb::MuxOp>(user); !writeMux && mux)
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writeMux = mux;
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else
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return false;
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}
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if (!readAccess || !writeAccess || !writeMux)
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return false;
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pattern.memReg = reg;
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pattern.clock = reg.getClk();
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// Find the mux that drives this register
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auto nextValue = reg.getNext();
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auto mux = nextValue.getDefiningOp<comb::MuxOp>();
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if (!mux)
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return false;
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LLVM_DEBUG(llvm::dbgs() << " Found driving mux: " << mux << "\n");
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pattern.writeMux = mux;
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// Check that the mux is only used by this register (safety check)
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if (!mux.getResult().hasOneUse()) {
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LLVM_DEBUG(llvm::dbgs() << " Mux has multiple uses, cannot transform\n");
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return false;
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}
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// Analyze mux inputs: sel ? write_result : current_memory
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Value writeResult = mux.getTrueValue();
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Value currentMemory = mux.getFalseValue();
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// Check if false value is the current register (feedback)
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if (currentMemory != reg.getResult())
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return false;
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// Look for array_inject operation in write path
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auto arrayInject = writeResult.getDefiningOp<hw::ArrayInjectOp>();
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if (!arrayInject)
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return false;
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LLVM_DEBUG(llvm::dbgs() << " Found array_inject: " << arrayInject << "\n");
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pattern.writeAccess = arrayInject;
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pattern.writeAddr = arrayInject.getIndex();
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pattern.writeData = arrayInject.getElement();
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pattern.writeEnable = mux.getCond();
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// Look for read pattern - find array_get users
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auto arrayGet = readAccess;
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LLVM_DEBUG(llvm::dbgs() << " Found array_get: " << arrayGet << "\n");
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pattern.readAccess = arrayGet;
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pattern.readAddr = arrayGet.getIndex();
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// Check if read goes through output register
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for (auto *readUser : arrayGet.getResult().getUsers()) {
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if (auto outputReg = dyn_cast<FirRegOp>(readUser)) {
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if (outputReg.getClk() == pattern.clock) {
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LLVM_DEBUG(llvm::dbgs()
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<< " Found output register: " << outputReg << "\n");
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pattern.outputReg = outputReg;
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break;
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}
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}
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}
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bool success = pattern.readAccess != nullptr;
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LLVM_DEBUG(llvm::dbgs() << " Pattern analysis "
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<< (success ? "succeeded" : "failed") << "\n");
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return success;
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}
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bool RegOfVecToMemPass::createFirMemory(MemoryPattern &pattern) {
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LLVM_DEBUG(llvm::dbgs() << "Creating FirMemory for pattern\n");
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auto dims = getArrayDimensions(pattern.memReg.getType());
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if (!dims)
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return false;
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uint64_t depth = dims->first;
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uint64_t width = dims->second;
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LLVM_DEBUG(llvm::dbgs() << " Memory dimensions: " << depth << " x " << width
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<< "\n");
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ImplicitLocOpBuilder builder(pattern.memReg.getLoc(), pattern.memReg);
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// Create FirMem
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auto memType =
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FirMemType::get(builder.getContext(), depth, width, /*maskWidth=*/1);
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auto firMem = builder.create<seq::FirMemOp>(
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memType, /*readLatency=*/0, /*writeLatency=*/1,
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/*readUnderWrite=*/seq::RUW::Undefined,
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/*writeUnderWrite=*/seq::WUW::Undefined,
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/*name=*/builder.getStringAttr("mem"), /*innerSym=*/hw::InnerSymAttr{},
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/*init=*/seq::FirMemInitAttr{}, /*prefix=*/StringAttr{},
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/*outputFile=*/Attribute{});
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// Create read port
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Value readData = builder.create<FirMemReadOp>(
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firMem, pattern.readAddr, pattern.clock,
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/*enable=*/builder.create<hw::ConstantOp>(builder.getI1Type(), 1));
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LLVM_DEBUG(llvm::dbgs() << " Created read port\n"
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<< firMem << "\n " << readData);
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Value mask;
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// Create write port
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builder.create<FirMemWriteOp>(firMem, pattern.writeAddr, pattern.clock,
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pattern.writeEnable, pattern.writeData, mask);
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LLVM_DEBUG(llvm::dbgs() << " Created write port\n");
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// Replace read access
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if (pattern.outputReg)
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// If there's an output register, replace its input
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pattern.outputReg.getNext().replaceAllUsesWith(readData);
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else
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// Replace direct read access
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pattern.readAccess.getResult().replaceAllUsesWith(readData);
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// Mark old operations for removal
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opsToErase.push_back(pattern.memReg);
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if (pattern.readAccess)
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opsToErase.push_back(pattern.readAccess);
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if (pattern.writeAccess)
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opsToErase.push_back(pattern.writeAccess);
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if (pattern.writeMux)
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opsToErase.push_back(pattern.writeMux);
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return true;
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}
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void RegOfVecToMemPass::runOnOperation() {
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auto module = getOperation();
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SmallVector<FirRegOp> arrayRegs;
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// Collect all FirRegOp with array types
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module.walk([&](FirRegOp reg) {
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if (isArrayType(reg.getType())) {
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arrayRegs.push_back(reg);
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}
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});
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// Analyze each array register for memory patterns
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for (auto reg : arrayRegs) {
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MemoryPattern pattern;
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if (analyzeMemoryPattern(reg, pattern)) {
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createFirMemory(pattern);
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}
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}
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// Erase all marked operations
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for (auto *op : opsToErase) {
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LLVM_DEBUG(llvm::dbgs()
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<< "Erasing operation: " << *op << " number of uses:"
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<< "\n");
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op->dropAllUses();
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op->erase();
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}
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opsToErase.clear();
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}
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@ -0,0 +1,78 @@
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// RUN: circt-opt %s --seq-reg-of-vec-to-mem | FileCheck %s
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// CHECK-LABEL: hw.module private @complex_mem
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hw.module private @complex_mem(in %CLK : i1, in %D : i46, in %ADR : i13, in %WE : i1, in %ME : i1, out Q : i46) {
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%true = hw.constant true
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%c0_i46 = hw.constant 0 : i46
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%0 = comb.xor %WE, %true : i1
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%1 = comb.and %ME, %0 : i1
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%2 = hw.array_get %mem_core[%ADR] : !hw.array<8192xi46>, i13
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%3 = comb.xor %1, %true : i1
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%4 = comb.mux %3, %c0_i46, %2 : i46
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%5 = seq.to_clock %CLK
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%6 = comb.mux %1, %4, %Q_int : i46
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%Q_int = seq.firreg %6 clock %5 : i46
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// NOTE: The transformation cannot identify the memory read enable signal.
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%7 = comb.and %ME, %WE : i1
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%8 = hw.array_inject %mem_core[%ADR], %D : !hw.array<8192xi46>, i13
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%9 = comb.mux %7, %8, %mem_core : !hw.array<8192xi46>
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%mem_core = seq.firreg %9 clock %5 : !hw.array<8192xi46>
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hw.output %Q_int : i46
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}
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// CHECK: %[[clock:.+]] = seq.to_clock %CLK
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// CHECK: %[[V6:.+]] = comb.and %ME, %WE : i1
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// CHECK: %mem = seq.firmem 0, 1, undefined, undefined : <8192 x 46, mask 1>
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// CHECK: %[[READ:.+]] = seq.firmem.read_port %mem[%ADR], clock %[[clock]] enable %true
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// CHECK: seq.firmem.write_port %mem[%ADR] = %D, clock %[[clock]] enable %[[V6]]
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// CHECK-NOT: seq.firreg %{{.*}} : !hw.array<8192xi46>
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// CHECK-NOT: hw.array_get
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// CHECK-NOT: hw.array_inject
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// Simple test case
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// CHECK-LABEL: hw.module @simple_mem
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hw.module @simple_mem(in %clk : i1, in %addr : i2, in %data : i8, in %we : i1, out out : i8) {
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%clock = seq.to_clock %clk
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%true = hw.constant true
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%read = hw.array_get %mem[%addr] : !hw.array<4xi8>, i2
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%write = hw.array_inject %mem[%addr], %data : !hw.array<4xi8>, i2
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%next = comb.mux %we, %write, %mem : !hw.array<4xi8>
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%mem = seq.firreg %next clock %clock : !hw.array<4xi8>
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hw.output %read : i8
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}
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// CHECK: %[[clock:.+]] = seq.to_clock %clk
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// CHECK: %mem = seq.firmem 0, 1, undefined, undefined : <4 x 8, mask 1>
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// CHECK: %[[READ:.+]] = seq.firmem.read_port %mem[%addr], clock %[[clock]] enable %true
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// CHECK: seq.firmem.write_port %mem[%addr] = %data, clock %[[clock]] enable %we
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// CHECK: hw.output %[[READ]] : i8
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// CHECK-NOT: seq.firreg %{{.*}} : !hw.array<8192xi46>
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// CHECK-NOT: hw.array_get
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// CHECK-NOT: hw.array_inject
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// Test that transformation is skipped when mux has multiple uses
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// CHECK-LABEL: hw.module @shared_mux_test(
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hw.module @shared_mux_test(in %clk: i1, in %addr: i2, in %data: i8, in %we: i1, out other_out: !hw.array<4xi8>) {
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%clock = seq.to_clock %clk
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%write = hw.array_inject %mem[%addr], %data : !hw.array<4xi8>, i2
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%next = comb.mux %we, %write, %mem : !hw.array<4xi8>
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// CHECK: %mem = seq.firreg %{{.*}} clock %{{.*}} : !hw.array<4xi8>
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%mem = seq.firreg %next clock %clock : !hw.array<4xi8>
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// Mux result used elsewhere - should prevent transformation
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hw.output %next : !hw.array<4xi8>
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}
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// Test that transformation is skipped when register has multiple uses
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// CHECK-LABEL: hw.module @shared_reg_test(
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hw.module @shared_reg_test(in %clk: i1, in %addr: i2, in %data: i8, in %we: i1, out reg_out: !hw.array<4xi8>, out read_out: i8) {
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%clock = seq.to_clock %clk
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%read = hw.array_get %mem[%addr] : !hw.array<4xi8>, i2
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%write = hw.array_inject %mem[%addr], %data : !hw.array<4xi8>, i2
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%next = comb.mux %we, %write, %mem : !hw.array<4xi8>
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// CHECK: %mem = seq.firreg %{{.*}} clock %{{.*}} : !hw.array<4xi8>
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%mem = seq.firreg %next clock %clock : !hw.array<4xi8>
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// Register used elsewhere - should prevent transformation
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hw.output %mem, %read : !hw.array<4xi8>, i8
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}
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