mirror of https://github.com/llvm/circt.git
[firld] Add firld to link FIRRTL circuits (#8561)
This commit is contained in:
unlsycn
GitHub
parent
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commit
5dc56952a8
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@ -194,6 +194,10 @@ std::unique_ptr<mlir::Pass> createAdvancedLayerSinkPass();
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std::unique_ptr<mlir::Pass> createMaterializeDebugInfoPass();
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std::unique_ptr<mlir::Pass>
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createLinkCircuitsPass(mlir::StringRef baseCircuitName = "",
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bool noMangle = false);
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std::unique_ptr<mlir::Pass> createLintingPass();
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std::unique_ptr<mlir::Pass> createProbesToSignalsPass();
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@ -839,6 +839,22 @@ def MaterializeDebugInfo :
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let dependentDialects = ["debug::DebugDialect"];
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}
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def LinkCircuits : Pass<"firrtl-link-circuits", "mlir::ModuleOp"> {
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let summary = "Links multiple circuits into a single one";
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let description = [{
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This pass concatenates all circuits into one, iterates through all extmodules
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to find matching public module implementations, replacing them when possible
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and any remaining extmodules are treated as blackboxes.
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}];
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let constructor = "circt::firrtl::createLinkCircuitsPass()";
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let options = [
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Option<"baseCircuitName", "base-circuit", "std::string", "",
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"The base circuit name.">,
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Option<"noMangle", "no-mangle", "bool", "",
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"Do not perform private symbol mangling.">
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];
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}
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def Lint :
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Pass<"firrtl-lint", "firrtl::FModuleOp"> {
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let summary = "An analysis pass to detect static simulation failures.";
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@ -25,6 +25,7 @@ add_circt_dialect_library(CIRCTFIRRTLTransforms
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InjectDUTHierarchy.cpp
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InnerSymbolDCE.cpp
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LegacyWiring.cpp
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LinkCircuits.cpp
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Lint.cpp
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LayerMerge.cpp
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LayerSink.cpp
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@ -0,0 +1,253 @@
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//===- LinkCircuits.cpp - Merge FIRRTL circuits --------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This pass links multiple circuits into a single one.
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//
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//===----------------------------------------------------------------------===//
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#include "circt/Dialect/FIRRTL/FIRRTLAnnotationHelper.h"
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#include "circt/Dialect/FIRRTL/FIRRTLAnnotations.h"
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#include "circt/Dialect/FIRRTL/FIRRTLOps.h"
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#include "circt/Dialect/FIRRTL/FIRRTLTypes.h"
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#include "circt/Dialect/FIRRTL/Passes.h"
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#include "mlir/IR/Attributes.h"
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#include "mlir/IR/Builders.h"
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#include "mlir/IR/BuiltinAttributes.h"
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#include "mlir/IR/Diagnostics.h"
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#include "mlir/IR/Operation.h"
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#include "mlir/IR/SymbolTable.h"
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#include "mlir/Pass/Pass.h"
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#include "mlir/Support/LLVM.h"
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#include "llvm/ADT/MapVector.h"
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#include "llvm/ADT/STLExtras.h"
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#include <iterator>
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namespace circt {
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namespace firrtl {
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#define GEN_PASS_DEF_LINKCIRCUITS
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#include "circt/Dialect/FIRRTL/Passes.h.inc"
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} // namespace firrtl
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} // namespace circt
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using namespace mlir;
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using namespace circt;
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using namespace firrtl;
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namespace {
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struct LinkCircuitsPass
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: public circt::firrtl::impl::LinkCircuitsBase<LinkCircuitsPass> {
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void runOnOperation() override;
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LogicalResult mergeCircuits();
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LinkCircuitsPass(StringRef baseCircuitNameOption, bool noMangleOption) {
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baseCircuitName = std::string(baseCircuitNameOption);
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noMangle = noMangleOption;
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}
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};
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} // namespace
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template <typename CallableT>
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static DictionaryAttr transformAnnotationTarget(DictionaryAttr anno,
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CallableT transformTokensFn) {
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return DictionaryAttr::getWithSorted(
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anno.getContext(),
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to_vector(map_range(
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anno.getValue(), [&](NamedAttribute namedAttr) -> NamedAttribute {
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if (namedAttr.getName() == "target")
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if (auto target = dyn_cast<StringAttr>(namedAttr.getValue()))
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if (auto tokens = tokenizePath(target.getValue()))
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return {
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namedAttr.getName(),
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StringAttr::get(target.getContext(),
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transformTokensFn(tokens.value()).str())};
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return namedAttr;
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})));
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}
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static LogicalResult mangleCircuitSymbols(CircuitOp circuit) {
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auto circuitName = circuit.getNameAttr();
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llvm::MapVector<StringRef, Operation *> renameTable;
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auto symbolTable = SymbolTable(circuit.getOperation());
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auto manglePrivateSymbol = [&](SymbolOpInterface symbolOp) {
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auto symbolName = symbolOp.getNameAttr();
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auto newSymbolName =
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StringAttr::get(symbolOp->getContext(),
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circuitName.getValue() + "_" + symbolName.getValue());
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renameTable.insert(std::pair(symbolName.getValue(), symbolOp));
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return symbolTable.rename(symbolOp, newSymbolName);
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};
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for (auto &op : circuit.getOps()) {
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auto symbolOp = dyn_cast<SymbolOpInterface>(op);
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if (!symbolOp)
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continue;
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if (symbolOp.isPrivate())
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if (failed(manglePrivateSymbol(symbolOp)))
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return failure();
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}
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circuit.walk([&](Operation *op) {
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auto updateType = [&](Type type) -> Type {
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if (auto cls = dyn_cast<ClassType>(type))
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if (auto *newOp = renameTable.lookup(cls.getName()))
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return ClassType::get(FlatSymbolRefAttr::get(newOp),
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cls.getElements());
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return type;
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};
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auto updateTypeAttr = [&](Attribute attr) -> Attribute {
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if (auto typeAttr = dyn_cast<TypeAttr>(attr)) {
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auto newType = updateType(typeAttr.getValue());
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if (newType != typeAttr.getValue())
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return TypeAttr::get(newType);
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}
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return attr;
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};
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auto updateResults = [&](auto &&results) {
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for (auto result : results)
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if (auto newType = updateType(result.getType());
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newType != result.getType())
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result.setType(newType);
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};
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TypeSwitch<Operation *>(op)
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.Case<CircuitOp>([&](CircuitOp circuit) {
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SmallVector<Attribute> newAnnotations;
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llvm::transform(
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circuit.getAnnotationsAttr(), std::back_inserter(newAnnotations),
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[&](Attribute attr) {
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return transformAnnotationTarget(
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cast<DictionaryAttr>(attr), [&](TokenAnnoTarget &tokens) {
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if (auto *newModule = renameTable.lookup(tokens.module))
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tokens.module =
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cast<SymbolOpInterface>(newModule).getName();
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return tokens;
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});
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});
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circuit.setAnnotationsAttr(
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ArrayAttr::get(circuit.getContext(), newAnnotations));
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})
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.Case<ObjectOp>([&](ObjectOp obj) {
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auto resultTypeName = obj.getResult().getType().getName();
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if (auto *newOp = renameTable.lookup(resultTypeName))
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obj.getResult().setType(dyn_cast<ClassOp>(newOp).getInstanceType());
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})
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.Case<FModuleOp>([&](FModuleOp module) {
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SmallVector<Attribute> newPortTypes;
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llvm::transform(module.getPortTypesAttr().getValue(),
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std::back_inserter(newPortTypes), updateTypeAttr);
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module.setPortTypesAttr(
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ArrayAttr::get(module->getContext(), newPortTypes));
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updateResults(module.getBodyBlock()->getArguments());
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})
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.Case<InstanceOp>(
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[&](InstanceOp instance) { updateResults(instance->getResults()); })
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.Case<WireOp>([&](WireOp wire) { updateResults(wire->getResults()); })
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.Default([](Operation *op) {});
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});
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return success();
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}
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/// return if the incomingOp has been erased
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static FailureOr<bool> linkExtmodule(SymbolOpInterface collidingOp,
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SymbolOpInterface incomingOp) {
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if (!((isa<FExtModuleOp>(collidingOp) && isa<FModuleOp>(incomingOp)) ||
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(isa<FExtModuleOp>(incomingOp) && isa<FModuleOp>(collidingOp))))
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return failure();
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auto [definition, declaration] = isa<FModuleOp>(collidingOp)
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? std::pair(collidingOp, incomingOp)
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: std::pair(incomingOp, collidingOp);
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if (!definition.isPublic())
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return definition->emitOpError("should be a public symbol");
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if (!declaration.isPublic())
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return declaration->emitOpError("should be a public symbol");
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constexpr const StringRef attrsToCompare[] = {
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"portDirections", "portSymbols", "portNames", "portTypes", "layers"};
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auto allAttrsMatch = all_of(attrsToCompare, [&](StringRef attr) {
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return definition->getAttr(attr) == declaration->getAttr(attr);
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});
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if (!allAttrsMatch)
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return false;
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declaration->erase();
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return declaration == incomingOp;
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}
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LogicalResult LinkCircuitsPass::mergeCircuits() {
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auto module = getOperation();
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SmallVector<CircuitOp> circuits;
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for (CircuitOp circuitOp : module.getOps<CircuitOp>())
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circuits.push_back(circuitOp);
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auto builder = OpBuilder(module);
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builder.setInsertionPointToEnd(module.getBody());
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auto mergedCircuit = builder.create<CircuitOp>(
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module.getLoc(), StringAttr::get(&getContext(), baseCircuitName));
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SmallVector<Attribute> mergedAnnotations;
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for (auto circuit : circuits) {
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if (!noMangle)
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if (failed(mangleCircuitSymbols(circuit)))
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return circuit->emitError("failed to mangle private symbol");
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// TODO: other circuit attributes (such as enable_layers...)
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llvm::transform(circuit.getAnnotations().getValue(),
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std::back_inserter(mergedAnnotations), [&](Attribute attr) {
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return transformAnnotationTarget(
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cast<DictionaryAttr>(attr),
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[&](TokenAnnoTarget &tokens) {
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tokens.circuit = mergedCircuit.getName();
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return tokens;
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});
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});
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// reconstruct symbol table after each merge
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auto mergedSymbolTable = SymbolTable(mergedCircuit.getOperation());
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SmallVector<Operation *> opsToMove;
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for (auto &op : circuit.getOps())
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opsToMove.push_back(&op);
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for (auto *op : opsToMove) {
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if (auto symbolOp = dyn_cast<SymbolOpInterface>(op))
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if (auto collidingOp = cast_if_present<SymbolOpInterface>(
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mergedSymbolTable.lookup(symbolOp.getNameAttr()))) {
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auto opErased = linkExtmodule(collidingOp, symbolOp);
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if (failed(opErased))
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return mergedCircuit->emitError("has colliding symbol " +
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symbolOp.getName() +
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" which cannot be merged");
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if (opErased.value())
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continue;
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}
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op->moveBefore(mergedCircuit.getBodyBlock(),
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mergedCircuit.getBodyBlock()->end());
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}
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circuit->erase();
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}
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mergedCircuit.setAnnotationsAttr(
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ArrayAttr::get(mergedCircuit.getContext(), mergedAnnotations));
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return mlir::detail::verifySymbolTable(mergedCircuit);
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}
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void LinkCircuitsPass::runOnOperation() {
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if (failed(mergeCircuits()))
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signalPassFailure();
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}
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std::unique_ptr<Pass>
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circt::firrtl::createLinkCircuitsPass(StringRef baseCircuitName,
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bool noMangle) {
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return std::make_unique<LinkCircuitsPass>(baseCircuitName, noMangle);
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}
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@ -35,6 +35,7 @@ set(CIRCT_TEST_DEPENDS
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circt-translate
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circt-reduce
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handshake-runner
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firld
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firtool
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hlstool
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kanagawatool
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@ -0,0 +1,52 @@
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// RUN: split-file %s %t
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// RUN: firld %t/Outer.mlir %t/Inner.mlir --base-circuit Outer | FileCheck %s
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//--- Outer.mlir
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module {
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// CHECK: firrtl.circuit "Outer"
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firrtl.circuit "Outer" {
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// CHECK: firrtl.module @Outer(in %i: !firrtl.uint<32>, out %o: !firrtl.uint<32>) attributes {convention = #firrtl<convention scalarized>}
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firrtl.module @Outer(in %i: !firrtl.uint<32>, out %o: !firrtl.uint<32>) attributes {convention = #firrtl<convention scalarized>} {
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%io = firrtl.wire : !firrtl.bundle<i flip: uint<32>, o: uint<32>>
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%probe = firrtl.wire : !firrtl.bundle<>
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%0 = firrtl.subfield %io[i] : !firrtl.bundle<i flip: uint<32>, o: uint<32>>
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firrtl.connect %0, %i : !firrtl.uint<32>
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%1 = firrtl.subfield %io[o] : !firrtl.bundle<i flip: uint<32>, o: uint<32>>
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firrtl.connect %o, %1 : !firrtl.uint<32>
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%inner_i, %inner_o = firrtl.instance inner interesting_name @Inner(in i: !firrtl.uint<32>, out o: !firrtl.uint<32>)
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%inner_io = firrtl.wire : !firrtl.bundle<i flip: uint<32>, o: uint<32>>
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%inner_probe = firrtl.wire : !firrtl.bundle<>
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%2 = firrtl.subfield %inner_io[i] : !firrtl.bundle<i flip: uint<32>, o: uint<32>>
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firrtl.connect %inner_i, %2 : !firrtl.uint<32>
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%3 = firrtl.subfield %inner_io[o] : !firrtl.bundle<i flip: uint<32>, o: uint<32>>
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firrtl.connect %3, %inner_o : !firrtl.uint<32>
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%4 = firrtl.subfield %inner_io[i] : !firrtl.bundle<i flip: uint<32>, o: uint<32>>
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%5 = firrtl.subfield %io[i] : !firrtl.bundle<i flip: uint<32>, o: uint<32>>
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firrtl.connect %4, %5 : !firrtl.uint<32>
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%6 = firrtl.subfield %io[o] : !firrtl.bundle<i flip: uint<32>, o: uint<32>>
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%7 = firrtl.subfield %inner_io[o] : !firrtl.bundle<i flip: uint<32>, o: uint<32>>
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firrtl.connect %6, %7 : !firrtl.uint<32>
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}
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// CHECK-NOT: firrtl.extmodule
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firrtl.extmodule @Inner(in i: !firrtl.uint<32>, out o: !firrtl.uint<32>) attributes {defname = "Inner"}
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}
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}
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//--- Inner.mlir
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module {
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// CHECK-NOT: firrtl.circuit "Inner"
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firrtl.circuit "Inner" {
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// CHECK: firrtl.module @Inner(in %i: !firrtl.uint<32>, out %o: !firrtl.uint<32>) attributes {convention = #firrtl<convention scalarized>}
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firrtl.module @Inner(in %i: !firrtl.uint<32>, out %o: !firrtl.uint<32>) attributes {convention = #firrtl<convention scalarized>} {
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%io = firrtl.wire : !firrtl.bundle<i flip: uint<32>, o: uint<32>>
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%probe = firrtl.wire : !firrtl.bundle<>
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%0 = firrtl.subfield %io[i] : !firrtl.bundle<i flip: uint<32>, o: uint<32>>
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firrtl.connect %0, %i : !firrtl.uint<32>
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%1 = firrtl.subfield %io[o] : !firrtl.bundle<i flip: uint<32>, o: uint<32>>
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firrtl.connect %o, %1 : !firrtl.uint<32>
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%2 = firrtl.subfield %io[o] : !firrtl.bundle<i flip: uint<32>, o: uint<32>>
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%3 = firrtl.subfield %io[i] : !firrtl.bundle<i flip: uint<32>, o: uint<32>>
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firrtl.connect %2, %3 : !firrtl.uint<32>
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}
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}
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}
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@ -0,0 +1,48 @@
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// RUN: split-file %s %t
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// RUN: firld %t/Outer.mlir %t/Inner.mlir --base-circuit Outer | FileCheck %s
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// CHECK: firrtl.circuit "Outer" attributes {annotations = [{class = "circt.test", target = "~Outer|Outer>io"}, {class = "circt.test", target = "~Outer|Inner>io"}]}
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//--- Outer.mlir
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module {
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firrtl.circuit "Outer" attributes {annotations = [{class = "circt.test", target = "~Outer|Outer>io"}]} {
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firrtl.module @Outer(in %i: !firrtl.uint<32>, out %o: !firrtl.uint<32>) attributes {convention = #firrtl<convention scalarized>} {
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%io = firrtl.wire : !firrtl.bundle<i flip: uint<32>, o: uint<32>>
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%probe = firrtl.wire : !firrtl.bundle<>
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%0 = firrtl.subfield %io[i] : !firrtl.bundle<i flip: uint<32>, o: uint<32>>
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firrtl.connect %0, %i : !firrtl.uint<32>
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%1 = firrtl.subfield %io[o] : !firrtl.bundle<i flip: uint<32>, o: uint<32>>
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firrtl.connect %o, %1 : !firrtl.uint<32>
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%inner_i, %inner_o = firrtl.instance inner interesting_name @Inner(in i: !firrtl.uint<32>, out o: !firrtl.uint<32>)
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%inner_io = firrtl.wire : !firrtl.bundle<i flip: uint<32>, o: uint<32>>
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%inner_probe = firrtl.wire : !firrtl.bundle<>
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%2 = firrtl.subfield %inner_io[i] : !firrtl.bundle<i flip: uint<32>, o: uint<32>>
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firrtl.connect %inner_i, %2 : !firrtl.uint<32>
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%3 = firrtl.subfield %inner_io[o] : !firrtl.bundle<i flip: uint<32>, o: uint<32>>
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firrtl.connect %3, %inner_o : !firrtl.uint<32>
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%4 = firrtl.subfield %inner_io[i] : !firrtl.bundle<i flip: uint<32>, o: uint<32>>
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%5 = firrtl.subfield %io[i] : !firrtl.bundle<i flip: uint<32>, o: uint<32>>
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firrtl.connect %4, %5 : !firrtl.uint<32>
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%6 = firrtl.subfield %io[o] : !firrtl.bundle<i flip: uint<32>, o: uint<32>>
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%7 = firrtl.subfield %inner_io[o] : !firrtl.bundle<i flip: uint<32>, o: uint<32>>
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firrtl.connect %6, %7 : !firrtl.uint<32>
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}
|
||||
firrtl.extmodule @Inner(in i: !firrtl.uint<32>, out o: !firrtl.uint<32>) attributes {defname = "Inner"}
|
||||
}
|
||||
}
|
||||
|
||||
//--- Inner.mlir
|
||||
module {
|
||||
firrtl.circuit "Inner" attributes {annotations = [{class = "circt.test", target = "~Inner|Inner>io"}]} {
|
||||
firrtl.module @Inner(in %i: !firrtl.uint<32>, out %o: !firrtl.uint<32>) attributes {convention = #firrtl<convention scalarized>} {
|
||||
%io = firrtl.wire : !firrtl.bundle<i flip: uint<32>, o: uint<32>>
|
||||
%probe = firrtl.wire : !firrtl.bundle<>
|
||||
%0 = firrtl.subfield %io[i] : !firrtl.bundle<i flip: uint<32>, o: uint<32>>
|
||||
firrtl.connect %0, %i : !firrtl.uint<32>
|
||||
%1 = firrtl.subfield %io[o] : !firrtl.bundle<i flip: uint<32>, o: uint<32>>
|
||||
firrtl.connect %o, %1 : !firrtl.uint<32>
|
||||
%2 = firrtl.subfield %io[o] : !firrtl.bundle<i flip: uint<32>, o: uint<32>>
|
||||
%3 = firrtl.subfield %io[i] : !firrtl.bundle<i flip: uint<32>, o: uint<32>>
|
||||
firrtl.connect %2, %3 : !firrtl.uint<32>
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,41 @@
|
|||
// RUN: firld %s --base-circuit Outer | FileCheck %s
|
||||
|
||||
module {
|
||||
// CHECK: {annotations = [{class = "circt.test", target = "~Outer|Outer_Inner>io"}]}
|
||||
firrtl.circuit "Outer" attributes {annotations = [{class = "circt.test", target = "~Outer|Inner>io"}]} {
|
||||
firrtl.module @Outer(in %i: !firrtl.uint<32>, out %o: !firrtl.uint<32>) attributes {convention = #firrtl<convention scalarized>} {
|
||||
%io = firrtl.wire : !firrtl.bundle<i flip: uint<32>, o: uint<32>>
|
||||
%probe = firrtl.wire : !firrtl.bundle<>
|
||||
%0 = firrtl.subfield %io[i] : !firrtl.bundle<i flip: uint<32>, o: uint<32>>
|
||||
firrtl.connect %0, %i : !firrtl.uint<32>
|
||||
%1 = firrtl.subfield %io[o] : !firrtl.bundle<i flip: uint<32>, o: uint<32>>
|
||||
firrtl.connect %o, %1 : !firrtl.uint<32>
|
||||
%inner_i, %inner_o = firrtl.instance inner interesting_name @Inner(in i: !firrtl.uint<32>, out o: !firrtl.uint<32>)
|
||||
%inner_io = firrtl.wire : !firrtl.bundle<i flip: uint<32>, o: uint<32>>
|
||||
%inner_probe = firrtl.wire : !firrtl.bundle<>
|
||||
%2 = firrtl.subfield %inner_io[i] : !firrtl.bundle<i flip: uint<32>, o: uint<32>>
|
||||
firrtl.connect %inner_i, %2 : !firrtl.uint<32>
|
||||
%3 = firrtl.subfield %inner_io[o] : !firrtl.bundle<i flip: uint<32>, o: uint<32>>
|
||||
firrtl.connect %3, %inner_o : !firrtl.uint<32>
|
||||
%4 = firrtl.subfield %inner_io[i] : !firrtl.bundle<i flip: uint<32>, o: uint<32>>
|
||||
%5 = firrtl.subfield %io[i] : !firrtl.bundle<i flip: uint<32>, o: uint<32>>
|
||||
firrtl.connect %4, %5 : !firrtl.uint<32>
|
||||
%6 = firrtl.subfield %io[o] : !firrtl.bundle<i flip: uint<32>, o: uint<32>>
|
||||
%7 = firrtl.subfield %inner_io[o] : !firrtl.bundle<i flip: uint<32>, o: uint<32>>
|
||||
firrtl.connect %6, %7 : !firrtl.uint<32>
|
||||
}
|
||||
|
||||
firrtl.module private @Inner(in %i: !firrtl.uint<32>, out %o: !firrtl.uint<32>) attributes {convention = #firrtl<convention scalarized>} {
|
||||
%io = firrtl.wire : !firrtl.bundle<i flip: uint<32>, o: uint<32>>
|
||||
%probe = firrtl.wire : !firrtl.bundle<>
|
||||
%0 = firrtl.subfield %io[i] : !firrtl.bundle<i flip: uint<32>, o: uint<32>>
|
||||
firrtl.connect %0, %i : !firrtl.uint<32>
|
||||
%1 = firrtl.subfield %io[o] : !firrtl.bundle<i flip: uint<32>, o: uint<32>>
|
||||
firrtl.connect %o, %1 : !firrtl.uint<32>
|
||||
%2 = firrtl.subfield %io[o] : !firrtl.bundle<i flip: uint<32>, o: uint<32>>
|
||||
%3 = firrtl.subfield %io[i] : !firrtl.bundle<i flip: uint<32>, o: uint<32>>
|
||||
firrtl.connect %2, %3 : !firrtl.uint<32>
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,23 @@
|
|||
// RUN: firld %s --base-circuit Outer | FileCheck %s
|
||||
|
||||
module {
|
||||
firrtl.circuit "Outer" {
|
||||
// CHECK: firrtl.class private @Outer_InnerOM
|
||||
firrtl.class private @InnerOM(out %width: !firrtl.integer) {
|
||||
%0 = firrtl.integer 16
|
||||
firrtl.propassign %width, %0 : !firrtl.integer
|
||||
}
|
||||
// CHECK: firrtl.module private @Outer_Inner(in %in: !firrtl.uint<16>, out %out: !firrtl.uint<16>, out %om: !firrtl.class<@Outer_InnerOM(out width: !firrtl.integer)>) {
|
||||
firrtl.module private @Inner(in %in: !firrtl.uint<16>, out %out: !firrtl.uint<16>, out %om: !firrtl.class<@InnerOM(out width: !firrtl.integer)>) {
|
||||
firrtl.matchingconnect %out, %in : !firrtl.uint<16>
|
||||
// CHECK: %omInstance = firrtl.object @Outer_InnerOM(out width: !firrtl.integer)
|
||||
%omInstance = firrtl.object @InnerOM(out width: !firrtl.integer)
|
||||
// CHECK: firrtl.propassign %om, %omInstance : !firrtl.class<@Outer_InnerOM(out width: !firrtl.integer)>
|
||||
firrtl.propassign %om, %omInstance : !firrtl.class<@InnerOM(out width: !firrtl.integer)>
|
||||
}
|
||||
firrtl.module @Outer() attributes {convention = #firrtl<convention scalarized>} {
|
||||
// CHECK: %Inner_in, %Inner_out, %Inner_om = firrtl.instance Inner interesting_name @Outer_Inner(in in: !firrtl.uint<16>, out out: !firrtl.uint<16>, out om: !firrtl.class<@Outer_InnerOM(out width: !firrtl.integer)>)
|
||||
%Inner_in, %Inner_out, %Inner_om = firrtl.instance Inner interesting_name @Inner(in in: !firrtl.uint<16>, out out: !firrtl.uint<16>, out om: !firrtl.class<@InnerOM(out width: !firrtl.integer)>)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -62,8 +62,8 @@ tools = [
|
|||
'circt-capi-firrtl-test', 'circt-capi-firtool-test',
|
||||
'circt-capi-rtg-pipelines-test', 'circt-capi-rtg-test',
|
||||
'circt-capi-rtgtest-test', 'circt-dis', 'circt-lec', 'circt-reduce',
|
||||
'circt-synth', 'circt-test', 'circt-translate', 'firtool', 'hlstool',
|
||||
'om-linker', 'kanagawatool'
|
||||
'circt-synth', 'circt-test', 'circt-translate', 'firld', 'firtool',
|
||||
'hlstool', 'om-linker', 'kanagawatool'
|
||||
]
|
||||
|
||||
if "CIRCT_OPT_CHECK_IR_ROUNDTRIP" in os.environ:
|
||||
|
|
|
|||
|
|
@ -11,6 +11,7 @@ add_subdirectory(circt-rtl-sim)
|
|||
add_subdirectory(circt-synth)
|
||||
add_subdirectory(circt-test)
|
||||
add_subdirectory(circt-translate)
|
||||
add_subdirectory(firld)
|
||||
add_subdirectory(firtool)
|
||||
add_subdirectory(handshake-runner)
|
||||
add_subdirectory(hlstool)
|
||||
|
|
|
|||
|
|
@ -0,0 +1,23 @@
|
|||
set(LLVM_LINK_COMPONENTS
|
||||
Support
|
||||
)
|
||||
|
||||
get_property(dialect_libs GLOBAL PROPERTY CIRCT_DIALECT_LIBS)
|
||||
get_property(mlir_dialect_libs GLOBAL PROPERTY MLIR_DIALECT_LIBS)
|
||||
|
||||
set(LIBS
|
||||
${dialect_libs}
|
||||
${mlir_dialect_libs}
|
||||
|
||||
MLIRIR
|
||||
MLIRBytecodeReader
|
||||
MLIRBytecodeWriter
|
||||
MLIRParser
|
||||
MLIRSupport
|
||||
)
|
||||
|
||||
add_circt_tool(firld firld.cpp DEPENDS ${LIBS})
|
||||
target_link_libraries(firld PRIVATE ${LIBS})
|
||||
|
||||
llvm_update_compile_flags(firld)
|
||||
mlir_check_all_link_libraries(firld)
|
||||
|
|
@ -0,0 +1,186 @@
|
|||
//===- firld.cpp - Link multiple circuits together ------------------------===//
|
||||
//
|
||||
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
|
||||
// See https://llvm.org/LICENSE.txt for license information.
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
//
|
||||
// Link FIRRTL circuits (.mlir or .mlirbc files) into one.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
#include "circt/Dialect/FIRRTL/FIRParser.h"
|
||||
#include "circt/Dialect/FIRRTL/FIRRTLOps.h"
|
||||
#include "circt/Dialect/FIRRTL/Passes.h"
|
||||
#include "circt/InitAllDialects.h"
|
||||
#include "circt/Support/Version.h"
|
||||
#include "mlir/Bytecode/BytecodeReader.h"
|
||||
#include "mlir/Bytecode/BytecodeWriter.h"
|
||||
#include "mlir/Dialect/Transform/IR/Utils.h"
|
||||
#include "mlir/IR/Block.h"
|
||||
#include "mlir/IR/Builders.h"
|
||||
#include "mlir/IR/BuiltinAttributes.h"
|
||||
#include "mlir/IR/Diagnostics.h"
|
||||
#include "mlir/IR/Location.h"
|
||||
#include "mlir/IR/MLIRContext.h"
|
||||
#include "mlir/IR/Operation.h"
|
||||
#include "mlir/IR/OperationSupport.h"
|
||||
#include "mlir/Parser/Parser.h"
|
||||
#include "mlir/Pass/PassManager.h"
|
||||
#include "mlir/Support/FileUtilities.h"
|
||||
#include "llvm/ADT/StringRef.h"
|
||||
#include "llvm/Support/Casting.h"
|
||||
#include "llvm/Support/CommandLine.h"
|
||||
#include "llvm/Support/InitLLVM.h"
|
||||
#include "llvm/Support/LogicalResult.h"
|
||||
#include "llvm/Support/SourceMgr.h"
|
||||
#include "llvm/Support/ToolOutputFile.h"
|
||||
#include "llvm/Support/WithColor.h"
|
||||
#include "llvm/Support/raw_ostream.h"
|
||||
|
||||
#include <string>
|
||||
|
||||
using namespace llvm;
|
||||
using namespace mlir;
|
||||
using namespace circt;
|
||||
|
||||
static constexpr const char toolName[] = "firld";
|
||||
static cl::OptionCategory mainCategory("firld Options");
|
||||
|
||||
static cl::list<std::string> inputFilenames(cl::Positional,
|
||||
cl::desc("<input files>"),
|
||||
cl::cat(mainCategory));
|
||||
|
||||
static cl::opt<std::string> baseCircuitName("base-circuit", cl::Required,
|
||||
cl::desc("Base circuit name"),
|
||||
cl::value_desc("circuit name"),
|
||||
cl::cat(mainCategory));
|
||||
|
||||
static cl::opt<std::string> outputFilename("o",
|
||||
cl::desc("Override output filename"),
|
||||
cl::value_desc("filename"),
|
||||
cl::init("-"),
|
||||
cl::cat(mainCategory));
|
||||
|
||||
static cl::opt<bool>
|
||||
emitBytecode("emit-bytecode",
|
||||
cl::desc("Emit bytecode when generating MLIR output"),
|
||||
cl::init(false), cl::cat(mainCategory));
|
||||
|
||||
static cl::opt<bool> force("f", cl::desc("Enable binary output on terminals"),
|
||||
cl::init(false), cl::cat(mainCategory));
|
||||
|
||||
static cl::opt<bool>
|
||||
noMangle("no-mangle", cl::desc("Do not perform private symbol mangling"),
|
||||
cl::init(false), cl::cat(mainCategory));
|
||||
|
||||
static LogicalResult emitError(const Twine &err) {
|
||||
WithColor::error(errs(), toolName) << err << "\n";
|
||||
return failure();
|
||||
}
|
||||
|
||||
static bool checkBytecodeOutputToConsole(raw_ostream &os) {
|
||||
if (os.is_displayed()) {
|
||||
WithColor::warning(errs(), toolName)
|
||||
<< "you're attempting to print out a bytecode file."
|
||||
<< " This is inadvisable as it may cause display problems\n";
|
||||
WithColor::remark(errs(), toolName)
|
||||
<< "if you really want to do this, force output with the `-f` option\n";
|
||||
return true;
|
||||
}
|
||||
return false;
|
||||
}
|
||||
|
||||
static LogicalResult printOp(Operation *op, raw_ostream &os) {
|
||||
if (emitBytecode && (force || !checkBytecodeOutputToConsole(os)))
|
||||
return writeBytecodeToFile(op, os, BytecodeWriterConfig(getCirctVersion()));
|
||||
op->print(os);
|
||||
return success();
|
||||
}
|
||||
|
||||
static LogicalResult mergeModules(MLIRContext &context,
|
||||
SmallVector<OwningOpRef<ModuleOp>> &&modules,
|
||||
ModuleOp mergedModule) {
|
||||
// destroy original modules after merge
|
||||
auto modulesToMerge = std::move(modules);
|
||||
|
||||
// firrtl.circuit doesn't have sym_name hence we have no need to process
|
||||
// SymbolTable
|
||||
SmallVector<Operation *> opsToMove;
|
||||
std::set<StringRef> circuitNames;
|
||||
for (auto &module : modulesToMerge) {
|
||||
for (auto &op : module->getBody()->getOperations()) {
|
||||
if (auto circuit = dyn_cast<firrtl::CircuitOp>(op)) {
|
||||
opsToMove.push_back(&op);
|
||||
circuitNames.insert(
|
||||
cast<StringAttr>(circuit->getAttr("name")).getValue());
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (circuitNames.size() != opsToMove.size())
|
||||
return emitError(
|
||||
"Duplicate circuit names detected, all circuit names must be unique");
|
||||
if (circuitNames.find(baseCircuitName) == circuitNames.end())
|
||||
return emitError("Base circuit '" + baseCircuitName +
|
||||
"' not found in circuit names");
|
||||
|
||||
for (auto *op : opsToMove)
|
||||
op->moveBefore(mergedModule.getBody(), mergedModule.getBody()->end());
|
||||
|
||||
return success();
|
||||
}
|
||||
|
||||
static LogicalResult execute(MLIRContext &context) {
|
||||
std::string errorMessage;
|
||||
SmallVector<OwningOpRef<ModuleOp>> modules;
|
||||
for (const auto &inputFile : inputFilenames) {
|
||||
auto input = openInputFile(inputFile, &errorMessage);
|
||||
if (!input)
|
||||
return emitError(errorMessage);
|
||||
|
||||
SourceMgr srcMgr;
|
||||
srcMgr.AddNewSourceBuffer(std::move(input), SMLoc());
|
||||
if (auto module = parseSourceFile<ModuleOp>(srcMgr, &context)) {
|
||||
modules.push_back(std::move(module));
|
||||
} else
|
||||
return emitError("Failed to parse input file:" + inputFile);
|
||||
}
|
||||
|
||||
auto mergedModule =
|
||||
OwningOpRef<ModuleOp>(ModuleOp::create(UnknownLoc::get(&context)));
|
||||
if (failed(mergeModules(context, std::move(modules), mergedModule.get())))
|
||||
return emitError("Failed to merge MLIR modules");
|
||||
|
||||
PassManager pm(&context);
|
||||
pm.addPass(firrtl::createLinkCircuitsPass(baseCircuitName, noMangle));
|
||||
if (failed(pm.run(mergedModule.get())))
|
||||
return emitError("Failed to link circuits together");
|
||||
|
||||
std::optional<std::unique_ptr<ToolOutputFile>> outputFile;
|
||||
outputFile.emplace(openOutputFile(outputFilename, &errorMessage));
|
||||
if (!(*outputFile))
|
||||
return emitError(errorMessage);
|
||||
|
||||
if (failed(printOp(*mergedModule, (*outputFile)->os())))
|
||||
return emitError("Failed to print output to" + outputFilename);
|
||||
if (outputFile.has_value())
|
||||
(*outputFile)->keep();
|
||||
|
||||
return success();
|
||||
}
|
||||
|
||||
int main(int argc, char **argv) {
|
||||
InitLLVM y(argc, argv);
|
||||
setBugReportMsg(circtBugReportMsg);
|
||||
|
||||
DialectRegistry registry;
|
||||
circt::registerAllDialects(registry);
|
||||
|
||||
cl::HideUnrelatedOptions({&mainCategory, &getColorCategory()});
|
||||
cl::ParseCommandLineOptions(argc, argv, "FIRRTL Circuits Linker\n");
|
||||
|
||||
MLIRContext context(registry);
|
||||
exit(failed(execute(context)));
|
||||
}
|
||||
Loading…
Reference in New Issue