diff --git a/lib/CAPI/Dialect/MSFT.cpp b/lib/CAPI/Dialect/MSFT.cpp index 909ddd9047..3922448608 100644 --- a/lib/CAPI/Dialect/MSFT.cpp +++ b/lib/CAPI/Dialect/MSFT.cpp @@ -165,8 +165,9 @@ void mlirMSFTAddPhysLocationAttr(MlirOperation cOp, const char *entityName, PhysLocationAttr loc = PhysLocationAttr::get( ctxt, PrimitiveTypeAttr::get(ctxt, type), x, y, num); StringAttr entity = StringAttr::get(ctxt, entityName); - OpBuilder(op).create(op->getLoc(), loc, entity, - FlatSymbolRefAttr::get(op)); + auto builder = OpBuilder(op); + PDPhysLocationOp::create(builder, op->getLoc(), loc, entity, + FlatSymbolRefAttr::get(op)); op->setAttr(entity, loc); } diff --git a/lib/Conversion/AIGToComb/AIGToComb.cpp b/lib/Conversion/AIGToComb/AIGToComb.cpp index 9d128b0258..27d9aea4ff 100644 --- a/lib/Conversion/AIGToComb/AIGToComb.cpp +++ b/lib/Conversion/AIGToComb/AIGToComb.cpp @@ -39,7 +39,7 @@ struct AIGAndInverterOpConversion : OpConversionPattern { // Convert to comb.and + comb.xor + hw.constant auto width = op.getResult().getType().getIntOrFloatBitWidth(); auto allOnes = - rewriter.create(op.getLoc(), APInt::getAllOnes(width)); + hw::ConstantOp::create(rewriter, op.getLoc(), APInt::getAllOnes(width)); SmallVector operands; operands.reserve(op.getNumOperands()); for (auto [input, inverted] : llvm::zip(op.getOperands(), op.getInverted())) diff --git a/lib/Conversion/AffineToLoopSchedule/AffineToLoopSchedule.cpp b/lib/Conversion/AffineToLoopSchedule/AffineToLoopSchedule.cpp index 53921674f3..77875dfaf0 100644 --- a/lib/Conversion/AffineToLoopSchedule/AffineToLoopSchedule.cpp +++ b/lib/Conversion/AffineToLoopSchedule/AffineToLoopSchedule.cpp @@ -432,8 +432,8 @@ LogicalResult AffineToLoopSchedule::createLoopSchedulePipeline( Value lowerBound = lowerAffineLowerBound(innerLoop, builder); Value upperBound = lowerAffineUpperBound(innerLoop, builder); int64_t stepValue = innerLoop.getStep().getSExtValue(); - auto step = builder.create( - IntegerAttr::get(builder.getIndexType(), stepValue)); + auto step = arith::ConstantOp::create( + builder, IntegerAttr::get(builder.getIndexType(), stepValue)); // Create the pipeline op, with the same result types as the inner loop. An // iter arg is created for the induction variable. @@ -451,16 +451,16 @@ LogicalResult AffineToLoopSchedule::createLoopSchedulePipeline( if (auto tripCount = getConstantTripCount(forOp)) tripCountAttr = builder.getI64IntegerAttr(*tripCount); - auto pipeline = builder.create( - resultTypes, ii, tripCountAttr, iterArgs); + auto pipeline = LoopSchedulePipelineOp::create(builder, resultTypes, ii, + tripCountAttr, iterArgs); // Create the condition, which currently just compares the induction variable // to the upper bound. Block &condBlock = pipeline.getCondBlock(); builder.setInsertionPointToStart(&condBlock); - auto cmpResult = builder.create( - builder.getI1Type(), arith::CmpIPredicate::ult, condBlock.getArgument(0), - upperBound); + auto cmpResult = arith::CmpIOp::create(builder, builder.getI1Type(), + arith::CmpIPredicate::ult, + condBlock.getArgument(0), upperBound); condBlock.getTerminator()->insertOperands(0, {cmpResult}); // Add the non-yield operations to their start time groups. @@ -581,7 +581,7 @@ LogicalResult AffineToLoopSchedule::createLoopSchedulePipeline( auto startTimeAttr = builder.getIntegerAttr( builder.getIntegerType(64, /*isSigned=*/true), startTime); auto stage = - builder.create(stageTypes, startTimeAttr); + LoopSchedulePipelineStageOp::create(builder, stageTypes, startTimeAttr); auto &stageBlock = stage.getBodyBlock(); auto *stageTerminator = stageBlock.getTerminator(); builder.setInsertionPointToStart(&stageBlock); @@ -620,7 +620,7 @@ LogicalResult AffineToLoopSchedule::createLoopSchedulePipeline( // Add the induction variable increment to the first stage. if (startTime == 0) { auto incResult = - builder.create(stagesBlock.getArgument(0), step); + arith::AddIOp::create(builder, stagesBlock.getArgument(0), step); stageTerminator->insertOperands(stageTerminator->getNumOperands(), incResult->getResults()); } diff --git a/lib/Conversion/ArcToLLVM/LowerArcToLLVM.cpp b/lib/Conversion/ArcToLLVM/LowerArcToLLVM.cpp index fb7feddc02..9624db512a 100644 --- a/lib/Conversion/ArcToLLVM/LowerArcToLLVM.cpp +++ b/lib/Conversion/ArcToLLVM/LowerArcToLLVM.cpp @@ -64,14 +64,14 @@ struct ModelOpLowering : public OpConversionPattern { { IRRewriter::InsertionGuard guard(rewriter); rewriter.setInsertionPointToEnd(&op.getBodyBlock()); - rewriter.create(op.getLoc()); + func::ReturnOp::create(rewriter, op.getLoc()); } auto funcName = rewriter.getStringAttr(evalSymbolFromModelName(op.getName())); auto funcType = rewriter.getFunctionType(op.getBody().getArgumentTypes(), {}); auto func = - rewriter.create(op.getLoc(), funcName, funcType); + mlir::func::FuncOp::create(rewriter, op.getLoc(), funcName, funcType); rewriter.inlineRegionBefore(op.getRegion(), func.getBody(), func.end()); rewriter.eraseOp(op); return success(); @@ -107,9 +107,9 @@ struct AllocStateLikeOpLowering : public OpConversionPattern { auto offsetAttr = op->template getAttrOfType("offset"); if (!offsetAttr) return failure(); - Value ptr = rewriter.create( - op->getLoc(), adaptor.getStorage().getType(), rewriter.getI8Type(), - adaptor.getStorage(), + Value ptr = LLVM::GEPOp::create( + rewriter, op->getLoc(), adaptor.getStorage().getType(), + rewriter.getI8Type(), adaptor.getStorage(), LLVM::GEPArg(offsetAttr.getValue().getZExtValue())); rewriter.replaceOp(op, ptr); return success(); @@ -135,9 +135,9 @@ struct StateWriteOpLowering : public OpConversionPattern { if (adaptor.getCondition()) { rewriter.replaceOpWithNewOp( op, adaptor.getCondition(), [&](auto &builder, auto loc) { - builder.template create(loc, adaptor.getValue(), - adaptor.getState()); - builder.template create(loc); + LLVM::StoreOp::create(builder, loc, adaptor.getValue(), + adaptor.getState()); + scf::YieldOp::create(builder, loc); }); } else { rewriter.replaceOpWithNewOp(op, adaptor.getValue(), @@ -155,9 +155,9 @@ struct AllocMemoryOpLowering : public OpConversionPattern { auto offsetAttr = op->getAttrOfType("offset"); if (!offsetAttr) return failure(); - Value ptr = rewriter.create( - op.getLoc(), adaptor.getStorage().getType(), rewriter.getI8Type(), - adaptor.getStorage(), + Value ptr = LLVM::GEPOp::create( + rewriter, op.getLoc(), adaptor.getStorage().getType(), + rewriter.getI8Type(), adaptor.getStorage(), LLVM::GEPArg(offsetAttr.getValue().getZExtValue())); rewriter.replaceOp(op, ptr); @@ -170,11 +170,11 @@ struct StorageGetOpLowering : public OpConversionPattern { LogicalResult matchAndRewrite(arc::StorageGetOp op, OpAdaptor adaptor, ConversionPatternRewriter &rewriter) const final { - Value offset = rewriter.create( - op.getLoc(), rewriter.getI32Type(), op.getOffsetAttr()); - Value ptr = rewriter.create( - op.getLoc(), adaptor.getStorage().getType(), rewriter.getI8Type(), - adaptor.getStorage(), offset); + Value offset = LLVM::ConstantOp::create( + rewriter, op.getLoc(), rewriter.getI32Type(), op.getOffsetAttr()); + Value ptr = LLVM::GEPOp::create( + rewriter, op.getLoc(), adaptor.getStorage().getType(), + rewriter.getI8Type(), adaptor.getStorage(), offset); rewriter.replaceOp(op, ptr); return success(); } @@ -190,13 +190,14 @@ static MemoryAccess prepareMemoryAccess(Location loc, Value memory, ConversionPatternRewriter &rewriter) { auto zextAddrType = rewriter.getIntegerType( cast(address.getType()).getWidth() + 1); - Value addr = rewriter.create(loc, zextAddrType, address); - Value addrLimit = rewriter.create( - loc, zextAddrType, rewriter.getI32IntegerAttr(type.getNumWords())); - Value withinBounds = rewriter.create( - loc, LLVM::ICmpPredicate::ult, addr, addrLimit); - Value ptr = rewriter.create( - loc, LLVM::LLVMPointerType::get(memory.getContext()), + Value addr = LLVM::ZExtOp::create(rewriter, loc, zextAddrType, address); + Value addrLimit = + LLVM::ConstantOp::create(rewriter, loc, zextAddrType, + rewriter.getI32IntegerAttr(type.getNumWords())); + Value withinBounds = LLVM::ICmpOp::create( + rewriter, loc, LLVM::ICmpPredicate::ult, addr, addrLimit); + Value ptr = LLVM::GEPOp::create( + rewriter, loc, LLVM::LLVMPointerType::get(memory.getContext()), rewriter.getIntegerType(type.getStride() * 8), memory, ValueRange{addr}); return {ptr, withinBounds}; } @@ -217,14 +218,14 @@ struct MemoryReadOpLowering : public OpConversionPattern { rewriter.replaceOpWithNewOp( op, access.withinBounds, [&](auto &builder, auto loc) { - Value loadOp = builder.template create( - loc, memoryType.getWordType(), access.ptr); - builder.template create(loc, loadOp); + Value loadOp = LLVM::LoadOp::create( + builder, loc, memoryType.getWordType(), access.ptr); + scf::YieldOp::create(builder, loc, loadOp); }, [&](auto &builder, auto loc) { - Value zeroValue = builder.template create( - loc, type, builder.getI64IntegerAttr(0)); - builder.template create(loc, zeroValue); + Value zeroValue = LLVM::ConstantOp::create( + builder, loc, type, builder.getI64IntegerAttr(0)); + scf::YieldOp::create(builder, loc, zeroValue); }); return success(); } @@ -240,15 +241,14 @@ struct MemoryWriteOpLowering : public OpConversionPattern { cast(op.getMemory().getType()), rewriter); auto enable = access.withinBounds; if (adaptor.getEnable()) - enable = rewriter.create(op.getLoc(), adaptor.getEnable(), - enable); + enable = LLVM::AndOp::create(rewriter, op.getLoc(), adaptor.getEnable(), + enable); // Only attempt to write the memory if the address is within bounds. rewriter.replaceOpWithNewOp( op, enable, [&](auto &builder, auto loc) { - builder.template create(loc, adaptor.getData(), - access.ptr); - builder.template create(loc); + LLVM::StoreOp::create(builder, loc, adaptor.getData(), access.ptr); + scf::YieldOp::create(builder, loc); }); return success(); } @@ -272,8 +272,8 @@ struct ClockInvOpLowering : public OpConversionPattern { LogicalResult matchAndRewrite(seq::ClockInverterOp op, OpAdaptor adaptor, ConversionPatternRewriter &rewriter) const final { - auto constTrue = rewriter.create(op->getLoc(), - rewriter.getI1Type(), 1); + auto constTrue = LLVM::ConstantOp::create(rewriter, op->getLoc(), + rewriter.getI1Type(), 1); rewriter.replaceOpWithNewOp(op, adaptor.getInput(), constTrue); return success(); } @@ -348,9 +348,9 @@ protected: Value createPtrToPortState(ConversionPatternRewriter &rewriter, Location loc, Value state, const StateInfo &port) const { MLIRContext *ctx = rewriter.getContext(); - return rewriter.create(loc, LLVM::LLVMPointerType::get(ctx), - IntegerType::get(ctx, 8), state, - LLVM::GEPArg(port.offset)); + return LLVM::GEPOp::create(rewriter, loc, LLVM::LLVMPointerType::get(ctx), + IntegerType::get(ctx, 8), state, + LLVM::GEPArg(port.offset)); } llvm::DenseMap &modelInfo; @@ -392,23 +392,23 @@ struct SimInstantiateOpLowering return freeFunc; Location loc = op.getLoc(); - Value numStateBytes = rewriter.create( - loc, convertedIndex, model.numStateBytes); - Value allocated = rewriter - .create(loc, mallocFunc.value(), - ValueRange{numStateBytes}) + Value numStateBytes = LLVM::ConstantOp::create( + rewriter, loc, convertedIndex, model.numStateBytes); + Value allocated = LLVM::CallOp::create(rewriter, loc, mallocFunc.value(), + ValueRange{numStateBytes}) .getResult(); Value zero = - rewriter.create(loc, rewriter.getI8Type(), 0); - rewriter.create(loc, allocated, zero, numStateBytes, false); + LLVM::ConstantOp::create(rewriter, loc, rewriter.getI8Type(), 0); + LLVM::MemsetOp::create(rewriter, loc, allocated, zero, numStateBytes, + false); // Call the model's 'initial' function if present. if (model.initialFnSymbol) { auto initialFnType = LLVM::LLVMFunctionType::get( LLVM::LLVMVoidType::get(op.getContext()), {LLVM::LLVMPointerType::get(op.getContext())}); - rewriter.create(loc, initialFnType, model.initialFnSymbol, - ValueRange{allocated}); + LLVM::CallOp::create(rewriter, loc, initialFnType, model.initialFnSymbol, + ValueRange{allocated}); } // Execute the body. @@ -420,11 +420,12 @@ struct SimInstantiateOpLowering auto finalFnType = LLVM::LLVMFunctionType::get( LLVM::LLVMVoidType::get(op.getContext()), {LLVM::LLVMPointerType::get(op.getContext())}); - rewriter.create(loc, finalFnType, model.finalFnSymbol, - ValueRange{allocated}); + LLVM::CallOp::create(rewriter, loc, finalFnType, model.finalFnSymbol, + ValueRange{allocated}); } - rewriter.create(loc, freeFunc.value(), ValueRange{allocated}); + LLVM::CallOp::create(rewriter, loc, freeFunc.value(), + ValueRange{allocated}); rewriter.eraseOp(op); return success(); @@ -543,14 +544,14 @@ struct SimEmitValueOpLowering sizeOfSizeT.getFixedValue() <= std::numeric_limits::max()); bool truncated = false; if (valueType.getWidth() > sizeOfSizeT) { - toPrint = rewriter.create( - loc, IntegerType::get(getContext(), sizeOfSizeT.getFixedValue()), - toPrint); + toPrint = LLVM::TruncOp::create( + rewriter, loc, + IntegerType::get(getContext(), sizeOfSizeT.getFixedValue()), toPrint); truncated = true; } else if (valueType.getWidth() < sizeOfSizeT) - toPrint = rewriter.create( - loc, IntegerType::get(getContext(), sizeOfSizeT.getFixedValue()), - toPrint); + toPrint = LLVM::ZExtOp::create( + rewriter, loc, + IntegerType::get(getContext(), sizeOfSizeT.getFixedValue()), toPrint); // Lookup of create printf function symbol. auto printfFunc = LLVM::lookupOrCreateFn( @@ -579,14 +580,15 @@ struct SimEmitValueOpLowering rewriter.setInsertionPointToStart(moduleOp.getBody()); auto globalType = LLVM::LLVMArrayType::get(rewriter.getI8Type(), formatStrVec.size()); - formatStrGlobal = rewriter.create( - loc, globalType, /*isConstant=*/true, LLVM::Linkage::Internal, + formatStrGlobal = LLVM::GlobalOp::create( + rewriter, loc, globalType, /*isConstant=*/true, + LLVM::Linkage::Internal, /*name=*/formatStrName, rewriter.getStringAttr(formatStrVec), /*alignment=*/0); } Value formatStrGlobalPtr = - rewriter.create(loc, formatStrGlobal); + LLVM::AddressOfOp::create(rewriter, loc, formatStrGlobal); rewriter.replaceOpWithNewOp( op, printfFunc.value(), ValueRange{formatStrGlobalPtr, toPrint}); diff --git a/lib/Conversion/CFToHandshake/CFToHandshake.cpp b/lib/Conversion/CFToHandshake/CFToHandshake.cpp index 33c728d94f..e692aeb311 100644 --- a/lib/Conversion/CFToHandshake/CFToHandshake.cpp +++ b/lib/Conversion/CFToHandshake/CFToHandshake.cpp @@ -305,14 +305,15 @@ HandshakeLowering::insertMerge(Block *block, Value val, // argument. Taking this step out should have no impact on functionality // but would make the resulting IR less "regular" operands.push_back(val); - mergeOp = rewriter.create(insertLoc, operands); + mergeOp = handshake::MergeOp::create(rewriter, insertLoc, operands); } else { for (unsigned i = 0; i < numPredecessors; i++) { auto edge = edgeBuilder.get(rewriter.getNoneType()); dataEdges.push_back(edge); operands.push_back(Value(edge)); } - mergeOp = rewriter.create(insertLoc, operands); + mergeOp = + handshake::ControlMergeOp::create(rewriter, insertLoc, operands); } setBlockEntryControl(block, mergeOp->getResult(0)); return MergeOpInfo{mergeOp, val, dataEdges}; @@ -336,7 +337,7 @@ HandshakeLowering::insertMerge(Block *block, Value val, dataEdges.push_back(edge); operands.push_back(Value(edge)); } - auto merge = rewriter.create(insertLoc, operands); + auto merge = handshake::MergeOp::create(rewriter, insertLoc, operands); return MergeOpInfo{merge, val, dataEdges}; } @@ -351,7 +352,7 @@ HandshakeLowering::insertMerge(Block *block, Value val, operands.push_back(Value(edge)); } auto mux = - rewriter.create(insertLoc, Value(indexEdge), operands); + handshake::MuxOp::create(rewriter, insertLoc, Value(indexEdge), operands); return MergeOpInfo{mux, val, dataEdges, indexEdge}; } @@ -725,8 +726,8 @@ BufferOp FeedForwardNetworkRewriter::buildSplitNetwork( // TODO how to size these? // Longest path in a CFG-DAG would be O(#blocks) - return rewriter.create(loc, cond, bufferSize, - BufferTypeEnum::fifo); + return handshake::BufferOp::create(rewriter, loc, cond, bufferSize, + BufferTypeEnum::fifo); } LogicalResult FeedForwardNetworkRewriter::buildMergeNetwork( @@ -752,22 +753,22 @@ LogicalResult FeedForwardNetworkRewriter::buildMergeNetwork( else muxOperands = llvm::to_vector(ctrlMerge.getOperands()); - Value newCtrl = rewriter.create(loc, buf, muxOperands); + Value newCtrl = handshake::MuxOp::create(rewriter, loc, buf, muxOperands); Value cond = buf.getResult(); if (requiresFlip) { // As the mux operand order is the flipped cmerge input order, the index // which replaces the output of the cmerge has to be flipped/negated as // well. - cond = rewriter.create( - loc, cond.getType(), cond, - rewriter.create( - loc, rewriter.getIntegerAttr(rewriter.getI1Type(), 1))); + cond = arith::XOrIOp::create( + rewriter, loc, cond.getType(), cond, + arith::ConstantOp::create( + rewriter, loc, rewriter.getIntegerAttr(rewriter.getI1Type(), 1))); } // Require a cast to index to stick to the type of the mux input. Value condAsIndex = - rewriter.create(loc, rewriter.getIndexType(), cond); + arith::IndexCastOp::create(rewriter, loc, rewriter.getIndexType(), cond); hl.setBlockEntryControl(mergeBlock, newCtrl); @@ -1149,10 +1150,10 @@ HandshakeLowering::addBranchOps(ConversionPatternRewriter &rewriter) { Operation *newOp = nullptr; if (auto condBranchOp = dyn_cast(termOp)) - newOp = rewriter.create( - termOp->getLoc(), condBranchOp.getCondition(), val); + newOp = handshake::ConditionalBranchOp::create( + rewriter, termOp->getLoc(), condBranchOp.getCondition(), val); else if (isa(termOp)) - newOp = rewriter.create(termOp->getLoc(), val); + newOp = handshake::BranchOp::create(rewriter, termOp->getLoc(), val); if (newOp == nullptr) continue; @@ -1189,8 +1190,8 @@ LogicalResult HandshakeLowering::connectConstantsToControl( auto value = constantOp.getValue(); rewriter.replaceOpWithNewOp( constantOp, value.getType(), value, - rewriter.create(constantOp.getLoc(), - rewriter.getNoneType())); + handshake::SourceOp::create(rewriter, constantOp.getLoc(), + rewriter.getNoneType())); } } else { for (Block &block : r) { @@ -1301,8 +1302,8 @@ HandshakeLowering::replaceMemoryOps(ConversionPatternRewriter &rewriter, // This will add all operands except alloc SmallVector operands(loadOp.getIndices()); - newOp = - rewriter.create(op.getLoc(), memref, operands); + newOp = handshake::LoadOp::create(rewriter, op.getLoc(), memref, + operands); op.getResult(0).replaceAllUsesWith(newOp->getResult(0)); }) .Case([&](auto storeOp) { @@ -1311,8 +1312,8 @@ HandshakeLowering::replaceMemoryOps(ConversionPatternRewriter &rewriter, SmallVector operands(storeOp.getIndices()); // Create new op where operands are store data and address indices - newOp = rewriter.create( - op.getLoc(), storeOp.getValueToStore(), operands); + newOp = handshake::StoreOp::create( + rewriter, op.getLoc(), storeOp.getValueToStore(), operands); }) .Case([&](auto) { // Get essential memref access inforamtion. @@ -1339,13 +1340,13 @@ HandshakeLowering::replaceMemoryOps(ConversionPatternRewriter &rewriter, "cannot be reduced."); if (isa(op)) { - auto loadOp = rewriter.create( - op.getLoc(), access.memref, *operands); + auto loadOp = handshake::LoadOp::create(rewriter, op.getLoc(), + access.memref, *operands); newOp = loadOp; op.getResult(0).replaceAllUsesWith(loadOp.getDataResult()); } else { - newOp = rewriter.create( - op.getLoc(), op.getOperand(0), *operands); + newOp = handshake::StoreOp::create(rewriter, op.getLoc(), + op.getOperand(0), *operands); } }) .Default([&](auto) { @@ -1417,7 +1418,7 @@ static void addJoinOps(ConversionPatternRewriter &rewriter, // Insert only single join per block if (!isa(srcOp)) { rewriter.setInsertionPointAfter(srcOp); - Operation *newJoin = rewriter.create(srcOp->getLoc(), ctrl); + Operation *newJoin = JoinOp::create(rewriter, srcOp->getLoc(), ctrl); op->replaceUsesOfWith(ctrl, newJoin->getResult(0)); } } @@ -1503,7 +1504,7 @@ void HandshakeLowering::setMemOpControlInputs( else { rewriter.setInsertionPoint(currOp); Operation *joinOp = - rewriter.create(currOp->getLoc(), controlOperands); + JoinOp::create(rewriter, currOp->getLoc(), controlOperands); addValueToOperands(currOp, joinOp->getResult(0)); } } @@ -1583,13 +1584,13 @@ HandshakeLowering::connectToMemory(ConversionPatternRewriter &rewriter, // Place memory op next to the alloc op Operation *newOp = nullptr; if (isExternalMemory) - newOp = rewriter.create( - entryBlock->front().getLoc(), memrefOperand, operands, ld_count, - cntrl_count - ld_count, mem_count++); + newOp = ExternalMemoryOp::create(rewriter, entryBlock->front().getLoc(), + memrefOperand, operands, ld_count, + cntrl_count - ld_count, mem_count++); else - newOp = rewriter.create(entryBlock->front().getLoc(), operands, - ld_count, cntrl_count, lsq, mem_count++, - memrefOperand); + newOp = MemoryOp::create(rewriter, entryBlock->front().getLoc(), operands, + ld_count, cntrl_count, lsq, mem_count++, + memrefOperand); setLoadDataInputs(memory.second, newOp); @@ -1636,9 +1637,9 @@ HandshakeLowering::replaceCallOps(ConversionPatternRewriter &rewriter) { llvm::copy(callOp.getOperands(), std::back_inserter(operands)); operands.push_back(blockEntryControl); rewriter.setInsertionPoint(callOp); - auto instanceOp = rewriter.create( - callOp.getLoc(), callOp.getCallee(), callOp.getResultTypes(), - operands); + auto instanceOp = handshake::InstanceOp::create( + rewriter, callOp.getLoc(), callOp.getCallee(), + callOp.getResultTypes(), operands); // Replace all results of the source callOp. for (auto it : llvm::zip(callOp.getResults(), instanceOp.getResults())) std::get<0>(it).replaceAllUsesWith(std::get<1>(it)); @@ -1705,8 +1706,9 @@ static LogicalResult lowerFuncOp(func::FuncOp funcOp, MLIRContext *ctx, resTypes.push_back(noneType); argTypes.push_back(noneType); auto func_type = rewriter.getFunctionType(argTypes, resTypes); - newFuncOp = rewriter.create( - funcOp.getLoc(), funcOp.getName(), func_type, attributes); + newFuncOp = handshake::FuncOp::create(rewriter, funcOp.getLoc(), + funcOp.getName(), func_type, + attributes); rewriter.inlineRegionBefore(funcOp.getBody(), newFuncOp.getBody(), newFuncOp.end()); if (!newFuncOp.isExternal()) { diff --git a/lib/Conversion/CalyxToFSM/CalyxToFSM.cpp b/lib/Conversion/CalyxToFSM/CalyxToFSM.cpp index f1f3bf24e3..e84da7cca6 100644 --- a/lib/Conversion/CalyxToFSM/CalyxToFSM.cpp +++ b/lib/Conversion/CalyxToFSM/CalyxToFSM.cpp @@ -260,7 +260,7 @@ LogicalResult CompileFSMVisitor::visit(StateOp currentState, EnableOp enableOp, // callers iterating over nested ops safer. OpBuilder::InsertionGuard g(builder); builder.setInsertionPointToStart(¤tState.getOutput().front()); - builder.create(enableOp.getLoc(), enableOp.getGroupName()); + calyx::EnableOp::create(builder, enableOp.getLoc(), enableOp.getGroupName()); if (nextState) graph.createTransition(builder, enableOp.getLoc(), currentState, nextState); @@ -319,31 +319,31 @@ void CompileInvoke::lowerInvokeOp(InvokeOp invokeOp) { // Create a ConstantOp to assign a value to the go port. Operation *prevNode = component.getWiresOp().getOperation()->getPrevNode(); builder.setInsertionPointAfter(prevNode); - hw::ConstantOp constantOp = builder.create( - prevNode->getLoc(), builder.getI1Type(), 1); + hw::ConstantOp constantOp = hw::ConstantOp::create( + builder, prevNode->getLoc(), builder.getI1Type(), 1); Location loc = component.getWiresOp().getLoc(); // Set the insertion point at the end of the wires block. builder.setInsertionPointToEnd(component.getWiresOp().getBodyBlock()); std::string transitionName = getTransitionName(invokeOp); - GroupOp groupOp = builder.create(loc, transitionName); + GroupOp groupOp = GroupOp::create(builder, loc, transitionName); builder.setInsertionPointToStart(groupOp.getBodyBlock()); Value go = invokeOp.getInstGoValue(); // Assign a value to the go port. - builder.create(loc, go, constantOp); + AssignOp::create(builder, loc, go, constantOp); auto ports = invokeOp.getPorts(); auto inputs = invokeOp.getInputs(); // Generate a series of assignment operations from a list of parameters. for (auto [port, input] : llvm::zip(ports, inputs)) - builder.create(loc, port, input); + AssignOp::create(builder, loc, port, input); Value done = invokeOp.getInstDoneValue(); // Generate a group_done operation with the instance's done port. - builder.create(loc, done); + calyx::GroupDoneOp::create(builder, loc, done); builder.setInsertionPointAfter(invokeOp.getOperation()); - builder.create(invokeOp.getLoc(), transitionName); + EnableOp::create(builder, invokeOp.getLoc(), transitionName); invokeOp.erase(); } @@ -369,9 +369,8 @@ void CalyxToFSMPass::runOnOperation() { // outlining the FSM (materializing FSM I/O) at a later point. auto machineName = ("control_" + component.getName()).str(); auto funcType = FunctionType::get(&getContext(), {}, {}); - auto machine = - builder.create(ctrlOp.getLoc(), machineName, - /*initialState=*/"fsm_entry", funcType); + auto machine = MachineOp::create(builder, ctrlOp.getLoc(), machineName, + /*initialState=*/"fsm_entry", funcType); auto graph = FSMGraph(machine); SymbolCache sc; diff --git a/lib/Conversion/CalyxToFSM/MaterializeFSM.cpp b/lib/Conversion/CalyxToFSM/MaterializeFSM.cpp index 1c72dd1f0f..ce5cac3110 100644 --- a/lib/Conversion/CalyxToFSM/MaterializeFSM.cpp +++ b/lib/Conversion/CalyxToFSM/MaterializeFSM.cpp @@ -87,7 +87,7 @@ struct MaterializeCalyxToFSMPass guardConjunction = guards.front(); else guardConjunction = - b.create(transition.getLoc(), guards, false); + comb::AndOp::create(b, transition.getLoc(), guards, false); guardOp.setOperand(guardConjunction); } } @@ -99,7 +99,7 @@ struct MaterializeCalyxToFSMPass OpBuilder::InsertionGuard g(b); b.setInsertionPointToStart(&machineOp.getBody().front()); - auto constantOp = b.create(machineOp.getLoc(), value); + auto constantOp = hw::ConstantOp::create(b, machineOp.getLoc(), value); constants[value] = constantOp; return constantOp; } diff --git a/lib/Conversion/CalyxToHW/CalyxToHW.cpp b/lib/Conversion/CalyxToHW/CalyxToHW.cpp index 29dda045b8..f8353e6989 100644 --- a/lib/Conversion/CalyxToHW/CalyxToHW.cpp +++ b/lib/Conversion/CalyxToHW/CalyxToHW.cpp @@ -53,8 +53,8 @@ struct ConvertComponentOp : public OpConversionPattern { ModulePortInfo hwPortInfo(hwInputInfo); SmallVector argValues; - auto hwMod = rewriter.create( - component.getLoc(), component.getNameAttr(), hwPortInfo, + auto hwMod = HWModuleOp::create( + rewriter, component.getLoc(), component.getNameAttr(), hwPortInfo, [&](OpBuilder &b, HWModulePortAccessor &ports) { for (auto [name, type, direction, _] : portInfo) { switch (direction) { @@ -63,9 +63,9 @@ struct ConvertComponentOp : public OpConversionPattern { argValues.push_back(ports.getInput(name)); break; case calyx::Direction::Output: - auto wire = b.create(component.getLoc(), type, name); + auto wire = sv::WireOp::create(b, component.getLoc(), type, name); auto wireRead = - b.create(component.getLoc(), wire); + sv::ReadInOutOp::create(b, component.getLoc(), wire); argValues.push_back(wireRead); ports.setOutput(name, wireRead); break; @@ -131,15 +131,15 @@ struct ConvertAssignOp : public OpConversionPattern { Value src = adaptor.getSrc(); if (auto guard = adaptor.getGuard()) { auto zero = - rewriter.create(assign.getLoc(), src.getType(), 0); - src = rewriter.create(assign.getLoc(), guard, src, zero); + hw::ConstantOp::create(rewriter, assign.getLoc(), src.getType(), 0); + src = MuxOp::create(rewriter, assign.getLoc(), guard, src, zero); for (Operation *destUser : llvm::make_early_inc_range(assign.getDest().getUsers())) { if (destUser == assign) continue; if (auto otherAssign = dyn_cast(destUser)) { - src = rewriter.create(assign.getLoc(), otherAssign.getGuard(), - otherAssign.getSrc(), src); + src = MuxOp::create(rewriter, assign.getLoc(), otherAssign.getGuard(), + otherAssign.getSrc(), src); rewriter.eraseOp(destUser); } } @@ -250,7 +250,7 @@ private: auto fal = wireIn(op.getFal(), op.instanceName(), op.portName(op.getFal()), b); - auto mux = b.create(sel, tru, fal); + auto mux = MuxOp::create(b, sel, tru, fal); auto out = wireOut(mux, op.instanceName(), op.portName(op.getOut()), b); @@ -282,12 +282,12 @@ private: op.portName(op.getClk()), b); auto reset = wireIn(op.getReset(), op.instanceName(), op.portName(op.getReset()), b); - auto seqClk = b.create(clk); + auto seqClk = seq::ToClockOp::create(b, clk); auto doneReg = reg(writeEn, seqClk, reset, op.instanceName() + "_done_reg", b); auto done = wireOut(doneReg, op.instanceName(), op.portName(op.getDone()), b); - auto clockEn = b.create(writeEn, createOrFoldNot(done, b)); + auto clockEn = AndOp::create(b, writeEn, createOrFoldNot(done, b)); auto outReg = regCe(in, seqClk, clockEn, reset, op.instanceName() + "_reg", b); auto out = wireOut(outReg, op.instanceName(), "", b); @@ -300,7 +300,7 @@ private: wireIn(op.getIn(), op.instanceName(), op.portName(op.getIn()), b); auto outWidth = op.getOut().getType().getIntOrFloatBitWidth(); - auto extract = b.create(in, 0, outWidth); + auto extract = ExtractOp::create(b, in, 0, outWidth); auto out = wireOut(extract, op.instanceName(), op.portName(op.getOut()), b); @@ -321,7 +321,7 @@ private: wires.append({wire.getInput(), wire}); }) .Case([&](UndefLibOp op) { - auto undef = b.create(op.getType()); + auto undef = sv::ConstantXOp::create(b, op.getType()); wires.append({undef}); }) .Case([&](PadLibOp op) { @@ -329,8 +329,8 @@ private: wireIn(op.getIn(), op.instanceName(), op.portName(op.getIn()), b); auto srcWidth = in.getType().getIntOrFloatBitWidth(); auto destWidth = op.getOut().getType().getIntOrFloatBitWidth(); - auto zero = b.create(op.getLoc(), - APInt(destWidth - srcWidth, 0)); + auto zero = hw::ConstantOp::create(b, op.getLoc(), + APInt(destWidth - srcWidth, 0)); auto padded = wireOut(b.createOrFold(zero, in), op.instanceName(), op.portName(op.getOut()), b); wires.append({in.getInput(), padded}); @@ -354,7 +354,7 @@ private: auto right = wireIn(op.getRight(), op.instanceName(), op.portName(op.getRight()), b); - auto add = b.create(left, right, false); + auto add = ResultTy::create(b, left, right, false); auto out = wireOut(add, op.instanceName(), op.portName(op.getOut()), b); wires.append({left.getInput(), right.getInput(), out}); @@ -369,7 +369,7 @@ private: auto right = wireIn(op.getRight(), op.instanceName(), op.portName(op.getRight()), b); - auto add = b.create(pred, left, right, false); + auto add = ICmpOp::create(b, pred, left, right, false); auto out = wireOut(add, op.instanceName(), op.portName(op.getOut()), b); wires.append({left.getInput(), right.getInput(), out}); @@ -395,11 +395,11 @@ private: auto done = wireOut(doneReg, op.instanceName(), op.portName(op.getDone()), b); - auto targetOp = b.create(left, right, false); + auto targetOp = TargetOpTy::create(b, left, right, false); for (auto &&[targetRes, sourceRes] : llvm::zip(targetOp->getResults(), op.getOutputPorts())) { auto portName = op.portName(sourceRes); - auto clockEn = b.create(go, createOrFoldNot(done, b)); + auto clockEn = AndOp::create(b, go, createOrFoldNot(done, b)); auto resReg = regCe(targetRes, clk, clockEn, reset, createName(op.instanceName(), portName), b); wires.push_back(wireOut(resReg, op.instanceName(), portName, b)); @@ -410,31 +410,31 @@ private: ReadInOutOp wireIn(Value source, StringRef instanceName, StringRef portName, ImplicitLocOpBuilder &b) const { - auto wire = b.create(source.getType(), - createName(instanceName, portName)); - return b.create(wire); + auto wire = sv::WireOp::create(b, source.getType(), + createName(instanceName, portName)); + return ReadInOutOp::create(b, wire); } ReadInOutOp wireOut(Value source, StringRef instanceName, StringRef portName, ImplicitLocOpBuilder &b) const { - auto wire = b.create(source.getType(), - createName(instanceName, portName)); - b.create(wire, source); - return b.create(wire); + auto wire = sv::WireOp::create(b, source.getType(), + createName(instanceName, portName)); + sv::AssignOp::create(b, wire, source); + return ReadInOutOp::create(b, wire); } CompRegOp reg(Value source, Value clock, Value reset, const Twine &name, ImplicitLocOpBuilder &b) const { - auto resetValue = b.create(source.getType(), 0); - return b.create(source, clock, reset, resetValue, name.str()); + auto resetValue = hw::ConstantOp::create(b, source.getType(), 0); + return CompRegOp::create(b, source, clock, reset, resetValue, name.str()); } CompRegClockEnabledOp regCe(Value source, Value clock, Value ce, Value reset, const Twine &name, ImplicitLocOpBuilder &b) const { - auto resetValue = b.create(source.getType(), 0); - return b.create(source, clock, ce, reset, resetValue, - name.str()); + auto resetValue = hw::ConstantOp::create(b, source.getType(), 0); + return CompRegClockEnabledOp::create(b, source, clock, ce, reset, + resetValue, name.str()); } std::string createName(StringRef instanceName, StringRef portName) const { diff --git a/lib/Conversion/CombToAIG/CombToAIG.cpp b/lib/Conversion/CombToAIG/CombToAIG.cpp index 1c59d8df57..6be7666153 100644 --- a/lib/Conversion/CombToAIG/CombToAIG.cpp +++ b/lib/Conversion/CombToAIG/CombToAIG.cpp @@ -88,8 +88,8 @@ static Value createShiftLogic(ConversionPatternRewriter &rewriter, Location loc, // Add bounds checking auto inBound = rewriter.createOrFold( loc, ICmpPredicate::ult, shiftAmount, - rewriter.create(loc, shiftAmount.getType(), - maxShiftAmount)); + hw::ConstantOp::create(rewriter, loc, shiftAmount.getType(), + maxShiftAmount)); return rewriter.createOrFold(loc, inBound, result, outOfBoundsValue); @@ -196,7 +196,7 @@ static LogicalResult emulateBinaryOpForUnknownBits( auto it = constantPool.find(attr); if (it != constantPool.end()) return it->second; - auto constant = rewriter.create(loc, value); + auto constant = hw::ConstantOp::create(rewriter, loc, value); constantPool[attr] = constant; return constant; }; @@ -261,8 +261,8 @@ struct CombOrOpConversion : OpConversionPattern { ConversionPatternRewriter &rewriter) const override { // Implement Or using And and invert flags: a | b = ~(~a & ~b) SmallVector allInverts(adaptor.getInputs().size(), true); - auto andOp = rewriter.create( - op.getLoc(), adaptor.getInputs(), allInverts); + auto andOp = aig::AndInverterOp::create(rewriter, op.getLoc(), + adaptor.getInputs(), allInverts); replaceOpWithNewOpAndCopyNamehint(rewriter, op, andOp, /*invert=*/true); return success(); @@ -287,9 +287,9 @@ struct CombXorOpConversion : OpConversionPattern { SmallVector allNotInverts(inputs.size(), false); auto notAAndNotB = - rewriter.create(op.getLoc(), inputs, allInverts); - auto aAndB = - rewriter.create(op.getLoc(), inputs, allNotInverts); + aig::AndInverterOp::create(rewriter, op.getLoc(), inputs, allInverts); + auto aAndB = aig::AndInverterOp::create(rewriter, op.getLoc(), inputs, + allNotInverts); replaceOpWithNewOpAndCopyNamehint(rewriter, op, notAAndNotB, aAndB, @@ -323,14 +323,14 @@ struct CombLowerVariadicOp : OpConversionPattern { case 2: lhs = operands[0]; rhs = operands[1]; - return rewriter.create(op.getLoc(), ValueRange{lhs, rhs}, true); + return OpTy::create(rewriter, op.getLoc(), ValueRange{lhs, rhs}, true); default: auto firstHalf = operands.size() / 2; lhs = lowerFullyAssociativeOp(op, operands.take_front(firstHalf), rewriter); rhs = lowerFullyAssociativeOp(op, operands.drop_front(firstHalf), rewriter); - return rewriter.create(op.getLoc(), ValueRange{lhs, rhs}, true); + return OpTy::create(rewriter, op.getLoc(), ValueRange{lhs, rhs}, true); } } }; @@ -352,26 +352,26 @@ struct CombMuxOpConversion : OpConversionPattern { // If the type of the mux is not integer, bitcast the operands first. auto widthType = rewriter.getIntegerType(hw::getBitWidth(op.getType())); trueVal = - rewriter.create(op->getLoc(), widthType, trueVal); + hw::BitcastOp::create(rewriter, op->getLoc(), widthType, trueVal); falseVal = - rewriter.create(op->getLoc(), widthType, falseVal); + hw::BitcastOp::create(rewriter, op->getLoc(), widthType, falseVal); } // Replicate condition if needed if (!trueVal.getType().isInteger(1)) - cond = rewriter.create(op.getLoc(), trueVal.getType(), - cond); + cond = comb::ReplicateOp::create(rewriter, op.getLoc(), trueVal.getType(), + cond); // c ? a : b => (replicate(c) & a) | (~replicate(c) & b) - auto lhs = rewriter.create(op.getLoc(), cond, trueVal); - auto rhs = rewriter.create(op.getLoc(), cond, falseVal, - true, false); + auto lhs = aig::AndInverterOp::create(rewriter, op.getLoc(), cond, trueVal); + auto rhs = aig::AndInverterOp::create(rewriter, op.getLoc(), cond, falseVal, + true, false); - Value result = rewriter.create(op.getLoc(), lhs, rhs); + Value result = comb::OrOp::create(rewriter, op.getLoc(), lhs, rhs); // Insert the bitcast if the type of the mux is not integer. if (result.getType() != op.getType()) result = - rewriter.create(op.getLoc(), op.getType(), result); + hw::BitcastOp::create(rewriter, op.getLoc(), op.getType(), result); replaceOpAndCopyNamehint(rewriter, op, result); return success(); } @@ -423,27 +423,27 @@ struct CombAddOpConversion : OpConversionPattern { // sum[i] = xor(carry[i-1], a[i], b[i]) // NOTE: The result is stored in reverse order. results[width - i - 1] = - rewriter.create(op.getLoc(), xorOperands, true); + comb::XorOp::create(rewriter, op.getLoc(), xorOperands, true); // If this is the last bit, we are done. if (i == width - 1) break; // carry[i] = (carry[i-1] & (a[i] ^ b[i])) | (a[i] & b[i]) - Value nextCarry = rewriter.create( - op.getLoc(), ValueRange{aBits[i], bBits[i]}, true); + Value nextCarry = comb::AndOp::create( + rewriter, op.getLoc(), ValueRange{aBits[i], bBits[i]}, true); if (!carry) { // This is the first bit, so the carry is the next carry. carry = nextCarry; continue; } - auto aXnorB = rewriter.create( - op.getLoc(), ValueRange{aBits[i], bBits[i]}, true); - auto andOp = rewriter.create( - op.getLoc(), ValueRange{carry, aXnorB}, true); - carry = rewriter.create(op.getLoc(), - ValueRange{andOp, nextCarry}, true); + auto aXnorB = comb::XorOp::create(rewriter, op.getLoc(), + ValueRange{aBits[i], bBits[i]}, true); + auto andOp = comb::AndOp::create(rewriter, op.getLoc(), + ValueRange{carry, aXnorB}, true); + carry = comb::OrOp::create(rewriter, op.getLoc(), + ValueRange{andOp, nextCarry}, true); } LLVM_DEBUG(llvm::dbgs() << "Lower comb.add to Ripple-Carry Adder of width " << width << "\n"); @@ -467,9 +467,9 @@ struct CombAddOpConversion : OpConversionPattern { for (auto [aBit, bBit] : llvm::zip(aBits, bBits)) { // p_i = a_i XOR b_i - p.push_back(rewriter.create(op.getLoc(), aBit, bBit)); + p.push_back(comb::XorOp::create(rewriter, op.getLoc(), aBit, bBit)); // g_i = a_i AND b_i - g.push_back(rewriter.create(op.getLoc(), aBit, bBit)); + g.push_back(comb::AndOp::create(rewriter, op.getLoc(), aBit, bBit)); } LLVM_DEBUG({ @@ -503,7 +503,7 @@ struct CombAddOpConversion : OpConversionPattern { // The carry into position i is the group generate from position i-1 for (int64_t i = 1; i < width; ++i) results[width - 1 - i] = - rewriter.create(op.getLoc(), p[i], gPrefix[i - 1]); + comb::XorOp::create(rewriter, op.getLoc(), p[i], gPrefix[i - 1]); replaceOpWithNewOpAndCopyNamehint(rewriter, op, results); @@ -530,13 +530,13 @@ struct CombAddOpConversion : OpConversionPattern { int64_t j = i - stride; // Group generate: g_i OR (p_i AND g_j) Value andPG = - rewriter.create(op.getLoc(), pPrefix[i], gPrefix[j]); + comb::AndOp::create(rewriter, op.getLoc(), pPrefix[i], gPrefix[j]); gPrefix[i] = - rewriter.create(op.getLoc(), gPrefix[i], andPG); + comb::OrOp::create(rewriter, op.getLoc(), gPrefix[i], andPG); // Group propagate: p_i AND p_j pPrefix[i] = - rewriter.create(op.getLoc(), pPrefix[i], pPrefix[j]); + comb::AndOp::create(rewriter, op.getLoc(), pPrefix[i], pPrefix[j]); } } LLVM_DEBUG({ @@ -579,13 +579,13 @@ struct CombAddOpConversion : OpConversionPattern { // Group generate: g_i OR (p_i AND g_j) Value andPG = - rewriter.create(op.getLoc(), pPrefix[i], gPrefix[j]); + comb::AndOp::create(rewriter, op.getLoc(), pPrefix[i], gPrefix[j]); gPrefix[i] = - rewriter.create(op.getLoc(), gPrefix[i], andPG); + comb::OrOp::create(rewriter, op.getLoc(), gPrefix[i], andPG); // Group propagate: p_i AND p_j pPrefix[i] = - rewriter.create(op.getLoc(), pPrefix[i], pPrefix[j]); + comb::AndOp::create(rewriter, op.getLoc(), pPrefix[i], pPrefix[j]); } } @@ -596,12 +596,12 @@ struct CombAddOpConversion : OpConversionPattern { // Group generate: g_i OR (p_i AND g_j) Value andPG = - rewriter.create(op.getLoc(), pPrefix[i], gPrefix[j]); - gPrefix[i] = rewriter.create(op.getLoc(), gPrefix[i], andPG); + comb::AndOp::create(rewriter, op.getLoc(), pPrefix[i], gPrefix[j]); + gPrefix[i] = OrOp::create(rewriter, op.getLoc(), gPrefix[i], andPG); // Group propagate: p_i AND p_j pPrefix[i] = - rewriter.create(op.getLoc(), pPrefix[i], pPrefix[j]); + comb::AndOp::create(rewriter, op.getLoc(), pPrefix[i], pPrefix[j]); } } @@ -659,9 +659,9 @@ struct CombSubOpConversion : OpConversionPattern { // Since `-rhs = ~rhs + 1` holds, rewrite `sub(lhs, rhs)` to: // sub(lhs, rhs) => add(lhs, -rhs) => add(lhs, add(~rhs, 1)) // => add(lhs, ~rhs, 1) - auto notRhs = rewriter.create(op.getLoc(), rhs, - /*invert=*/true); - auto one = rewriter.create(op.getLoc(), op.getType(), 1); + auto notRhs = aig::AndInverterOp::create(rewriter, op.getLoc(), rhs, + /*invert=*/true); + auto one = hw::ConstantOp::create(rewriter, op.getLoc(), op.getType(), 1); replaceOpWithNewOpAndCopyNamehint( rewriter, op, ValueRange{lhs, notRhs, one}, true); return success(); @@ -692,7 +692,7 @@ struct CombMulOpConversion : OpConversionPattern { SmallVector aBits = extractBits(rewriter, a); SmallVector bBits = extractBits(rewriter, b); - auto falseValue = rewriter.create(loc, APInt(1, 0)); + auto falseValue = hw::ConstantOp::create(rewriter, loc, APInt(1, 0)); // Generate partial products SmallVector> partialProducts; @@ -718,7 +718,7 @@ struct CombMulOpConversion : OpConversionPattern { auto addends = comb::wallaceReduction(rewriter, loc, width, 2, partialProducts); // Sum the two addends using a carry-propagate adder - auto newAdd = rewriter.create(loc, addends, true); + auto newAdd = comb::AddOp::create(rewriter, loc, addends, true); replaceOpAndCopyNamehint(rewriter, op, newAdd); return success(); } @@ -749,8 +749,8 @@ struct CombDivUOpConversion : DivModOpConversionBase { Value upperBits = rewriter.createOrFold( op.getLoc(), adaptor.getLhs(), extractAmount, width - extractAmount); - Value constZero = rewriter.create( - op.getLoc(), APInt::getZero(extractAmount)); + Value constZero = hw::ConstantOp::create(rewriter, op.getLoc(), + APInt::getZero(extractAmount)); replaceOpWithNewOpAndCopyNamehint( rewriter, op, op.getType(), ArrayRef{constZero, upperBits}); return success(); @@ -782,8 +782,8 @@ struct CombModUOpConversion : DivModOpConversionBase { size_t width = op.getType().getIntOrFloatBitWidth(); Value lowerBits = rewriter.createOrFold( op.getLoc(), adaptor.getLhs(), 0, extractAmount); - Value constZero = rewriter.create( - op.getLoc(), APInt::getZero(width - extractAmount)); + Value constZero = hw::ConstantOp::create( + rewriter, op.getLoc(), APInt::getZero(width - extractAmount)); replaceOpWithNewOpAndCopyNamehint( rewriter, op, op.getType(), ArrayRef{constZero, lowerBits}); return success(); @@ -851,7 +851,7 @@ struct CombICmpOpConversion : OpConversionPattern { // a >= b ==> ( a[n] & ~b[n]) | (a[n] == b[n] & a[n-1:0] >= b[n-1:0]) // a > b ==> ( a[n] & ~b[n]) | (a[n] == b[n] & a[n-1:0] > b[n-1:0]) Value acc = - rewriter.create(op.getLoc(), op.getType(), includeEq); + hw::ConstantOp::create(rewriter, op.getLoc(), op.getType(), includeEq); for (auto [aBit, bBit] : llvm::zip(aBits, bBits)) { auto aBitXorBBit = @@ -941,7 +941,7 @@ struct CombICmpOpConversion : OpConversionPattern { // XOR of signs: true if signs are different auto signsDiffer = - rewriter.create(op.getLoc(), signA, signB); + comb::XorOp::create(rewriter, op.getLoc(), signA, signB); // Result when signs are different Value diffSignResult = isLess ? signA : signB; diff --git a/lib/Conversion/CombToArith/CombToArith.cpp b/lib/Conversion/CombToArith/CombToArith.cpp index e4110ffd04..20d609cfe6 100644 --- a/lib/Conversion/CombToArith/CombToArith.cpp +++ b/lib/Conversion/CombToArith/CombToArith.cpp @@ -123,11 +123,11 @@ struct ExtractOpConversion : OpConversionPattern { matchAndRewrite(ExtractOp op, OpAdaptor adaptor, ConversionPatternRewriter &rewriter) const override { - Value lowBit = rewriter.create( - op.getLoc(), + Value lowBit = arith::ConstantOp::create( + rewriter, op.getLoc(), IntegerAttr::get(adaptor.getInput().getType(), adaptor.getLowBit())); Value shifted = - rewriter.create(op.getLoc(), adaptor.getInput(), lowBit); + ShRUIOp::create(rewriter, op.getLoc(), adaptor.getInput(), lowBit); rewriter.replaceOpWithNewOp(op, op.getResult().getType(), shifted); return success(); @@ -162,8 +162,8 @@ struct ConcatOpConversion : OpConversionPattern { unsigned offset = type.getIntOrFloatBitWidth(); for (auto operand : adaptor.getOperands().drop_back()) { offset -= operand.getType().getIntOrFloatBitWidth(); - auto offsetConst = rewriter.create( - loc, IntegerAttr::get(type, offset)); + auto offsetConst = arith::ConstantOp::create( + rewriter, loc, IntegerAttr::get(type, offset)); auto extended = rewriter.createOrFold(loc, type, operand); auto shifted = rewriter.createOrFold(loc, extended, offsetConst); aggregate = rewriter.createOrFold(loc, aggregate, shifted); @@ -201,14 +201,14 @@ struct DivOpConversion : OpConversionPattern { matchAndRewrite(SourceOp op, OpAdaptor adaptor, ConversionPatternRewriter &rewriter) const override { Location loc = op.getLoc(); - Value zero = rewriter.create( - loc, rewriter.getIntegerAttr(adaptor.getRhs().getType(), 0)); - Value one = rewriter.create( - loc, rewriter.getIntegerAttr(adaptor.getRhs().getType(), 1)); - Value isZero = rewriter.create(loc, CmpIPredicate::eq, - adaptor.getRhs(), zero); + Value zero = arith::ConstantOp::create( + rewriter, loc, rewriter.getIntegerAttr(adaptor.getRhs().getType(), 0)); + Value one = arith::ConstantOp::create( + rewriter, loc, rewriter.getIntegerAttr(adaptor.getRhs().getType(), 1)); + Value isZero = arith::CmpIOp::create(rewriter, loc, CmpIPredicate::eq, + adaptor.getRhs(), zero); Value divisor = - rewriter.create(loc, isZero, one, adaptor.getRhs()); + arith::SelectOp::create(rewriter, loc, isZero, one, adaptor.getRhs()); rewriter.replaceOpWithNewOp(op, adaptor.getLhs(), divisor); return success(); } @@ -229,7 +229,7 @@ struct VariadicOpConversion : OpConversionPattern { Value runner = operands[0]; for (Value operand : llvm::make_range(operands.begin() + 1, operands.end())) { - runner = rewriter.create(op.getLoc(), runner, operand); + runner = TargetOp::create(rewriter, op.getLoc(), runner, operand); } rewriter.replaceOp(op, runner); return success(); @@ -254,10 +254,10 @@ struct LogicalShiftConversion : OpConversionPattern { unsigned shifteeWidth = hw::type_cast(adaptor.getLhs().getType()) .getIntOrFloatBitWidth(); - auto zeroConstOp = rewriter.create( - op.getLoc(), IntegerAttr::get(adaptor.getLhs().getType(), 0)); - auto maxShamtConstOp = rewriter.create( - op.getLoc(), + auto zeroConstOp = arith::ConstantOp::create( + rewriter, op.getLoc(), IntegerAttr::get(adaptor.getLhs().getType(), 0)); + auto maxShamtConstOp = arith::ConstantOp::create( + rewriter, op.getLoc(), IntegerAttr::get(adaptor.getLhs().getType(), shifteeWidth)); auto shiftOp = rewriter.createOrFold( op.getLoc(), adaptor.getLhs(), adaptor.getRhs()); @@ -281,8 +281,8 @@ struct ShrSOpConversion : OpConversionPattern { hw::type_cast(adaptor.getLhs().getType()) .getIntOrFloatBitWidth(); // Clamp the shift amount to shifteeWidth - 1 - auto maxShamtMinusOneConstOp = rewriter.create( - op.getLoc(), + auto maxShamtMinusOneConstOp = arith::ConstantOp::create( + rewriter, op.getLoc(), IntegerAttr::get(adaptor.getLhs().getType(), shifteeWidth - 1)); auto shamtOp = rewriter.createOrFold(op.getLoc(), adaptor.getRhs(), maxShamtMinusOneConstOp); diff --git a/lib/Conversion/CombToDatapath/CombToDatapath.cpp b/lib/Conversion/CombToDatapath/CombToDatapath.cpp index 3a13736c34..f8887c80a0 100644 --- a/lib/Conversion/CombToDatapath/CombToDatapath.cpp +++ b/lib/Conversion/CombToDatapath/CombToDatapath.cpp @@ -45,8 +45,8 @@ struct CombAddOpConversion : OpConversionPattern { } // Reduce to two values (carry,save) - auto results = - rewriter.create(op.getLoc(), op.getOperands(), 2); + auto results = datapath::CompressOp::create(rewriter, op.getLoc(), + op.getOperands(), 2); // carry+saved rewriter.replaceOpWithNewOp(op, results.getResults(), true); return success(); @@ -66,8 +66,8 @@ struct CombMulOpConversion : OpConversionPattern { auto width = op.getType().getIntOrFloatBitWidth(); // Create partial product rows - number of rows == width - auto pp = rewriter.create( - op.getLoc(), op.getInputs(), width); + auto pp = datapath::PartialProductOp::create(rewriter, op.getLoc(), + op.getInputs(), width); // Sum partial products rewriter.replaceOpWithNewOp(op, pp.getResults(), true); return success(); diff --git a/lib/Conversion/CombToLLVM/CombToLLVM.cpp b/lib/Conversion/CombToLLVM/CombToLLVM.cpp index d257276c4f..d5a003bd2c 100644 --- a/lib/Conversion/CombToLLVM/CombToLLVM.cpp +++ b/lib/Conversion/CombToLLVM/CombToLLVM.cpp @@ -36,7 +36,7 @@ struct CombParityOpConversion : public ConvertToLLVMPattern { auto parityOp = cast(op); auto popCount = - rewriter.create(op->getLoc(), parityOp.getInput()); + LLVM::CtPopOp::create(rewriter, op->getLoc(), parityOp.getInput()); rewriter.replaceOpWithNewOp( op, IntegerType::get(rewriter.getContext(), 1), popCount); diff --git a/lib/Conversion/CombToSMT/CombToSMT.cpp b/lib/Conversion/CombToSMT/CombToSMT.cpp index 8a86e553c0..f3799831e1 100644 --- a/lib/Conversion/CombToSMT/CombToSMT.cpp +++ b/lib/Conversion/CombToSMT/CombToSMT.cpp @@ -59,11 +59,11 @@ struct IcmpOpConversion : OpConversionPattern { Value result; if (adaptor.getPredicate() == ICmpPredicate::eq) { - result = rewriter.create(op.getLoc(), adaptor.getLhs(), - adaptor.getRhs()); + result = smt::EqOp::create(rewriter, op.getLoc(), adaptor.getLhs(), + adaptor.getRhs()); } else if (adaptor.getPredicate() == ICmpPredicate::ne) { - result = rewriter.create(op.getLoc(), adaptor.getLhs(), - adaptor.getRhs()); + result = smt::DistinctOp::create(rewriter, op.getLoc(), adaptor.getLhs(), + adaptor.getRhs()); } else { smt::BVCmpPredicate pred; switch (adaptor.getPredicate()) { @@ -95,8 +95,8 @@ struct IcmpOpConversion : OpConversionPattern { llvm_unreachable("all cases handled above"); } - result = rewriter.create( - op.getLoc(), pred, adaptor.getLhs(), adaptor.getRhs()); + result = smt::BVCmpOp::create(rewriter, op.getLoc(), pred, + adaptor.getLhs(), adaptor.getRhs()); } Value convVal = typeConverter->materializeTargetConversion( @@ -148,7 +148,8 @@ struct SubOpConversion : OpConversionPattern { LogicalResult matchAndRewrite(SubOp op, OpAdaptor adaptor, ConversionPatternRewriter &rewriter) const override { - Value negRhs = rewriter.create(op.getLoc(), adaptor.getRhs()); + Value negRhs = + smt::BVNegOp::create(rewriter, op.getLoc(), adaptor.getRhs()); rewriter.replaceOpWithNewOp(op, adaptor.getLhs(), negRhs); return success(); } @@ -169,11 +170,11 @@ struct ParityOpConversion : OpConversionPattern { // the type conversion should already fail. Type oneBitTy = smt::BitVectorType::get(getContext(), 1); Value runner = - rewriter.create(loc, oneBitTy, 0, adaptor.getInput()); + smt::ExtractOp::create(rewriter, loc, oneBitTy, 0, adaptor.getInput()); for (unsigned i = 1; i < bitwidth; ++i) { - Value ext = - rewriter.create(loc, oneBitTy, i, adaptor.getInput()); - runner = rewriter.create(loc, runner, ext); + Value ext = smt::ExtractOp::create(rewriter, loc, oneBitTy, i, + adaptor.getInput()); + runner = smt::BVXOrOp::create(rewriter, loc, runner, ext); } rewriter.replaceOp(op, runner); @@ -218,11 +219,11 @@ struct DivisionOpConversion : OpConversionPattern { auto resultType = OpConversionPattern::typeConverter->convertType( op.getResult().getType()); Value zero = - rewriter.create(loc, APInt(type.getWidth(), 0)); - Value isZero = rewriter.create(loc, adaptor.getRhs(), zero); - Value symbolicVal = rewriter.create(loc, resultType); + smt::BVConstantOp::create(rewriter, loc, APInt(type.getWidth(), 0)); + Value isZero = smt::EqOp::create(rewriter, loc, adaptor.getRhs(), zero); + Value symbolicVal = smt::DeclareFunOp::create(rewriter, loc, resultType); Value division = - rewriter.create(loc, resultType, adaptor.getOperands()); + TargetOp::create(rewriter, loc, resultType, adaptor.getOperands()); rewriter.replaceOpWithNewOp(op, isZero, symbolicVal, division); return success(); } @@ -245,7 +246,7 @@ struct VariadicToBinaryOpConversion : OpConversionPattern { Value runner = operands[0]; for (Value operand : operands.drop_front()) - runner = rewriter.create(op.getLoc(), runner, operand); + runner = TargetOp::create(rewriter, op.getLoc(), runner, operand); rewriter.replaceOp(op, runner); return success(); diff --git a/lib/Conversion/ConvertToArcs/ConvertToArcs.cpp b/lib/Conversion/ConvertToArcs/ConvertToArcs.cpp index a74f1bb74d..e10f581eda 100644 --- a/lib/Conversion/ConvertToArcs/ConvertToArcs.cpp +++ b/lib/Conversion/ConvertToArcs/ConvertToArcs.cpp @@ -39,8 +39,8 @@ static LogicalResult convertInitialValue(seq::CompRegOp reg, // Use from_immutable cast to convert the seq.immutable type to the reg's // type. OpBuilder builder(reg); - auto init = builder.create(reg.getLoc(), reg.getType(), - reg.getInitialValue()); + auto init = seq::FromImmutableOp::create(builder, reg.getLoc(), reg.getType(), + reg.getInitialValue()); values.push_back(init); return success(); @@ -255,21 +255,21 @@ void Converter::extractArcs(HWModuleOp module) { } } assert(lastOp); - builder.create(lastOp->getLoc(), outputs); + arc::OutputOp::create(builder, lastOp->getLoc(), outputs); // Create the arc definition. builder.setInsertionPoint(module); - auto defOp = builder.create( - lastOp->getLoc(), - builder.getStringAttr( - globalNamespace.newName(module.getModuleName() + "_arc")), - builder.getFunctionType(inputTypes, outputTypes)); + auto defOp = + DefineOp::create(builder, lastOp->getLoc(), + builder.getStringAttr(globalNamespace.newName( + module.getModuleName() + "_arc")), + builder.getFunctionType(inputTypes, outputTypes)); defOp.getBody().push_back(block.release()); // Create the call to the arc definition to replace the operations that // we have just extracted. builder.setInsertionPoint(module.getBodyBlock()->getTerminator()); - auto arcOp = builder.create(lastOp->getLoc(), defOp, inputs); + auto arcOp = CallOp::create(builder, lastOp->getLoc(), defOp, inputs); arcUses.push_back(arcOp); for (auto [use, resultIdx] : externalUses) use->set(arcOp.getResult(resultIdx)); @@ -448,14 +448,13 @@ LogicalResult Converter::absorbRegs(HWModuleOp module) { } auto loc = regOps.back().getLoc(); - builder.create(loc, outputs); + arc::OutputOp::create(builder, loc, outputs); builder.setInsertionPoint(module); - auto defOp = - builder.create(loc, - builder.getStringAttr(globalNamespace.newName( - module.getModuleName() + "_arc")), - builder.getFunctionType(types, types)); + auto defOp = DefineOp::create(builder, loc, + builder.getStringAttr(globalNamespace.newName( + module.getModuleName() + "_arc")), + builder.getFunctionType(types, types)); defOp.getBody().push_back(block.release()); builder.setInsertionPoint(module.getBodyBlock()->getTerminator()); @@ -473,8 +472,8 @@ LogicalResult Converter::absorbRegs(HWModuleOp module) { } auto arcOp = - builder.create(loc, defOp, std::get<0>(clockAndResetAndOp), - /*enable=*/Value{}, 1, inputs, initialValues); + StateOp::create(builder, loc, defOp, std::get<0>(clockAndResetAndOp), + /*enable=*/Value{}, 1, inputs, initialValues); auto reset = std::get<1>(clockAndResetAndOp); if (reset) arcOp.getResetMutable().assign(reset); diff --git a/lib/Conversion/DCToHW/DCToHW.cpp b/lib/Conversion/DCToHW/DCToHW.cpp index e90a5ad6d2..eb31dc44f6 100644 --- a/lib/Conversion/DCToHW/DCToHW.cpp +++ b/lib/Conversion/DCToHW/DCToHW.cpp @@ -117,8 +117,8 @@ public: if (inputs.size() != 1) return Value(); - return builder - .create(loc, resultType, inputs[0]) + return UnrealizedConversionCastOp::create(builder, loc, resultType, + inputs[0]) ->getResult(0); }); @@ -128,8 +128,8 @@ public: if (inputs.size() != 1) return Value(); - return builder - .create(loc, resultType, inputs[0]) + return UnrealizedConversionCastOp::create(builder, loc, resultType, + inputs[0]) ->getResult(0); }); } @@ -230,7 +230,7 @@ struct RTLBuilder { return it->second; } - auto cval = b.create(loc, apv); + auto cval = hw::ConstantOp::create(b, loc, apv); if (!isZeroWidth) constants[apv] = cval; return cval; @@ -241,12 +241,12 @@ struct RTLBuilder { APInt(width, value, /*isSigned=*/false, /*implicitTrunc=*/true)); } std::pair wrap(Value data, Value valid, StringRef name = {}) { - auto wrapOp = b.create(loc, data, valid); + auto wrapOp = esi::WrapValidReadyOp::create(b, loc, data, valid); return {wrapOp.getResult(0), wrapOp.getResult(1)}; } std::pair unwrap(Value channel, Value ready, StringRef name = {}) { - auto unwrapOp = b.create(loc, channel, ready); + auto unwrapOp = esi::UnwrapValidReadyOp::create(b, loc, channel, ready); return {unwrapOp.getResult(0), unwrapOp.getResult(1)}; } @@ -262,13 +262,13 @@ struct RTLBuilder { "No global reset provided to this RTLBuilder - a reset " "signal must be provided to the reg(...) function."); - return b.create(loc, in, resolvedClk, resolvedRst, rstValue, - name); + return seq::CompRegOp::create(b, loc, in, resolvedClk, resolvedRst, + rstValue, name); } Value cmp(Value lhs, Value rhs, comb::ICmpPredicate predicate, StringRef name = {}) { - return b.create(loc, predicate, lhs, rhs); + return comb::ICmpOp::create(b, loc, predicate, lhs, rhs); } Value buildNamedOp(llvm::function_ref f, StringRef name) { @@ -285,13 +285,13 @@ struct RTLBuilder { /// Bitwise 'and'. Value bitAnd(ValueRange values, StringRef name = {}) { return buildNamedOp( - [&]() { return b.create(loc, values, false); }, name); + [&]() { return comb::AndOp::create(b, loc, values, false); }, name); } // Bitwise 'or'. Value bitOr(ValueRange values, StringRef name = {}) { return buildNamedOp( - [&]() { return b.create(loc, values, false); }, name); + [&]() { return comb::OrOp::create(b, loc, values, false); }, name); } /// Bitwise 'not'. @@ -308,23 +308,23 @@ struct RTLBuilder { } return buildNamedOp( - [&]() { return b.create(loc, value, allOnes); }, name); + [&]() { return comb::XorOp::create(b, loc, value, allOnes); }, name); } Value shl(Value value, Value shift, StringRef name = {}) { return buildNamedOp( - [&]() { return b.create(loc, value, shift); }, name); + [&]() { return comb::ShlOp::create(b, loc, value, shift); }, name); } Value concat(ValueRange values, StringRef name = {}) { - return buildNamedOp([&]() { return b.create(loc, values); }, - name); + return buildNamedOp( + [&]() { return comb::ConcatOp::create(b, loc, values); }, name); } llvm::SmallVector extractBits(Value v, StringRef name = {}) { llvm::SmallVector bits; for (unsigned i = 0, e = v.getType().getIntOrFloatBitWidth(); i != e; ++i) - bits.push_back(b.create(loc, v, i, /*bitWidth=*/1)); + bits.push_back(comb::ExtractOp::create(b, loc, v, i, /*bitWidth=*/1)); return bits; } @@ -337,7 +337,7 @@ struct RTLBuilder { Value extract(Value v, unsigned lo, unsigned hi, StringRef name = {}) { unsigned width = hi - lo + 1; return buildNamedOp( - [&]() { return b.create(loc, v, lo, width); }, name); + [&]() { return comb::ExtractOp::create(b, loc, v, lo, width); }, name); } /// Truncates 'value' to its lower 'width' bits. @@ -366,13 +366,13 @@ struct RTLBuilder { /// Creates a hw.array of the given values. Value arrayCreate(ValueRange values, StringRef name = {}) { return buildNamedOp( - [&]() { return b.create(loc, values); }, name); + [&]() { return hw::ArrayCreateOp::create(b, loc, values); }, name); } /// Extract the 'index'th value from the input array. Value arrayGet(Value array, Value index, StringRef name = {}) { return buildNamedOp( - [&]() { return b.create(loc, array, index); }, name); + [&]() { return hw::ArrayGetOp::create(b, loc, array, index); }, name); } /// Muxes a range of values. @@ -382,7 +382,7 @@ struct RTLBuilder { if (values.size() == 2) { return buildNamedOp( [&]() { - return b.create(loc, index, values[1], values[0]); + return comb::MuxOp::create(b, loc, index, values[1], values[0]); }, name); } @@ -447,7 +447,7 @@ static UnwrappedIO unwrapIO(Location loc, ValueRange operands, if (isZeroWidthType(innerType)) { // Feed the ESI wrap with an i0 constant. data = - rewriter.create(loc, rewriter.getIntegerType(0), 0); + hw::ConstantOp::create(rewriter, loc, rewriter.getIntegerType(0), 0); } else { // Create a backedge for the unresolved data. auto dataBackedge = bb.get(innerType); diff --git a/lib/Conversion/DatapathToComb/DatapathToComb.cpp b/lib/Conversion/DatapathToComb/DatapathToComb.cpp index 9d09fc5df0..5dba667727 100644 --- a/lib/Conversion/DatapathToComb/DatapathToComb.cpp +++ b/lib/Conversion/DatapathToComb/DatapathToComb.cpp @@ -49,9 +49,9 @@ struct DatapathCompressOpAddConversion : OpConversionPattern { auto inputs = op.getOperands(); unsigned width = inputs[0].getType().getIntOrFloatBitWidth(); // Sum all the inputs - set that to result value 0 - auto addOp = rewriter.create(loc, inputs, true); + auto addOp = comb::AddOp::create(rewriter, loc, inputs, true); // Replace remaining results with zeros - auto zeroOp = rewriter.create(loc, APInt(width, 0)); + auto zeroOp = hw::ConstantOp::create(rewriter, loc, APInt(width, 0)); SmallVector results(op.getNumResults() - 1, zeroOp); results.push_back(addOp); rewriter.replaceOp(op, results); @@ -134,10 +134,10 @@ private: "Cannot return more results than the operator width"); for (unsigned i = 0; i < op.getNumResults(); ++i) { - auto repl = rewriter.create(loc, bBits[i], width); - auto ppRow = rewriter.create(loc, repl, a); - auto shiftBy = rewriter.create(loc, APInt(width, i)); - auto ppAlign = rewriter.create(loc, ppRow, shiftBy); + auto repl = comb::ReplicateOp::create(rewriter, loc, bBits[i], width); + auto ppRow = comb::AndOp::create(rewriter, loc, repl, a); + auto shiftBy = hw::ConstantOp::create(rewriter, loc, APInt(width, i)); + auto ppAlign = comb::ShlOp::create(rewriter, loc, ppRow, shiftBy); partialProducts.push_back(ppAlign); } @@ -149,10 +149,10 @@ private: Value a, Value b, PartialProductOp op, unsigned width) { Location loc = op.getLoc(); - auto zeroFalse = rewriter.create(loc, APInt(1, 0)); - auto zeroWidth = rewriter.create(loc, APInt(width, 0)); - auto oneWidth = rewriter.create(loc, APInt(width, 1)); - Value twoA = rewriter.create(loc, a, oneWidth); + auto zeroFalse = hw::ConstantOp::create(rewriter, loc, APInt(1, 0)); + auto zeroWidth = hw::ConstantOp::create(rewriter, loc, APInt(width, 0)); + auto oneWidth = hw::ConstantOp::create(rewriter, loc, APInt(width, 1)); + Value twoA = comb::ShlOp::create(rewriter, loc, a, oneWidth); SmallVector bBits = extractBits(rewriter, b); @@ -176,30 +176,33 @@ private: // Is the encoding zero or negative (an approximation) Value encNeg = bip1; // Is the encoding one = b[i] xor b[i-1] - Value encOne = rewriter.create(loc, bi, bim1, true); + Value encOne = comb::XorOp::create(rewriter, loc, bi, bim1, true); // Is the encoding two = (bip1 & ~bi & ~bim1) | (~bip1 & bi & bim1) - Value constOne = rewriter.create(loc, APInt(1, 1)); - Value biInv = rewriter.create(loc, bi, constOne, true); - Value bip1Inv = rewriter.create(loc, bip1, constOne, true); - Value bim1Inv = rewriter.create(loc, bim1, constOne, true); + Value constOne = hw::ConstantOp::create(rewriter, loc, APInt(1, 1)); + Value biInv = comb::XorOp::create(rewriter, loc, bi, constOne, true); + Value bip1Inv = comb::XorOp::create(rewriter, loc, bip1, constOne, true); + Value bim1Inv = comb::XorOp::create(rewriter, loc, bim1, constOne, true); - Value andLeft = rewriter.create( - loc, ValueRange{bip1Inv, bi, bim1}, true); - Value andRight = rewriter.create( - loc, ValueRange{bip1, biInv, bim1Inv}, true); - Value encTwo = rewriter.create(loc, andLeft, andRight, true); + Value andLeft = comb::AndOp::create(rewriter, loc, + ValueRange{bip1Inv, bi, bim1}, true); + Value andRight = comb::AndOp::create( + rewriter, loc, ValueRange{bip1, biInv, bim1Inv}, true); + Value encTwo = comb::OrOp::create(rewriter, loc, andLeft, andRight, true); - Value encNegRepl = rewriter.create(loc, encNeg, width); - Value encOneRepl = rewriter.create(loc, encOne, width); - Value encTwoRepl = rewriter.create(loc, encTwo, width); + Value encNegRepl = + comb::ReplicateOp::create(rewriter, loc, encNeg, width); + Value encOneRepl = + comb::ReplicateOp::create(rewriter, loc, encOne, width); + Value encTwoRepl = + comb::ReplicateOp::create(rewriter, loc, encTwo, width); // Select between 2*a or 1*a or 0*a - Value selTwoA = rewriter.create(loc, encTwoRepl, twoA); - Value selOneA = rewriter.create(loc, encOneRepl, a); - Value magA = rewriter.create(loc, selTwoA, selOneA, true); + Value selTwoA = comb::AndOp::create(rewriter, loc, encTwoRepl, twoA); + Value selOneA = comb::AndOp::create(rewriter, loc, encOneRepl, a); + Value magA = comb::OrOp::create(rewriter, loc, selTwoA, selOneA, true); // Conditionally invert the row - Value ppRow = rewriter.create(loc, magA, encNegRepl, true); + Value ppRow = comb::XorOp::create(rewriter, loc, magA, encNegRepl, true); // No sign-correction in the first row if (i == 0) { @@ -211,12 +214,13 @@ private: // Insert a sign-correction from the previous row assert(i >= 2 && "Expected i to be at least 2 for sign correction"); // {ppRow, 0, encNegPrev} << 2*(i-1) - Value withSignCorrection = rewriter.create( - loc, ValueRange{ppRow, zeroFalse, encNegPrev}); + Value withSignCorrection = comb::ConcatOp::create( + rewriter, loc, ValueRange{ppRow, zeroFalse, encNegPrev}); Value ppAlignPre = - rewriter.create(loc, withSignCorrection, 0, width); - Value shiftBy = rewriter.create(loc, APInt(width, i - 2)); - Value ppAlign = rewriter.create(loc, ppAlignPre, shiftBy); + comb::ExtractOp::create(rewriter, loc, withSignCorrection, 0, width); + Value shiftBy = + hw::ConstantOp::create(rewriter, loc, APInt(width, i - 2)); + Value ppAlign = comb::ShlOp::create(rewriter, loc, ppAlignPre, shiftBy); partialProducts.push_back(ppAlign); encNegPrev = encNeg; diff --git a/lib/Conversion/DatapathToSMT/DatapathToSMT.cpp b/lib/Conversion/DatapathToSMT/DatapathToSMT.cpp index c39dabc8b7..d30a716b5e 100644 --- a/lib/Conversion/DatapathToSMT/DatapathToSMT.cpp +++ b/lib/Conversion/DatapathToSMT/DatapathToSMT.cpp @@ -46,14 +46,14 @@ struct CompressOpConversion : OpConversionPattern { Value operandRunner = operands[0]; for (Value operand : operands.drop_front()) operandRunner = - rewriter.create(op.getLoc(), operandRunner, operand); + smt::BVAddOp::create(rewriter, op.getLoc(), operandRunner, operand); // Create free variables SmallVector newResults; newResults.reserve(results.size()); for (Value result : results) { - auto declareFunOp = rewriter.create( - op.getLoc(), typeConverter->convertType(result.getType())); + auto declareFunOp = smt::DeclareFunOp::create( + rewriter, op.getLoc(), typeConverter->convertType(result.getType())); newResults.push_back(declareFunOp.getResult()); } @@ -61,13 +61,13 @@ struct CompressOpConversion : OpConversionPattern { Value resultRunner = newResults.front(); for (auto freeVar : llvm::drop_begin(newResults, 1)) resultRunner = - rewriter.create(op.getLoc(), resultRunner, freeVar); + smt::BVAddOp::create(rewriter, op.getLoc(), resultRunner, freeVar); // Assert sum operands == sum results (free variables) auto premise = - rewriter.create(op.getLoc(), operandRunner, resultRunner); + smt::EqOp::create(rewriter, op.getLoc(), operandRunner, resultRunner); // Encode via an assertion (could be relaxed to an assumption). - rewriter.create(op.getLoc(), premise); + smt::AssertOp::create(rewriter, op.getLoc(), premise); if (newResults.size() != results.size()) return rewriter.notifyMatchFailure(op, "expected same number of results"); @@ -93,14 +93,14 @@ struct PartialProductOpConversion : OpConversionPattern { // Multiply the operands auto mulResult = - rewriter.create(op.getLoc(), operands[0], operands[1]); + smt::BVMulOp::create(rewriter, op.getLoc(), operands[0], operands[1]); // Create free variables SmallVector newResults; newResults.reserve(results.size()); for (Value result : results) { - auto declareFunOp = rewriter.create( - op.getLoc(), typeConverter->convertType(result.getType())); + auto declareFunOp = smt::DeclareFunOp::create( + rewriter, op.getLoc(), typeConverter->convertType(result.getType())); newResults.push_back(declareFunOp.getResult()); } @@ -108,13 +108,13 @@ struct PartialProductOpConversion : OpConversionPattern { Value resultRunner = newResults.front(); for (auto freeVar : llvm::drop_begin(newResults, 1)) resultRunner = - rewriter.create(op.getLoc(), resultRunner, freeVar); + smt::BVAddOp::create(rewriter, op.getLoc(), resultRunner, freeVar); // Assert product of operands == sum results (free variables) auto premise = - rewriter.create(op.getLoc(), mulResult, resultRunner); + smt::EqOp::create(rewriter, op.getLoc(), mulResult, resultRunner); // Encode via an assertion (could be relaxed to an assumption). - rewriter.create(op.getLoc(), premise); + smt::AssertOp::create(rewriter, op.getLoc(), premise); if (newResults.size() != results.size()) return rewriter.notifyMatchFailure(op, "expected same number of results"); diff --git a/lib/Conversion/ExportVerilog/HWLowerInstanceChoices.cpp b/lib/Conversion/ExportVerilog/HWLowerInstanceChoices.cpp index bd43bdba6d..703071443c 100644 --- a/lib/Conversion/ExportVerilog/HWLowerInstanceChoices.cpp +++ b/lib/Conversion/ExportVerilog/HWLowerInstanceChoices.cpp @@ -83,20 +83,20 @@ LogicalResult ExportVerilog::lowerHWInstanceChoices(mlir::ModuleOp module) { auto symName = ns.newName(name); auto symNameAttr = declBuilder.getStringAttr(symName); auto symRef = FlatSymbolRefAttr::get(symNameAttr); - declBuilder.create(inst.getLoc(), symNameAttr, - /*args=*/ArrayAttr{}, - /*verilogName=*/StringAttr{}); + MacroDeclOp::create(declBuilder, inst.getLoc(), symNameAttr, + /*args=*/ArrayAttr{}, + /*verilogName=*/StringAttr{}); // This pass now generates the macros and attaches them to the instance // choice as an attribute. As a better solution, this pass should be moved // out of the umbrella of ExportVerilog and it should lower the `hw` // instance choices to a better SV-level representation of the operation. ImplicitLocOpBuilder builder(inst.getLoc(), inst); - builder.create( - symName, [&] {}, + sv::IfDefOp::create( + builder, symName, [&] {}, [&] { - builder.create( - symRef, builder.getStringAttr("{{0}}"), + sv::MacroDefOp::create( + builder, symRef, builder.getStringAttr("{{0}}"), builder.getArrayAttr( {FlatSymbolRefAttr::get(defaultModuleOp.getNameAttr())})); }); diff --git a/lib/Conversion/ExportVerilog/LegalizeAnonEnums.cpp b/lib/Conversion/ExportVerilog/LegalizeAnonEnums.cpp index 6418c429c4..9e6a37a122 100644 --- a/lib/Conversion/ExportVerilog/LegalizeAnonEnums.cpp +++ b/lib/Conversion/ExportVerilog/LegalizeAnonEnums.cpp @@ -34,7 +34,7 @@ struct LegalizeAnonEnums auto topLevel = getOperation(); if (!typeScope) { auto builder = OpBuilder::atBlockBegin(&topLevel.getRegion().front()); - typeScope = builder.create(topLevel.getLoc(), "Enums"); + typeScope = TypeScopeOp::create(builder, topLevel.getLoc(), "Enums"); typeScope.getBodyRegion().push_back(new Block()); mlir::SymbolTable symbolTable(topLevel); symbolTable.insert(typeScope); @@ -52,7 +52,7 @@ struct LegalizeAnonEnums auto typeScope = getTypeScope(); auto builder = OpBuilder::atBlockEnd(&typeScope.getRegion().front()); auto declName = StringAttr::get(context, "enum" + Twine(enumCount++)); - builder.create(loc, declName, TypeAttr::get(type), nullptr); + TypedeclOp::create(builder, loc, declName, TypeAttr::get(type), nullptr); auto symRef = SymbolRefAttr::get(typeScope.getSymNameAttr(), FlatSymbolRefAttr::get(declName)); typeAlias = TypeAliasType::get(symRef, type); diff --git a/lib/Conversion/ExportVerilog/PrepareForEmission.cpp b/lib/Conversion/ExportVerilog/PrepareForEmission.cpp index 8d5825c7eb..654158c5ea 100644 --- a/lib/Conversion/ExportVerilog/PrepareForEmission.cpp +++ b/lib/Conversion/ExportVerilog/PrepareForEmission.cpp @@ -99,9 +99,9 @@ static void spillWiresForInstanceInputs(HWInstanceLike op) { else nameTmp += std::to_string(opNum); - auto newWire = builder.create(src.getType(), nameTmp); - auto newWireRead = builder.create(newWire); - auto connect = builder.create(newWire, src); + auto newWire = sv::WireOp::create(builder, src.getType(), nameTmp); + auto newWireRead = ReadInOutOp::create(builder, newWire); + auto connect = AssignOp::create(builder, newWire, src); newWireRead->moveBefore(op); connect->moveBefore(op); op->setOperand(opNum, newWireRead); @@ -118,14 +118,14 @@ static void replacePortWithWire(ImplicitLocOpBuilder &builder, Operation *op, Value newTarget; if (isProcedural) { - newTarget = builder.create(result.getType(), - builder.getStringAttr(name)); + newTarget = sv::LogicOp::create(builder, result.getType(), + builder.getStringAttr(name)); } else { - newTarget = builder.create(result.getType(), name); + newTarget = sv::WireOp::create(builder, result.getType(), name); } while (!result.use_empty()) { - auto newRead = builder.create(newTarget); + auto newRead = sv::ReadInOutOp::create(builder, newTarget); OpOperand &use = *result.getUses().begin(); use.set(newRead); newRead->moveBefore(use.getOwner()); @@ -133,9 +133,9 @@ static void replacePortWithWire(ImplicitLocOpBuilder &builder, Operation *op, Operation *connect; if (isProcedural) { - connect = builder.create(newTarget, result); + connect = sv::BPAssignOp::create(builder, newTarget, result); } else { - connect = builder.create(newTarget, result); + connect = sv::AssignOp::create(builder, newTarget, result); } connect->moveAfter(op); } @@ -180,16 +180,16 @@ static void lowerInstanceResults(HWInstanceLike op) { nameTmp += n.getValue().str(); else nameTmp += std::to_string(resNum); - Value newWire = builder.create(result.getType(), nameTmp); + Value newWire = sv::WireOp::create(builder, result.getType(), nameTmp); while (!result.use_empty()) { - auto newWireRead = builder.create(newWire); + auto newWireRead = ReadInOutOp::create(builder, newWire); OpOperand &use = *result.getUses().begin(); use.set(newWireRead); newWireRead->moveBefore(use.getOwner()); } - auto connect = builder.create(newWire, result); + auto connect = AssignOp::create(builder, newWire, result); connect->moveAfter(op); } } @@ -246,9 +246,9 @@ static void lowerUsersToTemporaryWire(Operation &op, // If the op is in a procedural region, use logic op. if (isProceduralRegion) - newWire = builder.create(wireElementType, name); + newWire = LogicOp::create(builder, wireElementType, name); else - newWire = builder.create(wireElementType, name); + newWire = sv::WireOp::create(builder, wireElementType, name); // Replace all uses with newWire. Wrap in ReadInOutOp if required. while (!result.use_empty()) { @@ -256,7 +256,7 @@ static void lowerUsersToTemporaryWire(Operation &op, if (isResultInOut) { use.set(newWire); } else { - auto newWireRead = builder.create(newWire); + auto newWireRead = ReadInOutOp::create(builder, newWire); use.set(newWireRead); newWireRead->moveBefore(use.getOwner()); } @@ -267,14 +267,14 @@ static void lowerUsersToTemporaryWire(Operation &op, ReadInOutOp resultRead; if (isResultInOut) - resultRead = builder.create(result); + resultRead = ReadInOutOp::create(builder, result); if (isProceduralRegion) - connect = builder.create( - newWire, isResultInOut ? resultRead.getResult() : result); + connect = BPAssignOp::create( + builder, newWire, isResultInOut ? resultRead.getResult() : result); else - connect = builder.create( - newWire, isResultInOut ? resultRead.getResult() : result); + connect = AssignOp::create( + builder, newWire, isResultInOut ? resultRead.getResult() : result); connect->moveAfter(&op); if (resultRead) @@ -427,9 +427,9 @@ static Operation *rewriteAddWithNegativeConstant(comb::AddOp add, ImplicitLocOpBuilder builder(add.getLoc(), add); // Get the positive constant. - auto negCst = builder.create(-rhsCst.getValue()); - auto sub = - builder.create(add.getOperand(0), negCst, add.getTwoState()); + auto negCst = hw::ConstantOp::create(builder, -rhsCst.getValue()); + auto sub = comb::SubOp::create(builder, add.getOperand(0), negCst, + add.getTwoState()); add.getResult().replaceAllUsesWith(sub); add.erase(); if (rhsCst.use_empty()) @@ -446,7 +446,7 @@ static Operation *lowerStructExplodeOp(hw::StructExplodeOp op) { for (auto [res, field] : llvm::zip(op.getResults(), structType.getElements())) { auto extract = - builder.create(op.getInput(), field.name); + hw::StructExtractOp::create(builder, op.getInput(), field.name); if (!firstOp) firstOp = extract; res.replaceAllUsesWith(extract); @@ -493,16 +493,16 @@ static bool rewriteSideEffectingExpr(Operation *op) { // Scan to the top of the region tree to find out where to insert the reg. Operation *parentOp = findParentInNonProceduralRegion(op); OpBuilder builder(parentOp); - auto reg = builder.create(op->getLoc(), opValue.getType()); + auto reg = RegOp::create(builder, op->getLoc(), opValue.getType()); // Everything using the expr now uses a read_inout of the reg. - auto value = builder.create(op->getLoc(), reg); + auto value = ReadInOutOp::create(builder, op->getLoc(), reg); opValue.replaceAllUsesWith(value); // We assign the side effect expr to the reg immediately after that expression // is computed. builder.setInsertionPointAfter(op); - builder.create(op->getLoc(), reg, opValue); + BPAssignOp::create(builder, op->getLoc(), reg, opValue); return true; } @@ -715,7 +715,7 @@ static bool reuseExistingInOut(Operation *op, const LoweringOptions &options) { ImplicitLocOpBuilder builder(assign.getDest().getLoc(), op->getContext()); for (OpOperand *use : uses) { builder.setInsertionPoint(use->getOwner()); - auto read = builder.create(assign.getDest()); + auto read = ReadInOutOp::create(builder, assign.getDest()); use->set(read); } if (auto *destOp = assign.getDest().getDefiningOp()) @@ -852,12 +852,13 @@ static void applyWireLowerings(Block &block, ImplicitLocOpBuilder builder(hwWireOp.getLoc(), &block, declarePoint); Value decl; if (isProceduralRegion) { - decl = builder.create(hwWireOp.getType(), hwWireOp.getNameAttr(), - hwWireOp.getInnerSymAttr()); - } else { decl = - builder.create(hwWireOp.getType(), hwWireOp.getNameAttr(), - hwWireOp.getInnerSymAttr()); + LogicOp::create(builder, hwWireOp.getType(), hwWireOp.getNameAttr(), + hwWireOp.getInnerSymAttr()); + } else { + decl = sv::WireOp::create(builder, hwWireOp.getType(), + hwWireOp.getNameAttr(), + hwWireOp.getInnerSymAttr()); } // Carry attributes over to the lowered operation. @@ -873,9 +874,9 @@ static void applyWireLowerings(Block &block, if (assignPoint != declarePoint) builder.setInsertionPoint(&block, assignPoint); if (isProceduralRegion) - builder.create(decl, hwWireOp.getInput()); + BPAssignOp::create(builder, decl, hwWireOp.getInput()); else - builder.create(decl, hwWireOp.getInput()); + AssignOp::create(builder, decl, hwWireOp.getInput()); // Create the read. If we have created the assignment at a different point // than the declaration, reposition the builder to immediately after the @@ -883,7 +884,7 @@ static void applyWireLowerings(Block &block, // assignment. if (assignPoint != declarePoint) builder.setInsertionPointAfterValue(decl); - auto readOp = builder.create(decl); + auto readOp = sv::ReadInOutOp::create(builder, decl); // Replace the HW wire. hwWireOp.replaceAllUsesWith(readOp.getResult()); @@ -1035,15 +1036,15 @@ static LogicalResult legalizeHWModule(Block &block, llvm::zip(aggregateConstantOp.getFieldsAttr(), structType.getElements())) { if (auto arrayAttr = dyn_cast(value)) - operands.push_back( - builder.create(field.type, arrayAttr)); + operands.push_back(hw::AggregateConstantOp::create( + builder, field.type, arrayAttr)); else - operands.push_back(builder.create( - field.type, cast(value))); + operands.push_back(hw::ConstantOp::create( + builder, field.type, cast(value))); } auto structCreate = - builder.create(structType, operands); + hw::StructCreateOp::create(builder, structType, operands); aggregateConstantOp.getResult().replaceAllUsesWith(structCreate); // Reset the iterator. opIterator = std::next(op.getIterator()); @@ -1063,23 +1064,23 @@ static LogicalResult legalizeHWModule(Block &block, cast(structCreateOp.getResult().getType()); bool procedural = op.getParentOp()->hasTrait(); if (procedural) - wireOp = builder.create(structType); + wireOp = LogicOp::create(builder, structType); else - wireOp = builder.create(structType); + wireOp = sv::WireOp::create(builder, structType); for (auto [input, field] : llvm::zip(structCreateOp.getInput(), structType.getElements())) { auto target = - builder.create(wireOp, field.name); + sv::StructFieldInOutOp::create(builder, wireOp, field.name); if (procedural) - builder.create(target, input); + BPAssignOp::create(builder, target, input); else - builder.create(target, input); + AssignOp::create(builder, target, input); } // Have to create a separate read for each use to keep things legal. for (auto &use : llvm::make_early_inc_range(structCreateOp.getResult().getUses())) - use.set(builder.create(wireOp)); + use.set(ReadInOutOp::create(builder, wireOp)); structCreateOp.erase(); continue; @@ -1092,26 +1093,26 @@ static LogicalResult legalizeHWModule(Block &block, ImplicitLocOpBuilder builder(op.getLoc(), &op); Value decl; if (procedural) - decl = builder.create(arrayInjectOp.getType()); + decl = LogicOp::create(builder, arrayInjectOp.getType()); else - decl = builder.create(arrayInjectOp.getType()); + decl = sv::RegOp::create(builder, arrayInjectOp.getType()); for (auto &use : llvm::make_early_inc_range(arrayInjectOp->getUses())) - use.set(builder.create(decl)); + use.set(ReadInOutOp::create(builder, decl)); // Make sure we have a procedural region where we can first copy the input // array into `decl`, and then overwrite a single index. if (!procedural) { - auto alwaysOp = builder.create(); + auto alwaysOp = sv::AlwaysCombOp::create(builder); builder.setInsertionPointToStart(alwaysOp.getBodyBlock()); } // Copy the input array into `decl`. - builder.create(decl, arrayInjectOp.getInput()); + sv::BPAssignOp::create(builder, decl, arrayInjectOp.getInput()); // Overwrite the injected value. - auto target = - builder.create(decl, arrayInjectOp.getIndex()); - builder.create(target, arrayInjectOp.getElement()); + auto target = sv::ArrayIndexInOutOp::create(builder, decl, + arrayInjectOp.getIndex()); + sv::BPAssignOp::create(builder, target, arrayInjectOp.getElement()); arrayInjectOp.erase(); continue; @@ -1141,13 +1142,13 @@ static LogicalResult legalizeHWModule(Block &block, auto type = op.getOperand(1).getType(); const auto *name = "_GEN_ARRAY_IDX"; if (op.getParentOp()->hasTrait()) { - wireOp = builder.create(type, name); - builder.create(wireOp, op.getOperand(1)); + wireOp = LogicOp::create(builder, type, name); + BPAssignOp::create(builder, wireOp, op.getOperand(1)); } else { - wireOp = builder.create(type, name); - builder.create(wireOp, op.getOperand(1)); + wireOp = sv::WireOp::create(builder, type, name); + AssignOp::create(builder, wireOp, op.getOperand(1)); } - readOp = builder.create(wireOp); + readOp = ReadInOutOp::create(builder, wireOp); } op.setOperand(1, readOp); @@ -1349,16 +1350,16 @@ static void fixUpEmptyModules(hw::HWEmittableModuleLike module) { return; // Not empty so no need to fix up. OpBuilder builder(module->getContext()); builder.setInsertionPoint(outputOp); - auto constant = builder.create(module.getLoc(), - builder.getBoolAttr(true)); - auto wire = builder.create(module.getLoc(), builder.getI1Type()); + auto constant = hw::ConstantOp::create(builder, module.getLoc(), + builder.getBoolAttr(true)); + auto wire = sv::WireOp::create(builder, module.getLoc(), builder.getI1Type()); sv::setSVAttributes(wire, sv::SVAttributeAttr::get( builder.getContext(), "This wire is added to avoid emitting empty modules. " "See `fixUpEmptyModules` lowering option in CIRCT.", /*emitAsComment=*/true)); - builder.create(module.getLoc(), wire, constant); + sv::AssignOp::create(builder, module.getLoc(), wire, constant); } // NOLINTNEXTLINE(misc-no-recursion) diff --git a/lib/Conversion/FIRRTLToHW/LowerToHW.cpp b/lib/Conversion/FIRRTLToHW/LowerToHW.cpp index 43b7d63761..80e35d2b56 100644 --- a/lib/Conversion/FIRRTLToHW/LowerToHW.cpp +++ b/lib/Conversion/FIRRTLToHW/LowerToHW.cpp @@ -133,8 +133,8 @@ static Value castToFIRRTLType(Value val, Type type, val = builder.createOrFold(bundle.getPassiveType(), val); if (type != val.getType()) - val = builder.create(type, val).getResult( - 0); + val = mlir::UnrealizedConversionCastOp::create(builder, type, val) + .getResult(0); return val; } @@ -145,17 +145,16 @@ static Value castFromFIRRTLType(Value val, Type type, if (hw::StructType structTy = dyn_cast(type)) { // Strip off Flip type if needed. - val = - builder - .create( - type_cast(val.getType()).getPassiveType(), val) - .getResult(0); + val = mlir::UnrealizedConversionCastOp::create( + builder, + type_cast(val.getType()).getPassiveType(), val) + .getResult(0); val = builder.createOrFold(type, val); return val; } val = - builder.create(type, val).getResult(0); + mlir::UnrealizedConversionCastOp::create(builder, type, val).getResult(0); return val; } @@ -480,8 +479,8 @@ private: auto b = ImplicitLocOpBuilder::atBlockBegin( circuitOp.getLoc(), &circuitOp->getParentRegion()->getBlocks().back()); - typeScope = b.create( - b.getStringAttr(circuitOp.getName() + "__TYPESCOPE_")); + typeScope = hw::TypeScopeOp::create( + b, b.getStringAttr(circuitOp.getName() + "__TYPESCOPE_")); typeScope.getBodyRegion().push_back(new Block()); } auto typeName = firAlias.getName(); @@ -494,8 +493,8 @@ private: auto typeScopeBuilder = ImplicitLocOpBuilder::atBlockEnd(typeLoc, typeScope.getBodyBlock()); - auto typeDecl = typeScopeBuilder.create(typeLoc, typeName, - rawType, nullptr); + auto typeDecl = hw::TypedeclOp::create(typeScopeBuilder, typeLoc, + typeName, rawType, nullptr); auto hwAlias = hw::TypeAliasType::get( SymbolRefAttr::get(typeScope.getSymNameAttr(), {FlatSymbolRefAttr::get(typeDecl)}), @@ -706,9 +705,9 @@ void FIRRTLModuleLowering::runOnOperation() { }) .Case([&](auto oldOp) { auto builder = OpBuilder::atBlockEnd(topLevelModule); - auto newOp = builder.create( - oldOp.getLoc(), oldOp.getNameAttr(), - oldOp.getParametersAttr()); + auto newOp = verif::FormalOp::create(builder, oldOp.getLoc(), + oldOp.getNameAttr(), + oldOp.getParametersAttr()); newOp.getBody().emplaceBlock(); state.recordModuleMapping(oldOp, newOp); opsToProcess.push_back(newOp); @@ -717,8 +716,8 @@ void FIRRTLModuleLowering::runOnOperation() { .Case([&](auto oldOp) { auto loc = oldOp.getLoc(); auto builder = OpBuilder::atBlockEnd(topLevelModule); - auto newOp = builder.create( - loc, oldOp.getNameAttr(), oldOp.getParametersAttr()); + auto newOp = verif::SimulationOp::create( + builder, loc, oldOp.getNameAttr(), oldOp.getParametersAttr()); auto &body = newOp.getRegion().emplaceBlock(); body.addArgument(seq::ClockType::get(builder.getContext()), loc); body.addArgument(builder.getI1Type(), loc); @@ -811,7 +810,7 @@ void FIRRTLModuleLowering::runOnOperation() { if (!state.macroDeclNames.empty()) { ImplicitLocOpBuilder b(UnknownLoc::get(&getContext()), circuit); for (auto name : state.macroDeclNames) { - b.create(name); + sv::MacroDeclOp::create(b, name); } } @@ -836,23 +835,23 @@ void FIRRTLModuleLowering::lowerFileHeader(CircuitOp op, StringRef defineFalse = StringRef()) { if (!defineFalse.data()) { assert(defineTrue.data() && "didn't define anything"); - b.create( - guard, [&]() { b.create(defName, defineTrue); }); + sv::IfDefOp::create( + b, guard, [&]() { sv::MacroDefOp::create(b, defName, defineTrue); }); } else { - b.create( - guard, + sv::IfDefOp::create( + b, guard, [&]() { if (defineTrue.data()) - b.create(defName, defineTrue); + sv::MacroDefOp::create(b, defName, defineTrue); }, - [&]() { b.create(defName, defineFalse); }); + [&]() { sv::MacroDefOp::create(b, defName, defineFalse); }); } }; // Helper function to emit #ifndef guard. auto emitGuard = [&](const char *guard, llvm::function_ref body) { - b.create( - guard, []() {}, body); + sv::IfDefOp::create( + b, guard, []() {}, body); }; if (state.usedFileDescriptorLib) { @@ -885,8 +884,8 @@ void FIRRTLModuleLowering::lowerFileHeader(CircuitOp op, DictionaryAttr::get(b.getContext(), perArgumentsAttr)}; // Create the function declaration - auto func = b.create( - /*sym_name=*/ + auto func = sv::FuncOp::create( + b, /*sym_name=*/ "__circt_lib_logging::FileDescriptor::get", moduleType, /*perArgumentAttrs=*/ b.getArrayAttr( @@ -899,11 +898,11 @@ void FIRRTLModuleLowering::lowerFileHeader(CircuitOp op, b.getStringAttr("__circt_lib_logging::FileDescriptor::get")); func.setPrivate(); - b.create("__CIRCT_LIB_LOGGING"); + sv::MacroDeclOp::create(b, "__CIRCT_LIB_LOGGING"); // Create the fragment containing the FileDescriptor class. - b.create("CIRCT_LIB_LOGGING_FRAGMENT", [&] { + emit::FragmentOp::create(b, "CIRCT_LIB_LOGGING_FRAGMENT", [&] { emitGuard("__CIRCT_LIB_LOGGING", [&]() { - b.create(R"(// CIRCT Logging Library + sv::VerbatimOp::create(b, R"(// CIRCT Logging Library package __circt_lib_logging; class FileDescriptor; static int global_id [string]; @@ -919,18 +918,18 @@ package __circt_lib_logging; endpackage )"); - b.create("__CIRCT_LIB_LOGGING", ""); + sv::MacroDefOp::create(b, "__CIRCT_LIB_LOGGING", ""); }); }); } if (state.usedPrintf) { - b.create("PRINTF_COND"); - b.create("PRINTF_COND_"); - b.create("PRINTF_COND_FRAGMENT", [&] { - b.create( - "\n// Users can define 'PRINTF_COND' to add an extra gate to " - "prints."); + sv::MacroDeclOp::create(b, "PRINTF_COND"); + sv::MacroDeclOp::create(b, "PRINTF_COND_"); + emit::FragmentOp::create(b, "PRINTF_COND_FRAGMENT", [&] { + sv::VerbatimOp::create( + b, "\n// Users can define 'PRINTF_COND' to add an extra gate to " + "prints."); emitGuard("PRINTF_COND_", [&]() { emitGuardedDefine("PRINTF_COND", "PRINTF_COND_", "(`PRINTF_COND)", "1"); }); @@ -938,12 +937,12 @@ endpackage } if (state.usedAssertVerboseCond) { - b.create("ASSERT_VERBOSE_COND"); - b.create("ASSERT_VERBOSE_COND_"); - b.create("ASSERT_VERBOSE_COND_FRAGMENT", [&] { - b.create( - "\n// Users can define 'ASSERT_VERBOSE_COND' to add an extra " - "gate to assert error printing."); + sv::MacroDeclOp::create(b, "ASSERT_VERBOSE_COND"); + sv::MacroDeclOp::create(b, "ASSERT_VERBOSE_COND_"); + emit::FragmentOp::create(b, "ASSERT_VERBOSE_COND_FRAGMENT", [&] { + sv::VerbatimOp::create( + b, "\n// Users can define 'ASSERT_VERBOSE_COND' to add an extra " + "gate to assert error printing."); emitGuard("ASSERT_VERBOSE_COND_", [&]() { emitGuardedDefine("ASSERT_VERBOSE_COND", "ASSERT_VERBOSE_COND_", "(`ASSERT_VERBOSE_COND)", "1"); @@ -952,12 +951,12 @@ endpackage } if (state.usedStopCond) { - b.create("STOP_COND"); - b.create("STOP_COND_"); - b.create("STOP_COND_FRAGMENT", [&] { - b.create( - "\n// Users can define 'STOP_COND' to add an extra gate " - "to stop conditions."); + sv::MacroDeclOp::create(b, "STOP_COND"); + sv::MacroDeclOp::create(b, "STOP_COND_"); + emit::FragmentOp::create(b, "STOP_COND_FRAGMENT", [&] { + sv::VerbatimOp::create( + b, "\n// Users can define 'STOP_COND' to add an extra gate " + "to stop conditions."); emitGuard("STOP_COND_", [&]() { emitGuardedDefine("STOP_COND", "STOP_COND_", "(`STOP_COND)", "1"); }); @@ -1161,8 +1160,8 @@ FIRRTLModuleLowering::lowerExtModule(FExtModuleOp oldModule, // no known default values in the extmodule. This ensures that the // hw.instance will print all the parameters when generating verilog. auto parameters = getHWParameters(oldModule, /*ignoreValues=*/true); - auto newModule = builder.create( - oldModule.getLoc(), nameAttr, ports, verilogName, parameters); + auto newModule = hw::HWModuleExternOp::create( + builder, oldModule.getLoc(), nameAttr, ports, verilogName, parameters); SymbolTable::setSymbolVisibility(newModule, SymbolTable::getSymbolVisibility(oldModule)); @@ -1194,8 +1193,8 @@ FIRRTLModuleLowering::lowerMemModule(FMemModuleOp oldModule, // Build the new hw.module op. auto builder = OpBuilder::atBlockEnd(topLevelModule); - auto newModule = builder.create( - oldModule.getLoc(), oldModule.getModuleNameAttr(), ports, + auto newModule = hw::HWModuleExternOp::create( + builder, oldModule.getLoc(), oldModule.getModuleNameAttr(), ports, oldModule.getModuleNameAttr()); loweringState.processRemainingAnnotations(oldModule, AnnotationSet(oldModule)); @@ -1217,7 +1216,7 @@ FIRRTLModuleLowering::lowerModule(FModuleOp oldModule, Block *topLevelModule, auto builder = OpBuilder::atBlockEnd(topLevelModule); auto nameAttr = builder.getStringAttr(oldModule.getName()); auto newModule = - builder.create(oldModule.getLoc(), nameAttr, ports); + hw::HWModuleOp::create(builder, oldModule.getLoc(), nameAttr, ports); if (auto comment = oldModule->getAttrOfType("comment")) newModule.setCommentAttr(comment); @@ -1357,12 +1356,12 @@ tryEliminatingConnectsToValue(Value flipValue, Operation *insertPoint, // Convert fliped sources to passive sources. if (!type_cast(connectSrc.getType()).isPassive()) - connectSrc = builder - .create( - type_cast(connectSrc.getType()) - .getPassiveType(), - connectSrc) - .getResult(0); + connectSrc = + mlir::UnrealizedConversionCastOp::create( + builder, + type_cast(connectSrc.getType()).getPassiveType(), + connectSrc) + .getResult(0); // We know it must be the destination operand due to the types, but the // source may not match the destination width. @@ -1421,7 +1420,7 @@ LogicalResult FIRRTLModuleLowering::lowerModulePortsAndMoveBody( // move the new function body to. This is important because we insert some // ops at the start of the function and some at the end, and the body is // currently empty to avoid iterator invalidation. - auto cursor = bodyBuilder.create(APInt(1, 1)); + auto cursor = hw::ConstantOp::create(bodyBuilder, APInt(1, 1)); bodyBuilder.setInsertionPoint(cursor); // Insert argument casts, and re-vector users in the old body to use them. @@ -1463,10 +1462,10 @@ LogicalResult FIRRTLModuleLowering::lowerModulePortsAndMoveBody( // We lower zero width inout and outputs to a wire that isn't connected to // anything outside the module. Inputs are lowered to zero. if (isZeroWidth && port.isInput()) { - Value newArg = bodyBuilder - .create(port.type, "." + port.getName().str() + - ".0width_input") - .getResult(); + Value newArg = + WireOp::create(bodyBuilder, port.type, + "." + port.getName().str() + ".0width_input") + .getResult(); oldArg.replaceAllUsesWith(newArg); continue; } @@ -1482,8 +1481,8 @@ LogicalResult FIRRTLModuleLowering::lowerModulePortsAndMoveBody( // Outputs need a temporary wire so they can be connect'd to, which we // then return. - auto newArg = bodyBuilder.create( - port.type, "." + port.getName().str() + ".output"); + auto newArg = WireOp::create(bodyBuilder, port.type, + "." + port.getName().str() + ".output"); // Switch all uses of the old operands to the new ones. oldArg.replaceAllUsesWith(newArg.getResult()); @@ -1538,11 +1537,11 @@ FIRRTLModuleLowering::lowerFormalBody(verif::FormalOp newOp, SmallVector symbolicInputs; for (auto arg : newModule.getBody().getArguments()) symbolicInputs.push_back( - builder.create(arg.getLoc(), arg.getType())); + verif::SymbolicValueOp::create(builder, arg.getLoc(), arg.getType())); // Instantiate the module with the given symbolic inputs. - builder.create(newOp.getLoc(), newModule, - newModule.getNameAttr(), symbolicInputs); + hw::InstanceOp::create(builder, newOp.getLoc(), newModule, + newModule.getNameAttr(), symbolicInputs); return success(); } @@ -1565,9 +1564,9 @@ FIRRTLModuleLowering::lowerSimulationBody(verif::SimulationOp newOp, // and yield the module's outputs. SmallVector inputs(newOp.getBody()->args_begin(), newOp.getBody()->args_end()); - auto instOp = builder.create(newOp.getLoc(), newModule, - newModule.getNameAttr(), inputs); - builder.create(newOp.getLoc(), instOp.getResults()); + auto instOp = hw::InstanceOp::create(builder, newOp.getLoc(), newModule, + newModule.getNameAttr(), inputs); + verif::YieldOp::create(builder, newOp.getLoc(), instOp.getResults()); return success(); } @@ -2016,7 +2015,7 @@ LogicalResult FIRRTLModuleLowering::lowerFileBody(emit::FileOp fileOp) { fileOp->walk([&](Operation *op) { if (auto bindOp = dyn_cast(op)) { b.setInsertionPointAfter(bindOp); - b.create(bindOp.getLoc(), bindOp.getInstanceAttr()); + sv::BindOp::create(b, bindOp.getLoc(), bindOp.getInstanceAttr()); bindOp->erase(); } }); @@ -2133,8 +2132,8 @@ LogicalResult FIRRTLLowering::run() { continue; if (!zeroI0) { auto builder = OpBuilder::atBlockBegin(theModule.getBodyBlock()); - zeroI0 = builder.create(op->getLoc(), - builder.getIntegerType(0), 0); + zeroI0 = hw::ConstantOp::create(builder, op->getLoc(), + builder.getIntegerType(0), 0); maybeUnusedValues.insert(zeroI0); } result.replaceAllUsesWith(zeroI0); @@ -2188,7 +2187,7 @@ Value FIRRTLLowering::getOrCreateClockConstant(seq::ClockConst clock) { return entry; OpBuilder entryBuilder(&theModule.getBodyBlock()->front()); - entry = entryBuilder.create(builder.getLoc(), attr); + entry = seq::ConstClockOp::create(entryBuilder, builder.getLoc(), attr); return entry; } @@ -2203,7 +2202,7 @@ Value FIRRTLLowering::getOrCreateIntConstant(const APInt &value) { return entry; OpBuilder entryBuilder(&theModule.getBodyBlock()->front()); - entry = entryBuilder.create(builder.getLoc(), attr); + entry = hw::ConstantOp::create(entryBuilder, builder.getLoc(), attr); return entry; } @@ -2262,8 +2261,8 @@ Value FIRRTLLowering::getOrCreateXConstant(unsigned numBits) { return entry; OpBuilder entryBuilder(&theModule.getBodyBlock()->front()); - entry = entryBuilder.create( - builder.getLoc(), entryBuilder.getIntegerType(numBits)); + entry = sv::ConstantXOp::create(entryBuilder, builder.getLoc(), + entryBuilder.getIntegerType(numBits)); return entry; } @@ -2271,7 +2270,7 @@ Value FIRRTLLowering::getOrCreateZConstant(Type type) { auto &entry = hwConstantZMap[type]; if (!entry) { OpBuilder entryBuilder(&theModule.getBodyBlock()->front()); - entry = entryBuilder.create(builder.getLoc(), type); + entry = sv::ConstantZOp::create(entryBuilder, builder.getLoc(), type); } return entry; } @@ -2365,7 +2364,7 @@ Value FIRRTLLowering::getExtOrTruncAggregateValue(Value array, destVectorType.getNumElements()); i != e; ++i) { auto iIdx = getOrCreateIntConstant(indexWidth, i); - auto arrayIndex = builder.create(src, iIdx); + auto arrayIndex = hw::ArrayGetOp::create(builder, src, iIdx); if (failed(recurse(arrayIndex, srcVectorType.getElementType(), destVectorType.getElementType()))) return failure(); @@ -2387,7 +2386,7 @@ Value FIRRTLLowering::getExtOrTruncAggregateValue(Value array, for (auto elem : llvm::enumerate(destStructType)) { auto structExtract = - builder.create(src, elem.value().name); + hw::StructExtractOp::create(builder, src, elem.value().name); if (failed(recurse(structExtract, srcStructType.getElementType(elem.index()), destStructType.getElementType(elem.index())))) @@ -2581,7 +2580,7 @@ std::optional FIRRTLLowering::getLoweredFmtOperand(Value operand) { // Handle special substitutions. if (type_isa(operand.getType())) { if (isa(operand.getDefiningOp())) - return builder.create(); + return sv::TimeOp::create(builder); if (isa(operand.getDefiningOp())) return {nullptr}; } @@ -2598,8 +2597,8 @@ std::optional FIRRTLLowering::getLoweredFmtOperand(Value operand) { // it as signed decimal and have to wrap it in $signed(). if (auto intTy = firrtl::type_cast(operand.getType())) if (intTy.isSigned()) - loweredValue = builder.create( - loweredValue.getType(), "signed", loweredValue); + loweredValue = sv::SystemFunctionOp::create( + builder, loweredValue.getType(), "signed", loweredValue); return loweredValue; } @@ -2636,7 +2635,7 @@ LogicalResult FIRRTLLowering::lowerStatementWithFd( Value ifCond = cond; if (usePrintfCond) { ifCond = - builder.create(cond.getType(), "PRINTF_COND_"); + sv::MacroRefExprOp::create(builder, cond.getType(), "PRINTF_COND_"); ifCond = builder.createOrFold(ifCond, cond, true); } @@ -2646,7 +2645,7 @@ LogicalResult FIRRTLLowering::lowerStatementWithFd( Value fd; if (fileDescriptor.isDefaultFd()) { // Emit the sv.fwrite, writing to stderr by default. - fd = builder.create(APInt(32, 0x80000002)); + fd = hw::ConstantOp::create(builder, APInt(32, 0x80000002)); } else { // Call the library function to get the FD. auto fdOrError = callFileDescriptorLib(fileDescriptor); @@ -2674,21 +2673,19 @@ FIRRTLLowering::callFileDescriptorLib(const FileDescriptorInfo &info) { if (failed(loweredFmtOperands(info.getSubstitutions(), fileNameOperands))) return failure(); - fileName = builder - .create(info.getOutputFileFormat(), - fileNameOperands) + fileName = sv::SFormatFOp::create(builder, info.getOutputFileFormat(), + fileNameOperands) .getResult(); } else { // If substitution is not required, just use the output file name. - fileName = builder.create(info.getOutputFileFormat()) + fileName = sv::ConstantStrOp::create(builder, info.getOutputFileFormat()) .getResult(); } - return builder - .create( - mlir::TypeRange{builder.getIntegerType(32)}, - builder.getStringAttr("__circt_lib_logging::FileDescriptor::get"), - ValueRange{fileName}) + return sv::FuncCallProceduralOp::create( + builder, mlir::TypeRange{builder.getIntegerType(32)}, + builder.getStringAttr("__circt_lib_logging::FileDescriptor::get"), + ValueRange{fileName}) ->getResult(0); } @@ -2861,7 +2858,7 @@ Value FIRRTLLowering::getNonClockValue(Value v) { if (it.second) { ImplicitLocOpBuilder builder(v.getLoc(), v.getContext()); builder.setInsertionPointAfterValue(v); - it.first->second = builder.create(v); + it.first->second = seq::FromClockOp::create(builder, v); } return it.first->second; } @@ -2895,24 +2892,24 @@ void FIRRTLLowering::addToAlwaysBlock( auto createIfOp = [&]() { // It is weird but intended. Here we want to create an empty sv.if // with an else block. - insideIfOp = builder.create( - reset, []() {}, []() {}); + insideIfOp = sv::IfOp::create( + builder, reset, []() {}, []() {}); }; if (resetStyle == sv::ResetType::AsyncReset) { sv::EventControl events[] = {clockEdge, resetEdge}; Value clocks[] = {clock, reset}; - alwaysOp = builder.create(events, clocks, [&]() { + alwaysOp = sv::AlwaysOp::create(builder, events, clocks, [&]() { if (resetEdge == sv::EventControl::AtNegEdge) llvm_unreachable("negative edge for reset is not expected"); createIfOp(); }); } else { - alwaysOp = builder.create(clockEdge, clock, createIfOp); + alwaysOp = sv::AlwaysOp::create(builder, clockEdge, clock, createIfOp); } } else { assert(!resetBody); - alwaysOp = builder.create(clockEdge, clock); + alwaysOp = sv::AlwaysOp::create(builder, clockEdge, clock); insideIfOp = nullptr; } alwaysBlocks[key] = {alwaysOp, insideIfOp}; @@ -2969,7 +2966,7 @@ void FIRRTLLowering::addToIfDefBlock(StringRef cond, op->moveBefore(builder.getInsertionBlock(), builder.getInsertionPoint()); } else { ifdefBlocks[{builder.getBlock(), condAttr}] = - builder.create(condAttr, thenCtor, elseCtor); + sv::IfDefOp::create(builder, condAttr, thenCtor, elseCtor); } } @@ -2983,7 +2980,7 @@ void FIRRTLLowering::addToInitialBlock(std::function body) { // are defined ahead of the uses, which leads to better generated Verilog. op->moveBefore(builder.getInsertionBlock(), builder.getInsertionPoint()); } else { - initialBlocks[builder.getBlock()] = builder.create(body); + initialBlocks[builder.getBlock()] = sv::InitialOp::create(builder, body); } } @@ -3002,7 +2999,7 @@ void FIRRTLLowering::addIfProceduralBlock(Value cond, } } - builder.create(cond, thenCtor, elseCtor); + sv::IfOp::create(builder, cond, thenCtor, elseCtor); } //===----------------------------------------------------------------------===// @@ -3230,10 +3227,10 @@ LogicalResult FIRRTLLowering::visitExpr(FEnumCreateOp op) { if (auto structType = dyn_cast(newType)) { auto tagType = structType.getFieldType("tag"); auto tagValue = IntegerAttr::get(tagType, element.value.getValue()); - auto tag = builder.create(op.getLoc(), tagType, tagValue, - tagName); + auto tag = sv::LocalParamOp::create(builder, op.getLoc(), tagType, tagValue, + tagName); auto bodyType = structType.getFieldType("body"); - auto body = builder.create(bodyType, tagName, input); + auto body = hw::UnionCreateOp::create(builder, bodyType, tagName, input); SmallVector operands = {tag.getResult(), body.getResult()}; return setLoweringTo(op, structType, operands); } @@ -3255,15 +3252,15 @@ LogicalResult FIRRTLLowering::visitExpr(IsTagOp op) { auto tagName = op.getFieldNameAttr(); auto lhs = getLoweredValue(op.getInput()); if (isa(lhs.getType())) - lhs = builder.create(lhs, "tag"); + lhs = hw::StructExtractOp::create(builder, lhs, "tag"); auto index = op.getFieldIndex(); auto enumType = op.getInput().getType().base(); auto tagValue = enumType.getElementValueAttr(index); auto tagValueType = IntegerType::get(op.getContext(), enumType.getTagWidth()); auto loweredTagValue = IntegerAttr::get(tagValueType, tagValue.getValue()); - auto rhs = builder.create(op.getLoc(), tagValueType, - loweredTagValue, tagName); + auto rhs = sv::LocalParamOp::create(builder, op.getLoc(), tagValueType, + loweredTagValue, tagName); Type resultType = builder.getIntegerType(1); return setLoweringTo(op, resultType, ICmpPredicate::eq, lhs, @@ -3277,7 +3274,7 @@ LogicalResult FIRRTLLowering::visitExpr(SubtagOp op) { auto tagName = op.getFieldNameAttr(); auto input = getLoweredValue(op.getInput()); - auto field = builder.create(input, "body"); + auto field = hw::StructExtractOp::create(builder, input, "body"); return setLoweringTo(op, field, tagName); } @@ -3331,8 +3328,8 @@ LogicalResult FIRRTLLowering::visitDecl(WireOp op) { auto name = op.getNameAttr(); // This is not a temporary wire created by the compiler, so attach a symbol // name. - auto wire = builder.create( - op.getLoc(), getOrCreateZConstant(resultType), name, innerSym); + auto wire = hw::WireOp::create( + builder, op.getLoc(), getOrCreateZConstant(resultType), name, innerSym); if (auto svAttrs = sv::getSVAttributes(op)) sv::setSVAttributes(wire, svAttrs); @@ -3382,12 +3379,12 @@ LogicalResult FIRRTLLowering::visitDecl(NodeOp op) { auto innerSym = lowerInnerSymbol(op); if (innerSym) - operand = builder.create(operand, name, innerSym); + operand = hw::WireOp::create(builder, operand, name, innerSym); // Move SV attributes. if (auto svAttrs = sv::getSVAttributes(op)) { if (!innerSym) - operand = builder.create(operand, name); + operand = hw::WireOp::create(builder, operand, name); sv::setSVAttributes(operand.getDefiningOp(), svAttrs); } @@ -3408,8 +3405,8 @@ LogicalResult FIRRTLLowering::visitDecl(RegOp op) { // Create a reg op, wiring itself to its input. auto innerSym = lowerInnerSymbol(op); Backedge inputEdge = backedgeBuilder.get(resultType); - auto reg = builder.create(inputEdge, clockVal, - op.getNameAttr(), innerSym); + auto reg = seq::FirRegOp::create(builder, inputEdge, clockVal, + op.getNameAttr(), innerSym); // Pass along the start and end random initialization bits for this register. if (auto randomRegister = op->getAttr("firrtl.random_init_register")) @@ -3449,8 +3446,8 @@ LogicalResult FIRRTLLowering::visitDecl(RegResetOp op) { bool isAsync = type_isa(op.getResetSignal().getType()); Backedge inputEdge = backedgeBuilder.get(resultType); auto reg = - builder.create(inputEdge, clockVal, op.getNameAttr(), - resetSignal, resetValue, innerSym, isAsync); + seq::FirRegOp::create(builder, inputEdge, clockVal, op.getNameAttr(), + resetSignal, resetValue, innerSym, isAsync); // Pass along the start and end random initialization bits for this register. if (auto randomRegister = op->getAttr("firrtl.random_init_register")) @@ -3494,8 +3491,8 @@ LogicalResult FIRRTLLowering::visitDecl(MemOp op) { memInit = seq::FirMemInitAttr::get(init.getContext(), init.getFilename(), init.getIsBinary(), init.getIsInline()); - auto memDecl = builder.create( - memType, memSummary.readLatency, memSummary.writeLatency, + auto memDecl = seq::FirMemOp::create( + builder, memType, memSummary.readLatency, memSummary.writeLatency, memSummary.readUnderWrite, memSummary.writeUnderWrite, op.getNameAttr(), op.getInnerSymAttr(), memInit, op.getPrefixAttr(), Attribute{}); @@ -3556,7 +3553,7 @@ LogicalResult FIRRTLLowering::visitDecl(MemOp op) { auto addr = addInputPort("addr", op.getAddrBits()); auto en = addInputPort("en", 1); auto clk = addClock("clk"); - auto data = builder.create(memDecl, addr, clk, en); + auto data = seq::FirMemReadOp::create(builder, memDecl, addr, clk, en); addOutput("data", memSummary.dataWidth, data); } else if (memportKind == MemOp::PortKind::ReadWrite) { auto addr = addInputPort("addr", op.getAddrBits()); @@ -3573,8 +3570,8 @@ LogicalResult FIRRTLLowering::visitDecl(MemOp op) { Value mask; if (memSummary.isMasked) mask = addInputPort("wmask", memSummary.maskBits); - auto rdata = builder.create( - memDecl, addr, clk, en, wdata, mode, mask); + auto rdata = seq::FirMemReadWriteOp::create(builder, memDecl, addr, clk, + en, wdata, mode, mask); addOutput("rdata", memSummary.dataWidth, rdata); } else { auto addr = addInputPort("addr", op.getAddrBits()); @@ -3590,7 +3587,7 @@ LogicalResult FIRRTLLowering::visitDecl(MemOp op) { Value mask; if (memSummary.isMasked) mask = addInputPort("mask", memSummary.maskBits); - builder.create(memDecl, addr, clk, en, data, mask); + seq::FirMemWriteOp::create(builder, memDecl, addr, clk, en, data, mask); } } @@ -3668,8 +3665,8 @@ LogicalResult FIRRTLLowering::visitDecl(InstanceOp oldInstance) { // Create a wire for each inout operand, so there is something to connect // to. The instance becomes the sole driver of this wire. - auto wire = builder.create( - portType, "." + port.getName().str() + ".wire"); + auto wire = sv::WireOp::create(builder, portType, + "." + port.getName().str() + ".wire"); // Know that the argument FIRRTL value is equal to this wire, allowing // connects to it to be lowered. @@ -3689,8 +3686,8 @@ LogicalResult FIRRTLLowering::visitDecl(InstanceOp oldInstance) { oldInstance.getContext(), oldInstance.getInnerSymAttr(), 0, [&]() -> hw::InnerSymbolNamespace & { return moduleNamespace; }); - auto bindOp = builder.create(theModule.getNameAttr(), - innerSym.getSymName()); + auto bindOp = sv::BindOp::create(builder, theModule.getNameAttr(), + innerSym.getSymName()); // If the lowered op already had output file information, then use that. // Otherwise, generate some default bind information. if (auto outputFile = oldInstance->getAttr("output_file")) @@ -3701,8 +3698,9 @@ LogicalResult FIRRTLLowering::visitDecl(InstanceOp oldInstance) { } // Create the new hw.instance operation. - auto newInstance = builder.create( - newModule, oldInstance.getNameAttr(), operands, parameters, innerSym); + auto newInstance = + hw::InstanceOp::create(builder, newModule, oldInstance.getNameAttr(), + operands, parameters, innerSym); if (oldInstance.getLowerToBind() || oldInstance.getDoNotPrint()) newInstance.setDoNotPrintAttr(builder.getUnitAttr()); @@ -3741,7 +3739,7 @@ LogicalResult FIRRTLLowering::visitDecl(ContractOp oldOp) { types.push_back(lowered.getType()); } - auto newOp = builder.create(types, inputs); + auto newOp = verif::ContractOp::create(builder, types, inputs); newOp->setDiscardableAttrs(oldOp->getDiscardableAttrDictionary()); auto &body = newOp.getBody().emplaceBlock(); @@ -4127,7 +4125,7 @@ LogicalResult FIRRTLLowering::visitExpr(IsXIntrinsicOp op) { LogicalResult FIRRTLLowering::visitStmt(FPGAProbeIntrinsicOp op) { auto operand = getLoweredValue(op.getInput()); - builder.create(operand); + hw::WireOp::create(builder, operand); return success(); } @@ -4141,8 +4139,8 @@ LogicalResult FIRRTLLowering::visitExpr(PlusArgsValueIntrinsicOp op) { if (!type) return failure(); - auto valueOp = builder.create( - builder.getIntegerType(1), type, op.getFormatStringAttr()); + auto valueOp = sim::PlusArgsValueOp::create( + builder, builder.getIntegerType(1), type, op.getFormatStringAttr()); if (failed(setLowering(op.getResult(), valueOp.getResult()))) return failure(); if (failed(setLowering(op.getFound(), valueOp.getFound()))) @@ -4249,7 +4247,7 @@ template LogicalResult FIRRTLLowering::lowerVerifIntrinsicOp(IntrinsicOp op) { auto property = getLoweredValue(op.getProperty()); auto enable = op.getEnable() ? getLoweredValue(op.getEnable()) : Value(); - builder.create(property, enable, op.getLabelAttr()); + TargetOp::create(builder, property, enable, op.getLabelAttr()); return success(); } @@ -4337,7 +4335,7 @@ LogicalResult FIRRTLLowering::visitExpr(InvalidValueOp op) { auto constant = getOrCreateIntConstant(*bitwidth, 0); // If the result is an aggregate value, we have to bitcast the constant. if (!type_isa(resultTy)) - constant = builder.create(resultTy, constant); + constant = hw::BitcastOp::create(builder, resultTy, constant); return setLowering(op, constant); } @@ -4429,8 +4427,8 @@ LogicalResult FIRRTLLowering::visitExpr(Mux2CellIntrinsicOp op) { if (!cond || !ifTrue || !ifFalse) return failure(); - auto val = builder.create(ifTrue.getType(), cond, ifTrue, - ifFalse, true); + auto val = comb::MuxOp::create(builder, ifTrue.getType(), cond, ifTrue, + ifFalse, true); return setLowering(op, createValueWithMuxAnnotation(val, true)); } @@ -4443,8 +4441,8 @@ LogicalResult FIRRTLLowering::visitExpr(Mux4CellIntrinsicOp op) { if (!sel || !v3 || !v2 || !v1 || !v0) return failure(); Value array[] = {v3, v2, v1, v0}; - auto create = builder.create(array); - auto val = builder.create(create, sel); + auto create = hw::ArrayCreateOp::create(builder, array); + auto val = hw::ArrayGetOp::create(builder, create, sel); return setLowering(op, createValueWithMuxAnnotation(val, false)); } @@ -4467,7 +4465,7 @@ LogicalResult FIRRTLLowering::visitExpr(Mux4CellIntrinsicOp op) { Value FIRRTLLowering::createValueWithMuxAnnotation(Operation *op, bool isMux2) { assert(op->getNumResults() == 1 && "only expect a single result"); auto val = op->getResult(0); - auto valWire = builder.create(val.getType()); + auto valWire = sv::WireOp::create(builder, val.getType()); // Use SV attributes to annotate pragmas. circt::sv::setSVAttributes( op, sv::SVAttributeAttr::get(builder.getContext(), "cadence map_to_mux", @@ -4485,17 +4483,17 @@ Value FIRRTLLowering::createValueWithMuxAnnotation(Operation *op, bool isMux2) { op->getContext(), /*attr=*/nullptr, 0, [&]() -> hw::InnerSymbolNamespace & { return moduleNamespace; }); auto wire = - builder.create(operand, namehint + Twine(idx), innerSym); + hw::WireOp::create(builder, operand, namehint + Twine(idx), innerSym); op->setOperand(idx, wire); } } - auto assignOp = builder.create(valWire, val); + auto assignOp = sv::AssignOp::create(builder, valWire, val); sv::setSVAttributes(assignOp, sv::SVAttributeAttr::get(builder.getContext(), "synopsys infer_mux_override", /*emitAsComment=*/true)); - return builder.create(valWire); + return sv::ReadInOutOp::create(builder, valWire); } Value FIRRTLLowering::createArrayIndexing(Value array, Value index) { @@ -4507,14 +4505,14 @@ Value FIRRTLLowering::createArrayIndexing(Value array, Value index) { // optimization. if (!llvm::isPowerOf2_64(size)) { auto extElem = getOrCreateIntConstant(APInt(llvm::Log2_64_Ceil(size), 0)); - auto extValue = builder.create(array, extElem); + auto extValue = hw::ArrayGetOp::create(builder, array, extElem); SmallVector temp(llvm::NextPowerOf2(size) - size, extValue); - auto ext = builder.create(temp); + auto ext = hw::ArrayCreateOp::create(builder, temp); Value temp2[] = {ext.getResult(), array}; - array = builder.create(temp2); + array = hw::ArrayConcatOp::create(builder, temp2); } - Value inBoundsRead = builder.create(array, index); + Value inBoundsRead = hw::ArrayGetOp::create(builder, array, index); return inBoundsRead; } @@ -4537,7 +4535,7 @@ LogicalResult FIRRTLLowering::visitExpr(MultibitMuxOp op) { loweredInputs.push_back(lowered); } - Value array = builder.create(loweredInputs); + Value array = hw::ArrayCreateOp::create(builder, loweredInputs); return setLowering(op, createArrayIndexing(array, index)); } @@ -4588,8 +4586,8 @@ LogicalResult FIRRTLLowering::visitExpr(XMRDerefOp op) { else xmrType = lowerType(op.getType()); - auto xmr = builder.create( - sv::InOutType::get(xmrType), op.getRef(), op.getVerbatimSuffixAttr()); + auto xmr = sv::XMRRefOp::create(builder, sv::InOutType::get(xmrType), + op.getRef(), op.getVerbatimSuffixAttr()); auto readXmr = getReadValue(xmr); if (!isa(op.getType())) return setLowering(op, readXmr); @@ -4624,7 +4622,7 @@ FailureOr FIRRTLLowering::lowerConnect(Value destVal, Value srcVal) { auto dstType = destVal.getType(); if (srcType != dstType && (isa(srcType) || isa(dstType))) { - srcVal = builder.create(destVal.getType(), srcVal); + srcVal = hw::BitcastOp::create(builder, destVal.getType(), srcVal); } return TypeSwitch>(destVal.getDefiningOp()) .Case([&](auto op) { @@ -4672,7 +4670,7 @@ LogicalResult FIRRTLLowering::visitStmt(ConnectOp op) { if (!isa(destVal.getType())) return op.emitError("destination isn't an inout type"); - builder.create(destVal, srcVal); + sv::AssignOp::create(builder, destVal, srcVal); return success(); } @@ -4700,7 +4698,7 @@ LogicalResult FIRRTLLowering::visitStmt(MatchingConnectOp op) { if (!isa(destVal.getType())) return op.emitError("destination isn't an inout type"); - builder.create(destVal, srcVal); + sv::AssignOp::create(builder, destVal, srcVal); return success(); } @@ -4719,7 +4717,7 @@ LogicalResult FIRRTLLowering::visitStmt(ForceOp op) { // #ifndef SYNTHESIS circuitState.addMacroDecl(builder.getStringAttr("SYNTHESIS")); addToIfDefBlock("SYNTHESIS", std::function(), [&]() { - addToInitialBlock([&]() { builder.create(destVal, srcVal); }); + addToInitialBlock([&]() { sv::ForceOp::create(builder, destVal, srcVal); }); }); return success(); } @@ -4740,7 +4738,7 @@ LogicalResult FIRRTLLowering::visitStmt(RefForceOp op) { addToIfDefBlock("SYNTHESIS", std::function(), [&]() { addToAlwaysBlock(clock, [&]() { addIfProceduralBlock( - pred, [&]() { builder.create(destVal, src); }); + pred, [&]() { sv::ForceOp::create(builder, destVal, src); }); }); }); return success(); @@ -4760,7 +4758,7 @@ LogicalResult FIRRTLLowering::visitStmt(RefForceInitialOp op) { addToIfDefBlock("SYNTHESIS", std::function(), [&]() { addToInitialBlock([&]() { addIfProceduralBlock( - pred, [&]() { builder.create(destVal, src); }); + pred, [&]() { sv::ForceOp::create(builder, destVal, src); }); }); }); return success(); @@ -4780,7 +4778,7 @@ LogicalResult FIRRTLLowering::visitStmt(RefReleaseOp op) { addToIfDefBlock("SYNTHESIS", std::function(), [&]() { addToAlwaysBlock(clock, [&]() { addIfProceduralBlock(pred, - [&]() { builder.create(destVal); }); + [&]() { sv::ReleaseOp::create(builder, destVal); }); }); }); return success(); @@ -4796,7 +4794,7 @@ LogicalResult FIRRTLLowering::visitStmt(RefReleaseInitialOp op) { addToIfDefBlock("SYNTHESIS", std::function(), [&]() { addToInitialBlock([&]() { addIfProceduralBlock(pred, - [&]() { builder.create(destVal); }); + [&]() { sv::ReleaseOp::create(builder, destVal); }); }); }); return success(); @@ -4905,7 +4903,7 @@ LogicalResult FIRRTLLowering::visitPrintfLike( SmallVector operands; if (failed(loweredFmtOperands(op.getSubstitutions(), operands))) return failure(); - builder.create(op.getLoc(), fd, formatString, operands); + sv::FWriteOp::create(builder, op.getLoc(), fd, formatString, operands); return success(); }; @@ -4933,7 +4931,7 @@ LogicalResult FIRRTLLowering::visitStmt(FFlushOp op) { return failure(); auto fn = [&](Value fd) { - builder.create(op.getLoc(), fd); + sv::FFlushOp::create(builder, op.getLoc(), fd); return success(); }; @@ -4965,13 +4963,13 @@ LogicalResult FIRRTLLowering::visitStmt(StopOp op) { circuitState.addFragment(theModule, "STOP_COND_FRAGMENT"); Value stopCond = - builder.create(cond.getType(), "STOP_COND_"); + sv::MacroRefExprOp::create(builder, cond.getType(), "STOP_COND_"); Value exitCond = builder.createOrFold(stopCond, cond, true); if (op.getExitCode()) - builder.create(clock, exitCond); + sim::FatalOp::create(builder, clock, exitCond); else - builder.create(clock, exitCond); + sim::FinishOp::create(builder, clock, exitCond); return success(); } @@ -4983,11 +4981,11 @@ template static Operation *buildImmediateVerifOp(ImplicitLocOpBuilder &builder, StringRef opName, Args &&...args) { if (opName == "assert") - return builder.create(std::forward(args)...); + return sv::AssertOp::create(builder, std::forward(args)...); if (opName == "assume") - return builder.create(std::forward(args)...); + return sv::AssumeOp::create(builder, std::forward(args)...); if (opName == "cover") - return builder.create(std::forward(args)...); + return sv::CoverOp::create(builder, std::forward(args)...); llvm_unreachable("unknown verification op"); } @@ -4998,11 +4996,11 @@ template static Operation *buildConcurrentVerifOp(ImplicitLocOpBuilder &builder, StringRef opName, Args &&...args) { if (opName == "assert") - return builder.create(std::forward(args)...); + return sv::AssertConcurrentOp::create(builder, std::forward(args)...); if (opName == "assume") - return builder.create(std::forward(args)...); + return sv::AssumeConcurrentOp::create(builder, std::forward(args)...); if (opName == "cover") - return builder.create(std::forward(args)...); + return sv::CoverConcurrentOp::create(builder, std::forward(args)...); llvm_unreachable("unknown verification op"); } @@ -5086,7 +5084,7 @@ LogicalResult FIRRTLLowering::lowerVerificationStatement( // assertion triggers. (See SystemVerilog 2017 spec section 16.9.3 for // more information.) for (auto &loweredValue : messageOps) - loweredValue = builder.create(loweredValue); + loweredValue = sv::SampledOp::create(builder, loweredValue); } } @@ -5123,12 +5121,12 @@ LogicalResult FIRRTLLowering::lowerVerificationStatement( circuitState.addFragment(theModule, "ASSERT_VERBOSE_COND_FRAGMENT"); addIfProceduralBlock( - builder.create(boolType, - "ASSERT_VERBOSE_COND_"), - [&]() { builder.create(message, messageOps); }); + sv::MacroRefExprOp::create(builder, boolType, + "ASSERT_VERBOSE_COND_"), + [&]() { sv::ErrorOp::create(builder, message, messageOps); }); addIfProceduralBlock( - builder.create(boolType, "STOP_COND_"), - [&]() { builder.create(); }); + sv::MacroRefExprOp::create(builder, boolType, "STOP_COND_"), + [&]() { sv::FatalOp::create(builder); }); }); }); }); @@ -5234,8 +5232,9 @@ LogicalResult FIRRTLLowering::visitStmt(UnclockedAssumeIntrinsicOp op) { messageOps.push_back(loweredValue); } return emitGuards(op.getLoc(), guards, [&]() { - builder.create( - ArrayRef(sv::EventControl::AtEdge), ArrayRef(predicate), [&]() { + sv::AlwaysOp::create( + builder, ArrayRef(sv::EventControl::AtEdge), ArrayRef(predicate), + [&]() { if (op.getMessageAttr().getValue().empty()) buildImmediateVerifOp( builder, "assume", predicate, @@ -5311,28 +5310,29 @@ LogicalResult FIRRTLLowering::visitStmt(AttachOp op) { for (size_t i1 = 0, e = inoutValues.size(); i1 != e; ++i1) { for (size_t i2 = 0; i2 != e; ++i2) if (i1 != i2) - builder.create(inoutValues[i1], values[i2]); + sv::AssignOp::create(builder, inoutValues[i1], values[i2]); } }, // In the non-synthesis case, we emit a SystemVerilog alias // statement. [&]() { - builder.create( - "VERILATOR", + sv::IfDefOp::create( + builder, "VERILATOR", [&]() { - builder.create( + sv::VerbatimOp::create( + builder, "`error \"Verilator does not support alias and thus " "cannot " "arbitrarily connect bidirectional wires and ports\""); }, - [&]() { builder.create(inoutValues); }); + [&]() { sv::AliasOp::create(builder, inoutValues); }); }); return success(); } LogicalResult FIRRTLLowering::visitStmt(BindOp op) { - builder.create(op.getInstanceAttr()); + sv::BindOp::create(builder, op.getInstanceAttr()); return success(); } diff --git a/lib/Conversion/FSMToSV/FSMToSV.cpp b/lib/Conversion/FSMToSV/FSMToSV.cpp index a01b975725..990d213df3 100644 --- a/lib/Conversion/FSMToSV/FSMToSV.cpp +++ b/lib/Conversion/FSMToSV/FSMToSV.cpp @@ -152,8 +152,8 @@ StateEncoding::StateEncoding(OpBuilder &b, hw::TypeScopeOp typeScope, OpBuilder::InsertionGuard guard(b); b.setInsertionPointToStart(&typeScope.getBodyRegion().front()); - auto typedeclEnumType = b.create( - loc, b.getStringAttr(hwModule.getName() + "_state_t"), + auto typedeclEnumType = hw::TypedeclOp::create( + b, loc, b.getStringAttr(hwModule.getName() + "_state_t"), TypeAttr::get(rawEnumType), nullptr); stateType = hw::TypeAliasType::get( @@ -166,8 +166,8 @@ StateEncoding::StateEncoding(OpBuilder &b, hw::TypeScopeOp typeScope, for (auto state : machine.getBody().getOps()) { auto fieldAttr = hw::EnumFieldAttr::get( loc, b.getStringAttr(state.getName()), stateType); - auto enumConstantOp = b.create( - loc, fieldAttr.getType().getValue(), fieldAttr); + auto enumConstantOp = hw::EnumConstantOp::create( + b, loc, fieldAttr.getType().getValue(), fieldAttr); setEncoding(state, enumConstantOp, /*wire=*/true); } @@ -203,11 +203,11 @@ void StateEncoding::setEncoding(StateOp state, Value v, bool wire) { if (wire) { auto loc = machine.getLoc(); auto stateType = getStateType(); - auto stateEncodingWire = b.create( - loc, stateType, b.getStringAttr("to_" + state.getName()), + auto stateEncodingWire = sv::RegOp::create( + b, loc, stateType, b.getStringAttr("to_" + state.getName()), hw::InnerSymAttr::get(state.getNameAttr())); - b.create(loc, stateEncodingWire, v); - encodedValue = b.create(loc, stateEncodingWire); + sv::AssignOp::create(b, loc, stateEncodingWire, v); + encodedValue = sv::ReadInOutOp::create(b, loc, stateEncodingWire); } else encodedValue = v; stateToValue[state] = encodedValue; @@ -368,13 +368,13 @@ void MachineOpConverter::buildStateCaseMux( // Default assignments. for (auto &assignment : assignments) { if (assignment.defaultValue) - b.create(assignment.wire.getLoc(), assignment.wire, - *assignment.defaultValue); + sv::BPAssignOp::create(b, assignment.wire.getLoc(), assignment.wire, + *assignment.defaultValue); } // Case assignments. - caseMux = b.create( - machineOp.getLoc(), CaseStmtType::CaseStmt, + caseMux = sv::CaseOp::create( + b, machineOp.getLoc(), CaseStmtType::CaseStmt, /*sv::ValidationQualifierTypeEnum::ValidationQualifierUnique, */ select, /*numCases=*/machineOp.getNumStates() + 1, [&](size_t caseIdx) { // Make Verilator happy for sized enums. @@ -395,7 +395,7 @@ void MachineOpConverter::buildStateCaseMux( continue; b.setInsertionPointToEnd(caseInfo.block); if (auto v = std::get_if(&assignmentInState->second); v) { - b.create(machineOp.getLoc(), assignment.wire, *v); + sv::BPAssignOp::create(b, machineOp.getLoc(), assignment.wire, *v); } else { // Nested case statement. llvm::SmallVector nestedAssignments; @@ -420,7 +420,8 @@ LogicalResult MachineOpConverter::dispatch() { // 1) Get the port info of the machine and create a new HW module for it. SmallVector ports; auto clkRstIdxs = getMachinePortInfo(ports, machineOp, b); - hwModuleOp = b.create(loc, machineOp.getSymNameAttr(), ports); + hwModuleOp = + hw::HWModuleOp::create(b, loc, machineOp.getSymNameAttr(), ports); hwModuleOp->setAttr(emit::getFragmentsAttrName(), b.getArrayAttr({headerName})); b.setInsertionPointToStart(hwModuleOp.getBodyBlock()); @@ -443,10 +444,10 @@ LogicalResult MachineOpConverter::dispatch() { auto stateType = encoding->getStateType(); auto nextStateWire = - b.create(loc, stateType, b.getStringAttr("state_next")); - auto nextStateWireRead = b.create(loc, nextStateWire); - stateReg = b.create( - loc, nextStateWireRead, clock, reset, + sv::RegOp::create(b, loc, stateType, b.getStringAttr("state_next")); + auto nextStateWireRead = sv::ReadInOutOp::create(b, loc, nextStateWire); + stateReg = seq::CompRegOp::create( + b, loc, nextStateWireRead, clock, reset, /*reset value=*/encoding->encode(machineOp.getInitialStateOp()), "state_reg"); @@ -458,12 +459,12 @@ LogicalResult MachineOpConverter::dispatch() { "for the initial value."; Type varType = variableOp.getType(); auto varLoc = variableOp.getLoc(); - auto varNextState = b.create( - varLoc, varType, b.getStringAttr(variableOp.getName() + "_next")); - auto varResetVal = b.create(varLoc, initValueAttr); - auto variableReg = b.create( - varLoc, b.create(varLoc, varNextState), clock, reset, - varResetVal, b.getStringAttr(variableOp.getName() + "_reg")); + auto varNextState = sv::RegOp::create( + b, varLoc, varType, b.getStringAttr(variableOp.getName() + "_next")); + auto varResetVal = hw::ConstantOp::create(b, varLoc, initValueAttr); + auto variableReg = seq::CompRegOp::create( + b, varLoc, sv::ReadInOutOp::create(b, varLoc, varNextState), clock, + reset, varResetVal, b.getStringAttr(variableOp.getName() + "_reg")); variableToRegister[variableOp] = variableReg; variableNextStateWires[variableOp] = varNextState; // Postpone value replacement until all logic has been created. @@ -500,8 +501,8 @@ LogicalResult MachineOpConverter::dispatch() { continue; auto outputPortType = port.type; CaseMuxItem outputAssignment; - outputAssignment.wire = b.create( - machineOp.getLoc(), outputPortType, + outputAssignment.wire = sv::RegOp::create( + b, machineOp.getLoc(), outputPortType, b.getStringAttr("output_" + std::to_string(portIndex))); outputAssignment.select = stateReg; for (auto &state : orderedStates) @@ -563,7 +564,7 @@ LogicalResult MachineOpConverter::dispatch() { outputCaseAssignments.end()); { - auto alwaysCombOp = b.create(loc); + auto alwaysCombOp = sv::AlwaysCombOp::create(b, loc); OpBuilder::InsertionGuard g(b); b.setInsertionPointToStart(alwaysCombOp.getBodyBlock()); buildStateCaseMux(nextStateCaseAssignments); @@ -577,12 +578,12 @@ LogicalResult MachineOpConverter::dispatch() { llvm::SmallVector outputPortAssignments; for (auto outputAssignment : outputCaseAssignments) outputPortAssignments.push_back( - b.create(machineOp.getLoc(), outputAssignment.wire)); + sv::ReadInOutOp::create(b, machineOp.getLoc(), outputAssignment.wire)); // Delete the default created output op and replace it with the output // muxes. auto *oldOutputOp = hwModuleOp.getBodyBlock()->getTerminator(); - b.create(loc, outputPortAssignments); + hw::OutputOp::create(b, loc, outputPortAssignments); oldOutputOp->erase(); // Erase the original machine op. @@ -640,8 +641,8 @@ MachineOpConverter::convertTransitions( // NOLINT(misc-no-recursion) convertTransitions(currentState, transitions.drop_front()); if (failed(otherNextState)) return failure(); - comb::MuxOp nextStateMux = b.create( - transition.getLoc(), guard, nextState, *otherNextState, false); + comb::MuxOp nextStateMux = comb::MuxOp::create( + b, transition.getLoc(), guard, nextState, *otherNextState, false); nextState = nextStateMux; } } @@ -707,15 +708,15 @@ void FSMToSVPass::runOnOperation() { // typedefs. b.setInsertionPointToStart(module.getBody()); hw::TypeScopeOp typeScope = - b.create(loc, b.getStringAttr("fsm_enum_typedecls")); + hw::TypeScopeOp::create(b, loc, b.getStringAttr("fsm_enum_typedecls")); typeScope.getBodyRegion().push_back(new Block()); - auto file = b.create(loc, "fsm_enum_typedefs.sv", [&] { - b.create(loc, - FlatSymbolRefAttr::get(typeScope.getSymNameAttr())); + auto file = emit::FileOp::create(b, loc, "fsm_enum_typedefs.sv", [&] { + emit::RefOp::create(b, loc, + FlatSymbolRefAttr::get(typeScope.getSymNameAttr())); }); - auto fragment = b.create(loc, "FSM_ENUM_TYPEDEFS", [&] { - b.create(loc, "`include \"" + file.getFileName() + "\""); + auto fragment = emit::FragmentOp::create(b, loc, "FSM_ENUM_TYPEDEFS", [&] { + sv::VerbatimOp::create(b, loc, "`include \"" + file.getFileName() + "\""); }); auto headerName = FlatSymbolRefAttr::get(fragment.getSymNameAttr()); @@ -743,8 +744,8 @@ void FSMToSVPass::runOnOperation() { llvm::SmallVector operands; llvm::transform(instance.getOperands(), std::back_inserter(operands), [&](auto operand) { return operand; }); - auto hwInstance = b.create( - instance.getLoc(), fsmHWModule, b.getStringAttr(instance.getName()), + auto hwInstance = hw::InstanceOp::create( + b, instance.getLoc(), fsmHWModule, b.getStringAttr(instance.getName()), operands, nullptr); instance.replaceAllUsesWith(hwInstance); instance.erase(); diff --git a/lib/Conversion/HWArithToHW/HWArithToHW.cpp b/lib/Conversion/HWArithToHW/HWArithToHW.cpp index bdaeee705e..044e64090c 100644 --- a/lib/Conversion/HWArithToHW/HWArithToHW.cpp +++ b/lib/Conversion/HWArithToHW/HWArithToHW.cpp @@ -90,13 +90,13 @@ static Value extendTypeWidth(OpBuilder &builder, Location loc, Value value, builder.createOrFold(loc, highBit, extensionLength); } else { // Zero extension - extensionBits = builder - .create( - loc, builder.getIntegerType(extensionLength), 0) - ->getOpResult(0); + extensionBits = + hw::ConstantOp::create(builder, loc, + builder.getIntegerType(extensionLength), 0) + ->getOpResult(0); } - auto extOp = builder.create(loc, extensionBits, value); + auto extOp = comb::ConcatOp::create(builder, loc, extensionBits, value); improveNamehint(value, extOp, [&](StringRef oldNamehint) { return (oldNamehint + "_" + (signExtension ? "sext_" : "zext_") + std::to_string(targetWidth)) @@ -210,10 +210,10 @@ struct DivOpLowering : public OpConversionPattern { Value divResult; if (signedDivision) - divResult = rewriter.create(loc, lhsValue, rhsValue, false) + divResult = comb::DivSOp::create(rewriter, loc, lhsValue, rhsValue, false) ->getOpResult(0); else - divResult = rewriter.create(loc, lhsValue, rhsValue, false) + divResult = comb::DivUOp::create(rewriter, loc, lhsValue, rhsValue, false) ->getOpResult(0); // Carry over any attributes from the original div op. @@ -313,8 +313,8 @@ struct ICmpOpLowering : public OpConversionPattern { Value rhsValue = extendTypeWidth(rewriter, loc, adaptor.getRhs(), cmpWidth, rhsType.isSigned()); - auto newOp = rewriter.create(op->getLoc(), combPred, lhsValue, - rhsValue, false); + auto newOp = comb::ICmpOp::create(rewriter, op->getLoc(), combPred, + lhsValue, rhsValue, false); rewriter.modifyOpInPlace( newOp, [&]() { newOp->setDialectAttrs(op->getDialectAttrs()); }); rewriter.replaceOp(op, newOp); @@ -343,7 +343,7 @@ struct BinaryOpLowering : public OpConversionPattern { Value rhsValue = extendTypeWidth(rewriter, loc, adaptor.getInputs()[1], targetWidth, isRhsTypeSigned); auto newOp = - rewriter.create(op.getLoc(), lhsValue, rhsValue, false); + ReplaceOp::create(rewriter, op.getLoc(), lhsValue, rhsValue, false); rewriter.modifyOpInPlace( newOp, [&]() { newOp->setDialectAttrs(op->getDialectAttrs()); }); rewriter.replaceOp(op, newOp); @@ -404,8 +404,8 @@ HWArithToHWTypeConverter::HWArithToHWTypeConverter() { mlir::Location loc) -> mlir::Value { if (inputs.size() != 1) return Value(); - return builder - .create(loc, resultType, inputs[0]) + return UnrealizedConversionCastOp::create(builder, loc, resultType, + inputs[0]) ->getResult(0); }); @@ -414,8 +414,8 @@ HWArithToHWTypeConverter::HWArithToHWTypeConverter() { mlir::Location loc) -> mlir::Value { if (inputs.size() != 1) return Value(); - return builder - .create(loc, resultType, inputs[0]) + return UnrealizedConversionCastOp::create(builder, loc, resultType, + inputs[0]) ->getResult(0); }); } diff --git a/lib/Conversion/HWToLLVM/HWToLLVM.cpp b/lib/Conversion/HWToLLVM/HWToLLVM.cpp index 370ae24cb6..a301840698 100644 --- a/lib/Conversion/HWToLLVM/HWToLLVM.cpp +++ b/lib/Conversion/HWToLLVM/HWToLLVM.cpp @@ -76,7 +76,7 @@ static Value zextByOne(Location loc, ConversionPatternRewriter &rewriter, auto valueTy = value.getType(); auto zextTy = IntegerType::get(valueTy.getContext(), valueTy.getIntOrFloatBitWidth() + 1); - return rewriter.create(loc, zextTy, value); + return LLVM::ZExtOp::create(rewriter, loc, zextTy, value); } //===----------------------------------------------------------------------===// @@ -103,8 +103,8 @@ struct StructExplodeOpConversion .size(); i < e; ++i) - replacements.push_back(rewriter.create( - op->getLoc(), adaptor.getInput(), + replacements.push_back(LLVM::ExtractValueOp::create( + rewriter, op->getLoc(), adaptor.getInput(), HWToLLVMEndianessConverter::convertToLLVMEndianess( op.getInput().getType(), i))); @@ -152,14 +152,15 @@ struct ArrayGetOpConversion : public ConvertOpToLLVMPattern { // just grab that address instead of reallocating the array on the stack. arrPtr = load.getAddr(); } else { - auto oneC = rewriter.create( - op->getLoc(), IntegerType::get(rewriter.getContext(), 32), + auto oneC = LLVM::ConstantOp::create( + rewriter, op->getLoc(), IntegerType::get(rewriter.getContext(), 32), rewriter.getI32IntegerAttr(1)); - arrPtr = rewriter.create( - op->getLoc(), LLVM::LLVMPointerType::get(rewriter.getContext()), + arrPtr = LLVM::AllocaOp::create( + rewriter, op->getLoc(), + LLVM::LLVMPointerType::get(rewriter.getContext()), adaptor.getInput().getType(), oneC, /*alignment=*/4); - rewriter.create(op->getLoc(), adaptor.getInput(), arrPtr); + LLVM::StoreOp::create(rewriter, op->getLoc(), adaptor.getInput(), arrPtr); } auto arrTy = typeConverter->convertType(op.getInput().getType()); @@ -169,9 +170,10 @@ struct ArrayGetOpConversion : public ConvertOpToLLVMPattern { // During the ongoing migration to opaque types, use the constructor that // accepts an element type when the array pointer type is opaque, and // otherwise use the typed pointer constructor. - auto gep = rewriter.create( - op->getLoc(), LLVM::LLVMPointerType::get(rewriter.getContext()), arrTy, - arrPtr, ArrayRef{0, zextIndex}); + auto gep = LLVM::GEPOp::create( + rewriter, op->getLoc(), + LLVM::LLVMPointerType::get(rewriter.getContext()), arrTy, arrPtr, + ArrayRef{0, zextIndex}); rewriter.replaceOpWithNewOp(op, elemTy, gep); return success(); @@ -193,24 +195,27 @@ struct ArraySliceOpConversion auto dstTy = typeConverter->convertType(op.getDst().getType()); - auto oneC = rewriter.create( - op->getLoc(), rewriter.getI32Type(), rewriter.getI32IntegerAttr(1)); + auto oneC = + LLVM::ConstantOp::create(rewriter, op->getLoc(), rewriter.getI32Type(), + rewriter.getI32IntegerAttr(1)); - auto arrPtr = rewriter.create( - op->getLoc(), LLVM::LLVMPointerType::get(rewriter.getContext()), + auto arrPtr = LLVM::AllocaOp::create( + rewriter, op->getLoc(), + LLVM::LLVMPointerType::get(rewriter.getContext()), adaptor.getInput().getType(), oneC, /*alignment=*/4); - rewriter.create(op->getLoc(), adaptor.getInput(), arrPtr); + LLVM::StoreOp::create(rewriter, op->getLoc(), adaptor.getInput(), arrPtr); auto zextIndex = zextByOne(op->getLoc(), rewriter, op.getLowIndex()); // During the ongoing migration to opaque types, use the constructor that // accepts an element type when the array pointer type is opaque, and // otherwise use the typed pointer constructor. - auto gep = rewriter.create( - op->getLoc(), LLVM::LLVMPointerType::get(rewriter.getContext()), dstTy, - arrPtr, ArrayRef{0, zextIndex}); + auto gep = LLVM::GEPOp::create( + rewriter, op->getLoc(), + LLVM::LLVMPointerType::get(rewriter.getContext()), dstTy, arrPtr, + ArrayRef{0, zextIndex}); rewriter.replaceOpWithNewOp(op, dstTy, gep); @@ -263,15 +268,16 @@ struct ArrayConcatOpConversion hw::ArrayType arrTy = cast(op.getResult().getType()); Type resultTy = typeConverter->convertType(arrTy); - Value arr = rewriter.create(op->getLoc(), resultTy); + Value arr = LLVM::UndefOp::create(rewriter, op->getLoc(), resultTy); // Attention: j is hardcoded for little endian machines. size_t j = op.getInputs().size() - 1, k = 0; for (size_t i = 0, e = arrTy.getNumElements(); i < e; ++i) { - Value element = rewriter.create( - op->getLoc(), adaptor.getInputs()[j], k); - arr = rewriter.create(op->getLoc(), arr, element, i); + Value element = LLVM::ExtractValueOp::create(rewriter, op->getLoc(), + adaptor.getInputs()[j], k); + arr = + LLVM::InsertValueOp::create(rewriter, op->getLoc(), arr, element, i); ++k; if (k >= @@ -308,12 +314,13 @@ struct BitcastOpConversion : public ConvertOpToLLVMPattern { auto oneC = rewriter.createOrFold( op->getLoc(), rewriter.getI32Type(), rewriter.getI32IntegerAttr(1)); - auto ptr = rewriter.create( - op->getLoc(), LLVM::LLVMPointerType::get(rewriter.getContext()), + auto ptr = LLVM::AllocaOp::create( + rewriter, op->getLoc(), + LLVM::LLVMPointerType::get(rewriter.getContext()), adaptor.getInput().getType(), oneC, /*alignment=*/4); - rewriter.create(op->getLoc(), adaptor.getInput(), ptr); + LLVM::StoreOp::create(rewriter, op->getLoc(), adaptor.getInput(), ptr); rewriter.replaceOpWithNewOp(op, resultTy, ptr); @@ -362,13 +369,13 @@ struct HWDynamicArrayCreateOpConversion auto arrayTy = typeConverter->convertType(op->getResult(0).getType()); assert(arrayTy); - Value arr = rewriter.create(op->getLoc(), arrayTy); + Value arr = LLVM::UndefOp::create(rewriter, op->getLoc(), arrayTy); for (size_t i = 0, e = op.getInputs().size(); i < e; ++i) { Value input = adaptor .getInputs()[HWToLLVMEndianessConverter::convertToLLVMEndianess( op.getResult().getType(), i)]; - arr = rewriter.create(op->getLoc(), arr, input, i); + arr = LLVM::InsertValueOp::create(rewriter, op->getLoc(), arr, input, i); } rewriter.replaceOp(op, arr); @@ -430,13 +437,13 @@ struct HWStructCreateOpConversion auto resTy = typeConverter->convertType(op.getResult().getType()); - Value tup = rewriter.create(op->getLoc(), resTy); + Value tup = LLVM::UndefOp::create(rewriter, op->getLoc(), resTy); for (size_t i = 0, e = cast(resTy).getBody().size(); i < e; ++i) { Value input = adaptor.getInput()[HWToLLVMEndianessConverter::convertToLLVMEndianess( op.getResult().getType(), i)]; - tup = rewriter.create(op->getLoc(), tup, input, i); + tup = LLVM::InsertValueOp::create(rewriter, op->getLoc(), tup, input, i); } rewriter.replaceOp(op, tup); @@ -517,10 +524,10 @@ Value AggregateConstantOpConversion::constructAggregate( return TypeSwitch(type) .Case([&](auto ty) { - return builder.create(loc, cast(data)); + return LLVM::ConstantOp::create(builder, loc, cast(data)); }) .Case([&](auto ty) { - Value aggVal = builder.create(loc, llvmType); + Value aggVal = LLVM::UndefOp::create(builder, loc, llvmType); auto arrayAttr = cast(data); for (size_t i = 0, e = arrayAttr.size(); i < e; ++i) { size_t currIdx = @@ -530,7 +537,8 @@ Value AggregateConstantOpConversion::constructAggregate( Value element = constructAggregate(builder, typeConverter, loc, elementType, input); - aggVal = builder.create(loc, aggVal, element, i); + aggVal = + LLVM::InsertValueOp::create(builder, loc, aggVal, element, i); } return aggVal; @@ -572,12 +580,13 @@ LogicalResult AggregateConstantOpConversion::matchAndRewrite( dims, cast(ints.front()).getType()); auto denseAttr = DenseElementsAttr::get(shapedType, ints); - constAggregateGlobalsMap[typeAttrPair] = rewriter.create( - op.getLoc(), llvmTy, true, LLVM::Linkage::Internal, name, denseAttr); + constAggregateGlobalsMap[typeAttrPair] = + LLVM::GlobalOp::create(rewriter, op.getLoc(), llvmTy, true, + LLVM::Linkage::Internal, name, denseAttr); } else { - auto global = rewriter.create(op.getLoc(), llvmTy, false, - LLVM::Linkage::Internal, - name, Attribute()); + auto global = + LLVM::GlobalOp::create(rewriter, op.getLoc(), llvmTy, false, + LLVM::Linkage::Internal, name, Attribute()); Block *blk = new Block(); global.getInitializerRegion().push_back(blk); rewriter.setInsertionPointToStart(blk); @@ -585,7 +594,7 @@ LogicalResult AggregateConstantOpConversion::matchAndRewrite( Value aggregate = constructAggregate(rewriter, *typeConverter, op.getLoc(), aggregateType, adaptor.getFields()); - rewriter.create(op.getLoc(), aggregate); + LLVM::ReturnOp::create(rewriter, op.getLoc(), aggregate); constAggregateGlobalsMap[typeAttrPair] = global; } @@ -593,8 +602,8 @@ LogicalResult AggregateConstantOpConversion::matchAndRewrite( } // Get the global array address and load it to return an array value. - auto addr = rewriter.create( - op->getLoc(), constAggregateGlobalsMap[typeAttrPair]); + auto addr = LLVM::AddressOfOp::create(rewriter, op->getLoc(), + constAggregateGlobalsMap[typeAttrPair]); rewriter.replaceOpWithNewOp(op, llvmTy, addr); return success(); diff --git a/lib/Conversion/HWToSMT/HWToSMT.cpp b/lib/Conversion/HWToSMT/HWToSMT.cpp index 06316ac51b..7dc9e200fa 100644 --- a/lib/Conversion/HWToSMT/HWToSMT.cpp +++ b/lib/Conversion/HWToSMT/HWToSMT.cpp @@ -59,8 +59,8 @@ struct HWModuleOpConversion : OpConversionPattern { return failure(); if (failed(rewriter.convertRegionTypes(&op.getBody(), *typeConverter))) return failure(); - auto funcOp = rewriter.create( - op.getLoc(), adaptor.getSymNameAttr(), + auto funcOp = mlir::func::FuncOp::create( + rewriter, op.getLoc(), adaptor.getSymNameAttr(), rewriter.getFunctionType(inputTypes, resultTypes)); rewriter.inlineRegionBefore(op.getBody(), funcOp.getBody(), funcOp.end()); rewriter.eraseOp(op); @@ -112,11 +112,11 @@ struct ArrayCreateOpConversion : OpConversionPattern { unsigned width = adaptor.getInputs().size(); - Value arr = rewriter.create(loc, arrTy); + Value arr = mlir::smt::DeclareFunOp::create(rewriter, loc, arrTy); for (auto [i, el] : llvm::enumerate(adaptor.getInputs())) { - Value idx = rewriter.create( - loc, width - i - 1, llvm::Log2_64_Ceil(width)); - arr = rewriter.create(loc, arr, idx, el); + Value idx = mlir::smt::BVConstantOp::create(rewriter, loc, width - i - 1, + llvm::Log2_64_Ceil(width)); + arr = mlir::smt::ArrayStoreOp::create(rewriter, loc, arr, idx, el); } rewriter.replaceOp(op, arr); @@ -140,14 +140,14 @@ struct ArrayGetOpConversion : OpConversionPattern { return rewriter.notifyMatchFailure(op.getLoc(), "unsupported array element type"); - Value oobVal = rewriter.create(loc, type); - Value numElementsVal = rewriter.create( - loc, numElements - 1, llvm::Log2_64_Ceil(numElements)); - Value inBounds = - rewriter.create(loc, mlir::smt::BVCmpPredicate::ule, - adaptor.getIndex(), numElementsVal); - Value indexed = rewriter.create( - loc, adaptor.getInput(), adaptor.getIndex()); + Value oobVal = mlir::smt::DeclareFunOp::create(rewriter, loc, type); + Value numElementsVal = mlir::smt::BVConstantOp::create( + rewriter, loc, numElements - 1, llvm::Log2_64_Ceil(numElements)); + Value inBounds = mlir::smt::BVCmpOp::create( + rewriter, loc, mlir::smt::BVCmpPredicate::ule, adaptor.getIndex(), + numElementsVal); + Value indexed = mlir::smt::ArraySelectOp::create( + rewriter, loc, adaptor.getInput(), adaptor.getIndex()); rewriter.replaceOpWithNewOp(op, inBounds, indexed, oobVal); return success(); @@ -170,15 +170,16 @@ struct ArrayInjectOpConversion : OpConversionPattern { return rewriter.notifyMatchFailure(op.getLoc(), "unsupported array type"); // Check if the index is within bounds - Value numElementsVal = rewriter.create( - loc, numElements - 1, llvm::Log2_64_Ceil(numElements)); - Value inBounds = - rewriter.create(loc, mlir::smt::BVCmpPredicate::ule, - adaptor.getIndex(), numElementsVal); + Value numElementsVal = mlir::smt::BVConstantOp::create( + rewriter, loc, numElements - 1, llvm::Log2_64_Ceil(numElements)); + Value inBounds = mlir::smt::BVCmpOp::create( + rewriter, loc, mlir::smt::BVCmpPredicate::ule, adaptor.getIndex(), + numElementsVal); // Store the element at the given index - Value stored = rewriter.create( - loc, adaptor.getInput(), adaptor.getIndex(), adaptor.getElement()); + Value stored = mlir::smt::ArrayStoreOp::create( + rewriter, loc, adaptor.getInput(), adaptor.getIndex(), + adaptor.getElement()); // Return the original array if out of bounds, otherwise return the new // array @@ -245,8 +246,8 @@ void circt::populateHWToSMTTypeConverter(TypeConverter &converter) { converter.addTargetMaterialization([&](OpBuilder &builder, Type resultType, ValueRange inputs, Location loc) -> Value { - return builder - .create(loc, resultType, inputs) + return mlir::UnrealizedConversionCastOp::create(builder, loc, resultType, + inputs) ->getResult(0); }); @@ -262,10 +263,11 @@ void circt::populateHWToSMTTypeConverter(TypeConverter &converter) { unsigned width = resultType.getWidth(); Value constZero = - builder.create(loc, 0, width); - Value constOne = builder.create(loc, 1, width); - return builder.create(loc, inputs[0], constOne, - constZero); + mlir::smt::BVConstantOp::create(builder, loc, 0, width); + Value constOne = + mlir::smt::BVConstantOp::create(builder, loc, 1, width); + return mlir::smt::IteOp::create(builder, loc, inputs[0], constOne, + constZero); }); // Convert an unrealized conversion cast from 'smt.bool' to i1 @@ -288,10 +290,10 @@ void circt::populateHWToSMTTypeConverter(TypeConverter &converter) { if (!isa(castOp.getInputs()[0].getType())) return Value(); - Value constZero = builder.create(loc, 0, 1); - Value constOne = builder.create(loc, 1, 1); - return builder.create(loc, castOp.getInputs()[0], - constOne, constZero); + Value constZero = mlir::smt::BVConstantOp::create(builder, loc, 0, 1); + Value constOne = mlir::smt::BVConstantOp::create(builder, loc, 1, 1); + return mlir::smt::IteOp::create(builder, loc, castOp.getInputs()[0], + constOne, constZero); }); // Convert a 'smt.bv<1>'-typed value to a 'smt.bool'-typed value @@ -305,8 +307,8 @@ void circt::populateHWToSMTTypeConverter(TypeConverter &converter) { if (!bvType || bvType.getWidth() != 1) return Value(); - Value constOne = builder.create(loc, 1, 1); - return builder.create(loc, inputs[0], constOne); + Value constOne = mlir::smt::BVConstantOp::create(builder, loc, 1, 1); + return mlir::smt::EqOp::create(builder, loc, inputs[0], constOne); }); // Default source materialization to convert from illegal types to legal @@ -314,8 +316,8 @@ void circt::populateHWToSMTTypeConverter(TypeConverter &converter) { converter.addSourceMaterialization([&](OpBuilder &builder, Type resultType, ValueRange inputs, Location loc) -> Value { - return builder - .create(loc, resultType, inputs) + return mlir::UnrealizedConversionCastOp::create(builder, loc, resultType, + inputs) ->getResult(0); }); } diff --git a/lib/Conversion/HWToSV/HWToSV.cpp b/lib/Conversion/HWToSV/HWToSV.cpp index 454abf619c..284bcb1b5c 100644 --- a/lib/Conversion/HWToSV/HWToSV.cpp +++ b/lib/Conversion/HWToSV/HWToSV.cpp @@ -50,8 +50,8 @@ struct TriggeredOpConversionPattern : public OpConversionPattern { LogicalResult matchAndRewrite(TriggeredOp op, OpAdaptor operands, ConversionPatternRewriter &rewriter) const override { - auto alwaysOp = rewriter.create( - op.getLoc(), + auto alwaysOp = AlwaysOp::create( + rewriter, op.getLoc(), llvm::SmallVector{hwToSvEventControl(op.getEvent())}, llvm::SmallVector{op.getTrigger()}); rewriter.mergeBlocks(op.getBodyBlock(), alwaysOp.getBodyBlock(), diff --git a/lib/Conversion/HWToSystemC/HWToSystemC.cpp b/lib/Conversion/HWToSystemC/HWToSystemC.cpp index 7fde70d94f..db8cd6ffed 100644 --- a/lib/Conversion/HWToSystemC/HWToSystemC.cpp +++ b/lib/Conversion/HWToSystemC/HWToSystemC.cpp @@ -58,8 +58,8 @@ struct ConvertHWModule : public OpConversionPattern { for (size_t i = 0; i < ports.size(); ++i) ports[i].type = typeConverter->convertType(ports[i].type); - auto scModule = rewriter.create(module.getLoc(), - module.getNameAttr(), ports); + auto scModule = SCModuleOp::create(rewriter, module.getLoc(), + module.getNameAttr(), ports); auto *outputOp = module.getBodyBlock()->getTerminator(); scModule.setVisibility(module.getVisibility()); @@ -70,8 +70,8 @@ struct ConvertHWModule : public OpConversionPattern { // Create a systemc.func operation inside the module after the ctor. // TODO: implement logic to extract a better name and properly unique it. rewriter.setInsertionPointToStart(scModule.getBodyBlock()); - auto scFunc = rewriter.create( - module.getLoc(), rewriter.getStringAttr("innerLogic")); + auto scFunc = SCFuncOp::create(rewriter, module.getLoc(), + rewriter.getStringAttr("innerLogic")); // Inline the HW module body into the systemc.func body. // TODO: do some dominance analysis to detect use-before-def and cycles in @@ -84,7 +84,7 @@ struct ConvertHWModule : public OpConversionPattern { // Register the systemc.func inside the systemc.ctor rewriter.setInsertionPointToStart( scModule.getOrCreateCtor().getBodyBlock()); - rewriter.create(scModule.getLoc(), scFunc.getHandle()); + MethodOp::create(rewriter, scModule.getLoc(), scFunc.getHandle()); // Register the sensitivities of above SC_METHOD registration. SmallVector sensitivityValues( @@ -92,17 +92,16 @@ struct ConvertHWModule : public OpConversionPattern { return !isa(arg.getType()); })); if (!sensitivityValues.empty()) - rewriter.create(scModule.getLoc(), sensitivityValues); + SensitiveOp::create(rewriter, scModule.getLoc(), sensitivityValues); // Move the block arguments of the systemc.func (that we got from the // hw.module) to the systemc.module rewriter.setInsertionPointToStart(scFunc.getBodyBlock()); auto portsLocal = module.getPortList(); for (size_t i = 0, e = scFunc.getRegion().getNumArguments(); i < e; ++i) { - auto inputRead = - rewriter - .create(scFunc.getLoc(), scModule.getArgument(i)) - .getResult(); + auto inputRead = SignalReadOp::create(rewriter, scFunc.getLoc(), + scModule.getArgument(i)) + .getResult(); auto converted = typeConverter->materializeSourceConversion( rewriter, scModule.getLoc(), portsLocal[i].type, inputRead); scFuncBody.getArgument(0).replaceAllUsesWith(converted); @@ -124,7 +123,7 @@ struct ConvertHWModule : public OpConversionPattern { auto converted = typeConverter->materializeTargetConversion( rewriter, scModule.getLoc(), getSignalBaseType(portValue.getType()), std::get<1>(args)); - rewriter.create(outputOp->getLoc(), portValue, converted); + SignalWriteOp::create(rewriter, outputOp->getLoc(), portValue, converted); } // Erase the HW OutputOp. @@ -192,8 +191,8 @@ public: auto instModuleName = instanceOp.getModuleNameAttr(); // Declare the instance. - auto instDecl = stateBuilder.create( - loc, instanceName, instModuleName, portInfo); + auto instDecl = InstanceDeclOp::create(stateBuilder, loc, instanceName, + instModuleName, portInfo); // Bind the input ports. for (size_t i = 0, numInputs = adaptor.getInputs().size(); i < numInputs; @@ -206,16 +205,16 @@ public: if (auto readOp = input.getDefiningOp()) { // Use the read channel directly without adding an // intermediate signal. - initBuilder.create(loc, instDecl, portId, - readOp.getInput()); + BindPortOp::create(initBuilder, loc, instDecl, portId, + readOp.getInput()); continue; } // Otherwise, create an intermediate signal to bind the instance port to. Type sigType = SignalType::get(getSignalBaseType(portInfo[i].type)); - Value channel = stateBuilder.create(loc, sigType, signalName); - initBuilder.create(loc, instDecl, portId, channel); - rewriter.create(loc, channel, input); + Value channel = SignalOp::create(stateBuilder, loc, sigType, signalName); + BindPortOp::create(initBuilder, loc, instDecl, portId, channel); + SignalWriteOp::create(rewriter, loc, channel, input); } // Bind the output ports. @@ -236,8 +235,8 @@ public: // we cannot insert multiple bind statements for one submodule port. // It is also necessary to bind it to an intermediate signal when it // has no uses as every port has to be bound to a channel. - initBuilder.create(loc, instDecl, portId, - writeOp.getDest()); + BindPortOp::create(initBuilder, loc, instDecl, portId, + writeOp.getDest()); writeOp->erase(); continue; } @@ -246,9 +245,9 @@ public: // Otherwise, create an intermediate signal. Type sigType = SignalType::get(getSignalBaseType(portInfo[i + numInputs].type)); - Value channel = stateBuilder.create(loc, sigType, signalName); - initBuilder.create(loc, instDecl, portId, channel); - auto instOut = rewriter.create(loc, channel); + Value channel = SignalOp::create(stateBuilder, loc, sigType, signalName); + BindPortOp::create(initBuilder, loc, instDecl, portId, channel); + auto instOut = SignalReadOp::create(rewriter, loc, channel); output.replaceAllUsesWith(instOut); } @@ -317,14 +316,14 @@ static void populateTypeConversion(TypeConverter &converter) { converter.addSourceMaterialization( [](OpBuilder &builder, Type type, ValueRange values, Location loc) { assert(values.size() == 1); - auto op = builder.create(loc, type, values[0]); + auto op = ConvertOp::create(builder, loc, type, values[0]); return op.getResult(); }); converter.addTargetMaterialization( [](OpBuilder &builder, Type type, ValueRange values, Location loc) { assert(values.size() == 1); - auto op = builder.create(loc, type, values[0]); + auto op = ConvertOp::create(builder, loc, type, values[0]); return op.getResult(); }); } @@ -353,7 +352,7 @@ void HWToSystemCPass::runOnOperation() { // Create the include operation here to have exactly one 'systemc' include at // the top instead of one per module. OpBuilder builder(module.getRegion()); - builder.create(module->getLoc(), "systemc.h", true); + emitc::IncludeOp::create(builder, module->getLoc(), "systemc.h", true); ConversionTarget target(context); TypeConverter typeConverter; diff --git a/lib/Conversion/HandshakeToDC/HandshakeToDC.cpp b/lib/Conversion/HandshakeToDC/HandshakeToDC.cpp index ea855769d1..c9344100f6 100644 --- a/lib/Conversion/HandshakeToDC/HandshakeToDC.cpp +++ b/lib/Conversion/HandshakeToDC/HandshakeToDC.cpp @@ -54,7 +54,7 @@ struct DCTuple { // Unpack a !dc.value<...> into a DCTuple. static DCTuple unpack(OpBuilder &b, Value v) { if (isa(v.getType())) - return DCTuple(b.create(v.getLoc(), v)); + return DCTuple(dc::UnpackOp::create(b, v.getLoc(), v)); assert(isa(v.getType()) && "Expected a dc::TokenType"); return DCTuple(v, {}); } @@ -62,7 +62,7 @@ static DCTuple unpack(OpBuilder &b, Value v) { static Value pack(OpBuilder &b, Value token, Value data = {}) { if (!data) return token; - return b.create(token.getLoc(), token, data); + return dc::PackOp::create(b, token.getLoc(), token, data); } // NOLINTNEXTLINE(misc-no-recursion) @@ -113,8 +113,8 @@ public: if (vt && !vt.getInnerType()) return pack(builder, inputs.front()); - return builder - .create(loc, resultType, inputs[0]) + return UnrealizedConversionCastOp::create(builder, loc, resultType, + inputs[0]) ->getResult(0); }); @@ -134,8 +134,8 @@ public: if (vt && !vt.getInnerType()) return pack(builder, inputs.front()); - return builder - .create(loc, resultType, inputs[0]) + return UnrealizedConversionCastOp::create(builder, loc, resultType, + inputs[0]) ->getResult(0); }); } @@ -168,14 +168,14 @@ public: auto data = unpack(rewriter, adaptor.getDataOperand()); // Join the token of the condition and the input. - auto join = rewriter.create( - op.getLoc(), ValueRange{condition.token, data.token}); + auto join = dc::JoinOp::create(rewriter, op.getLoc(), + ValueRange{condition.token, data.token}); // Pack that together with the condition data. auto packedCondition = pack(rewriter, join, condition.data); // Branch on the input data and the joined control input. - auto branch = rewriter.create(op.getLoc(), packedCondition); + auto branch = dc::BranchOp::create(rewriter, op.getLoc(), packedCondition); // Pack the branch output tokens with the input data, and replace the uses. llvm::SmallVector packed; @@ -197,8 +197,8 @@ public: matchAndRewrite(handshake::ForkOp op, OpAdaptor adaptor, ConversionPatternRewriter &rewriter) const override { auto input = unpack(rewriter, adaptor.getOperand()); - auto forkOut = rewriter.create(op.getLoc(), input.token, - op.getNumResults()); + auto forkOut = dc::ForkOp::create(rewriter, op.getLoc(), input.token, + op.getNumResults()); // Pack the fork result tokens with the input data, and replace the uses. llvm::SmallVector packed; @@ -248,14 +248,14 @@ public: } // Control side - Value selectedIndex = rewriter.create(op.getLoc(), tokens); + Value selectedIndex = dc::MergeOp::create(rewriter, op.getLoc(), tokens); auto selectedIndexUnpacked = unpack(rewriter, selectedIndex); Value mergeOutput; if (!data.empty()) { // Data-merge; mux the selected input. - auto dataMux = rewriter.create( - op.getLoc(), selectedIndexUnpacked.data, data[0], data[1]); + auto dataMux = arith::SelectOp::create( + rewriter, op.getLoc(), selectedIndexUnpacked.data, data[0], data[1]); convertedOps->insert(dataMux); // Pack the data mux with the control token. @@ -290,11 +290,11 @@ public: inputData.push_back(dct.data); } - auto join = rewriter.create(op.getLoc(), inputTokens); + auto join = dc::JoinOp::create(rewriter, op.getLoc(), inputTokens); StructType structType = tupleToStruct(cast(op.getResult().getType())); - auto packedData = - rewriter.create(op.getLoc(), structType, inputData); + auto packedData = hw::StructCreateOp::create(rewriter, op.getLoc(), + structType, inputData); convertedOps->insert(packedData); rewriter.replaceOp(op, pack(rewriter, join, packedData)); return success(); @@ -313,7 +313,7 @@ public: // values. DCTuple unpackedInput = unpack(rewriter, adaptor.getInput()); auto unpackedData = - rewriter.create(op.getLoc(), unpackedInput.data); + hw::StructExplodeOp::create(rewriter, op.getLoc(), unpackedInput.data); convertedOps->insert(unpackedData); // Re-pack each of the tuple elements with the token. llvm::SmallVector repackedInputs; @@ -349,15 +349,15 @@ public: bool isIndexType = isa(op.getIndex().getType()); // control-side - Value selectedIndex = rewriter.create(op.getLoc(), tokens); + Value selectedIndex = dc::MergeOp::create(rewriter, op.getLoc(), tokens); auto mergeOpUnpacked = unpack(rewriter, selectedIndex); auto selValue = mergeOpUnpacked.data; Value dataSide = selectedIndex; if (!data.empty()) { // Data side mux using the selected input. - auto dataMux = rewriter.create(op.getLoc(), selValue, - data[0], data[1]); + auto dataMux = arith::SelectOp::create(rewriter, op.getLoc(), selValue, + data[0], data[1]); convertedOps->insert(dataMux); // Pack the data mux with the control token. auto packed = pack(rewriter, mergeOpUnpacked.token, dataMux); @@ -368,15 +368,15 @@ public: // if the original op used `index` as the select operand type, we need to // index-cast the unpacked select operand if (isIndexType) { - selValue = rewriter.create( - op.getLoc(), rewriter.getIndexType(), selValue); + selValue = arith::IndexCastOp::create(rewriter, op.getLoc(), + rewriter.getIndexType(), selValue); convertedOps->insert(selValue.getDefiningOp()); selectedIndex = pack(rewriter, mergeOpUnpacked.token, selValue); } else { // The cmerge had a specific type defined for the index type. dc.merge // provides an i1 operand for the selected index, so we need to cast it. - selValue = rewriter.create( - op.getLoc(), op.getIndex().getType(), selValue); + selValue = arith::ExtUIOp::create(rewriter, op.getLoc(), + op.getIndex().getType(), selValue); convertedOps->insert(selValue.getDefiningOp()); selectedIndex = pack(rewriter, mergeOpUnpacked.token, selValue); } @@ -402,7 +402,7 @@ public: inputData.push_back(unpacked.data); } - auto syncToken = rewriter.create(op.getLoc(), inputTokens); + auto syncToken = dc::JoinOp::create(rewriter, op.getLoc(), inputTokens); // Wrap all outputs with the synchronization token llvm::SmallVector wrappedInputs; @@ -425,9 +425,9 @@ public: matchAndRewrite(handshake::ConstantOp op, OpAdaptor adaptor, ConversionPatternRewriter &rewriter) const override { // Wrap the constant with a token. - auto token = rewriter.create(op.getLoc()); + auto token = dc::SourceOp::create(rewriter, op.getLoc()); auto cst = - rewriter.create(op.getLoc(), adaptor.getValue()); + arith::ConstantOp::create(rewriter, op.getLoc(), adaptor.getValue()); convertedOps->insert(cst); rewriter.replaceOp(op, pack(rewriter, token, cst)); return success(); @@ -458,7 +458,7 @@ public: // Constant-like operation; assume the token can be represented as a // constant `dc.source`. - outToken = rewriter.create(op->getLoc()); + outToken = dc::SourceOp::create(rewriter, op->getLoc()); } else { llvm::SmallVector inputTokens; for (auto input : operands) { @@ -468,7 +468,7 @@ public: } // Join the tokens of the inputs. assert(!inputTokens.empty() && "Expected at least one input token"); - outToken = rewriter.create(op->getLoc(), inputTokens); + outToken = dc::JoinOp::create(rewriter, op->getLoc(), inputTokens); } // Patchwork to fix bad IR design in Handshake. @@ -600,15 +600,17 @@ public: Value inputData = input.data; Value inputControl = input.token; if (isIndexType) { - cmpIndex = rewriter.create(op.getLoc(), i); + cmpIndex = arith::ConstantIndexOp::create(rewriter, op.getLoc(), i); } else { size_t width = cast(selectData.getType()).getWidth(); - cmpIndex = rewriter.create(op.getLoc(), i, width); + cmpIndex = + arith::ConstantIntOp::create(rewriter, op.getLoc(), i, width); } - auto inputSelected = rewriter.create( - op.getLoc(), arith::CmpIPredicate::eq, selectData, cmpIndex); - dataMux = rewriter.create(op.getLoc(), inputSelected, - inputData, dataMux); + auto inputSelected = + arith::CmpIOp::create(rewriter, op.getLoc(), arith::CmpIPredicate::eq, + selectData, cmpIndex); + dataMux = arith::SelectOp::create(rewriter, op.getLoc(), inputSelected, + inputData, dataMux); // Legalize the newly created operations. convertedOps->insert(cmpIndex.getDefiningOp()); @@ -619,8 +621,9 @@ public: // select value that has it's control from the original select token + // the inputSelected value. auto inputSelectedControl = pack(rewriter, selectToken, inputSelected); - controlMux = rewriter.create( - op.getLoc(), inputSelectedControl, inputControl, controlMux); + controlMux = + dc::SelectOp::create(rewriter, op.getLoc(), inputSelectedControl, + inputControl, controlMux); convertedOps->insert(controlMux.getDefiningOp()); } @@ -671,12 +674,12 @@ public: ModulePortInfo ports = getModulePortInfoHS(*getTypeConverter(), op); if (op.isExternal()) { - auto mod = rewriter.create( - op.getLoc(), rewriter.getStringAttr(op.getName()), ports); + auto mod = hw::HWModuleExternOp::create( + rewriter, op.getLoc(), rewriter.getStringAttr(op.getName()), ports); convertedOps->insert(mod); } else { - auto hwModule = rewriter.create( - op.getLoc(), rewriter.getStringAttr(op.getName()), ports); + auto hwModule = hw::HWModuleOp::create( + rewriter, op.getLoc(), rewriter.getStringAttr(op.getName()), ports); auto ®ion = op->getRegions().front(); @@ -712,18 +715,18 @@ public: for (size_t i = ESIInstanceOp::NumFixedOperands, e = op.getNumOperands(); i < e; ++i) operands.push_back( - rewriter.create(loc, adaptor.getOperands()[i])); + dc::FromESIOp::create(rewriter, loc, adaptor.getOperands()[i])); operands.push_back(adaptor.getClk()); operands.push_back(adaptor.getRst()); // Locate the lowered module so the instance builder can get all the // metadata. Operation *targetModule = symCache.getDefinition(op.getModuleAttr()); // And replace the op with an instance of the target module. - auto inst = rewriter.create(loc, targetModule, - op.getInstNameAttr(), operands); + auto inst = hw::InstanceOp::create(rewriter, loc, targetModule, + op.getInstNameAttr(), operands); SmallVector esiResults( llvm::map_range(inst.getResults(), [&](Value v) { - return rewriter.create(loc, v); + return dc::ToESIOp::create(rewriter, loc, v); })); rewriter.replaceOp(op, esiResults); return success(); diff --git a/lib/Conversion/HandshakeToHW/HandshakeToHW.cpp b/lib/Conversion/HandshakeToHW/HandshakeToHW.cpp index 4f61272909..cc272cc5f0 100644 --- a/lib/Conversion/HandshakeToHW/HandshakeToHW.cpp +++ b/lib/Conversion/HandshakeToHW/HandshakeToHW.cpp @@ -71,8 +71,8 @@ public: mlir::Location loc) -> mlir::Value { if (inputs.size() != 1) return Value(); - return builder - .create(loc, resultType, inputs[0]) + return UnrealizedConversionCastOp::create(builder, loc, resultType, + inputs[0]) ->getResult(0); }); @@ -81,8 +81,8 @@ public: mlir::Location loc) -> mlir::Value { if (inputs.size() != 1) return Value(); - return builder - .create(loc, resultType, inputs[0]) + return UnrealizedConversionCastOp::create(builder, loc, resultType, + inputs[0]) ->getResult(0); }); } @@ -350,8 +350,8 @@ static LogicalResult convertExtMemoryOps(HWModuleOp mod) { auto newInPort = mod.getArgumentForInput(i); // Replace the extmemory submodule outputs with the newly created inputs. b.setInsertionPointToStart(mod.getBodyBlock()); - auto newInPortExploded = b.create( - arg.getLoc(), extmemMod.getOutputTypes(), newInPort); + auto newInPortExploded = hw::StructExplodeOp::create( + b, arg.getLoc(), extmemMod.getOutputTypes(), newInPort); extmemInstance.replaceAllUsesWith(newInPortExploded.getResults()); // Add memory output - this is the inputs of the extmemory op (without the @@ -364,8 +364,8 @@ static LogicalResult convertExtMemoryOps(HWModuleOp mod) { auto memOutputArgs = extmemInstance.getOperands().drop_front(); b.setInsertionPoint(mod.getBodyBlock()->getTerminator()); - auto memOutputStruct = b.create( - arg.getLoc(), outPortInfo.type, memOutputArgs); + auto memOutputStruct = hw::StructCreateOp::create( + b, arg.getLoc(), outPortInfo.type, memOutputArgs); mod.appendOutputs({{outPortInfo.name, memOutputStruct}}); // Erase the extmemory submodule instace since the i/o has now been @@ -476,7 +476,7 @@ struct RTLBuilder { return it->second; } - auto cval = b.create(loc, apv); + auto cval = hw::ConstantOp::create(b, loc, apv); if (!isZeroWidth) constants[apv] = cval; return cval; @@ -489,12 +489,12 @@ struct RTLBuilder { } std::pair wrap(Value data, Value valid, std::optional name = {}) { - auto wrapOp = b.create(loc, data, valid); + auto wrapOp = esi::WrapValidReadyOp::create(b, loc, data, valid); return {wrapOp.getResult(0), wrapOp.getResult(1)}; } std::pair unwrap(Value channel, Value ready, std::optional name = {}) { - auto unwrapOp = b.create(loc, channel, ready); + auto unwrapOp = esi::UnwrapValidReadyOp::create(b, loc, channel, ready); return {unwrapOp.getResult(0), unwrapOp.getResult(1)}; } @@ -510,13 +510,13 @@ struct RTLBuilder { "No global reset provided to this RTLBuilder - a reset " "signal must be provided to the reg(...) function."); - return b.create(loc, in, resolvedClk, resolvedRst, rstValue, - name); + return seq::CompRegOp::create(b, loc, in, resolvedClk, resolvedRst, + rstValue, name); } Value cmp(Value lhs, Value rhs, comb::ICmpPredicate predicate, std::optional name = {}) { - return b.create(loc, predicate, lhs, rhs); + return comb::ICmpOp::create(b, loc, predicate, lhs, rhs); } Value buildNamedOp(llvm::function_ref f, @@ -534,12 +534,12 @@ struct RTLBuilder { // Bitwise 'and'. Value bAnd(ValueRange values, std::optional name = {}) { return buildNamedOp( - [&]() { return b.create(loc, values, false); }, name); + [&]() { return comb::AndOp::create(b, loc, values, false); }, name); } Value bOr(ValueRange values, std::optional name = {}) { return buildNamedOp( - [&]() { return b.create(loc, values, false); }, name); + [&]() { return comb::OrOp::create(b, loc, values, false); }, name); } // Bitwise 'not'. @@ -556,19 +556,19 @@ struct RTLBuilder { } return buildNamedOp( - [&]() { return b.create(loc, value, allOnes); }, name); + [&]() { return comb::XorOp::create(b, loc, value, allOnes); }, name); return b.createOrFold(loc, value, allOnes, false); } Value shl(Value value, Value shift, std::optional name = {}) { return buildNamedOp( - [&]() { return b.create(loc, value, shift); }, name); + [&]() { return comb::ShlOp::create(b, loc, value, shift); }, name); } Value concat(ValueRange values, std::optional name = {}) { - return buildNamedOp([&]() { return b.create(loc, values); }, - name); + return buildNamedOp( + [&]() { return comb::ConcatOp::create(b, loc, values); }, name); } // Packs a list of values into a hw.struct. @@ -577,7 +577,9 @@ struct RTLBuilder { if (!structType) structType = tupleToStruct(values.getTypes()); return buildNamedOp( - [&]() { return b.create(loc, structType, values); }, + [&]() { + return hw::StructCreateOp::create(b, loc, structType, values); + }, name); } @@ -586,13 +588,13 @@ struct RTLBuilder { auto structType = cast(value.getType()); llvm::SmallVector innerTypes; structType.getInnerTypes(innerTypes); - return b.create(loc, innerTypes, value).getResults(); + return hw::StructExplodeOp::create(b, loc, innerTypes, value).getResults(); } llvm::SmallVector toBits(Value v, std::optional name = {}) { llvm::SmallVector bits; for (unsigned i = 0, e = v.getType().getIntOrFloatBitWidth(); i != e; ++i) - bits.push_back(b.create(loc, v, i, /*bitWidth=*/1)); + bits.push_back(comb::ExtractOp::create(b, loc, v, i, /*bitWidth=*/1)); return bits; } @@ -606,7 +608,7 @@ struct RTLBuilder { std::optional name = {}) { unsigned width = hi - lo + 1; return buildNamedOp( - [&]() { return b.create(loc, v, lo, width); }, name); + [&]() { return comb::ExtractOp::create(b, loc, v, lo, width); }, name); } // Truncates 'value' to its lower 'width' bits. @@ -638,13 +640,13 @@ struct RTLBuilder { // Creates a hw.array of the given values. Value arrayCreate(ValueRange values, std::optional name = {}) { return buildNamedOp( - [&]() { return b.create(loc, values); }, name); + [&]() { return hw::ArrayCreateOp::create(b, loc, values); }, name); } // Extract the 'index'th value from the input array. Value arrayGet(Value array, Value index, std::optional name = {}) { return buildNamedOp( - [&]() { return b.create(loc, array, index); }, name); + [&]() { return hw::ArrayGetOp::create(b, loc, array, index); }, name); } // Muxes a range of values. @@ -653,7 +655,7 @@ struct RTLBuilder { Value mux(Value index, ValueRange values, std::optional name = {}) { if (values.size() == 2) - return b.create(loc, index, values[1], values[0]); + return comb::MuxOp::create(b, loc, index, values[1], values[0]); return arrayGet(arrayCreate(values), index, name); } @@ -702,7 +704,7 @@ static Value createZeroDataConst(RTLBuilder &s, Location loc, Type type) { SmallVector zeroValues; for (auto field : structType.getElements()) zeroValues.push_back(createZeroDataConst(s, loc, field.type)); - return s.b.create(loc, structType, zeroValues); + return hw::StructCreateOp::create(s.b, loc, structType, zeroValues); }) .Default([&](Type) -> Value { emitError(loc) << "unsupported type for zero value: " << type; @@ -748,9 +750,10 @@ public: auto portInfo = ModulePortInfo(getPortInfoForOp(op)); submoduleBuilder.setInsertionPoint(op->getParentOp()); - implModule = submoduleBuilder.create( - op.getLoc(), submoduleBuilder.getStringAttr(getSubModuleName(op)), - portInfo, [&](OpBuilder &b, hw::HWModulePortAccessor &ports) { + implModule = hw::HWModuleOp::create( + submoduleBuilder, op.getLoc(), + submoduleBuilder.getStringAttr(getSubModuleName(op)), portInfo, + [&](OpBuilder &b, hw::HWModulePortAccessor &ports) { // if 'op' has clock trait, extract these and provide them to the // RTL builder. Value clk, rst; @@ -1122,8 +1125,8 @@ public: // constructs from the input data signals of TIn. // To disambiguate ambiguous builders with default arguments (e.g., // twoState UnitAttr), specify attribute array explicitly. - return s.b.create(op.getLoc(), inputs, - /* attributes */ ArrayRef{}); + return TOut::create(s.b, op.getLoc(), inputs, + /* attributes */ ArrayRef{}); }); }; }; @@ -1217,8 +1220,8 @@ public: auto unwrappedIO = this->unwrapIO(s, bb, ports); auto buildCompareLogic = [&](comb::ICmpPredicate predicate) { return buildUnitRateJoinLogic(s, unwrappedIO, [&](ValueRange inputs) { - return s.b.create(op.getLoc(), predicate, inputs[0], - inputs[1]); + return comb::ICmpOp::create(s.b, op.getLoc(), predicate, inputs[0], + inputs[1]); }); }; @@ -1537,16 +1540,17 @@ public: auto c0I0 = s.constant(0, 0); auto cl2dim = llvm::Log2_64_Ceil(op.getMemRefType().getShape()[0]); - auto hlmem = s.b.create( - loc, s.clk, s.rst, "_handshake_memory_" + std::to_string(op.getId()), + auto hlmem = seq::HLMemOp::create( + s.b, loc, s.clk, s.rst, + "_handshake_memory_" + std::to_string(op.getId()), op.getMemRefType().getShape(), op.getMemRefType().getElementType()); // Create load ports... for (auto &ld : loadPorts) { llvm::SmallVector addresses = {s.truncate(ld.addr.data, cl2dim)}; - auto readData = s.b.create(loc, hlmem.getHandle(), - addresses, ld.addr.valid, - /*latency=*/0); + auto readData = seq::ReadPortOp::create(s.b, loc, hlmem.getHandle(), + addresses, ld.addr.valid, + /*latency=*/0); ld.data.data->setValue(readData); ld.done.data->setValue(c0I0); // Create control fork for the load address valid and ready signals. @@ -1591,9 +1595,9 @@ public: // Instantiate the write port operation - truncate address width to memory // width. llvm::SmallVector addresses = {s.truncate(st.addr.data, cl2dim)}; - s.b.create(loc, hlmem.getHandle(), addresses, - st.data.data, writeValid, - /*latency=*/1); + seq::WritePortOp::create(s.b, loc, hlmem.getHandle(), addresses, + st.data.data, writeValid, + /*latency=*/1); } } }; // namespace @@ -1851,11 +1855,11 @@ public: HWModuleLike hwModule; if (op.isExternal()) { - hwModule = rewriter.create( - op.getLoc(), rewriter.getStringAttr(op.getName()), ports); + hwModule = hw::HWModuleExternOp::create( + rewriter, op.getLoc(), rewriter.getStringAttr(op.getName()), ports); } else { - auto hwModuleOp = rewriter.create( - op.getLoc(), rewriter.getStringAttr(op.getName()), ports); + auto hwModuleOp = hw::HWModuleOp::create( + rewriter, op.getLoc(), rewriter.getStringAttr(op.getName()), ports); auto args = hwModuleOp.getBodyBlock()->getArguments().drop_back(2); rewriter.inlineBlockBefore(&op.getBody().front(), hwModuleOp.getBodyBlock()->getTerminator(), diff --git a/lib/Conversion/ImportAIGER/ImportAIGER.cpp b/lib/Conversion/ImportAIGER/ImportAIGER.cpp index 5b8768cae4..ec76e6d8c6 100644 --- a/lib/Conversion/ImportAIGER/ImportAIGER.cpp +++ b/lib/Conversion/ImportAIGER/ImportAIGER.cpp @@ -723,15 +723,15 @@ Value AIGERParser::getLiteralValue(unsigned literal, // Handle constants if (literal == 0) { // FALSE constant - return builder.create( - loc, builder.getI1Type(), + return hw::ConstantOp::create( + builder, loc, builder.getI1Type(), builder.getIntegerAttr(builder.getI1Type(), 0)); } if (literal == 1) { // TRUE constant - return builder.create( - loc, builder.getI1Type(), + return hw::ConstantOp::create( + builder, loc, builder.getI1Type(), builder.getIntegerAttr(builder.getI1Type(), 1)); } @@ -770,8 +770,8 @@ Value AIGERParser::getLiteralValue(unsigned literal, if (inverted) { // Create an inverter using aig.and_inv with single input SmallVector inverts = {true}; - return builder.create(loc, builder.getI1Type(), - ValueRange{baseValue}, inverts); + return aig::AndInverterOp::create(builder, loc, builder.getI1Type(), + ValueRange{baseValue}, inverts); } return baseValue; @@ -825,8 +825,9 @@ ParseResult AIGERParser::createModule() { } // Create the HW module - auto hwModule = builder.create( - builder.getUnknownLoc(), builder.getStringAttr(moduleName), ports); + auto hwModule = + hw::HWModuleOp::create(builder, builder.getUnknownLoc(), + builder.getStringAttr(moduleName), ports); // Set insertion point inside the module builder.setInsertionPointToStart(hwModule.getBodyBlock()); @@ -865,8 +866,8 @@ ParseResult AIGERParser::createModule() { auto nextBackedge = bb.get(builder.getI1Type()); // Create the register with the backedge as input - auto regValue = builder.create( - lexer.translateLocation(loc), (Value)nextBackedge, clockValue); + auto regValue = seq::CompRegOp::create( + builder, lexer.translateLocation(loc), (Value)nextBackedge, clockValue); if (auto name = symbolTable.lookup({SymbolKind::Latch, i})) regValue.setNameAttr(name); @@ -889,9 +890,9 @@ ParseResult AIGERParser::createModule() { static_cast(rhs1 % 2)}; // Create AND gate with potential inversions - auto andResult = builder.create( - location, builder.getI1Type(), ValueRange{rhs0Value, rhs1Value}, - inverts); + auto andResult = + aig::AndInverterOp::create(builder, location, builder.getI1Type(), + ValueRange{rhs0Value, rhs1Value}, inverts); // Set the backedge for this AND gate's result backedges[lhs].setValue(andResult); diff --git a/lib/Conversion/ImportVerilog/AssertionExpr.cpp b/lib/Conversion/ImportVerilog/AssertionExpr.cpp index 6bc5110068..e512b82a58 100644 --- a/lib/Conversion/ImportVerilog/AssertionExpr.cpp +++ b/lib/Conversion/ImportVerilog/AssertionExpr.cpp @@ -65,14 +65,14 @@ struct AssertionExprVisitor { switch (repetition.kind) { case SequenceRepetition::Consecutive: - return builder.create(loc, inputSequence, minRepetitions, - repetitionRange); + return ltl::RepeatOp::create(builder, loc, inputSequence, minRepetitions, + repetitionRange); case SequenceRepetition::Nonconsecutive: - return builder.create( - loc, inputSequence, minRepetitions, repetitionRange); + return ltl::NonConsecutiveRepeatOp::create( + builder, loc, inputSequence, minRepetitions, repetitionRange); case SequenceRepetition::GoTo: - return builder.create(loc, inputSequence, - minRepetitions, repetitionRange); + return ltl::GoToRepeatOp::create(builder, loc, inputSequence, + minRepetitions, repetitionRange); } llvm_unreachable("All enum values handled in switch"); } @@ -120,8 +120,8 @@ struct AssertionExprVisitor { auto [delayMin, delayRange] = convertRangeToAttrs(concatElement.delay.min, concatElement.delay.max); - auto delayedSequence = builder.create(loc, sequenceValue, - delayMin, delayRange); + auto delayedSequence = ltl::DelayOp::create(builder, loc, sequenceValue, + delayMin, delayRange); sequenceElements.push_back(delayedSequence); } @@ -135,13 +135,13 @@ struct AssertionExprVisitor { using slang::ast::UnaryAssertionOperator; switch (expr.op) { case UnaryAssertionOperator::Not: - return builder.create(loc, value); + return ltl::NotOp::create(builder, loc, value); case UnaryAssertionOperator::SEventually: if (expr.range.has_value()) { mlir::emitError(loc, "Strong eventually with range not supported"); return {}; } else { - return builder.create(loc, value); + return ltl::EventuallyOp::create(builder, loc, value); } case UnaryAssertionOperator::Always: { std::pair attr = { @@ -150,15 +150,16 @@ struct AssertionExprVisitor { attr = convertRangeToAttrs(expr.range.value().min, expr.range.value().max); } - return builder.create(loc, value, attr.first, attr.second); + return ltl::RepeatOp::create(builder, loc, value, attr.first, + attr.second); } case UnaryAssertionOperator::NextTime: { auto minRepetitions = builder.getI64IntegerAttr(1); if (expr.range.has_value()) { minRepetitions = builder.getI64IntegerAttr(expr.range.value().min); } - return builder.create(loc, value, minRepetitions, - builder.getI64IntegerAttr(0)); + return ltl::DelayOp::create(builder, loc, value, minRepetitions, + builder.getI64IntegerAttr(0)); } case UnaryAssertionOperator::Eventually: case UnaryAssertionOperator::SNextTime: @@ -179,81 +180,86 @@ struct AssertionExprVisitor { using slang::ast::BinaryAssertionOperator; switch (expr.op) { case BinaryAssertionOperator::And: - return builder.create(loc, operands); + return ltl::AndOp::create(builder, loc, operands); case BinaryAssertionOperator::Or: - return builder.create(loc, operands); + return ltl::OrOp::create(builder, loc, operands); case BinaryAssertionOperator::Intersect: - return builder.create(loc, operands); + return ltl::IntersectOp::create(builder, loc, operands); case BinaryAssertionOperator::Throughout: { - auto lhsRepeat = builder.create( - loc, lhs, builder.getI64IntegerAttr(0), mlir::IntegerAttr{}); - return builder.create( - loc, SmallVector{lhsRepeat, rhs}); + auto lhsRepeat = ltl::RepeatOp::create( + builder, loc, lhs, builder.getI64IntegerAttr(0), mlir::IntegerAttr{}); + return ltl::IntersectOp::create(builder, loc, + SmallVector{lhsRepeat, rhs}); } case BinaryAssertionOperator::Within: { auto constOne = - builder.create(loc, builder.getI1Type(), 1); - auto oneRepeat = builder.create( - loc, constOne, builder.getI64IntegerAttr(0), mlir::IntegerAttr{}); - auto repeatDelay = builder.create( - loc, oneRepeat, builder.getI64IntegerAttr(1), - builder.getI64IntegerAttr(0)); - auto lhsDelay = builder.create( - loc, lhs, builder.getI64IntegerAttr(1), builder.getI64IntegerAttr(0)); - auto combined = builder.create( - loc, SmallVector{repeatDelay, lhsDelay, constOne}); - return builder.create( - loc, SmallVector{combined, rhs}); + hw::ConstantOp::create(builder, loc, builder.getI1Type(), 1); + auto oneRepeat = ltl::RepeatOp::create(builder, loc, constOne, + builder.getI64IntegerAttr(0), + mlir::IntegerAttr{}); + auto repeatDelay = ltl::DelayOp::create(builder, loc, oneRepeat, + builder.getI64IntegerAttr(1), + builder.getI64IntegerAttr(0)); + auto lhsDelay = + ltl::DelayOp::create(builder, loc, lhs, builder.getI64IntegerAttr(1), + builder.getI64IntegerAttr(0)); + auto combined = ltl::ConcatOp::create( + builder, loc, SmallVector{repeatDelay, lhsDelay, constOne}); + return ltl::IntersectOp::create(builder, loc, + SmallVector{combined, rhs}); } case BinaryAssertionOperator::Iff: { - auto ored = builder.create(loc, operands); - auto notOred = builder.create(loc, ored); - auto anded = builder.create(loc, operands); - return builder.create(loc, - SmallVector{notOred, anded}); + auto ored = ltl::OrOp::create(builder, loc, operands); + auto notOred = ltl::NotOp::create(builder, loc, ored); + auto anded = ltl::AndOp::create(builder, loc, operands); + return ltl::OrOp::create(builder, loc, + SmallVector{notOred, anded}); } case BinaryAssertionOperator::Until: - return builder.create(loc, operands); + return ltl::UntilOp::create(builder, loc, operands); case BinaryAssertionOperator::UntilWith: { - auto untilOp = builder.create(loc, operands); - auto andOp = builder.create(loc, operands); - auto notUntil = builder.create(loc, untilOp); - return builder.create(loc, - SmallVector{notUntil, andOp}); + auto untilOp = ltl::UntilOp::create(builder, loc, operands); + auto andOp = ltl::AndOp::create(builder, loc, operands); + auto notUntil = ltl::NotOp::create(builder, loc, untilOp); + return ltl::OrOp::create(builder, loc, + SmallVector{notUntil, andOp}); } case BinaryAssertionOperator::Implies: { - auto notLhs = builder.create(loc, lhs); - return builder.create(loc, SmallVector{notLhs, rhs}); + auto notLhs = ltl::NotOp::create(builder, loc, lhs); + return ltl::OrOp::create(builder, loc, + SmallVector{notLhs, rhs}); } case BinaryAssertionOperator::OverlappedImplication: - return builder.create(loc, operands); + return ltl::ImplicationOp::create(builder, loc, operands); case BinaryAssertionOperator::NonOverlappedImplication: { auto constOne = - builder.create(loc, builder.getI1Type(), 1); - auto lhsDelay = builder.create( - loc, lhs, builder.getI64IntegerAttr(1), builder.getI64IntegerAttr(0)); - auto antecedent = builder.create( - loc, SmallVector{lhsDelay, constOne}); - return builder.create( - loc, SmallVector{antecedent, rhs}); + hw::ConstantOp::create(builder, loc, builder.getI1Type(), 1); + auto lhsDelay = + ltl::DelayOp::create(builder, loc, lhs, builder.getI64IntegerAttr(1), + builder.getI64IntegerAttr(0)); + auto antecedent = ltl::ConcatOp::create( + builder, loc, SmallVector{lhsDelay, constOne}); + return ltl::ImplicationOp::create(builder, loc, + SmallVector{antecedent, rhs}); } case BinaryAssertionOperator::OverlappedFollowedBy: { - auto notRhs = builder.create(loc, rhs); - auto implication = builder.create( - loc, SmallVector{lhs, notRhs}); - return builder.create(loc, implication); + auto notRhs = ltl::NotOp::create(builder, loc, rhs); + auto implication = ltl::ImplicationOp::create( + builder, loc, SmallVector{lhs, notRhs}); + return ltl::NotOp::create(builder, loc, implication); } case BinaryAssertionOperator::NonOverlappedFollowedBy: { auto constOne = - builder.create(loc, builder.getI1Type(), 1); - auto notRhs = builder.create(loc, rhs); - auto lhsDelay = builder.create( - loc, lhs, builder.getI64IntegerAttr(1), builder.getI64IntegerAttr(0)); - auto antecedent = builder.create( - loc, SmallVector{lhsDelay, constOne}); - auto implication = builder.create( - loc, SmallVector{antecedent, notRhs}); - return builder.create(loc, implication); + hw::ConstantOp::create(builder, loc, builder.getI1Type(), 1); + auto notRhs = ltl::NotOp::create(builder, loc, rhs); + auto lhsDelay = + ltl::DelayOp::create(builder, loc, lhs, builder.getI64IntegerAttr(1), + builder.getI64IntegerAttr(0)); + auto antecedent = ltl::ConcatOp::create( + builder, loc, SmallVector{lhsDelay, constOne}); + auto implication = ltl::ImplicationOp::create( + builder, loc, SmallVector{antecedent, notRhs}); + return ltl::NotOp::create(builder, loc, implication); } case BinaryAssertionOperator::SUntil: case BinaryAssertionOperator::SUntilWith: @@ -303,6 +309,6 @@ Value Context::convertToI1(Value value) { return {}; } - return builder.create(value.getLoc(), - builder.getI1Type(), value); + return moore::ConversionOp::create(builder, value.getLoc(), + builder.getI1Type(), value); } diff --git a/lib/Conversion/ImportVerilog/Expressions.cpp b/lib/Conversion/ImportVerilog/Expressions.cpp index 586aa2fb25..c49cd11e7d 100644 --- a/lib/Conversion/ImportVerilog/Expressions.cpp +++ b/lib/Conversion/ImportVerilog/Expressions.cpp @@ -45,8 +45,9 @@ static Value getSelectIndex(OpBuilder &builder, Location loc, Value index, Value newIndex = builder.createOrFold(loc, intType, index); - Value offset = builder.create( - loc, intType, range.lower(), /*isSigned = */ range.lower() < 0); + Value offset = + moore::ConstantOp::create(builder, loc, intType, range.lower(), + /*isSigned = */ range.lower() < 0); return builder.createOrFold(loc, newIndex, offset); } @@ -55,8 +56,8 @@ static Value getSelectIndex(OpBuilder &builder, Location loc, Value index, Value newIndex = builder.createOrFold(loc, intType, index); - Value offset = builder.create( - loc, intType, range.upper(), /* isSigned = */ range.upper() < 0); + Value offset = moore::ConstantOp::create(builder, loc, intType, range.upper(), + /* isSigned = */ range.upper() < 0); return builder.createOrFold(loc, offset, newIndex); } @@ -97,22 +98,22 @@ struct ExprVisitor { auto lowBit = constValue->integer().as().value(); if (isLvalue) - return builder.create( - loc, resultType, value, range.translateIndex(lowBit)); + return moore::ExtractRefOp::create(builder, loc, resultType, value, + range.translateIndex(lowBit)); else - return builder.create(loc, resultType, value, - range.translateIndex(lowBit)); + return moore::ExtractOp::create(builder, loc, resultType, value, + range.translateIndex(lowBit)); } auto lowBit = context.convertRvalueExpression(expr.selector()); if (!lowBit) return {}; lowBit = getSelectIndex(builder, loc, lowBit, range); if (isLvalue) - return builder.create(loc, resultType, value, - lowBit); + return moore::DynExtractRefOp::create(builder, loc, resultType, value, + lowBit); else - return builder.create(loc, resultType, value, - lowBit); + return moore::DynExtractOp::create(builder, loc, resultType, value, + lowBit); } /// Handle range bit selections. @@ -200,10 +201,11 @@ struct ExprVisitor { // Adjust the offset such that it matches the right bound of the range. if (offsetAdd != 0) { if (offsetDyn) - offsetDyn = builder.create( - loc, offsetDyn, - builder.create( - loc, cast(offsetDyn.getType()), offsetAdd, + offsetDyn = moore::AddOp::create( + builder, loc, offsetDyn, + moore::ConstantOp::create( + builder, loc, cast(offsetDyn.getType()), + offsetAdd, /*isSigned=*/offsetAdd < 0)); else offsetConst += offsetAdd; @@ -222,20 +224,20 @@ struct ExprVisitor { if (offsetDyn) { offsetDyn = getSelectIndex(builder, loc, offsetDyn, range); if (isLvalue) { - return builder.create(loc, resultType, value, - offsetDyn); + return moore::DynExtractRefOp::create(builder, loc, resultType, value, + offsetDyn); } else { - return builder.create(loc, resultType, value, - offsetDyn); + return moore::DynExtractOp::create(builder, loc, resultType, value, + offsetDyn); } } else { offsetConst = range.translateIndex(offsetConst); if (isLvalue) { - return builder.create(loc, resultType, value, - offsetConst); + return moore::ExtractRefOp::create(builder, loc, resultType, value, + offsetConst); } else { - return builder.create(loc, resultType, value, - offsetConst); + return moore::ExtractOp::create(builder, loc, resultType, value, + offsetConst); } } } @@ -257,9 +259,9 @@ struct ExprVisitor { operands.push_back(value); } if (isLvalue) - return builder.create(loc, operands); + return moore::ConcatRefOp::create(builder, loc, operands); else - return builder.create(loc, operands); + return moore::ConcatOp::create(builder, loc, operands); } /// Handle member accesses. @@ -277,21 +279,21 @@ struct ExprVisitor { // Handle structs. if (valueType->isStruct()) { if (isLvalue) - return builder.create(loc, resultType, - memberName, value); + return moore::StructExtractRefOp::create(builder, loc, resultType, + memberName, value); else - return builder.create(loc, resultType, - memberName, value); + return moore::StructExtractOp::create(builder, loc, resultType, + memberName, value); } // Handle unions. if (valueType->isPackedUnion() || valueType->isUnpackedUnion()) { if (isLvalue) - return builder.create(loc, resultType, - memberName, value); + return moore::UnionExtractRefOp::create(builder, loc, resultType, + memberName, value); else - return builder.create(loc, type, memberName, - value); + return moore::UnionExtractOp::create(builder, loc, type, memberName, + value); } mlir::emitError(loc, "expression of type ") @@ -316,14 +318,14 @@ struct RvalueExprVisitor : public ExprVisitor { Value visit(const slang::ast::LValueReferenceExpression &expr) { assert(!context.lvalueStack.empty() && "parent assignments push lvalue"); auto lvalue = context.lvalueStack.back(); - return builder.create(loc, lvalue); + return moore::ReadOp::create(builder, loc, lvalue); } // Handle named values, such as references to declared variables. Value visit(const slang::ast::NamedValueExpression &expr) { if (auto value = context.valueSymbols.lookup(&expr.symbol)) { if (isa(value.getType())) { - auto readOp = builder.create(loc, value); + auto readOp = moore::ReadOp::create(builder, loc, value); if (context.rvalueReadCallback) context.rvalueReadCallback(readOp); value = readOp.getResult(); @@ -349,7 +351,7 @@ struct RvalueExprVisitor : public ExprVisitor { auto hierLoc = context.convertLocation(expr.symbol.location); if (auto value = context.valueSymbols.lookup(&expr.symbol)) { if (isa(value.getType())) { - auto readOp = builder.create(hierLoc, value); + auto readOp = moore::ReadOp::create(builder, hierLoc, value); if (context.rvalueReadCallback) context.rvalueReadCallback(readOp); value = readOp.getResult(); @@ -394,9 +396,9 @@ struct RvalueExprVisitor : public ExprVisitor { } if (expr.isNonBlocking()) - builder.create(loc, lhs, rhs); + moore::NonBlockingAssignOp::create(builder, loc, lhs, rhs); else - builder.create(loc, lhs, rhs); + moore::BlockingAssignOp::create(builder, loc, lhs, rhs); return rhs; } @@ -407,21 +409,21 @@ struct RvalueExprVisitor : public ExprVisitor { arg = context.convertToSimpleBitVector(arg); if (!arg) return {}; - Value result = builder.create(loc, arg); + Value result = ConcreteOp::create(builder, loc, arg); if (invert) - result = builder.create(loc, result); + result = moore::NotOp::create(builder, loc, result); return result; } // Helper function to create pre and post increments and decrements. Value createIncrement(Value arg, bool isInc, bool isPost) { - auto preValue = builder.create(loc, arg); - auto one = builder.create( - loc, cast(preValue.getType()), 1); + auto preValue = moore::ReadOp::create(builder, loc, arg); + auto one = moore::ConstantOp::create( + builder, loc, cast(preValue.getType()), 1); auto postValue = - isInc ? builder.create(loc, preValue, one).getResult() - : builder.create(loc, preValue, one).getResult(); - builder.create(loc, arg, postValue); + isInc ? moore::AddOp::create(builder, loc, preValue, one).getResult() + : moore::SubOp::create(builder, loc, preValue, one).getResult(); + moore::BlockingAssignOp::create(builder, loc, arg, postValue); if (isPost) return preValue; return postValue; @@ -451,13 +453,13 @@ struct RvalueExprVisitor : public ExprVisitor { arg = context.convertToSimpleBitVector(arg); if (!arg) return {}; - return builder.create(loc, arg); + return moore::NegOp::create(builder, loc, arg); case UnaryOperator::BitwiseNot: arg = context.convertToSimpleBitVector(arg); if (!arg) return {}; - return builder.create(loc, arg); + return moore::NotOp::create(builder, loc, arg); case UnaryOperator::BitwiseAnd: return createReduction(arg, false); @@ -476,7 +478,7 @@ struct RvalueExprVisitor : public ExprVisitor { arg = context.convertToBool(arg); if (!arg) return {}; - return builder.create(loc, arg); + return moore::NotOp::create(builder, loc, arg); case UnaryOperator::Preincrement: return createIncrement(arg, true, false); @@ -502,7 +504,7 @@ struct RvalueExprVisitor : public ExprVisitor { rhs = context.convertToSimpleBitVector(rhs); if (!rhs) return {}; - return builder.create(loc, lhs, rhs); + return ConcreteOp::create(builder, loc, lhs, rhs); } // Handle binary operators. @@ -544,7 +546,7 @@ struct RvalueExprVisitor : public ExprVisitor { // maintain uniform types across operands and results, cast the RHS to // that four-valued type as well. auto rhsCast = - builder.create(loc, lhs.getType(), rhs); + moore::ConversionOp::create(builder, loc, lhs.getType(), rhs); if (expr.type->isSigned()) return createBinary(lhs, rhsCast); else @@ -561,25 +563,25 @@ struct RvalueExprVisitor : public ExprVisitor { auto result = createBinary(lhs, rhs); if (!result) return {}; - return builder.create(loc, result); + return moore::NotOp::create(builder, loc, result); } case BinaryOperator::Equality: if (isa(lhs.getType())) - return builder.create( - loc, moore::UArrayCmpPredicate::eq, lhs, rhs); + return moore::UArrayCmpOp::create( + builder, loc, moore::UArrayCmpPredicate::eq, lhs, rhs); else if (isa(lhs.getType())) - return builder.create( - loc, moore::StringCmpPredicate::eq, lhs, rhs); + return moore::StringCmpOp::create( + builder, loc, moore::StringCmpPredicate::eq, lhs, rhs); else return createBinary(lhs, rhs); case BinaryOperator::Inequality: if (isa(lhs.getType())) - return builder.create( - loc, moore::UArrayCmpPredicate::ne, lhs, rhs); + return moore::UArrayCmpOp::create( + builder, loc, moore::UArrayCmpPredicate::ne, lhs, rhs); else if (isa(lhs.getType())) - return builder.create( - loc, moore::StringCmpPredicate::ne, lhs, rhs); + return moore::StringCmpOp::create( + builder, loc, moore::StringCmpPredicate::ne, lhs, rhs); else return createBinary(lhs, rhs); case BinaryOperator::CaseEquality: @@ -595,32 +597,32 @@ struct RvalueExprVisitor : public ExprVisitor { if (expr.left().type->isSigned()) return createBinary(lhs, rhs); else if (isa(lhs.getType())) - return builder.create( - loc, moore::StringCmpPredicate::ge, lhs, rhs); + return moore::StringCmpOp::create( + builder, loc, moore::StringCmpPredicate::ge, lhs, rhs); else return createBinary(lhs, rhs); case BinaryOperator::GreaterThan: if (expr.left().type->isSigned()) return createBinary(lhs, rhs); else if (isa(lhs.getType())) - return builder.create( - loc, moore::StringCmpPredicate::gt, lhs, rhs); + return moore::StringCmpOp::create( + builder, loc, moore::StringCmpPredicate::gt, lhs, rhs); else return createBinary(lhs, rhs); case BinaryOperator::LessThanEqual: if (expr.left().type->isSigned()) return createBinary(lhs, rhs); else if (isa(lhs.getType())) - return builder.create( - loc, moore::StringCmpPredicate::le, lhs, rhs); + return moore::StringCmpOp::create( + builder, loc, moore::StringCmpPredicate::le, lhs, rhs); else return createBinary(lhs, rhs); case BinaryOperator::LessThan: if (expr.left().type->isSigned()) return createBinary(lhs, rhs); else if (isa(lhs.getType())) - return builder.create( - loc, moore::StringCmpPredicate::lt, lhs, rhs); + return moore::StringCmpOp::create( + builder, loc, moore::StringCmpPredicate::lt, lhs, rhs); else return createBinary(lhs, rhs); @@ -634,7 +636,7 @@ struct RvalueExprVisitor : public ExprVisitor { rhs = context.convertToBool(rhs, domain); if (!rhs) return {}; - return builder.create(loc, lhs, rhs); + return moore::AndOp::create(builder, loc, lhs, rhs); } case BinaryOperator::LogicalOr: { // TODO: This should short-circuit. Put the RHS code into a separate @@ -645,7 +647,7 @@ struct RvalueExprVisitor : public ExprVisitor { rhs = context.convertToBool(rhs, domain); if (!rhs) return {}; - return builder.create(loc, lhs, rhs); + return moore::OrOp::create(builder, loc, lhs, rhs); } case BinaryOperator::LogicalImplication: { // `(lhs -> rhs)` equivalent to `(!lhs || rhs)`. @@ -655,8 +657,8 @@ struct RvalueExprVisitor : public ExprVisitor { rhs = context.convertToBool(rhs, domain); if (!rhs) return {}; - auto notLHS = builder.create(loc, lhs); - return builder.create(loc, notLHS, rhs); + auto notLHS = moore::NotOp::create(builder, loc, lhs); + return moore::OrOp::create(builder, loc, notLHS, rhs); } case BinaryOperator::LogicalEquivalence: { // `(lhs <-> rhs)` equivalent to `(lhs && rhs) || (!lhs && !rhs)`. @@ -666,11 +668,11 @@ struct RvalueExprVisitor : public ExprVisitor { rhs = context.convertToBool(rhs, domain); if (!rhs) return {}; - auto notLHS = builder.create(loc, lhs); - auto notRHS = builder.create(loc, rhs); - auto both = builder.create(loc, lhs, rhs); - auto notBoth = builder.create(loc, notLHS, notRHS); - return builder.create(loc, both, notBoth); + auto notLHS = moore::NotOp::create(builder, loc, lhs); + auto notRHS = moore::NotOp::create(builder, loc, rhs); + auto both = moore::AndOp::create(builder, loc, lhs, rhs); + auto notBoth = moore::AndOp::create(builder, loc, notLHS, notRHS); + return moore::OrOp::create(builder, loc, both, notBoth); } case BinaryOperator::LogicalShiftLeft: @@ -687,8 +689,8 @@ struct RvalueExprVisitor : public ExprVisitor { if (!lhs || !rhs) return {}; if (expr.type->isSigned()) - return builder.create(loc, lhs, rhs); - return builder.create(loc, lhs, rhs); + return moore::AShrOp::create(builder, loc, lhs, rhs); + return moore::ShrOp::create(builder, loc, lhs, rhs); } } @@ -712,7 +714,7 @@ struct RvalueExprVisitor : public ExprVisitor { auto value = context.convertRvalueExpression(expr.concat()); if (!value) return {}; - return builder.create(loc, type, value); + return moore::ReplicateOp::create(builder, loc, type, value); } // Handle set membership operator. @@ -743,17 +745,17 @@ struct RvalueExprVisitor : public ExprVisitor { // within the range. if (openRange->left().type->isSigned() || expr.left().type->isSigned()) { - leftValue = builder.create(loc, lhs, lowBound); + leftValue = moore::SgeOp::create(builder, loc, lhs, lowBound); } else { - leftValue = builder.create(loc, lhs, lowBound); + leftValue = moore::UgeOp::create(builder, loc, lhs, lowBound); } if (openRange->right().type->isSigned() || expr.left().type->isSigned()) { - rightValue = builder.create(loc, lhs, highBound); + rightValue = moore::SleOp::create(builder, loc, lhs, highBound); } else { - rightValue = builder.create(loc, lhs, highBound); + rightValue = moore::UleOp::create(builder, loc, lhs, highBound); } - cond = builder.create(loc, leftValue, rightValue); + cond = moore::AndOp::create(builder, loc, leftValue, rightValue); } else { // Handle expressions. if (!listExpr->type->isIntegral()) { @@ -771,7 +773,7 @@ struct RvalueExprVisitor : public ExprVisitor { context.convertRvalueExpression(*listExpr)); if (!value) return {}; - cond = builder.create(loc, lhs, value); + cond = moore::WildcardEqOp::create(builder, loc, lhs, value); } conditions.push_back(cond); } @@ -780,7 +782,7 @@ struct RvalueExprVisitor : public ExprVisitor { auto result = conditions.back(); conditions.pop_back(); while (!conditions.empty()) { - result = builder.create(loc, conditions.back(), result); + result = moore::OrOp::create(builder, loc, conditions.back(), result); conditions.pop_back(); } return result; @@ -805,7 +807,8 @@ struct RvalueExprVisitor : public ExprVisitor { context.convertToBool(context.convertRvalueExpression(*cond.expr)); if (!value) return {}; - auto conditionalOp = builder.create(loc, type, value); + auto conditionalOp = + moore::ConditionalOp::create(builder, loc, type, value); // Create blocks for true region and false region. auto &trueBlock = conditionalOp.getTrueRegion().emplaceBlock(); @@ -818,14 +821,14 @@ struct RvalueExprVisitor : public ExprVisitor { auto trueValue = context.convertRvalueExpression(expr.left(), type); if (!trueValue) return {}; - builder.create(loc, trueValue); + moore::YieldOp::create(builder, loc, trueValue); // Handle right expression. builder.setInsertionPointToStart(&falseBlock); auto falseValue = context.convertRvalueExpression(expr.right(), type); if (!falseValue) return {}; - builder.create(loc, falseValue); + moore::YieldOp::create(builder, loc, falseValue); return conditionalOp.getResult(); } @@ -880,15 +883,15 @@ struct RvalueExprVisitor : public ExprVisitor { // Create the call. auto callOp = - builder.create(loc, lowering->op, arguments); + mlir::func::CallOp::create(builder, loc, lowering->op, arguments); // For calls to void functions we need to have a value to return from this // function. Create a dummy `unrealized_conversion_cast`, which will get // deleted again later on. if (callOp.getNumResults() == 0) - return builder - .create( - loc, moore::VoidType::get(context.getContext()), ValueRange{}) + return mlir::UnrealizedConversionCastOp::create( + builder, loc, moore::VoidType::get(context.getContext()), + ValueRange{}) .getResult(0); return callOp.getResult(0); @@ -919,13 +922,13 @@ struct RvalueExprVisitor : public ExprVisitor { /// Handle string literals. Value visit(const slang::ast::StringLiteral &expr) { auto type = context.convertType(*expr.type); - return builder.create(loc, type, expr.getValue()); + return moore::StringConstantOp::create(builder, loc, type, expr.getValue()); } /// Handle real literals. Value visit(const slang::ast::RealLiteral &expr) { - return builder.create( - loc, builder.getF64FloatAttr(expr.getValue())); + return moore::RealLiteralOp::create( + builder, loc, builder.getF64FloatAttr(expr.getValue())); } /// Handle assignment patterns. @@ -952,31 +955,31 @@ struct RvalueExprVisitor : public ExprVisitor { if (auto intType = dyn_cast(type)) { assert(intType.getWidth() == elements.size()); std::reverse(elements.begin(), elements.end()); - return builder.create(loc, intType, elements); + return moore::ConcatOp::create(builder, loc, intType, elements); } // Handle packed structs. if (auto structType = dyn_cast(type)) { assert(structType.getMembers().size() == elements.size()); - return builder.create(loc, structType, elements); + return moore::StructCreateOp::create(builder, loc, structType, elements); } // Handle unpacked structs. if (auto structType = dyn_cast(type)) { assert(structType.getMembers().size() == elements.size()); - return builder.create(loc, structType, elements); + return moore::StructCreateOp::create(builder, loc, structType, elements); } // Handle packed arrays. if (auto arrayType = dyn_cast(type)) { assert(arrayType.getSize() == elements.size()); - return builder.create(loc, arrayType, elements); + return moore::ArrayCreateOp::create(builder, loc, arrayType, elements); } // Handle unpacked arrays. if (auto arrayType = dyn_cast(type)) { assert(arrayType.getSize() == elements.size()); - return builder.create(loc, arrayType, elements); + return moore::ArrayCreateOp::create(builder, loc, arrayType, elements); } mlir::emitError(loc) << "unsupported assignment pattern with type " << type; @@ -1032,7 +1035,7 @@ struct RvalueExprVisitor : public ExprVisitor { // error. value = operands.front(); } else { - value = builder.create(loc, operands).getResult(); + value = moore::ConcatOp::create(builder, loc, operands).getResult(); } if (expr.sliceSize == 0) { @@ -1048,8 +1051,8 @@ struct RvalueExprVisitor : public ExprVisitor { auto extractResultType = moore::IntType::get( context.getContext(), expr.sliceSize, type.getDomain()); - auto extracted = builder.create( - loc, extractResultType, value, i * expr.sliceSize); + auto extracted = moore::ExtractOp::create(builder, loc, extractResultType, + value, i * expr.sliceSize); slicedOperands.push_back(extracted); } // Handle other wire @@ -1057,12 +1060,12 @@ struct RvalueExprVisitor : public ExprVisitor { auto extractResultType = moore::IntType::get( context.getContext(), remainSize, type.getDomain()); - auto extracted = builder.create( - loc, extractResultType, value, iterMax * expr.sliceSize); + auto extracted = moore::ExtractOp::create( + builder, loc, extractResultType, value, iterMax * expr.sliceSize); slicedOperands.push_back(extracted); } - return builder.create(loc, slicedOperands); + return moore::ConcatOp::create(builder, loc, slicedOperands); } Value visit(const slang::ast::AssertionInstanceExpression &expr) { @@ -1151,7 +1154,7 @@ struct LvalueExprVisitor : public ExprVisitor { // error. value = operands.front(); } else { - value = builder.create(loc, operands).getResult(); + value = moore::ConcatRefOp::create(builder, loc, operands).getResult(); } if (expr.sliceSize == 0) { @@ -1170,8 +1173,8 @@ struct LvalueExprVisitor : public ExprVisitor { auto extractResultType = moore::RefType::get( moore::IntType::get(context.getContext(), expr.sliceSize, domain)); - auto extracted = builder.create( - loc, extractResultType, value, i * expr.sliceSize); + auto extracted = moore::ExtractRefOp::create( + builder, loc, extractResultType, value, i * expr.sliceSize); slicedOperands.push_back(extracted); } // Handle other wire @@ -1179,12 +1182,12 @@ struct LvalueExprVisitor : public ExprVisitor { auto extractResultType = moore::RefType::get( moore::IntType::get(context.getContext(), remainSize, domain)); - auto extracted = builder.create( - loc, extractResultType, value, iterMax * expr.sliceSize); + auto extracted = moore::ExtractRefOp::create( + builder, loc, extractResultType, value, iterMax * expr.sliceSize); slicedOperands.push_back(extracted); } - return builder.create(loc, slicedOperands); + return moore::ConcatRefOp::create(builder, loc, slicedOperands); } /// Emit an error for all other expressions. @@ -1228,7 +1231,7 @@ Value Context::convertToBool(Value value) { if (type.getBitSize() == 1) return value; if (auto type = dyn_cast_or_null(value.getType())) - return builder.create(value.getLoc(), value); + return moore::BoolCastOp::create(builder, value.getLoc(), value); mlir::emitError(value.getLoc(), "expression of type ") << value.getType() << " cannot be cast to a boolean"; return {}; @@ -1250,9 +1253,9 @@ Value Context::materializeSVInt(const slang::SVInt &svint, fvint.hasUnknown() || typeIsFourValued ? moore::Domain::FourValued : moore::Domain::TwoValued); - Value result = builder.create(loc, intType, fvint); + Value result = moore::ConstantOp::create(builder, loc, intType, fvint); if (result.getType() != type) - result = builder.create(loc, type, result); + result = moore::ConversionOp::create(builder, loc, type, result); return result; } @@ -1280,7 +1283,7 @@ Value Context::convertToBool(Value value, Domain domain) { auto type = moore::IntType::get(getContext(), 1, domain); if (value.getType() == type) return value; - return builder.create(value.getLoc(), type, value); + return moore::ConversionOp::create(builder, value.getLoc(), type, value); } Value Context::convertToSimpleBitVector(Value value) { @@ -1297,8 +1300,8 @@ Value Context::convertToSimpleBitVector(Value value) { if (auto bits = packed.getBitSize()) { auto sbvType = moore::IntType::get(value.getContext(), *bits, packed.getDomain()); - return builder.create(value.getLoc(), sbvType, - value); + return moore::ConversionOp::create(builder, value.getLoc(), sbvType, + value); } } @@ -1325,25 +1328,25 @@ Value Context::materializeConversion(Type type, Value value, bool isSigned, auto srcWidthType = moore::IntType::get(value.getContext(), srcWidth, srcPacked.getDomain()); if (value.getType() != srcWidthType) - value = builder.create(value.getLoc(), srcWidthType, - value); + value = moore::ConversionOp::create(builder, value.getLoc(), srcWidthType, + value); // Create truncation or sign/zero extension ops depending on the source and // destination width. auto dstWidthType = moore::IntType::get(value.getContext(), dstWidth, srcPacked.getDomain()); if (dstWidth < srcWidth) { - value = builder.create(loc, dstWidthType, value); + value = moore::TruncOp::create(builder, loc, dstWidthType, value); } else if (dstWidth > srcWidth) { if (isSigned) - value = builder.create(loc, dstWidthType, value); + value = moore::SExtOp::create(builder, loc, dstWidthType, value); else - value = builder.create(loc, dstWidthType, value); + value = moore::ZExtOp::create(builder, loc, dstWidthType, value); } } if (value.getType() != type) - value = builder.create(loc, type, value); + value = moore::ConversionOp::create(builder, loc, type, value); return value; } @@ -1362,79 +1365,79 @@ Context::convertSystemCallArity1(const slang::ast::SystemSubroutine &subroutine, value = convertToSimpleBitVector(value); if (!value) return failure(); - return (Value)builder.create(loc, value); + return (Value)moore::Clog2BIOp::create(builder, loc, value); }) .Case("$ln", [&]() -> Value { - return builder.create(loc, value); + return moore::LnBIOp::create(builder, loc, value); }) .Case("$log10", [&]() -> Value { - return builder.create(loc, value); + return moore::Log10BIOp::create(builder, loc, value); }) .Case("$sin", [&]() -> Value { - return builder.create(loc, value); + return moore::SinBIOp::create(builder, loc, value); }) .Case("$cos", [&]() -> Value { - return builder.create(loc, value); + return moore::CosBIOp::create(builder, loc, value); }) .Case("$tan", [&]() -> Value { - return builder.create(loc, value); + return moore::TanBIOp::create(builder, loc, value); }) .Case("$exp", [&]() -> Value { - return builder.create(loc, value); + return moore::ExpBIOp::create(builder, loc, value); }) .Case("$sqrt", [&]() -> Value { - return builder.create(loc, value); + return moore::SqrtBIOp::create(builder, loc, value); }) .Case("$floor", [&]() -> Value { - return builder.create(loc, value); + return moore::FloorBIOp::create(builder, loc, value); }) .Case("$ceil", [&]() -> Value { - return builder.create(loc, value); + return moore::CeilBIOp::create(builder, loc, value); }) .Case("$asin", [&]() -> Value { - return builder.create(loc, value); + return moore::AsinBIOp::create(builder, loc, value); }) .Case("$acos", [&]() -> Value { - return builder.create(loc, value); + return moore::AcosBIOp::create(builder, loc, value); }) .Case("$atan", [&]() -> Value { - return builder.create(loc, value); + return moore::AtanBIOp::create(builder, loc, value); }) .Case("$sinh", [&]() -> Value { - return builder.create(loc, value); + return moore::SinhBIOp::create(builder, loc, value); }) .Case("$cosh", [&]() -> Value { - return builder.create(loc, value); + return moore::CoshBIOp::create(builder, loc, value); }) .Case("$tanh", [&]() -> Value { - return builder.create(loc, value); + return moore::TanhBIOp::create(builder, loc, value); }) .Case("$asinh", [&]() -> Value { - return builder.create(loc, value); + return moore::AsinhBIOp::create(builder, loc, value); }) .Case("$acosh", [&]() -> Value { - return builder.create(loc, value); + return moore::AcoshBIOp::create(builder, loc, value); }) .Case("$atanh", [&]() -> Value { - return builder.create(loc, value); + return moore::AtanhBIOp::create(builder, loc, value); }) .Default([&]() -> Value { return {}; }); return systemCallRes(); diff --git a/lib/Conversion/ImportVerilog/FormatStrings.cpp b/lib/Conversion/ImportVerilog/FormatStrings.cpp index 7698ad142b..bb37b4d14a 100644 --- a/lib/Conversion/ImportVerilog/FormatStrings.cpp +++ b/lib/Conversion/ImportVerilog/FormatStrings.cpp @@ -65,7 +65,7 @@ struct FormatStringParser { return Value{}; if (fragments.size() == 1) return fragments[0]; - return builder.create(loc, fragments).getResult(); + return moore::FormatConcatOp::create(builder, loc, fragments).getResult(); } /// Parse a format string literal and consume and format the arguments @@ -93,7 +93,7 @@ struct FormatStringParser { /// Emit a string literal that requires no additional formatting. void emitLiteral(StringRef literal) { - fragments.push_back(builder.create(loc, literal)); + fragments.push_back(moore::FormatLiteralOp::create(builder, loc, literal)); } /// Consume the next argument from the list and emit it according to the given @@ -177,8 +177,8 @@ struct FormatStringParser { auto padding = format == IntFormat::Decimal ? IntPadding::Space : IntPadding::Zero; - fragments.push_back(builder.create( - loc, value, format, width, alignment, padding)); + fragments.push_back(moore::FormatIntOp::create(builder, loc, value, format, + width, alignment, padding)); return success(); } diff --git a/lib/Conversion/ImportVerilog/Statements.cpp b/lib/Conversion/ImportVerilog/Statements.cpp index bab7be3f98..bebae81c09 100644 --- a/lib/Conversion/ImportVerilog/Statements.cpp +++ b/lib/Conversion/ImportVerilog/Statements.cpp @@ -56,30 +56,30 @@ struct StmtVisitor { if (!type) return failure(); - Value initial = builder.create( - loc, cast(type), loopDim.range->lower()); + Value initial = moore::ConstantOp::create( + builder, loc, cast(type), loopDim.range->lower()); // Create loop varirable in this dimension - Value varOp = builder.create( - loc, moore::RefType::get(cast(type)), + Value varOp = moore::VariableOp::create( + builder, loc, moore::RefType::get(cast(type)), builder.getStringAttr(iter->name), initial); context.valueSymbols.insertIntoScope(context.valueSymbols.getCurScope(), iter, varOp); - builder.create(loc, &checkBlock); + cf::BranchOp::create(builder, loc, &checkBlock); builder.setInsertionPointToEnd(&checkBlock); // When the loop variable is greater than the upper bound, goto exit - auto upperBound = builder.create( - loc, cast(type), loopDim.range->upper()); + auto upperBound = moore::ConstantOp::create( + builder, loc, cast(type), loopDim.range->upper()); - auto var = builder.create(loc, varOp); - Value cond = builder.create(loc, var, upperBound); + auto var = moore::ReadOp::create(builder, loc, varOp); + Value cond = moore::SleOp::create(builder, loc, var, upperBound); if (!cond) return failure(); cond = builder.createOrFold(loc, cond); - cond = builder.create(loc, builder.getI1Type(), cond); - builder.create(loc, cond, &bodyBlock, &exitBlock); + cond = moore::ConversionOp::create(builder, loc, builder.getI1Type(), cond); + cf::CondBranchOp::create(builder, loc, cond, &bodyBlock, &exitBlock); builder.setInsertionPointToEnd(&bodyBlock); @@ -101,17 +101,17 @@ struct StmtVisitor { return failure(); } if (!isTerminated()) - builder.create(loc, &stepBlock); + cf::BranchOp::create(builder, loc, &stepBlock); builder.setInsertionPointToEnd(&stepBlock); // add one to loop variable - var = builder.create(loc, varOp); + var = moore::ReadOp::create(builder, loc, varOp); auto one = - builder.create(loc, cast(type), 1); - auto postValue = builder.create(loc, var, one).getResult(); - builder.create(loc, varOp, postValue); - builder.create(loc, &checkBlock); + moore::ConstantOp::create(builder, loc, cast(type), 1); + auto postValue = moore::AddOp::create(builder, loc, var, one).getResult(); + moore::BlockingAssignOp::create(builder, loc, varOp, postValue); + cf::BranchOp::create(builder, loc, &checkBlock); if (exitBlock.hasNoPredecessors()) { exitBlock.erase(); @@ -193,8 +193,8 @@ struct StmtVisitor { } // Collect local temporary variables. - auto varOp = builder.create( - loc, moore::RefType::get(cast(type)), + auto varOp = moore::VariableOp::create( + builder, loc, moore::RefType::get(cast(type)), builder.getStringAttr(var.name), initial); context.valueSymbols.insertIntoScope(context.valueSymbols.getCurScope(), &var, varOp); @@ -215,27 +215,27 @@ struct StmtVisitor { return failure(); cond = builder.createOrFold(loc, cond); if (allConds) - allConds = builder.create(loc, allConds, cond); + allConds = moore::AndOp::create(builder, loc, allConds, cond); else allConds = cond; } assert(allConds && "slang guarantees at least one condition"); - allConds = - builder.create(loc, builder.getI1Type(), allConds); + allConds = moore::ConversionOp::create(builder, loc, builder.getI1Type(), + allConds); // Create the blocks for the true and false branches, and the exit block. Block &exitBlock = createBlock(); Block *falseBlock = stmt.ifFalse ? &createBlock() : nullptr; Block &trueBlock = createBlock(); - builder.create(loc, allConds, &trueBlock, - falseBlock ? falseBlock : &exitBlock); + cf::CondBranchOp::create(builder, loc, allConds, &trueBlock, + falseBlock ? falseBlock : &exitBlock); // Generate the true branch. builder.setInsertionPointToEnd(&trueBlock); if (failed(context.convertStatement(stmt.ifTrue))) return failure(); if (!isTerminated()) - builder.create(loc, &exitBlock); + cf::BranchOp::create(builder, loc, &exitBlock); // Generate the false branch if present. if (stmt.ifFalse) { @@ -243,7 +243,7 @@ struct StmtVisitor { if (failed(context.convertStatement(*stmt.ifFalse))) return failure(); if (!isTerminated()) - builder.create(loc, &exitBlock); + cf::BranchOp::create(builder, loc, &exitBlock); } // If control never reaches the exit block, remove it and mark control flow @@ -298,26 +298,26 @@ struct StmtVisitor { Value cond; switch (caseStmt.condition) { case CaseStatementCondition::Normal: - cond = builder.create(itemLoc, caseExpr, value); + cond = moore::CaseEqOp::create(builder, itemLoc, caseExpr, value); break; case CaseStatementCondition::WildcardXOrZ: - cond = builder.create(itemLoc, caseExpr, value); + cond = moore::CaseXZEqOp::create(builder, itemLoc, caseExpr, value); break; case CaseStatementCondition::WildcardJustZ: - cond = builder.create(itemLoc, caseExpr, value); + cond = moore::CaseZEqOp::create(builder, itemLoc, caseExpr, value); break; case CaseStatementCondition::Inside: mlir::emitError(loc, "unsupported set membership case statement"); return failure(); } - cond = builder.create(itemLoc, builder.getI1Type(), - cond); + cond = moore::ConversionOp::create(builder, itemLoc, + builder.getI1Type(), cond); // If the condition matches, branch to the match block. Otherwise // continue checking the next expression in a new block. auto &nextBlock = createBlock(); - builder.create(itemLoc, cond, &matchBlock, - &nextBlock); + mlir::cf::CondBranchOp::create(builder, itemLoc, cond, &matchBlock, + &nextBlock); builder.setInsertionPointToEnd(&nextBlock); } @@ -333,7 +333,7 @@ struct StmtVisitor { return failure(); if (!isTerminated()) { auto loc = context.convertLocation(item.stmt->sourceRange); - builder.create(loc, &exitBlock); + mlir::cf::BranchOp::create(builder, loc, &exitBlock); } } @@ -385,14 +385,14 @@ struct StmtVisitor { if ((twoStateExhaustive || (hasFullCaseAttr && !caseStmt.defaultCase)) && lastMatchBlock && caseStmt.condition == CaseStatementCondition::Normal) { - builder.create(loc, lastMatchBlock); + mlir::cf::BranchOp::create(builder, loc, lastMatchBlock); } else { // Generate the default case if present. if (caseStmt.defaultCase) if (failed(context.convertStatement(*caseStmt.defaultCase))) return failure(); if (!isTerminated()) - builder.create(loc, &exitBlock); + mlir::cf::BranchOp::create(builder, loc, &exitBlock); } // If control never reaches the exit block, remove it and mark control flow @@ -418,7 +418,7 @@ struct StmtVisitor { auto &stepBlock = createBlock(); auto &bodyBlock = createBlock(); auto &checkBlock = createBlock(); - builder.create(loc, &checkBlock); + cf::BranchOp::create(builder, loc, &checkBlock); // Push the blocks onto the loop stack such that we can continue and break. context.loopStack.push_back({&stepBlock, &exitBlock}); @@ -430,15 +430,15 @@ struct StmtVisitor { if (!cond) return failure(); cond = builder.createOrFold(loc, cond); - cond = builder.create(loc, builder.getI1Type(), cond); - builder.create(loc, cond, &bodyBlock, &exitBlock); + cond = moore::ConversionOp::create(builder, loc, builder.getI1Type(), cond); + cf::CondBranchOp::create(builder, loc, cond, &bodyBlock, &exitBlock); // Generate the loop body. builder.setInsertionPointToEnd(&bodyBlock); if (failed(context.convertStatement(stmt.body))) return failure(); if (!isTerminated()) - builder.create(loc, &stepBlock); + cf::BranchOp::create(builder, loc, &stepBlock); // Generate the step expressions. builder.setInsertionPointToEnd(&stepBlock); @@ -446,7 +446,7 @@ struct StmtVisitor { if (!context.convertRvalueExpression(*stepExpr)) return failure(); if (!isTerminated()) - builder.create(loc, &checkBlock); + cf::BranchOp::create(builder, loc, &checkBlock); // If control never reaches the exit block, remove it and mark control flow // as terminated. Otherwise we continue inserting ops in the exit block. @@ -479,7 +479,7 @@ struct StmtVisitor { auto &bodyBlock = createBlock(); auto &checkBlock = createBlock(); auto currentCount = checkBlock.addArgument(count.getType(), count.getLoc()); - builder.create(loc, &checkBlock, count); + cf::BranchOp::create(builder, loc, &checkBlock, count); // Push the blocks onto the loop stack such that we can continue and break. context.loopStack.push_back({&stepBlock, &exitBlock}); @@ -488,23 +488,23 @@ struct StmtVisitor { // Generate the loop condition check. builder.setInsertionPointToEnd(&checkBlock); auto cond = builder.createOrFold(loc, currentCount); - cond = builder.create(loc, builder.getI1Type(), cond); - builder.create(loc, cond, &bodyBlock, &exitBlock); + cond = moore::ConversionOp::create(builder, loc, builder.getI1Type(), cond); + cf::CondBranchOp::create(builder, loc, cond, &bodyBlock, &exitBlock); // Generate the loop body. builder.setInsertionPointToEnd(&bodyBlock); if (failed(context.convertStatement(stmt.body))) return failure(); if (!isTerminated()) - builder.create(loc, &stepBlock); + cf::BranchOp::create(builder, loc, &stepBlock); // Decrement the current count and branch back to the check block. builder.setInsertionPointToEnd(&stepBlock); - auto one = builder.create( - count.getLoc(), cast(count.getType()), 1); + auto one = moore::ConstantOp::create( + builder, count.getLoc(), cast(count.getType()), 1); Value nextCount = - builder.create(count.getLoc(), currentCount, one); - builder.create(loc, &checkBlock, nextCount); + moore::SubOp::create(builder, count.getLoc(), currentCount, one); + cf::BranchOp::create(builder, loc, &checkBlock, nextCount); // If control never reaches the exit block, remove it and mark control flow // as terminated. Otherwise we continue inserting ops in the exit block. @@ -525,7 +525,7 @@ struct StmtVisitor { auto &exitBlock = createBlock(); auto &bodyBlock = createBlock(); auto &checkBlock = createBlock(); - builder.create(loc, atLeastOnce ? &bodyBlock : &checkBlock); + cf::BranchOp::create(builder, loc, atLeastOnce ? &bodyBlock : &checkBlock); if (atLeastOnce) bodyBlock.moveBefore(&checkBlock); @@ -539,15 +539,15 @@ struct StmtVisitor { if (!cond) return failure(); cond = builder.createOrFold(loc, cond); - cond = builder.create(loc, builder.getI1Type(), cond); - builder.create(loc, cond, &bodyBlock, &exitBlock); + cond = moore::ConversionOp::create(builder, loc, builder.getI1Type(), cond); + cf::CondBranchOp::create(builder, loc, cond, &bodyBlock, &exitBlock); // Generate the loop body. builder.setInsertionPointToEnd(&bodyBlock); if (failed(context.convertStatement(bodyStmt))) return failure(); if (!isTerminated()) - builder.create(loc, &checkBlock); + cf::BranchOp::create(builder, loc, &checkBlock); // If control never reaches the exit block, remove it and mark control flow // as terminated. Otherwise we continue inserting ops in the exit block. @@ -573,7 +573,7 @@ struct StmtVisitor { // Create the blocks for the loop body and exit. auto &exitBlock = createBlock(); auto &bodyBlock = createBlock(); - builder.create(loc, &bodyBlock); + cf::BranchOp::create(builder, loc, &bodyBlock); // Push the blocks onto the loop stack such that we can continue and break. context.loopStack.push_back({&bodyBlock, &exitBlock}); @@ -584,7 +584,7 @@ struct StmtVisitor { if (failed(context.convertStatement(stmt.body))) return failure(); if (!isTerminated()) - builder.create(loc, &bodyBlock); + cf::BranchOp::create(builder, loc, &bodyBlock); // If control never reaches the exit block, remove it and mark control flow // as terminated. Otherwise we continue inserting ops in the exit block. @@ -608,9 +608,9 @@ struct StmtVisitor { auto expr = context.convertRvalueExpression(*stmt.expr); if (!expr) return failure(); - builder.create(loc, expr); + mlir::func::ReturnOp::create(builder, loc, expr); } else { - builder.create(loc); + mlir::func::ReturnOp::create(builder, loc); } setTerminated(); return success(); @@ -621,7 +621,7 @@ struct StmtVisitor { if (context.loopStack.empty()) return mlir::emitError(loc, "cannot `continue` without a surrounding loop"); - builder.create(loc, context.loopStack.back().continueBlock); + cf::BranchOp::create(builder, loc, context.loopStack.back().continueBlock); setTerminated(); return success(); } @@ -630,7 +630,7 @@ struct StmtVisitor { LogicalResult visit(const slang::ast::BreakStatement &stmt) { if (context.loopStack.empty()) return mlir::emitError(loc, "cannot `break` without a surrounding loop"); - builder.create(loc, context.loopStack.back().breakBlock); + cf::BranchOp::create(builder, loc, context.loopStack.back().breakBlock); setTerminated(); return success(); } @@ -652,13 +652,13 @@ struct StmtVisitor { switch (stmt.assertionKind) { case slang::ast::AssertionKind::Assert: - builder.create(loc, defer, cond, StringAttr{}); + moore::AssertOp::create(builder, loc, defer, cond, StringAttr{}); return success(); case slang::ast::AssertionKind::Assume: - builder.create(loc, defer, cond, StringAttr{}); + moore::AssumeOp::create(builder, loc, defer, cond, StringAttr{}); return success(); case slang::ast::AssertionKind::CoverProperty: - builder.create(loc, defer, cond, StringAttr{}); + moore::CoverOp::create(builder, loc, defer, cond, StringAttr{}); return success(); default: break; @@ -669,21 +669,21 @@ struct StmtVisitor { } // Regard assertion statements with an action block as the "if-else". - cond = builder.create(loc, builder.getI1Type(), cond); + cond = moore::ConversionOp::create(builder, loc, builder.getI1Type(), cond); // Create the blocks for the true and false branches, and the exit block. Block &exitBlock = createBlock(); Block *falseBlock = stmt.ifFalse ? &createBlock() : nullptr; Block &trueBlock = createBlock(); - builder.create(loc, cond, &trueBlock, - falseBlock ? falseBlock : &exitBlock); + cf::CondBranchOp::create(builder, loc, cond, &trueBlock, + falseBlock ? falseBlock : &exitBlock); // Generate the true branch. builder.setInsertionPointToEnd(&trueBlock); if (stmt.ifTrue && failed(context.convertStatement(*stmt.ifTrue))) return failure(); if (!isTerminated()) - builder.create(loc, &exitBlock); + cf::BranchOp::create(builder, loc, &exitBlock); if (stmt.ifFalse) { // Generate the false branch if present. @@ -691,7 +691,7 @@ struct StmtVisitor { if (failed(context.convertStatement(*stmt.ifFalse))) return failure(); if (!isTerminated()) - builder.create(loc, &exitBlock); + cf::BranchOp::create(builder, loc, &exitBlock); } // If control never reaches the exit block, remove it and mark control flow @@ -716,10 +716,10 @@ struct StmtVisitor { if (stmt.ifTrue && stmt.ifTrue->as_if()) { switch (stmt.assertionKind) { case slang::ast::AssertionKind::Assert: - builder.create(loc, property, Value(), StringAttr{}); + verif::AssertOp::create(builder, loc, property, Value(), StringAttr{}); return success(); case slang::ast::AssertionKind::Assume: - builder.create(loc, property, Value(), StringAttr{}); + verif::AssumeOp::create(builder, loc, property, Value(), StringAttr{}); return success(); default: break; @@ -749,14 +749,14 @@ struct StmtVisitor { if (subroutine.name == "$stop") { createFinishMessage(args.size() >= 1 ? args[0] : nullptr); - builder.create(loc); + moore::StopBIOp::create(builder, loc); return true; } if (subroutine.name == "$finish") { createFinishMessage(args.size() >= 1 ? args[0] : nullptr); - builder.create(loc, 0); - builder.create(loc); + moore::FinishBIOp::create(builder, loc, 0); + moore::UnreachableOp::create(builder, loc); setTerminated(); return true; } @@ -802,7 +802,7 @@ struct StmtVisitor { return failure(); if (*message == Value{}) return true; - builder.create(loc, *message); + moore::DisplayBIOp::create(builder, loc, *message); return true; } @@ -831,15 +831,15 @@ struct StmtVisitor { if (failed(message)) return failure(); if (*message == Value{}) - *message = builder.create(loc, ""); + *message = moore::FormatLiteralOp::create(builder, loc, ""); - builder.create(loc, *severity, *message); + moore::SeverityBIOp::create(builder, loc, *severity, *message); // Handle the `$fatal` case which behaves like a `$finish`. if (severity == Severity::Fatal) { createFinishMessage(verbosityExpr); - builder.create(loc, 1); - builder.create(loc); + moore::FinishBIOp::create(builder, loc, 1); + moore::UnreachableOp::create(builder, loc); setTerminated(); } return true; @@ -861,7 +861,7 @@ struct StmtVisitor { } if (verbosity == 0) return; - builder.create(loc, verbosity > 1); + moore::FinishMessageBIOp::create(builder, loc, verbosity > 1); } /// Emit an error for all other statements. diff --git a/lib/Conversion/ImportVerilog/Structure.cpp b/lib/Conversion/ImportVerilog/Structure.cpp index fd253ea09c..1038ebb949 100644 --- a/lib/Conversion/ImportVerilog/Structure.cpp +++ b/lib/Conversion/ImportVerilog/Structure.cpp @@ -108,8 +108,8 @@ struct BaseVisitor { guessNamespacePrefix(param.getParentScope()->asSymbol(), paramName); paramName += param.name; - builder.create(loc, builder.getStringAttr(paramName), - value, Value{}); + debug::VariableOp::create(builder, loc, builder.getStringAttr(paramName), + value, Value{}); } }; } // namespace @@ -296,18 +296,19 @@ struct ModuleVisitor : public BaseVisitor { if (const auto *net = port->internalSymbol->as_if()) { - auto netOp = builder.create( - loc, refType, StringAttr::get(builder.getContext(), net->name), + auto netOp = moore::NetOp::create( + builder, loc, refType, + StringAttr::get(builder.getContext(), net->name), convertNetKind(net->netType.netKind), nullptr); - auto readOp = builder.create(loc, netOp); + auto readOp = moore::ReadOp::create(builder, loc, netOp); portValues.insert({port, readOp}); } else if (const auto *var = port->internalSymbol ->as_if()) { - auto varOp = builder.create( - loc, refType, StringAttr::get(builder.getContext(), var->name), - nullptr); - auto readOp = builder.create(loc, varOp); + auto varOp = moore::VariableOp::create( + builder, loc, refType, + StringAttr::get(builder.getContext(), var->name), nullptr); + auto readOp = moore::ReadOp::create(builder, loc, varOp); portValues.insert({port, readOp}); } else { return mlir::emitError(loc) @@ -369,12 +370,13 @@ struct ModuleVisitor : public BaseVisitor { auto sliceType = context.convertType(port->getType()); if (!sliceType) return failure(); - Value slice = builder.create( - loc, moore::RefType::get(cast(sliceType)), - value, offset); + Value slice = moore::ExtractRefOp::create( + builder, loc, + moore::RefType::get(cast(sliceType)), value, + offset); // Create the "ReadOp" for input ports. if (port->direction == ArgumentDirection::In) - slice = builder.create(loc, slice); + slice = moore::ReadOp::create(builder, loc, slice); portValues.insert({port, slice}); offset += width; } @@ -406,7 +408,7 @@ struct ModuleVisitor : public BaseVisitor { llvm::zip(inputValues, moduleType.getInputTypes())) if (value.getType() != type) value = - builder.create(value.getLoc(), type, value); + moore::ConversionOp::create(builder, value.getLoc(), type, value); // Here we use the hierarchical value recorded in `Context::valueSymbols`. // Then we pass it as the input port with the ref type of the instance. @@ -418,8 +420,8 @@ struct ModuleVisitor : public BaseVisitor { // Create the instance op itself. auto inputNames = builder.getArrayAttr(moduleType.getInputNames()); auto outputNames = builder.getArrayAttr(moduleType.getOutputNames()); - auto inst = builder.create( - loc, moduleType.getOutputTypes(), + auto inst = moore::InstanceOp::create( + builder, loc, moduleType.getOutputTypes(), builder.getStringAttr(Twine(blockNamePrefix) + instNode.name), FlatSymbolRefAttr::get(module.getSymNameAttr()), inputValues, inputNames, outputNames); @@ -437,8 +439,8 @@ struct ModuleVisitor : public BaseVisitor { Value rvalue = output; auto dstType = cast(lvalue.getType()).getNestedType(); if (dstType != rvalue.getType()) - rvalue = builder.create(loc, dstType, rvalue); - builder.create(loc, lvalue, rvalue); + rvalue = moore::ConversionOp::create(builder, loc, dstType, rvalue); + moore::ContinuousAssignOp::create(builder, loc, lvalue, rvalue); } return success(); @@ -457,8 +459,9 @@ struct ModuleVisitor : public BaseVisitor { return failure(); } - auto varOp = builder.create( - loc, moore::RefType::get(cast(loweredType)), + auto varOp = moore::VariableOp::create( + builder, loc, + moore::RefType::get(cast(loweredType)), builder.getStringAttr(Twine(blockNamePrefix) + varNode.name), initial); context.valueSymbols.insert(&varNode, varOp); return success(); @@ -484,8 +487,9 @@ struct ModuleVisitor : public BaseVisitor { return mlir::emitError(loc, "unsupported net kind `") << netNode.netType.name << "`"; - auto netOp = builder.create( - loc, moore::RefType::get(cast(loweredType)), + auto netOp = moore::NetOp::create( + builder, loc, + moore::RefType::get(cast(loweredType)), builder.getStringAttr(Twine(blockNamePrefix) + netNode.name), netkind, assignment); context.valueSymbols.insert(&netNode, netOp); @@ -511,21 +515,21 @@ struct ModuleVisitor : public BaseVisitor { if (!rhs) return failure(); - builder.create(loc, lhs, rhs); + moore::ContinuousAssignOp::create(builder, loc, lhs, rhs); return success(); } // Handle procedures. LogicalResult convertProcedure(moore::ProcedureKind kind, const slang::ast::Statement &body) { - auto procOp = builder.create(loc, kind); + auto procOp = moore::ProcedureOp::create(builder, loc, kind); OpBuilder::InsertionGuard guard(builder); builder.setInsertionPointToEnd(&procOp.getBody().emplaceBlock()); Context::ValueSymbolScope scope(context.valueSymbols); if (failed(context.convertStatement(body))) return failure(); if (builder.getBlock()) - builder.create(loc); + moore::ReturnOp::create(builder, loc); return success(); } @@ -835,7 +839,7 @@ Context::convertModuleHeader(const slang::ast::InstanceBodySymbol *module) { // Create an empty module that corresponds to this module. auto moduleOp = - builder.create(loc, module->name, moduleType); + moore::SVModuleOp::create(builder, loc, module->name, moduleType); orderedRootOps.insert(it, {module->location, moduleOp}); moduleOp.getBodyRegion().push_back(block.release()); lowering.op = moduleOp; @@ -900,7 +904,7 @@ Context::convertModuleBody(const slang::ast::InstanceBodySymbol *module) { // Collect output port values to be returned in the terminator. if (port.ast.direction == slang::ast::ArgumentDirection::Out) { if (isa(value.getType())) - value = builder.create(value.getLoc(), value); + value = moore::ReadOp::create(builder, value.getLoc(), value); outputs.push_back(value); continue; } @@ -909,8 +913,8 @@ Context::convertModuleBody(const slang::ast::InstanceBodySymbol *module) { // of that port. Value portArg = port.arg; if (port.ast.direction != slang::ast::ArgumentDirection::In) - portArg = builder.create(port.loc, port.arg); - builder.create(port.loc, value, portArg); + portArg = moore::ReadOp::create(builder, port.loc, port.arg); + moore::ContinuousAssignOp::create(builder, port.loc, value, portArg); } // Ensure the number of operands of this module's terminator and the number of @@ -920,7 +924,7 @@ Context::convertModuleBody(const slang::ast::InstanceBodySymbol *module) { if (hierPath.direction == slang::ast::ArgumentDirection::Out) outputs.push_back(hierValue); - builder.create(lowering.op.getLoc(), outputs); + moore::OutputOp::create(builder, lowering.op.getLoc(), outputs); return success(); } @@ -1000,7 +1004,7 @@ Context::declareFunction(const slang::ast::SubroutineSymbol &subroutine) { funcName += subroutine.name; // Create a function declaration. - auto funcOp = builder.create(loc, funcName, funcType); + auto funcOp = mlir::func::FuncOp::create(builder, loc, funcName, funcType); SymbolTable::setSymbolVisibility(funcOp, SymbolTable::Visibility::Private); orderedRootOps.insert(it, {subroutine.location, funcOp}); lowering->op = funcOp; @@ -1037,8 +1041,8 @@ Context::convertFunction(const slang::ast::SubroutineSymbol &subroutine) { OpBuilder::InsertionGuard g(builder); builder.setInsertionPointToEnd(&block); - auto shadowArg = builder.create( - loc, moore::RefType::get(cast(type)), + auto shadowArg = moore::VariableOp::create( + builder, loc, moore::RefType::get(cast(type)), StringAttr{}, blockArg); valueSymbols.insert(astArg, shadowArg); argVariables.push_back(shadowArg); @@ -1054,8 +1058,8 @@ Context::convertFunction(const slang::ast::SubroutineSymbol &subroutine) { auto type = convertType(*subroutine.returnValVar->getDeclaredType()); if (!type) return failure(); - returnVar = builder.create( - lowering->op.getLoc(), + returnVar = moore::VariableOp::create( + builder, lowering->op.getLoc(), moore::RefType::get(cast(type)), StringAttr{}, Value{}); valueSymbols.insert(subroutine.returnValVar, returnVar); @@ -1068,10 +1072,12 @@ Context::convertFunction(const slang::ast::SubroutineSymbol &subroutine) { // default one. if (builder.getBlock()) { if (returnVar && !subroutine.getReturnType().isVoid()) { - Value read = builder.create(returnVar.getLoc(), returnVar); - builder.create(lowering->op.getLoc(), read); + Value read = + moore::ReadOp::create(builder, returnVar.getLoc(), returnVar); + mlir::func::ReturnOp::create(builder, lowering->op.getLoc(), read); } else { - builder.create(lowering->op.getLoc(), ValueRange{}); + mlir::func::ReturnOp::create(builder, lowering->op.getLoc(), + ValueRange{}); } } if (returnVar && returnVar.use_empty()) diff --git a/lib/Conversion/ImportVerilog/TimingControls.cpp b/lib/Conversion/ImportVerilog/TimingControls.cpp index eb57fc09ca..e8566521cd 100644 --- a/lib/Conversion/ImportVerilog/TimingControls.cpp +++ b/lib/Conversion/ImportVerilog/TimingControls.cpp @@ -67,7 +67,7 @@ struct EventControlVisitor { if (!condition) return failure(); } - builder.create(loc, edge, expr, condition); + moore::DetectEventOp::create(builder, loc, edge, expr, condition); return success(); } @@ -125,7 +125,7 @@ struct LTLClockControlVisitor { expr = context.convertToI1(expr); if (!expr) return Value{}; - return builder.create(loc, seqOrPro, edge, expr); + return ltl::ClockOp::create(builder, loc, seqOrPro, edge, expr); } template @@ -168,13 +168,13 @@ static LogicalResult handleRoot(Context &context, // empty wait op and let `Context::convertTimingControl` populate it once // the statement has been lowered. case TimingControlKind::ImplicitEvent: - implicitWaitOp = builder.create(loc); + implicitWaitOp = moore::WaitEventOp::create(builder, loc); return success(); // Handle event control. case TimingControlKind::SignalEvent: case TimingControlKind::EventList: { - auto waitOp = builder.create(loc); + auto waitOp = moore::WaitEventOp::create(builder, loc); OpBuilder::InsertionGuard guard(builder); builder.setInsertionPointToStart(&waitOp.getBody().emplaceBlock()); EventControlVisitor visitor{context, loc, builder}; @@ -242,9 +242,9 @@ Context::convertTimingControl(const slang::ast::TimingControl &ctrl, builder.setInsertionPointToStart(&implicitWaitOp.getBody().emplaceBlock()); for (auto readValue : readValues) { auto value = - builder.create(implicitWaitOp.getLoc(), readValue); - builder.create( - implicitWaitOp.getLoc(), moore::Edge::AnyChange, value, Value{}); + moore::ReadOp::create(builder, implicitWaitOp.getLoc(), readValue); + moore::DetectEventOp::create(builder, implicitWaitOp.getLoc(), + moore::Edge::AnyChange, value, Value{}); } } diff --git a/lib/Conversion/LTLToCore/LTLToCore.cpp b/lib/Conversion/LTLToCore/LTLToCore.cpp index b09de727b4..229be7c182 100644 --- a/lib/Conversion/LTLToCore/LTLToCore.cpp +++ b/lib/Conversion/LTLToCore/LTLToCore.cpp @@ -57,7 +57,7 @@ struct HasBeenResetOpConversion : OpConversionPattern { rewriter, op->getLoc(), rewriter.getIntegerAttr(i1, 0)); // Generate the constant used to negate the reset value - Value constOne = rewriter.create(op.getLoc(), i1, 1); + Value constOne = hw::ConstantOp::create(rewriter, op.getLoc(), i1, 1); // Create a backedge for the register to be used in the OrOp circt::BackedgeBuilder bb(rewriter, op.getLoc()); @@ -66,15 +66,15 @@ struct HasBeenResetOpConversion : OpConversionPattern { // Generate an or between the reset and the register's value to store // whether or not the reset has been active at least once Value orReset = - rewriter.create(op.getLoc(), adaptor.getReset(), reg); + comb::OrOp::create(rewriter, op.getLoc(), adaptor.getReset(), reg); // This register should not be reset, so we give it dummy reset and resetval // operands to fit the build signature Value reset, resetval; // Finally generate the register to set the backedge - reg.setValue(rewriter.create( - op.getLoc(), orReset, + reg.setValue(seq::CompRegOp::create( + rewriter, op.getLoc(), orReset, rewriter.createOrFold(op.getLoc(), adaptor.getClock()), rewriter.getStringAttr("hbr"), reset, resetval, constZero, InnerSymAttr{} // inner_sym @@ -83,8 +83,8 @@ struct HasBeenResetOpConversion : OpConversionPattern { // We also need to consider the case where we are currently in a reset cycle // in which case our hbr register should be down- // Practically this means converting it to (and hbr (not reset)) - Value notReset = - rewriter.create(op.getLoc(), adaptor.getReset(), constOne); + Value notReset = comb::XorOp::create(rewriter, op.getLoc(), + adaptor.getReset(), constOne); rewriter.replaceOpWithNewOp(op, reg, notReset); return success(); @@ -137,8 +137,8 @@ void LowerLTLToCorePass::runOnOperation() { mlir::ValueRange inputs, mlir::Location loc) -> mlir::Value { if (inputs.size() != 1) return Value(); - return builder - .create(loc, resultType, inputs[0]) + return UnrealizedConversionCastOp::create(builder, loc, resultType, + inputs[0]) ->getResult(0); }); @@ -147,8 +147,8 @@ void LowerLTLToCorePass::runOnOperation() { mlir::ValueRange inputs, mlir::Location loc) -> mlir::Value { if (inputs.size() != 1) return Value(); - return builder - .create(loc, resultType, inputs[0]) + return UnrealizedConversionCastOp::create(builder, loc, resultType, + inputs[0]) ->getResult(0); }); diff --git a/lib/Conversion/LoopScheduleToCalyx/LoopScheduleToCalyx.cpp b/lib/Conversion/LoopScheduleToCalyx/LoopScheduleToCalyx.cpp index c97d65eed6..21ceaf7c71 100644 --- a/lib/Conversion/LoopScheduleToCalyx/LoopScheduleToCalyx.cpp +++ b/lib/Conversion/LoopScheduleToCalyx/LoopScheduleToCalyx.cpp @@ -160,11 +160,11 @@ public: auto stages = pipelinePrologue[op]; for (size_t i = 0, e = stages.size(); i < e; ++i) { PatternRewriter::InsertionGuard g(rewriter); - auto parOp = rewriter.create(op->getLoc()); + auto parOp = calyx::ParOp::create(rewriter, op->getLoc()); rewriter.setInsertionPointToStart(parOp.getBodyBlock()); for (size_t j = 0; j < i + 1; ++j) for (auto group : stages[j]) - rewriter.create(op->getLoc(), group); + calyx::EnableOp::create(rewriter, op->getLoc(), group); } } @@ -173,11 +173,11 @@ public: auto stages = pipelineEpilogue[op]; for (size_t i = 0, e = stages.size(); i < e; ++i) { PatternRewriter::InsertionGuard g(rewriter); - auto parOp = rewriter.create(op->getLoc()); + auto parOp = calyx::ParOp::create(rewriter, op->getLoc()); rewriter.setInsertionPointToStart(parOp.getBodyBlock()); for (size_t j = i, f = stages.size(); j < f; ++j) for (auto group : stages[j]) - rewriter.create(op->getLoc(), group); + calyx::EnableOp::create(rewriter, op->getLoc(), group); } } @@ -326,7 +326,7 @@ private: getState().getPipelineRegister(srcOp); if (pipelineRegister.has_value()) srcOp = pipelineRegister->getOut(); - rewriter.create(op.getLoc(), dstOp.value(), srcOp); + calyx::AssignOp::create(rewriter, op.getLoc(), dstOp.value(), srcOp); } /// Replace the result values of the source operator with the new operator. @@ -376,17 +376,17 @@ private: group); rewriter.setInsertionPointToEnd(group.getBodyBlock()); - rewriter.create(loc, opPipe.getLeft(), op.getLhs()); - rewriter.create(loc, opPipe.getRight(), op.getRhs()); + calyx::AssignOp::create(rewriter, loc, opPipe.getLeft(), op.getLhs()); + calyx::AssignOp::create(rewriter, loc, opPipe.getRight(), op.getRhs()); // Write the output to this register. - rewriter.create(loc, reg.getIn(), out); + calyx::AssignOp::create(rewriter, loc, reg.getIn(), out); // The write enable port is high when the pipeline is done. - rewriter.create(loc, reg.getWriteEn(), opPipe.getDone()); - rewriter.create( - loc, opPipe.getGo(), + calyx::AssignOp::create(rewriter, loc, reg.getWriteEn(), opPipe.getDone()); + calyx::AssignOp::create( + rewriter, loc, opPipe.getGo(), createConstant(loc, rewriter, getComponent(), 1, 1)); // The group is done when the register write is complete. - rewriter.create(loc, reg.getDone()); + calyx::GroupDoneOp::create(rewriter, loc, reg.getDone()); // Register the values for the pipeline. getState().registerEvaluatingGroup(out, group); @@ -413,16 +413,16 @@ private: "We expected a 1 dimensional memory of size 1 because there were no " "address assignment values"); // Assign 1'd0 to the address port. - rewriter.create( - loc, addrPorts[0], + calyx::AssignOp::create( + rewriter, loc, addrPorts[0], createConstant(loc, rewriter, getComponent(), 1, 0)); } else { assert(addrPorts.size() == addressValues.size() && "Mismatch between number of address ports of the provided memory " "and address assignment values"); for (auto address : enumerate(addressValues)) - rewriter.create(loc, addrPorts[address.index()], - address.value()); + calyx::AssignOp::create(rewriter, loc, addrPorts[address.index()], + address.value()); } } }; @@ -494,18 +494,20 @@ LogicalResult BuildOpGroups::buildOp(PatternRewriter &rewriter, assignAddressPorts(rewriter, storeOp.getLoc(), group, memoryInterface, storeOp.getIndices()); rewriter.setInsertionPointToEnd(group.getBodyBlock()); - rewriter.create( - storeOp.getLoc(), memoryInterface.writeData(), storeOp.getValueToStore()); - rewriter.create( - storeOp.getLoc(), memoryInterface.writeEn(), + calyx::AssignOp::create(rewriter, storeOp.getLoc(), + memoryInterface.writeData(), + storeOp.getValueToStore()); + calyx::AssignOp::create( + rewriter, storeOp.getLoc(), memoryInterface.writeEn(), createConstant(storeOp.getLoc(), rewriter, getComponent(), 1, 1)); if (memoryInterface.contentEnOpt().has_value()) { // If memory has content enable, it must be asserted when writing - rewriter.create( - storeOp.getLoc(), memoryInterface.contentEn(), + calyx::AssignOp::create( + rewriter, storeOp.getLoc(), memoryInterface.contentEn(), createConstant(storeOp.getLoc(), rewriter, getComponent(), 1, 1)); } - rewriter.create(storeOp.getLoc(), memoryInterface.done()); + calyx::GroupDoneOp::create(rewriter, storeOp.getLoc(), + memoryInterface.done()); getState().registerNonPipelineOperations(storeOp, group); @@ -570,8 +572,8 @@ static LogicalResult buildAllocOp(ComponentLoweringState &componentState, sizes.push_back(1); addrSizes.push_back(1); } - auto memoryOp = rewriter.create( - allocOp.getLoc(), componentState.getUniqueName("mem"), + auto memoryOp = calyx::MemoryOp::create( + rewriter, allocOp.getLoc(), componentState.getUniqueName("mem"), memtype.getElementType().getIntOrFloatBitWidth(), sizes, addrSizes); // Externalize memories by default. This makes it easier for the native // compiler to provide initialized memories. @@ -832,8 +834,9 @@ struct FuncOpConversion : public calyx::FuncOpPartialLoweringPattern { calyx::addMandatoryComponentPorts(rewriter, ports); /// Create a calyx::ComponentOp corresponding to the to-be-lowered function. - auto compOp = rewriter.create( - funcOp.getLoc(), rewriter.getStringAttr(funcOp.getSymName()), ports); + auto compOp = calyx::ComponentOp::create( + rewriter, funcOp.getLoc(), rewriter.getStringAttr(funcOp.getSymName()), + ports); /// Mark this component as the toplevel. compOp->setAttr("toplevel", rewriter.getUnitAttr()); @@ -1139,8 +1142,8 @@ class BuildPipelineGroups : public calyx::FuncOpPartialLoweringPattern { // Create a sequential group and replace the comb group. PatternRewriter::InsertionGuard g(rewriter); rewriter.setInsertionPoint(combGroup); - auto group = rewriter.create(combGroup.getLoc(), - combGroup.getName()); + auto group = calyx::GroupOp::create(rewriter, combGroup.getLoc(), + combGroup.getName()); rewriter.cloneRegionBefore(combGroup.getBodyRegion(), &group.getBody().front()); group.getBodyRegion().back().erase(); @@ -1202,7 +1205,7 @@ class BuildControl : public calyx::FuncOpPartialLoweringPattern { auto *entryBlock = &funcOp.getBlocks().front(); rewriter.setInsertionPointToStart( getComponent().getControlOp().getBodyBlock()); - auto topLevelSeqOp = rewriter.create(funcOp.getLoc()); + auto topLevelSeqOp = calyx::SeqOp::create(rewriter, funcOp.getLoc()); DenseSet path; return buildCFGControl(path, rewriter, topLevelSeqOp.getBodyBlock(), nullptr, entryBlock); @@ -1220,15 +1223,15 @@ private: auto loc = block->front().getLoc(); if (compBlockScheduleables.size() > 1) { - auto seqOp = rewriter.create(loc); + auto seqOp = calyx::SeqOp::create(rewriter, loc); parentCtrlBlock = seqOp.getBodyBlock(); } for (auto &group : compBlockScheduleables) { rewriter.setInsertionPointToEnd(parentCtrlBlock); if (auto groupPtr = std::get_if(&group); groupPtr) { - rewriter.create(groupPtr->getLoc(), - groupPtr->getSymName()); + calyx::EnableOp::create(rewriter, groupPtr->getLoc(), + groupPtr->getSymName()); } else if (auto *pipeSchedPtr = std::get_if(&group); pipeSchedPtr) { auto &whileOp = pipeSchedPtr->whileOp; @@ -1237,7 +1240,7 @@ private: buildWhileCtrlOp(whileOp, pipeSchedPtr->initGroups, rewriter); rewriter.setInsertionPointToEnd(whileCtrlOp.getBodyBlock()); auto whileBodyOp = - rewriter.create(whileOp.getOperation()->getLoc()); + calyx::ParOp::create(rewriter, whileOp.getOperation()->getLoc()); rewriter.setInsertionPointToEnd(whileBodyOp.getBodyBlock()); /// Schedule pipeline stages in the parallel group directly. @@ -1246,8 +1249,8 @@ private: whileOp.getBodyBlock()); for (auto &group : bodyBlockScheduleables) if (auto *groupPtr = std::get_if(&group); groupPtr) - rewriter.create(groupPtr->getLoc(), - groupPtr->getSymName()); + calyx::EnableOp::create(rewriter, groupPtr->getLoc(), + groupPtr->getSymName()); else return whileOp.getOperation()->emitError( "Unsupported block schedulable"); @@ -1278,11 +1281,11 @@ private: /// Schedule any registered block arguments to be executed before the body /// of the branch. rewriter.setInsertionPointToEnd(parentCtrlBlock); - auto preSeqOp = rewriter.create(loc); + auto preSeqOp = calyx::SeqOp::create(rewriter, loc); rewriter.setInsertionPointToEnd(preSeqOp.getBodyBlock()); for (auto barg : getState().getBlockArgGroups(from, to)) - rewriter.create(barg.getLoc(), barg.getSymName()); + calyx::EnableOp::create(rewriter, barg.getLoc(), barg.getSymName()); return buildCFGControl(path, rewriter, parentCtrlBlock, from, to); } @@ -1322,12 +1325,13 @@ private: auto symbolAttr = FlatSymbolRefAttr::get( StringAttr::get(getContext(), condGroup.getSymName())); - auto ifOp = rewriter.create( - brOp->getLoc(), cond, symbolAttr, /*initializeElseBody=*/true); + auto ifOp = + calyx::IfOp::create(rewriter, brOp->getLoc(), cond, symbolAttr, + /*initializeElseBody=*/true); rewriter.setInsertionPointToStart(ifOp.getThenBody()); - auto thenSeqOp = rewriter.create(brOp.getLoc()); + auto thenSeqOp = calyx::SeqOp::create(rewriter, brOp.getLoc()); rewriter.setInsertionPointToStart(ifOp.getElseBody()); - auto elseSeqOp = rewriter.create(brOp.getLoc()); + auto elseSeqOp = calyx::SeqOp::create(rewriter, brOp.getLoc()); bool trueBrSchedSuccess = schedulePath(rewriter, path, brOp.getLoc(), block, successors[0], @@ -1359,10 +1363,10 @@ private: /// parallel group to assign one or more registers all at once. { PatternRewriter::InsertionGuard g(rewriter); - auto parOp = rewriter.create(loc); + auto parOp = calyx::ParOp::create(rewriter, loc); rewriter.setInsertionPointToStart(parOp.getBodyBlock()); for (calyx::GroupOp group : initGroups) - rewriter.create(group.getLoc(), group.getName()); + calyx::EnableOp::create(rewriter, group.getLoc(), group.getName()); } /// Insert the while op itself. @@ -1371,7 +1375,7 @@ private: .getEvaluatingGroup(cond); auto symbolAttr = FlatSymbolRefAttr::get( StringAttr::get(getContext(), condGroup.getSymName())); - auto whileCtrlOp = rewriter.create(loc, cond, symbolAttr); + auto whileCtrlOp = calyx::WhileOp::create(rewriter, loc, cond, symbolAttr); /// If a bound was specified, add it. if (auto bound = whileOp.getBound()) { diff --git a/lib/Conversion/MooreToCore/MooreToCore.cpp b/lib/Conversion/MooreToCore/MooreToCore.cpp index cc4c1eb679..6359864d2a 100644 --- a/lib/Conversion/MooreToCore/MooreToCore.cpp +++ b/lib/Conversion/MooreToCore/MooreToCore.cpp @@ -58,21 +58,21 @@ static Value adjustIntegerWidth(OpBuilder &builder, Value value, return value; if (intWidth < targetWidth) { - Value zeroExt = builder.create( - loc, builder.getIntegerType(targetWidth - intWidth), 0); - return builder.create(loc, ValueRange{zeroExt, value}); + Value zeroExt = hw::ConstantOp::create( + builder, loc, builder.getIntegerType(targetWidth - intWidth), 0); + return comb::ConcatOp::create(builder, loc, ValueRange{zeroExt, value}); } - Value hi = builder.create(loc, value, targetWidth, - intWidth - targetWidth); - Value zero = builder.create( - loc, builder.getIntegerType(intWidth - targetWidth), 0); - Value isZero = builder.create(loc, comb::ICmpPredicate::eq, hi, - zero, false); - Value lo = builder.create(loc, value, 0, targetWidth); - Value max = builder.create( - loc, builder.getIntegerType(targetWidth), -1); - return builder.create(loc, isZero, lo, max, false); + Value hi = comb::ExtractOp::create(builder, loc, value, targetWidth, + intWidth - targetWidth); + Value zero = hw::ConstantOp::create( + builder, loc, builder.getIntegerType(intWidth - targetWidth), 0); + Value isZero = comb::ICmpOp::create(builder, loc, comb::ICmpPredicate::eq, hi, + zero, false); + Value lo = comb::ExtractOp::create(builder, loc, value, 0, targetWidth); + Value max = hw::ConstantOp::create(builder, loc, + builder.getIntegerType(targetWidth), -1); + return comb::MuxOp::create(builder, loc, isZero, lo, max, false); } /// Get the ModulePortInfo from a SVModuleOp. @@ -125,8 +125,8 @@ struct SVModuleOpConversion : public OpConversionPattern { // Create the hw.module to replace moore.module auto hwModuleOp = - rewriter.create(op.getLoc(), op.getSymNameAttr(), - getModulePortInfo(*typeConverter, op)); + hw::HWModuleOp::create(rewriter, op.getLoc(), op.getSymNameAttr(), + getModulePortInfo(*typeConverter, op)); // Make hw.module have the same visibility as the moore.module. // The entry/top level module is public, otherwise is private. SymbolTable::setSymbolVisibility(hwModuleOp, @@ -166,9 +166,9 @@ struct InstanceOpConversion : public OpConversionPattern { // Create the new hw instanceOp to replace the original one. rewriter.setInsertionPoint(op); - auto instOp = rewriter.create( - op.getLoc(), op.getResultTypes(), instName, moduleName, op.getInputs(), - op.getInputNamesAttr(), op.getOutputNamesAttr(), + auto instOp = hw::InstanceOp::create( + rewriter, op.getLoc(), op.getResultTypes(), instName, moduleName, + op.getInputs(), op.getInputNamesAttr(), op.getOutputNamesAttr(), /*Parameter*/ rewriter.getArrayAttr({}), /*InnerSymbol*/ nullptr, /*doNotPrint*/ nullptr); @@ -190,7 +190,7 @@ static void getValuesToObserve(Region *region, auto probeIfSignal = [&](Value value) -> Value { if (!isa(value.getType())) return value; - return rewriter.create(loc, value); + return llhd::PrbOp::create(rewriter, loc, value); }; region->getParentOp()->walk>( @@ -249,9 +249,9 @@ struct ProcedureOpConversion : public OpConversionPattern { op.getKind() == ProcedureKind::Final) { Operation *newOp; if (op.getKind() == ProcedureKind::Initial) - newOp = rewriter.create(loc, TypeRange{}); + newOp = llhd::ProcessOp::create(rewriter, loc, TypeRange{}); else - newOp = rewriter.create(loc); + newOp = llhd::FinalOp::create(rewriter, loc); auto &body = newOp->getRegion(0); rewriter.inlineRegionBefore(op.getBody(), body, body.end()); for (auto returnOp : @@ -264,14 +264,14 @@ struct ProcedureOpConversion : public OpConversionPattern { } // All other procedures lower to a an `llhd.process`. - auto newOp = rewriter.create(loc, TypeRange{}); + auto newOp = llhd::ProcessOp::create(rewriter, loc, TypeRange{}); // We need to add an empty entry block because it is not allowed in MLIR to // branch back to the entry block. Instead we put the logic in the second // block and branch to that. rewriter.createBlock(&newOp.getBody()); auto *block = &op.getBody().front(); - rewriter.create(loc, block); + cf::BranchOp::create(rewriter, loc, block); rewriter.inlineRegionBefore(op.getBody(), newOp.getBody(), newOp.getBody().end()); @@ -284,8 +284,8 @@ struct ProcedureOpConversion : public OpConversionPattern { if (op.getKind() == ProcedureKind::AlwaysComb || op.getKind() == ProcedureKind::AlwaysLatch) { Block *waitBlock = rewriter.createBlock(&newOp.getBody()); - rewriter.create(loc, ValueRange{}, Value(), observedValues, - ValueRange{}, block); + llhd::WaitOp::create(rewriter, loc, ValueRange{}, Value(), observedValues, + ValueRange{}, block); block = waitBlock; } @@ -294,7 +294,7 @@ struct ProcedureOpConversion : public OpConversionPattern { // `always_latch` procedures. for (auto returnOp : llvm::make_early_inc_range(newOp.getOps())) { rewriter.setInsertionPoint(returnOp); - rewriter.create(loc, block); + cf::BranchOp::create(rewriter, loc, block); rewriter.eraseOp(returnOp); } @@ -360,7 +360,7 @@ struct WaitEventOpConversion : public OpConversionPattern { auto loc = op.getLoc(); rewriter.setInsertionPoint(op); - rewriter.create(loc, waitBlock); + cf::BranchOp::create(rewriter, loc, waitBlock); // We need to inline two copies of the `wait_event`'s body region: one is // used to determine the values going into `detect_event` ops before the @@ -399,8 +399,8 @@ struct WaitEventOpConversion : public OpConversionPattern { // Create the `llhd.wait` op that suspends the current process and waits for // a change in the interesting values listed in `observeValues`. When a // change is detected, execution resumes in the "check" block. - auto waitOp = rewriter.create( - loc, ValueRange{}, Value(), observeValues, ValueRange{}, checkBlock); + auto waitOp = llhd::WaitOp::create(rewriter, loc, ValueRange{}, Value(), + observeValues, ValueRange{}, checkBlock); rewriter.inlineBlockBefore(&clonedOp.getBody().front(), waitOp); rewriter.eraseOp(clonedOp); @@ -425,8 +425,8 @@ struct WaitEventOpConversion : public OpConversionPattern { beforeType = IntType::get(rewriter.getContext(), 1, beforeType.getDomain()); before = - rewriter.create(loc, beforeType, before, LSB); - after = rewriter.create(loc, beforeType, after, LSB); + moore::ExtractOp::create(rewriter, loc, beforeType, before, LSB); + after = moore::ExtractOp::create(rewriter, loc, beforeType, after, LSB); } auto intType = rewriter.getIntegerType(beforeType.getWidth()); @@ -436,25 +436,25 @@ struct WaitEventOpConversion : public OpConversionPattern { after); if (edge == Edge::AnyChange) - return rewriter.create(loc, ICmpPredicate::ne, before, - after, true); + return comb::ICmpOp::create(rewriter, loc, ICmpPredicate::ne, before, + after, true); SmallVector disjuncts; - Value trueVal = rewriter.create(loc, APInt(1, 1)); + Value trueVal = hw::ConstantOp::create(rewriter, loc, APInt(1, 1)); if (edge == Edge::PosEdge || edge == Edge::BothEdges) { Value notOldVal = - rewriter.create(loc, before, trueVal, true); + comb::XorOp::create(rewriter, loc, before, trueVal, true); Value posedge = - rewriter.create(loc, notOldVal, after, true); + comb::AndOp::create(rewriter, loc, notOldVal, after, true); disjuncts.push_back(posedge); } if (edge == Edge::NegEdge || edge == Edge::BothEdges) { Value notCurrVal = - rewriter.create(loc, after, trueVal, true); + comb::XorOp::create(rewriter, loc, after, trueVal, true); Value posedge = - rewriter.create(loc, before, notCurrVal, true); + comb::AndOp::create(rewriter, loc, before, notCurrVal, true); disjuncts.push_back(posedge); } @@ -477,7 +477,8 @@ struct WaitEventOpConversion : public OpConversionPattern { if (detectOp.getCondition()) { auto condition = typeConverter->materializeTargetConversion( rewriter, loc, rewriter.getI1Type(), detectOp.getCondition()); - trigger = rewriter.create(loc, trigger, condition, true); + trigger = + comb::AndOp::create(rewriter, loc, trigger, condition, true); } triggers.push_back(trigger); } @@ -491,14 +492,15 @@ struct WaitEventOpConversion : public OpConversionPattern { // block. If there are no detect_event operations in the wait event, the // 'llhd.wait' operation will not have any observed values and thus the // process will hang there forever. - rewriter.create(loc, resumeBlock); + cf::BranchOp::create(rewriter, loc, resumeBlock); } else { // If any `detect_event` op detected an event, branch to the "resume" // block which contains any code after the `wait_event` op. If no events // were detected, branch back to the "wait" block to wait for the next // change on the interesting signals. auto triggered = rewriter.createOrFold(loc, triggers, true); - rewriter.create(loc, triggered, resumeBlock, waitBlock); + cf::CondBranchOp::create(rewriter, loc, triggered, resumeBlock, + waitBlock); } return success(); @@ -531,7 +533,7 @@ struct VariableOpConversion : public OpConversionPattern { // TODO: Once the core dialects support four-valued integers, this code // will additionally need to generate an all-X value for four-valued // variables. - Value constZero = rewriter.create(loc, APInt(width, 0)); + Value constZero = hw::ConstantOp::create(rewriter, loc, APInt(width, 0)); init = rewriter.createOrFold(loc, elementType, constZero); } @@ -561,7 +563,7 @@ struct NetOpConversion : public OpConversionPattern { int64_t width = hw::getBitWidth(elementType); if (width == -1) return failure(); - auto constZero = rewriter.create(loc, APInt(width, 0)); + auto constZero = hw::ConstantOp::create(rewriter, loc, APInt(width, 0)); auto init = rewriter.createOrFold(loc, elementType, constZero); @@ -571,8 +573,8 @@ struct NetOpConversion : public OpConversionPattern { if (auto assignedValue = adaptor.getAssignment()) { auto timeAttr = llhd::TimeAttr::get(resultType.getContext(), 0U, llvm::StringRef("ns"), 0, 1); - auto time = rewriter.create(loc, timeAttr); - rewriter.create(loc, signal, assignedValue, time, Value{}); + auto time = llhd::ConstantTimeOp::create(rewriter, loc, timeAttr); + llhd::DrvOp::create(rewriter, loc, signal, assignedValue, time, Value{}); } return success(); @@ -668,8 +670,8 @@ struct ExtractOpConversion : public OpConversionPattern { SmallVector toConcat; if (low < 0) - toConcat.push_back(rewriter.create( - op.getLoc(), APInt(std::min(-low, resultWidth), 0))); + toConcat.push_back(hw::ConstantOp::create( + rewriter, op.getLoc(), APInt(std::min(-low, resultWidth), 0))); if (low < inputWidth && high > 0) { int32_t lowIdx = std::max(low, 0); @@ -684,7 +686,7 @@ struct ExtractOpConversion : public OpConversionPattern { int32_t diff = high - inputWidth; if (diff > 0) { Value val = - rewriter.create(op.getLoc(), APInt(diff, 0)); + hw::ConstantOp::create(rewriter, op.getLoc(), APInt(diff, 0)); toConcat.push_back(val); } @@ -708,8 +710,8 @@ struct ExtractOpConversion : public OpConversionPattern { SmallVector toConcat; if (low < 0) { - Value val = rewriter.create( - op.getLoc(), + Value val = hw::ConstantOp::create( + rewriter, op.getLoc(), APInt(std::min((-low) * elementWidth, resWidth * elementWidth), 0)); Value res = rewriter.createOrFold( @@ -720,8 +722,8 @@ struct ExtractOpConversion : public OpConversionPattern { if (low < inputWidth && high > 0) { int32_t lowIdx = std::max(0, low); - Value lowIdxVal = rewriter.create( - op.getLoc(), rewriter.getIntegerType(width), lowIdx); + Value lowIdxVal = hw::ConstantOp::create( + rewriter, op.getLoc(), rewriter.getIntegerType(width), lowIdx); Value middle = rewriter.createOrFold( op.getLoc(), hw::ArrayType::get( @@ -733,11 +735,11 @@ struct ExtractOpConversion : public OpConversionPattern { int32_t diff = high - inputWidth; if (diff > 0) { - Value constZero = rewriter.create( - op.getLoc(), APInt(diff * elementWidth, 0)); - Value val = rewriter.create( - op.getLoc(), hw::ArrayType::get(arrTy.getElementType(), diff), - constZero); + Value constZero = hw::ConstantOp::create( + rewriter, op.getLoc(), APInt(diff * elementWidth, 0)); + Value val = hw::BitcastOp::create( + rewriter, op.getLoc(), + hw::ArrayType::get(arrTy.getElementType(), diff), constZero); toConcat.push_back(val); } @@ -753,15 +755,16 @@ struct ExtractOpConversion : public OpConversionPattern { if (bw < 0) return failure(); - Value val = rewriter.create(op.getLoc(), APInt(bw, 0)); + Value val = hw::ConstantOp::create(rewriter, op.getLoc(), APInt(bw, 0)); Value bitcast = rewriter.createOrFold(op.getLoc(), resultType, val); rewriter.replaceOp(op, bitcast); return success(); } - Value idx = rewriter.create( - op.getLoc(), rewriter.getIntegerType(width), adaptor.getLowBit()); + Value idx = hw::ConstantOp::create(rewriter, op.getLoc(), + rewriter.getIntegerType(width), + adaptor.getLowBit()); rewriter.replaceOpWithNewOp(op, adaptor.getInput(), idx); return success(); } @@ -786,8 +789,9 @@ struct ExtractRefOpConversion : public OpConversionPattern { if (width == -1) return failure(); - Value lowBit = rewriter.create( - op.getLoc(), rewriter.getIntegerType(llvm::Log2_64_Ceil(width)), + Value lowBit = hw::ConstantOp::create( + rewriter, op.getLoc(), + rewriter.getIntegerType(llvm::Log2_64_Ceil(width)), adaptor.getLowBit()); rewriter.replaceOpWithNewOp( op, resultType, adaptor.getInput(), lowBit); @@ -795,8 +799,8 @@ struct ExtractRefOpConversion : public OpConversionPattern { } if (auto arrType = dyn_cast(inputType)) { - Value lowBit = rewriter.create( - op.getLoc(), + Value lowBit = hw::ConstantOp::create( + rewriter, op.getLoc(), rewriter.getIntegerType(llvm::Log2_64_Ceil(arrType.getNumElements())), adaptor.getLowBit()); @@ -828,8 +832,8 @@ struct DynExtractOpConversion : public OpConversionPattern { if (auto intType = dyn_cast(inputType)) { Value amount = adjustIntegerWidth(rewriter, adaptor.getLowBit(), intType.getWidth(), op->getLoc()); - Value value = rewriter.create(op->getLoc(), - adaptor.getInput(), amount); + Value value = comb::ShrUOp::create(rewriter, op->getLoc(), + adaptor.getInput(), amount); rewriter.replaceOpWithNewOp(op, resultType, value, 0); return success(); @@ -956,7 +960,7 @@ struct ReduceAndOpConversion : public OpConversionPattern { matchAndRewrite(ReduceAndOp op, OpAdaptor adaptor, ConversionPatternRewriter &rewriter) const override { Type resultType = typeConverter->convertType(op.getInput().getType()); - Value max = rewriter.create(op->getLoc(), resultType, -1); + Value max = hw::ConstantOp::create(rewriter, op->getLoc(), resultType, -1); rewriter.replaceOpWithNewOp(op, comb::ICmpPredicate::eq, adaptor.getInput(), max); @@ -970,7 +974,7 @@ struct ReduceOrOpConversion : public OpConversionPattern { matchAndRewrite(ReduceOrOp op, OpAdaptor adaptor, ConversionPatternRewriter &rewriter) const override { Type resultType = typeConverter->convertType(op.getInput().getType()); - Value zero = rewriter.create(op->getLoc(), resultType, 0); + Value zero = hw::ConstantOp::create(rewriter, op->getLoc(), resultType, 0); rewriter.replaceOpWithNewOp(op, comb::ICmpPredicate::ne, adaptor.getInput(), zero); @@ -996,7 +1000,8 @@ struct BoolCastOpConversion : public OpConversionPattern { ConversionPatternRewriter &rewriter) const override { Type resultType = typeConverter->convertType(op.getInput().getType()); if (isa_and_nonnull(resultType)) { - Value zero = rewriter.create(op->getLoc(), resultType, 0); + Value zero = + hw::ConstantOp::create(rewriter, op->getLoc(), resultType, 0); rewriter.replaceOpWithNewOp(op, comb::ICmpPredicate::ne, adaptor.getInput(), zero); return success(); @@ -1012,7 +1017,7 @@ struct NotOpConversion : public OpConversionPattern { ConversionPatternRewriter &rewriter) const override { Type resultType = ConversionPattern::typeConverter->convertType(op.getResult().getType()); - Value max = rewriter.create(op.getLoc(), resultType, -1); + Value max = hw::ConstantOp::create(rewriter, op.getLoc(), resultType, -1); rewriter.replaceOpWithNewOp(op, adaptor.getInput(), max); return success(); @@ -1026,7 +1031,7 @@ struct NegOpConversion : public OpConversionPattern { ConversionPatternRewriter &rewriter) const override { Type resultType = ConversionPattern::typeConverter->convertType(op.getResult().getType()); - Value zero = rewriter.create(op.getLoc(), resultType, 0); + Value zero = hw::ConstantOp::create(rewriter, op.getLoc(), resultType, 0); rewriter.replaceOpWithNewOp(op, zero, adaptor.getInput()); return success(); @@ -1098,7 +1103,7 @@ struct CaseXZEqOpConversion : public OpConversionPattern { Value rhs = adaptor.getRhs(); if (!ignoredBits.isZero()) { ignoredBits.flipAllBits(); - auto maskOp = rewriter.create(op.getLoc(), ignoredBits); + auto maskOp = hw::ConstantOp::create(rewriter, op.getLoc(), ignoredBits); lhs = rewriter.createOrFold(op.getLoc(), lhs, maskOp); rhs = rewriter.createOrFold(op.getLoc(), rhs, maskOp); } @@ -1157,8 +1162,9 @@ struct ZExtOpConversion : public OpConversionPattern { auto targetWidth = op.getType().getWidth(); auto inputWidth = op.getInput().getType().getWidth(); - auto zeroExt = rewriter.create( - op.getLoc(), rewriter.getIntegerType(targetWidth - inputWidth), 0); + auto zeroExt = hw::ConstantOp::create( + rewriter, op.getLoc(), + rewriter.getIntegerType(targetWidth - inputWidth), 0); rewriter.replaceOpWithNewOp( op, ValueRange{zeroExt, adaptor.getInput()}); @@ -1326,14 +1332,14 @@ struct PowUOpConversion : public OpConversionPattern { Location loc = op->getLoc(); - Value zeroVal = rewriter.create(loc, APInt(1, 0)); + Value zeroVal = hw::ConstantOp::create(rewriter, loc, APInt(1, 0)); // zero extend both LHS & RHS to ensure the unsigned integers are // interpreted correctly when calculating power - auto lhs = rewriter.create(loc, zeroVal, adaptor.getLhs()); - auto rhs = rewriter.create(loc, zeroVal, adaptor.getRhs()); + auto lhs = comb::ConcatOp::create(rewriter, loc, zeroVal, adaptor.getLhs()); + auto rhs = comb::ConcatOp::create(rewriter, loc, zeroVal, adaptor.getRhs()); // lower the exponentiation via MLIR's math dialect - auto pow = rewriter.create(loc, lhs, rhs); + auto pow = mlir::math::IPowIOp::create(rewriter, loc, lhs, rhs); rewriter.replaceOpWithNewOp(op, resultType, pow, 0); return success(); @@ -1410,7 +1416,7 @@ struct AssignOpConversion : public OpConversionPattern { // this conversion. auto timeAttr = llhd::TimeAttr::get( op->getContext(), 0U, llvm::StringRef("ns"), DeltaTime, EpsilonTime); - auto time = rewriter.create(op->getLoc(), timeAttr); + auto time = llhd::ConstantTimeOp::create(rewriter, op->getLoc(), timeAttr); rewriter.replaceOpWithNewOp(op, adaptor.getDst(), adaptor.getSrc(), time, Value{}); return success(); @@ -1466,7 +1472,7 @@ struct ConditionalOpConversion : public OpConversionPattern { } auto ifOp = - rewriter.create(op.getLoc(), type, adaptor.getCondition()); + scf::IfOp::create(rewriter, op.getLoc(), type, adaptor.getCondition()); rewriter.inlineRegionBefore(op.getTrueRegion(), ifOp.getThenRegion(), ifOp.getThenRegion().end()); rewriter.inlineRegionBefore(op.getFalseRegion(), ifOp.getElseRegion(), @@ -1723,8 +1729,8 @@ static void populateTypeConversion(TypeConverter &typeConverter) { mlir::ValueRange inputs, mlir::Location loc) -> mlir::Value { if (inputs.size() != 1 || !inputs[0]) return Value(); - return builder - .create(loc, resultType, inputs[0]) + return UnrealizedConversionCastOp::create(builder, loc, resultType, + inputs[0]) .getResult(0); }); @@ -1733,8 +1739,8 @@ static void populateTypeConversion(TypeConverter &typeConverter) { mlir::ValueRange inputs, mlir::Location loc) -> mlir::Value { if (inputs.size() != 1) return Value(); - return builder - .create(loc, resultType, inputs[0]) + return UnrealizedConversionCastOp::create(builder, loc, resultType, + inputs[0]) ->getResult(0); }); } diff --git a/lib/Conversion/PipelineToHW/PipelineToHW.cpp b/lib/Conversion/PipelineToHW/PipelineToHW.cpp index 940d12fbc0..4bbacdb6f3 100644 --- a/lib/Conversion/PipelineToHW/PipelineToHW.cpp +++ b/lib/Conversion/PipelineToHW/PipelineToHW.cpp @@ -125,14 +125,14 @@ public: break; case StageKind::Stallable: stageValid = - builder.create(loc, args.enable, getOrSetNotStalled()); + comb::AndOp::create(builder, loc, args.enable, getOrSetNotStalled()); stageValid.getDefiningOp()->setAttr("sv.namehint", validSignalName); break; case StageKind::Runoff: assert(args.lnsEn && "Expected an LNS signal if this was a runoff stage"); - stageValid = builder.create( - loc, args.enable, - builder.create(loc, args.lnsEn, getOrSetNotStalled())); + stageValid = comb::AndOp::create( + builder, loc, args.enable, + comb::OrOp::create(builder, loc, args.lnsEn, getOrSetNotStalled())); stageValid.getDefiningOp()->setAttr("sv.namehint", validSignalName); break; } @@ -156,8 +156,8 @@ public: Value notStalledClockGate; if (this->clockGateRegs) { // Create the top-level clock gate. - notStalledClockGate = builder.create( - loc, args.clock, stageValid, /*test_enable=*/Value(), + notStalledClockGate = seq::ClockGateOp::create( + builder, loc, args.clock, stageValid, /*test_enable=*/Value(), /*inner_sym=*/hw::InnerSymAttr()); } @@ -172,23 +172,24 @@ public: Value currClockGate = notStalledClockGate; for (auto hierClockGateEnable : stageOp.getClockGatesForReg(regIdx)) { // Create clock gates for any hierarchically nested clock gates. - currClockGate = builder.create( - loc, currClockGate, hierClockGateEnable, + currClockGate = seq::ClockGateOp::create( + builder, loc, currClockGate, hierClockGateEnable, /*test_enable=*/Value(), /*inner_sym=*/hw::InnerSymAttr()); } - dataReg = builder.create(stageOp->getLoc(), regIn, - currClockGate, regName); + dataReg = seq::CompRegOp::create(builder, stageOp->getLoc(), regIn, + currClockGate, regName); } else { // Only clock-enable the register if the pipeline is stallable. // For non-stallable (continuous) pipelines, a data register can always // be clocked. if (isStallablePipeline) { - dataReg = builder.create( - stageOp->getLoc(), regIn, args.clock, stageValid, regName); + dataReg = seq::CompRegClockEnabledOp::create( + builder, stageOp->getLoc(), regIn, args.clock, stageValid, + regName); } else { - dataReg = builder.create(stageOp->getLoc(), regIn, - args.clock, regName); + dataReg = seq::CompRegOp::create(builder, stageOp->getLoc(), regIn, + args.clock, regName); } } rets.regs.push_back(dataReg); @@ -381,30 +382,30 @@ public: Value enableRegResetVal; if (args.reset) enableRegResetVal = - builder.create(loc, APInt(1, 0, false)).getResult(); + hw::ConstantOp::create(builder, loc, APInt(1, 0, false)) + .getResult(); switch (stageKind) { case StageKind::Continuous: LLVM_FALLTHROUGH; case StageKind::NonStallable: - stageEnabled = builder.create( - loc, args.enable, args.clock, args.reset, enableRegResetVal, - enableRegName); + stageEnabled = seq::CompRegOp::create(builder, loc, args.enable, + args.clock, args.reset, + enableRegResetVal, enableRegName); break; case StageKind::Stallable: - stageEnabled = builder.create( - loc, args.enable, args.clock, + stageEnabled = seq::CompRegClockEnabledOp::create( + builder, loc, args.enable, args.clock, comb::createOrFoldNot(loc, args.stall, builder), args.reset, enableRegResetVal, enableRegName); break; case StageKind::Runoff: assert(args.lnsEn && "Expected an LNS signal if this was a runoff stage"); - stageEnabled = builder.create( - loc, args.enable, args.clock, - builder.create( - loc, args.lnsEn, - comb::createOrFoldNot(loc, args.stall, builder)), + stageEnabled = seq::CompRegClockEnabledOp::create( + builder, loc, args.enable, args.clock, + comb::OrOp::create(builder, loc, args.lnsEn, + comb::createOrFoldNot(loc, args.stall, builder)), args.reset, enableRegResetVal, enableRegName); break; } diff --git a/lib/Conversion/SCFToCalyx/SCFToCalyx.cpp b/lib/Conversion/SCFToCalyx/SCFToCalyx.cpp index a1d6c700c5..e6dfad1ce6 100644 --- a/lib/Conversion/SCFToCalyx/SCFToCalyx.cpp +++ b/lib/Conversion/SCFToCalyx/SCFToCalyx.cpp @@ -495,14 +495,14 @@ private: calyx::SgeLibOp, calyx::SgtLibOp>(calyxOp.getOperation())) && "Must be a Calyx comparison library operation."); int64_t outputIndex = 2; - rewriter.create(loc, condReg.getIn(), - calyxOp.getResult(outputIndex)); - rewriter.create( - loc, condReg.getWriteEn(), + calyx::AssignOp::create(rewriter, loc, condReg.getIn(), + calyxOp.getResult(outputIndex)); + calyx::AssignOp::create( + rewriter, loc, condReg.getWriteEn(), createConstant(loc, rewriter, getState().getComponentOp(), 1, 1)); - rewriter.create(loc, condReg.getDone()); + calyx::GroupDoneOp::create(rewriter, loc, condReg.getDone()); getState().addSeqGuardCmpLibOp(cmpIOp); } @@ -565,7 +565,7 @@ private: auto srcOp = calyx::parentIsSeqCell(dstOp.value()) ? condReg.getOut() : op->getOperand(dstOp.index()); - rewriter.create(op.getLoc(), dstOp.value(), srcOp); + calyx::AssignOp::create(rewriter, op.getLoc(), dstOp.value(), srcOp); } /// Replace the result values of the source operator with the new operator. @@ -620,24 +620,24 @@ private: if constexpr (std::is_same_v) // According to the Hardfloat library: "If sqrtOp is 1, the operation is // the square root of a, and operand b is ignored." - rewriter.create(loc, opPipe.getLeft(), op.getOperand()); + calyx::AssignOp::create(rewriter, loc, opPipe.getLeft(), op.getOperand()); else { - rewriter.create(loc, opPipe.getLeft(), op.getLhs()); - rewriter.create(loc, opPipe.getRight(), op.getRhs()); + calyx::AssignOp::create(rewriter, loc, opPipe.getLeft(), op.getLhs()); + calyx::AssignOp::create(rewriter, loc, opPipe.getRight(), op.getRhs()); } // Write the output to this register. - rewriter.create(loc, reg.getIn(), out); + calyx::AssignOp::create(rewriter, loc, reg.getIn(), out); // The write enable port is high when the pipeline is done. - rewriter.create(loc, reg.getWriteEn(), opPipe.getDone()); + calyx::AssignOp::create(rewriter, loc, reg.getWriteEn(), opPipe.getDone()); // Set pipelineOp to high as long as its done signal is not high. // This prevents the pipelineOP from executing for the cycle that we write // to register. To get !(pipelineOp.done) we do 1 xor pipelineOp.done hw::ConstantOp c1 = createConstant(loc, rewriter, getComponent(), 1, 1); - rewriter.create( - loc, opPipe.getGo(), c1, + calyx::AssignOp::create( + rewriter, loc, opPipe.getGo(), c1, comb::createOrFoldNot(group.getLoc(), opPipe.getDone(), builder)); // The group is done when the register write is complete. - rewriter.create(loc, reg.getDone()); + calyx::GroupDoneOp::create(rewriter, loc, reg.getDone()); // Pass the result from the source operation to register holding the resullt // from the Calyx primitive. @@ -653,13 +653,13 @@ private: subOp = createConstant(loc, rewriter, getComponent(), /*width=*/1, /*subtract=*/1); } - rewriter.create(loc, opFOp.getSubOp(), subOp); + calyx::AssignOp::create(rewriter, loc, opFOp.getSubOp(), subOp); } else if (auto opFOp = dyn_cast(opPipe.getOperation())) { bool isSqrt = !isa(op); hw::ConstantOp sqrtOp = createConstant(loc, rewriter, getComponent(), /*width=*/1, isSqrt); - rewriter.create(loc, opFOp.getSqrtOp(), sqrtOp); + calyx::AssignOp::create(rewriter, loc, opFOp.getSqrtOp(), sqrtOp); } // Register the values for the pipeline. @@ -698,23 +698,25 @@ private: group); rewriter.setInsertionPointToEnd(group.getBodyBlock()); - rewriter.create(loc, calyxOp.getIn(), op.getIn()); + calyx::AssignOp::create(rewriter, loc, calyxOp.getIn(), op.getIn()); if (isa(calyxOp)) { - rewriter.create( - loc, cast(calyxOp).getSignedOut(), c1); + calyx::AssignOp::create( + rewriter, loc, cast(calyxOp).getSignedOut(), + c1); } else if (isa(calyxOp)) { - rewriter.create( - loc, cast(calyxOp).getSignedIn(), c1); + calyx::AssignOp::create( + rewriter, loc, cast(calyxOp).getSignedIn(), + c1); } op.getResult().replaceAllUsesWith(reg.getOut()); - rewriter.create(loc, reg.getIn(), calyxOp.getOut()); - rewriter.create(loc, reg.getWriteEn(), c1); + calyx::AssignOp::create(rewriter, loc, reg.getIn(), calyxOp.getOut()); + calyx::AssignOp::create(rewriter, loc, reg.getWriteEn(), c1); - rewriter.create( - loc, calyxOp.getGo(), c1, + calyx::AssignOp::create( + rewriter, loc, calyxOp.getGo(), c1, comb::createOrFoldNot(loc, calyxOp.getDone(), builder)); - rewriter.create(loc, reg.getDone()); + calyx::GroupDoneOp::create(rewriter, loc, reg.getDone()); return success(); } @@ -734,16 +736,16 @@ private: "We expected a 1 dimensional memory of size 1 because there were no " "address assignment values"); // Assign to address 1'd0 in memory. - rewriter.create( - loc, addrPorts[0], + calyx::AssignOp::create( + rewriter, loc, addrPorts[0], createConstant(loc, rewriter, getComponent(), 1, 0)); } else { assert(addrPorts.size() == addressValues.size() && "Mismatch between number of address ports of the provided memory " "and address assignment values"); for (auto address : enumerate(addressValues)) - rewriter.create(loc, addrPorts[address.index()], - address.value()); + calyx::AssignOp::create(rewriter, loc, addrPorts[address.index()], + address.value()); } } @@ -759,18 +761,18 @@ private: auto reg = createRegister( loc, rewriter, component, 1, getState().getUniqueName(nameSuffix)); - rewriter.create(loc, reg.getWriteEn(), - calyxCmpFOp.getDone()); + calyx::AssignOp::create(rewriter, loc, reg.getWriteEn(), + calyxCmpFOp.getDone()); if (invert) { auto notLibOp = getState() .getNewLibraryOpInstance( rewriter, loc, {one, one}); - rewriter.create(loc, notLibOp.getIn(), signal); - rewriter.create(loc, reg.getIn(), notLibOp.getOut()); + calyx::AssignOp::create(rewriter, loc, notLibOp.getIn(), signal); + calyx::AssignOp::create(rewriter, loc, reg.getIn(), notLibOp.getOut()); getState().registerEvaluatingGroup( notLibOp.getOut(), group); } else - rewriter.create(loc, reg.getIn(), signal); + calyx::AssignOp::create(rewriter, loc, reg.getIn(), signal); return reg; }; }; @@ -793,8 +795,8 @@ LogicalResult BuildOpGroups::buildOp(PatternRewriter &rewriter, if (memoryInterface.readEnOpt().has_value()) { auto oneI1 = calyx::createConstant(loadOp.getLoc(), rewriter, getComponent(), 1, 1); - rewriter.create(loadOp.getLoc(), memoryInterface.readEn(), - oneI1); + calyx::AssignOp::create(rewriter, loadOp.getLoc(), memoryInterface.readEn(), + oneI1); regWriteEn = memoryInterface.done(); if (calyx::noStoresToMemory(memref) && calyx::singleLoadFromMemory(memref)) { @@ -802,8 +804,8 @@ LogicalResult BuildOpGroups::buildOp(PatternRewriter &rewriter, // register. The readData value will be held until readEn is asserted // again needReg = false; - rewriter.create(loadOp.getLoc(), - memoryInterface.done()); + calyx::GroupDoneOp::create(rewriter, loadOp.getLoc(), + memoryInterface.done()); // We refrain from replacing the loadOp result with // memoryInterface.readData, since multiple loadOp's need to be converted // to a single memory's ReadData. If this replacement is done now, we lose @@ -820,10 +822,10 @@ LogicalResult BuildOpGroups::buildOp(PatternRewriter &rewriter, calyx::createConstant(loadOp.getLoc(), rewriter, getComponent(), 1, 1); auto zeroI1 = calyx::createConstant(loadOp.getLoc(), rewriter, getComponent(), 1, 0); - rewriter.create(loadOp.getLoc(), - memoryInterface.contentEn(), oneI1); - rewriter.create(loadOp.getLoc(), memoryInterface.writeEn(), - zeroI1); + calyx::AssignOp::create(rewriter, loadOp.getLoc(), + memoryInterface.contentEn(), oneI1); + calyx::AssignOp::create(rewriter, loadOp.getLoc(), + memoryInterface.writeEn(), zeroI1); regWriteEn = memoryInterface.done(); if (calyx::noStoresToMemory(memref) && calyx::singleLoadFromMemory(memref)) { @@ -831,8 +833,8 @@ LogicalResult BuildOpGroups::buildOp(PatternRewriter &rewriter, // register. The readData value will be held until contentEn is asserted // again needReg = false; - rewriter.create(loadOp.getLoc(), - memoryInterface.done()); + calyx::GroupDoneOp::create(rewriter, loadOp.getLoc(), + memoryInterface.done()); // We refrain from replacing the loadOp result with // memoryInterface.readData, since multiple loadOp's need to be converted // to a single memory's ReadData. If this replacement is done now, we lose @@ -859,11 +861,11 @@ LogicalResult BuildOpGroups::buildOp(PatternRewriter &rewriter, loadOp.getMemRefType().getElementTypeBitWidth(), getState().getUniqueName("load")); rewriter.setInsertionPointToEnd(group.getBodyBlock()); - rewriter.create(loadOp.getLoc(), reg.getIn(), - memoryInterface.readData()); - rewriter.create(loadOp.getLoc(), reg.getWriteEn(), - regWriteEn); - rewriter.create(loadOp.getLoc(), reg.getDone()); + calyx::AssignOp::create(rewriter, loadOp.getLoc(), reg.getIn(), + memoryInterface.readData()); + calyx::AssignOp::create(rewriter, loadOp.getLoc(), reg.getWriteEn(), + regWriteEn); + calyx::GroupDoneOp::create(rewriter, loadOp.getLoc(), reg.getDone()); loadOp.getResult().replaceAllUsesWith(reg.getOut()); res = reg.getOut(); } @@ -887,18 +889,20 @@ LogicalResult BuildOpGroups::buildOp(PatternRewriter &rewriter, assignAddressPorts(rewriter, storeOp.getLoc(), group, memoryInterface, storeOp.getIndices()); rewriter.setInsertionPointToEnd(group.getBodyBlock()); - rewriter.create( - storeOp.getLoc(), memoryInterface.writeData(), storeOp.getValueToStore()); - rewriter.create( - storeOp.getLoc(), memoryInterface.writeEn(), + calyx::AssignOp::create(rewriter, storeOp.getLoc(), + memoryInterface.writeData(), + storeOp.getValueToStore()); + calyx::AssignOp::create( + rewriter, storeOp.getLoc(), memoryInterface.writeEn(), createConstant(storeOp.getLoc(), rewriter, getComponent(), 1, 1)); if (memoryInterface.contentEnOpt().has_value()) { // If memory has content enable, it must be asserted when writing - rewriter.create( - storeOp.getLoc(), memoryInterface.contentEn(), + calyx::AssignOp::create( + rewriter, storeOp.getLoc(), memoryInterface.contentEn(), createConstant(storeOp.getLoc(), rewriter, getComponent(), 1, 1)); } - rewriter.create(storeOp.getLoc(), memoryInterface.done()); + calyx::GroupDoneOp::create(rewriter, storeOp.getLoc(), + memoryInterface.done()); return success(); } @@ -1060,8 +1064,8 @@ LogicalResult BuildOpGroups::buildOp(PatternRewriter &rewriter, group); rewriter.setInsertionPointToEnd(group.getBodyBlock()); - rewriter.create(loc, calyxCmpFOp.getLeft(), cmpf.getLhs()); - rewriter.create(loc, calyxCmpFOp.getRight(), cmpf.getRhs()); + calyx::AssignOp::create(rewriter, loc, calyxCmpFOp.getLeft(), cmpf.getLhs()); + calyx::AssignOp::create(rewriter, loc, calyxCmpFOp.getRight(), cmpf.getRhs()); bool signalingFlag = false; switch (cmpf.getPredicate()) { @@ -1089,8 +1093,8 @@ LogicalResult BuildOpGroups::buildOp(PatternRewriter &rewriter, // The IEEE Standard mandates that equality comparisons ordinarily are quiet, // while inequality comparisons ordinarily are signaling. - rewriter.create(loc, calyxCmpFOp.getSignaling(), - signalingFlag ? c1 : c0); + calyx::AssignOp::create(rewriter, loc, calyxCmpFOp.getSignaling(), + signalingFlag ? c1 : c0); // Prepare signals and create registers SmallVector inputRegs; @@ -1136,10 +1140,10 @@ LogicalResult BuildOpGroups::buildOp(PatternRewriter &rewriter, auto outputLibOp = getState() .getNewLibraryOpInstance( rewriter, loc, {one, one, one}); - rewriter.create(loc, outputLibOp.getLeft(), - inputRegs[0].getOut()); - rewriter.create(loc, outputLibOp.getRight(), - inputRegs[1].getOut()); + calyx::AssignOp::create(rewriter, loc, outputLibOp.getLeft(), + inputRegs[0].getOut()); + calyx::AssignOp::create(rewriter, loc, outputLibOp.getRight(), + inputRegs[1].getOut()); outputValue = outputLibOp.getOut(); break; @@ -1148,10 +1152,10 @@ LogicalResult BuildOpGroups::buildOp(PatternRewriter &rewriter, auto outputLibOp = getState() .getNewLibraryOpInstance( rewriter, loc, {one, one, one}); - rewriter.create(loc, outputLibOp.getLeft(), - inputRegs[0].getOut()); - rewriter.create(loc, outputLibOp.getRight(), - inputRegs[1].getOut()); + calyx::AssignOp::create(rewriter, loc, outputLibOp.getLeft(), + inputRegs[0].getOut()); + calyx::AssignOp::create(rewriter, loc, outputLibOp.getRight(), + inputRegs[1].getOut()); outputValue = outputLibOp.getOut(); break; @@ -1162,22 +1166,22 @@ LogicalResult BuildOpGroups::buildOp(PatternRewriter &rewriter, auto doneLibOp = getState() .getNewLibraryOpInstance( rewriter, loc, {one, one, one}); - rewriter.create(loc, doneLibOp.getLeft(), - inputRegs[0].getDone()); - rewriter.create(loc, doneLibOp.getRight(), - inputRegs[1].getDone()); + calyx::AssignOp::create(rewriter, loc, doneLibOp.getLeft(), + inputRegs[0].getDone()); + calyx::AssignOp::create(rewriter, loc, doneLibOp.getRight(), + inputRegs[1].getDone()); doneValue = doneLibOp.getOut(); } // Write to the output register - rewriter.create(loc, reg.getIn(), outputValue); - rewriter.create(loc, reg.getWriteEn(), doneValue); + calyx::AssignOp::create(rewriter, loc, reg.getIn(), outputValue); + calyx::AssignOp::create(rewriter, loc, reg.getWriteEn(), doneValue); // Set the go and done signal - rewriter.create( - loc, calyxCmpFOp.getGo(), c1, + calyx::AssignOp::create( + rewriter, loc, calyxCmpFOp.getGo(), c1, comb::createOrFoldNot(loc, calyxCmpFOp.getDone(), builder)); - rewriter.create(loc, reg.getDone()); + calyx::GroupDoneOp::create(rewriter, loc, reg.getDone()); cmpf.getResult().replaceAllUsesWith(reg.getOut()); @@ -1254,7 +1258,7 @@ LogicalResult BuildOpGroups::buildOp(PatternRewriter &rewriter, uint64_t signBit = 1ULL << (bitwidth - 1); uint64_t absMask = ~signBit & ((1ULL << bitwidth) - 1); // clear sign bit - Value maskOp = rewriter.create(loc, intTy, absMask); + Value maskOp = arith::ConstantIntOp::create(rewriter, loc, intTy, absMask); auto combGroup = createGroupForOp(rewriter, absFOp); rewriter.setInsertionPointToStart(combGroup.getBodyBlock()); @@ -1262,8 +1266,8 @@ LogicalResult BuildOpGroups::buildOp(PatternRewriter &rewriter, auto andLibOp = getState() .getNewLibraryOpInstance( rewriter, loc, {intTy, intTy, intTy}); - rewriter.create(loc, andLibOp.getLeft(), maskOp); - rewriter.create(loc, andLibOp.getRight(), input); + calyx::AssignOp::create(rewriter, loc, andLibOp.getLeft(), maskOp); + calyx::AssignOp::create(rewriter, loc, andLibOp.getRight(), input); getState().registerEvaluatingGroup(andLibOp.getOut(), combGroup); @@ -1290,8 +1294,8 @@ static LogicalResult buildAllocOp(ComponentLoweringState &componentState, sizes.push_back(1); addrSizes.push_back(1); } - auto memoryOp = rewriter.create( - allocOp.getLoc(), componentState.getUniqueName("mem"), + auto memoryOp = calyx::SeqMemoryOp::create( + rewriter, allocOp.getLoc(), componentState.getUniqueName("mem"), memtype.getElementType().getIntOrFloatBitWidth(), sizes, addrSizes); // Externalize memories conditionally (only in the top-level component because @@ -1443,12 +1447,12 @@ LogicalResult BuildOpGroups::buildOp(PatternRewriter &rewriter, // Assign inductionReg.out to the left port of the adder. Value leftOp = opInputPorts.front(); - rewriter.create(forOp.getLoc(), leftOp, - inductionReg.getOut()); + calyx::AssignOp::create(rewriter, forOp.getLoc(), leftOp, + inductionReg.getOut()); // Assign forOp.getConstantStep to the right port of the adder. Value rightOp = opInputPorts.back(); - rewriter.create( - forOp.getLoc(), rightOp, + calyx::AssignOp::create( + rewriter, forOp.getLoc(), rightOp, createConstant(forOp->getLoc(), rewriter, componentOp, regWidth.getIntOrFloatBitWidth(), forOp.getConstantStep().value().getSExtValue())); @@ -1602,8 +1606,8 @@ LogicalResult BuildOpGroups::buildOp(PatternRewriter &rewriter, auto floatAttr = cast(constOp.getValueAttr()); auto intType = rewriter.getIntegerType(floatAttr.getType().getIntOrFloatBitWidth()); - auto calyxConstOp = rewriter.create( - constOp.getLoc(), name, floatAttr, intType); + auto calyxConstOp = calyx::ConstantOp::create(rewriter, constOp.getLoc(), + name, floatAttr, intType); calyxConstOp->moveAfter(getComponent().getBodyBlock(), getComponent().getBodyBlock()->begin()); rewriter.replaceAllUsesWith(constOp, calyxConstOp.getOut()); @@ -1942,8 +1946,9 @@ struct FuncOpConversion : public calyx::FuncOpPartialLoweringPattern { calyx::addMandatoryComponentPorts(rewriter, ports); /// Create a calyx::ComponentOp corresponding to the to-be-lowered function. - auto compOp = rewriter.create( - funcOp.getLoc(), rewriter.getStringAttr(funcOp.getSymName()), ports); + auto compOp = calyx::ComponentOp::create( + rewriter, funcOp.getLoc(), rewriter.getStringAttr(funcOp.getSymName()), + ports); std::string funcName = "func_" + funcOp.getSymName().str(); rewriter.modifyOpInPlace(funcOp, [&]() { funcOp.setSymName(funcName); }); @@ -1976,8 +1981,8 @@ struct FuncOpConversion : public calyx::FuncOpPartialLoweringPattern { sizes.push_back(1); addrSizes.push_back(1); } - auto memOp = rewriter.create( - funcOp.getLoc(), memName, + auto memOp = calyx::SeqMemoryOp::create( + rewriter, funcOp.getLoc(), memName, memtype.getElementType().getIntOrFloatBitWidth(), sizes, addrSizes); // we don't set the memory to "external", which implies it's a reference @@ -2210,7 +2215,7 @@ class BuildControl : public calyx::FuncOpPartialLoweringPattern { auto *entryBlock = &funcOp.getBlocks().front(); rewriter.setInsertionPointToStart( getComponent().getControlOp().getBodyBlock()); - auto topLevelSeqOp = rewriter.create(funcOp.getLoc()); + auto topLevelSeqOp = calyx::SeqOp::create(rewriter, funcOp.getLoc()); DenseSet path; return buildCFGControl(path, rewriter, topLevelSeqOp.getBodyBlock(), nullptr, entryBlock); @@ -2229,15 +2234,15 @@ private: if (compBlockScheduleables.size() > 1 && !isa(block->getParentOp())) { - auto seqOp = rewriter.create(loc); + auto seqOp = calyx::SeqOp::create(rewriter, loc); parentCtrlBlock = seqOp.getBodyBlock(); } for (auto &group : compBlockScheduleables) { rewriter.setInsertionPointToEnd(parentCtrlBlock); if (auto groupPtr = std::get_if(&group); groupPtr) { - rewriter.create(groupPtr->getLoc(), - groupPtr->getSymName()); + calyx::EnableOp::create(rewriter, groupPtr->getLoc(), + groupPtr->getSymName()); } else if (auto whileSchedPtr = std::get_if(&group); whileSchedPtr) { auto &whileOp = whileSchedPtr->whileOp; @@ -2248,7 +2253,7 @@ private: rewriter); rewriter.setInsertionPointToEnd(whileCtrlOp.getBodyBlock()); auto whileBodyOp = - rewriter.create(whileOp.getOperation()->getLoc()); + calyx::SeqOp::create(rewriter, whileOp.getOperation()->getLoc()); auto *whileBodyOpBlock = whileBodyOp.getBodyBlock(); /// Only schedule the 'after' block. The 'before' block is @@ -2263,16 +2268,16 @@ private: rewriter.setInsertionPointToEnd(whileBodyOpBlock); calyx::GroupOp whileLatchGroup = getState().getWhileLoopLatchGroup(whileOp); - rewriter.create(whileLatchGroup.getLoc(), - whileLatchGroup.getName()); + calyx::EnableOp::create(rewriter, whileLatchGroup.getLoc(), + whileLatchGroup.getName()); } else if (auto *parSchedPtr = std::get_if(&group)) { auto parOp = parSchedPtr->parOp; - auto calyxParOp = rewriter.create(parOp.getLoc()); + auto calyxParOp = calyx::ParOp::create(rewriter, parOp.getLoc()); WalkResult walkResult = parOp.walk([&](scf::ExecuteRegionOp execRegion) { rewriter.setInsertionPointToEnd(calyxParOp.getBodyBlock()); - auto seqOp = rewriter.create(execRegion.getLoc()); + auto seqOp = calyx::SeqOp::create(rewriter, execRegion.getLoc()); rewriter.setInsertionPointToEnd(seqOp.getBodyBlock()); for (auto &execBlock : execRegion.getRegion().getBlocks()) { @@ -2297,7 +2302,7 @@ private: forSchedPtr->bound, rewriter); rewriter.setInsertionPointToEnd(forCtrlOp.getBodyBlock()); auto forBodyOp = - rewriter.create(forOp.getOperation()->getLoc()); + calyx::SeqOp::create(rewriter, forOp.getOperation()->getLoc()); auto *forBodyOpBlock = forBodyOp.getBodyBlock(); // Schedule the body of the for loop. @@ -2310,8 +2315,8 @@ private: rewriter.setInsertionPointToEnd(forBodyOpBlock); calyx::GroupOp forLatchGroup = getState().getForLoopLatchGroup(forOp); - rewriter.create(forLatchGroup.getLoc(), - forLatchGroup.getName()); + calyx::EnableOp::create(rewriter, forLatchGroup.getLoc(), + forLatchGroup.getName()); } else if (auto *ifSchedPtr = std::get_if(&group); ifSchedPtr) { auto ifOp = ifSchedPtr->ifOp; @@ -2331,13 +2336,13 @@ private: } bool initElse = !ifOp.getElseRegion().empty(); - auto ifCtrlOp = rewriter.create( - loc, cond, symbolAttr, /*initializeElseBody=*/initElse); + auto ifCtrlOp = calyx::IfOp::create(rewriter, loc, cond, symbolAttr, + /*initializeElseBody=*/initElse); rewriter.setInsertionPointToEnd(ifCtrlOp.getBodyBlock()); auto thenSeqOp = - rewriter.create(ifOp.getThenRegion().getLoc()); + calyx::SeqOp::create(rewriter, ifOp.getThenRegion().getLoc()); auto *thenSeqOpBlock = thenSeqOp.getBodyBlock(); auto *thenBlock = &ifOp.getThenRegion().front(); @@ -2352,15 +2357,15 @@ private: rewriter.setInsertionPointToEnd(thenSeqOpBlock); calyx::GroupOp thenGroup = getState().getThenGroup(ifOp); - rewriter.create(thenGroup.getLoc(), - thenGroup.getName()); + calyx::EnableOp::create(rewriter, thenGroup.getLoc(), + thenGroup.getName()); } if (!ifOp.getElseRegion().empty()) { rewriter.setInsertionPointToEnd(ifCtrlOp.getElseBody()); auto elseSeqOp = - rewriter.create(ifOp.getElseRegion().getLoc()); + calyx::SeqOp::create(rewriter, ifOp.getElseRegion().getLoc()); auto *elseSeqOpBlock = elseSeqOp.getBodyBlock(); auto *elseBlock = &ifOp.getElseRegion().front(); @@ -2373,14 +2378,14 @@ private: rewriter.setInsertionPointToEnd(elseSeqOpBlock); calyx::GroupOp elseGroup = getState().getElseGroup(ifOp); - rewriter.create(elseGroup.getLoc(), - elseGroup.getName()); + calyx::EnableOp::create(rewriter, elseGroup.getLoc(), + elseGroup.getName()); } } } else if (auto *callSchedPtr = std::get_if(&group)) { auto instanceOp = callSchedPtr->instanceOp; OpBuilder::InsertionGuard g(rewriter); - auto callBody = rewriter.create(instanceOp.getLoc()); + auto callBody = calyx::SeqOp::create(rewriter, instanceOp.getLoc()); rewriter.setInsertionPointToStart(callBody.getBodyBlock()); auto callee = callSchedPtr->callOp.getCallee(); @@ -2428,10 +2433,11 @@ private: ArrayAttr refCellsAttr = ArrayAttr::get(rewriter.getContext(), refCells); - rewriter.create( - instanceOp.getLoc(), instanceOp.getSymName(), instancePorts, - inputPorts, refCellsAttr, ArrayAttr::get(rewriter.getContext(), {}), - ArrayAttr::get(rewriter.getContext(), {})); + calyx::InvokeOp::create(rewriter, instanceOp.getLoc(), + instanceOp.getSymName(), instancePorts, + inputPorts, refCellsAttr, + ArrayAttr::get(rewriter.getContext(), {}), + ArrayAttr::get(rewriter.getContext(), {})); } else llvm_unreachable("Unknown scheduleable"); } @@ -2450,11 +2456,11 @@ private: /// Schedule any registered block arguments to be executed before the body /// of the branch. rewriter.setInsertionPointToEnd(parentCtrlBlock); - auto preSeqOp = rewriter.create(loc); + auto preSeqOp = calyx::SeqOp::create(rewriter, loc); rewriter.setInsertionPointToEnd(preSeqOp.getBodyBlock()); for (auto barg : getState().getBlockArgGroups(from, to)) - rewriter.create(barg.getLoc(), barg.getSymName()); + calyx::EnableOp::create(rewriter, barg.getLoc(), barg.getSymName()); return buildCFGControl(path, rewriter, parentCtrlBlock, from, to); } @@ -2494,12 +2500,13 @@ private: auto symbolAttr = FlatSymbolRefAttr::get( StringAttr::get(getContext(), condGroup.getSymName())); - auto ifOp = rewriter.create( - brOp->getLoc(), cond, symbolAttr, /*initializeElseBody=*/true); + auto ifOp = + calyx::IfOp::create(rewriter, brOp->getLoc(), cond, symbolAttr, + /*initializeElseBody=*/true); rewriter.setInsertionPointToStart(ifOp.getThenBody()); - auto thenSeqOp = rewriter.create(brOp.getLoc()); + auto thenSeqOp = calyx::SeqOp::create(rewriter, brOp.getLoc()); rewriter.setInsertionPointToStart(ifOp.getElseBody()); - auto elseSeqOp = rewriter.create(brOp.getLoc()); + auto elseSeqOp = calyx::SeqOp::create(rewriter, brOp.getLoc()); bool trueBrSchedSuccess = schedulePath(rewriter, path, brOp.getLoc(), block, successors[0], @@ -2529,10 +2536,10 @@ private: insertParInitGroups(PatternRewriter &rewriter, Location loc, const SmallVector &initGroups) const { PatternRewriter::InsertionGuard g(rewriter); - auto parOp = rewriter.create(loc); + auto parOp = calyx::ParOp::create(rewriter, loc); rewriter.setInsertionPointToStart(parOp.getBodyBlock()); for (calyx::GroupOp group : initGroups) - rewriter.create(group.getLoc(), group.getName()); + calyx::EnableOp::create(rewriter, group.getLoc(), group.getName()); } calyx::WhileOp buildWhileCtrlOp(ScfWhileOp whileOp, @@ -2549,7 +2556,7 @@ private: .getEvaluatingGroup(cond); auto symbolAttr = FlatSymbolRefAttr::get( StringAttr::get(getContext(), condGroup.getSymName())); - return rewriter.create(loc, cond, symbolAttr); + return calyx::WhileOp::create(rewriter, loc, cond, symbolAttr); } calyx::RepeatOp buildForCtrlOp(ScfForOp forOp, @@ -2562,7 +2569,7 @@ private: insertParInitGroups(rewriter, loc, initGroups); // Insert the repeatOp that corresponds to the For loop. - return rewriter.create(loc, bound); + return calyx::RepeatOp::create(rewriter, loc, bound); } }; @@ -2792,7 +2799,7 @@ private: FunctionType funcType = builder.getFunctionType({}, {}); if (auto newFunc = - builder.create(moduleOp.getLoc(), newName, funcType)) + FuncOp::create(builder, moduleOp.getLoc(), newName, funcType)) return newFunc; return nullptr; @@ -2852,16 +2859,17 @@ private: Value newOpRes; TypeSwitch(op) .Case([&](memref::AllocaOp allocaOp) { - newOpRes = builder.create(callee.getLoc(), - allocaOp.getType()); + newOpRes = memref::AllocaOp::create(builder, callee.getLoc(), + allocaOp.getType()); }) .Case([&](memref::AllocOp allocOp) { - newOpRes = builder.create(callee.getLoc(), - allocOp.getType()); + newOpRes = memref::AllocOp::create(builder, callee.getLoc(), + allocOp.getType()); }) .Case([&](memref::GetGlobalOp getGlobalOp) { - newOpRes = builder.create( - caller.getLoc(), getGlobalOp.getType(), getGlobalOp.getName()); + newOpRes = memref::GetGlobalOp::create(builder, caller.getLoc(), + getGlobalOp.getType(), + getGlobalOp.getName()); }) .Default([&](Operation *defaultOp) { llvm::report_fatal_error("Unsupported operation in TypeSwitch"); @@ -2890,7 +2898,7 @@ private: if (isa(arg.getType())) { auto memrefType = cast(arg.getType()); auto allocOp = - builder.create(callee.getLoc(), memrefType); + memref::AllocOp::create(builder, callee.getLoc(), memrefType); calleeArgFnOperands.push_back(allocOp); } else { auto callerArg = callerEntryBlock->getArgument(otherArgsCount++); @@ -2906,9 +2914,9 @@ private: auto resultTypes = callee.getResultTypes(); builder.setInsertionPointToEnd(callerEntryBlock); - builder.create(caller.getLoc(), calleeName, resultTypes, - fnOperands); - builder.create(caller.getLoc()); + CallOp::create(builder, caller.getLoc(), calleeName, resultTypes, + fnOperands); + ReturnOp::create(builder, caller.getLoc()); } /// Conditionally creates an optional new top-level function; and inserts a diff --git a/lib/Conversion/SMTToZ3LLVM/LowerSMTToZ3LLVM.cpp b/lib/Conversion/SMTToZ3LLVM/LowerSMTToZ3LLVM.cpp index 92760ce8b0..58a730ae68 100644 --- a/lib/Conversion/SMTToZ3LLVM/LowerSMTToZ3LLVM.cpp +++ b/lib/Conversion/SMTToZ3LLVM/LowerSMTToZ3LLVM.cpp @@ -56,13 +56,13 @@ SMTGlobalsHandler SMTGlobalsHandler::create(OpBuilder &builder, auto ptrTy = LLVM::LLVMPointerType::get(builder.getContext()); auto createGlobal = [&](StringRef namePrefix) { - auto global = builder.create( - loc, ptrTy, false, LLVM::Linkage::Internal, names.newName(namePrefix), - Attribute{}, /*alignment=*/8); + auto global = LLVM::GlobalOp::create( + builder, loc, ptrTy, false, LLVM::Linkage::Internal, + names.newName(namePrefix), Attribute{}, /*alignment=*/8); OpBuilder::InsertionGuard g(builder); builder.createBlock(&global.getInitializer()); - Value res = builder.create(loc, ptrTy); - builder.create(loc, res); + Value res = LLVM::ZeroOp::create(builder, loc, ptrTy); + LLVM::ReturnOp::create(builder, loc, res); return global; }; @@ -111,9 +111,9 @@ private: OpBuilder::InsertionGuard g(builder); builder.setInsertionPointToStart(block); - Value globalAddr = builder.create(loc, global); - return cache[block] = builder.create( - loc, LLVM::LLVMPointerType::get(builder.getContext()), + Value globalAddr = LLVM::AddressOfOp::create(builder, loc, global); + return cache[block] = LLVM::LoadOp::create( + builder, loc, LLVM::LLVMPointerType::get(builder.getContext()), globalAddr); } @@ -155,7 +155,7 @@ protected: assert(succeeded(funcOpResult) && "expected to lookup or create printf"); funcOp = funcOpResult.value(); } - return builder.create(loc, funcOp, args); + return LLVM::CallOp::create(builder, loc, funcOp, args); } /// Build a global constant for the given string and construct an 'addressof' @@ -172,11 +172,11 @@ protected: auto arrayTy = LLVM::LLVMArrayType::get(builder.getI8Type(), str.size() + 1); auto strAttr = builder.getStringAttr(str.str() + '\00'); - global = builder.create( - loc, arrayTy, /*isConstant=*/true, LLVM::Linkage::Internal, + global = LLVM::GlobalOp::create( + builder, loc, arrayTy, /*isConstant=*/true, LLVM::Linkage::Internal, globals.names.newName("str"), strAttr); } - return builder.create(loc, global); + return LLVM::AddressOfOp::create(builder, loc, global); } /// Most API functions require a pointer to the the Z3 context object as the /// first argument. This helper function prepends this pointer value to the @@ -215,8 +215,8 @@ protected: return buildPtrAPICall(builder, loc, "Z3_mk_int_sort"); }) .Case([&](smt::BitVectorType ty) { - Value bitwidth = builder.create( - loc, builder.getI32Type(), ty.getWidth()); + Value bitwidth = LLVM::ConstantOp::create( + builder, loc, builder.getI32Type(), ty.getWidth()); return buildPtrAPICall(builder, loc, "Z3_mk_bv_sort", {bitwidth}); }) .Case([&](smt::BoolType ty) { @@ -267,8 +267,8 @@ struct DeclareFunOpLowering : public SMTLoweringPattern { if (adaptor.getNamePrefix()) prefix = buildString(rewriter, loc, *adaptor.getNamePrefix()); else - prefix = rewriter.create( - loc, LLVM::LLVMPointerType::get(getContext())); + prefix = LLVM::ZeroOp::create(rewriter, loc, + LLVM::LLVMPointerType::get(getContext())); // Handle the constant value case. if (!isa(op.getType())) { @@ -287,20 +287,20 @@ struct DeclareFunOpLowering : public SMTLoweringPattern { Type arrTy = LLVM::LLVMArrayType::get(llvmPtrTy, funcType.getDomainTypes().size()); - Value domain = rewriter.create(loc, arrTy); + Value domain = LLVM::UndefOp::create(rewriter, loc, arrTy); for (auto [i, ty] : llvm::enumerate(funcType.getDomainTypes())) { Value sort = buildSort(rewriter, loc, ty); - domain = rewriter.create(loc, domain, sort, i); + domain = LLVM::InsertValueOp::create(rewriter, loc, domain, sort, i); } Value one = - rewriter.create(loc, rewriter.getI32Type(), 1); + LLVM::ConstantOp::create(rewriter, loc, rewriter.getI32Type(), 1); Value domainStorage = - rewriter.create(loc, llvmPtrTy, arrTy, one); - rewriter.create(loc, domain, domainStorage); + LLVM::AllocaOp::create(rewriter, loc, llvmPtrTy, arrTy, one); + LLVM::StoreOp::create(rewriter, loc, domain, domainStorage); - Value domainSize = rewriter.create( - loc, rewriter.getI32Type(), funcType.getDomainTypes().size()); + Value domainSize = LLVM::ConstantOp::create( + rewriter, loc, rewriter.getI32Type(), funcType.getDomainTypes().size()); Value decl = buildPtrAPICall(rewriter, loc, "Z3_mk_fresh_func_decl", {prefix, domainSize, domainStorage, rangeSort}); @@ -326,21 +326,21 @@ struct ApplyFuncOpLowering : public SMTLoweringPattern { Type arrTy = LLVM::LLVMArrayType::get(llvmPtrTy, adaptor.getArgs().size()); // Create an array of the function arguments. - Value domain = rewriter.create(loc, arrTy); + Value domain = LLVM::UndefOp::create(rewriter, loc, arrTy); for (auto [i, arg] : llvm::enumerate(adaptor.getArgs())) - domain = rewriter.create(loc, domain, arg, i); + domain = LLVM::InsertValueOp::create(rewriter, loc, domain, arg, i); // Store the array on the stack. Value one = - rewriter.create(loc, rewriter.getI32Type(), 1); + LLVM::ConstantOp::create(rewriter, loc, rewriter.getI32Type(), 1); Value domainStorage = - rewriter.create(loc, llvmPtrTy, arrTy, one); - rewriter.create(loc, domain, domainStorage); + LLVM::AllocaOp::create(rewriter, loc, llvmPtrTy, arrTy, one); + LLVM::StoreOp::create(rewriter, loc, domain, domainStorage); // Call the API function with a pointer to the function, the number of // arguments, and the pointer to the arguments stored on the stack. - Value domainSize = rewriter.create( - loc, rewriter.getI32Type(), adaptor.getArgs().size()); + Value domainSize = LLVM::ConstantOp::create( + rewriter, loc, rewriter.getI32Type(), adaptor.getArgs().size()); Value returnVal = buildPtrAPICall(rewriter, loc, "Z3_mk_app", {adaptor.getFunc(), domainSize, domainStorage}); @@ -374,8 +374,8 @@ struct BVConstantOpLowering : public SMTLoweringPattern { APInt val = adaptor.getValue().getValue(); if (width <= 64) { - Value bvConst = rewriter.create( - loc, rewriter.getI64Type(), val.getZExtValue()); + Value bvConst = LLVM::ConstantOp::create( + rewriter, loc, rewriter.getI64Type(), val.getZExtValue()); Value res = buildPtrAPICall(rewriter, loc, "Z3_mk_unsigned_int64", {bvConst, bvSort}); rewriter.replaceOp(op, res); @@ -417,21 +417,21 @@ struct VariadicSMTPattern : public SMTLoweringPattern { return failure(); Location loc = op.getLoc(); - Value numOperands = rewriter.create( - loc, rewriter.getI32Type(), op->getNumOperands()); + Value numOperands = LLVM::ConstantOp::create( + rewriter, loc, rewriter.getI32Type(), op->getNumOperands()); Value constOne = - rewriter.create(loc, rewriter.getI32Type(), 1); + LLVM::ConstantOp::create(rewriter, loc, rewriter.getI32Type(), 1); Type ptrTy = LLVM::LLVMPointerType::get(rewriter.getContext()); Type arrTy = LLVM::LLVMArrayType::get(ptrTy, op->getNumOperands()); Value storage = - rewriter.create(loc, ptrTy, arrTy, constOne); - Value array = rewriter.create(loc, arrTy); + LLVM::AllocaOp::create(rewriter, loc, ptrTy, arrTy, constOne); + Value array = LLVM::UndefOp::create(rewriter, loc, arrTy); for (auto [i, operand] : llvm::enumerate(adaptor.getOperands())) - array = rewriter.create( - loc, array, operand, ArrayRef{(int64_t)i}); + array = LLVM::InsertValueOp::create(rewriter, loc, array, operand, + ArrayRef{(int64_t)i}); - rewriter.create(loc, array, storage); + LLVM::StoreOp::create(rewriter, loc, array, storage); rewriter.replaceOp(op, SMTLoweringPattern::buildPtrAPICall( @@ -490,8 +490,8 @@ class LowerChainableSMTPattern : public SMTLoweringPattern { Location loc = op.getLoc(); SmallVector elements; for (int i = 1, e = adaptor.getOperands().size(); i < e; ++i) { - Value val = rewriter.create( - loc, op->getResultTypes(), + Value val = SourceTy::create( + rewriter, loc, op->getResultTypes(), ValueRange{adaptor.getOperands()[i - 1], adaptor.getOperands()[i]}); elements.push_back(val); } @@ -515,8 +515,8 @@ class LowerLeftAssocSMTPattern : public SMTLoweringPattern { Value runner = adaptor.getOperands()[0]; for (Value val : adaptor.getOperands().drop_front()) - runner = rewriter.create(op.getLoc(), op->getResultTypes(), - ValueRange{runner, val}); + runner = SourceTy::create(rewriter, op.getLoc(), op->getResultTypes(), + ValueRange{runner, val}); rewriter.replaceOp(op, runner); return success(); @@ -597,8 +597,8 @@ struct SolverOpLowering : public SMTLoweringPattern { Value ctx = buildCall(rewriter, loc, "Z3_mk_context", ptrToPtrFunc, config) .getResult(); Value ctxAddr = - rewriter.create(loc, globals.ctx).getResult(); - rewriter.create(loc, ctx, ctxAddr); + LLVM::AddressOfOp::create(rewriter, loc, globals.ctx).getResult(); + LLVM::StoreOp::create(rewriter, loc, ctx, ctxAddr); // Delete the configuration again. buildCall(rewriter, loc, "Z3_del_config", ptrToVoidFunc, {config}); @@ -618,8 +618,8 @@ struct SolverOpLowering : public SMTLoweringPattern { buildCall(rewriter, loc, "Z3_solver_inc_ref", ptrPtrToVoidFunc, {ctx, solver}); Value solverAddr = - rewriter.create(loc, globals.solver).getResult(); - rewriter.create(loc, solver, solverAddr); + LLVM::AddressOfOp::create(rewriter, loc, globals.solver).getResult(); + LLVM::StoreOp::create(rewriter, loc, solver, solverAddr); // This assumes that no constant hoisting of the like happens inbetween // the patterns defined in this pass because once the solver initialization @@ -638,8 +638,8 @@ struct SolverOpLowering : public SMTLoweringPattern { auto module = op->getParentOfType(); rewriter.setInsertionPointToEnd(module.getBody()); - funcOp = rewriter.create( - loc, globals.names.newName("solver"), + funcOp = func::FuncOp::create( + rewriter, loc, globals.names.newName("solver"), rewriter.getFunctionType(adaptor.getInputs().getTypes(), convertedTypes)); rewriter.inlineRegionBefore(op.getBodyRegion(), funcOp.getBody(), @@ -647,7 +647,7 @@ struct SolverOpLowering : public SMTLoweringPattern { } ValueRange results = - rewriter.create(loc, funcOp, adaptor.getInputs()) + func::CallOp::create(rewriter, loc, funcOp, adaptor.getInputs()) ->getResults(); // At the end of the region, decrease the solver's reference counter and @@ -740,8 +740,8 @@ struct PopOpLowering : public SMTLoweringPattern { matchAndRewrite(PopOp op, OpAdaptor adaptor, ConversionPatternRewriter &rewriter) const final { Location loc = op.getLoc(); - Value constVal = rewriter.create( - loc, rewriter.getI32Type(), op.getCount()); + Value constVal = LLVM::ConstantOp::create( + rewriter, loc, rewriter.getI32Type(), op.getCount()); buildAPICallWithContext(rewriter, loc, "Z3_solver_pop", LLVM::LLVMVoidType::get(getContext()), {buildSolverPtr(rewriter, loc), constVal}); @@ -831,12 +831,12 @@ struct CheckOpLowering : public SMTLoweringPattern { rewriter.getI32Type(), {solver}) ->getResult(0); Value constOne = - rewriter.create(loc, checkResult.getType(), 1); - Value isSat = rewriter.create(loc, LLVM::ICmpPredicate::eq, - checkResult, constOne); + LLVM::ConstantOp::create(rewriter, loc, checkResult.getType(), 1); + Value isSat = LLVM::ICmpOp::create(rewriter, loc, LLVM::ICmpPredicate::eq, + checkResult, constOne); // Simply inline the 'sat' region into the 'then' region of the 'scf.if' - auto satIfOp = rewriter.create(loc, resultTypes, isSat); + auto satIfOp = scf::IfOp::create(rewriter, loc, resultTypes, isSat); rewriter.inlineRegionBefore(op.getSatRegion(), satIfOp.getThenRegion(), satIfOp.getThenRegion().end()); @@ -845,11 +845,11 @@ struct CheckOpLowering : public SMTLoweringPattern { // two branches of this nested if-statement as well. rewriter.createBlock(&satIfOp.getElseRegion()); Value constNegOne = - rewriter.create(loc, checkResult.getType(), -1); - Value isUnsat = rewriter.create(loc, LLVM::ICmpPredicate::eq, - checkResult, constNegOne); - auto unsatIfOp = rewriter.create(loc, resultTypes, isUnsat); - rewriter.create(loc, unsatIfOp->getResults()); + LLVM::ConstantOp::create(rewriter, loc, checkResult.getType(), -1); + Value isUnsat = LLVM::ICmpOp::create(rewriter, loc, LLVM::ICmpPredicate::eq, + checkResult, constNegOne); + auto unsatIfOp = scf::IfOp::create(rewriter, loc, resultTypes, isUnsat); + scf::YieldOp::create(rewriter, loc, unsatIfOp->getResults()); rewriter.inlineRegionBefore(op.getUnsatRegion(), unsatIfOp.getThenRegion(), unsatIfOp.getThenRegion().end()); @@ -922,16 +922,16 @@ struct QuantifierLowering : public SMTLoweringPattern { Type ptrTy = LLVM::LLVMPointerType::get(rewriter.getContext()); Type arrTy = LLVM::LLVMArrayType::get(ptrTy, values.size()); Value constOne = - rewriter.create(loc, rewriter.getI32Type(), 1); + LLVM::ConstantOp::create(rewriter, loc, rewriter.getI32Type(), 1); Value storage = - rewriter.create(loc, ptrTy, arrTy, constOne); - Value array = rewriter.create(loc, arrTy); + LLVM::AllocaOp::create(rewriter, loc, ptrTy, arrTy, constOne); + Value array = LLVM::UndefOp::create(rewriter, loc, arrTy); for (auto [i, val] : llvm::enumerate(values)) - array = rewriter.create(loc, array, val, - ArrayRef(i)); + array = LLVM::InsertValueOp::create(rewriter, loc, array, val, + ArrayRef(i)); - rewriter.create(loc, array, storage); + LLVM::StoreOp::create(rewriter, loc, array, storage); return storage; } @@ -953,13 +953,13 @@ struct QuantifierLowering : public SMTLoweringPattern { rewriter.setInsertionPoint(op); // Weight attribute - Value weight = rewriter.create(loc, rewriter.getI32Type(), - adaptor.getWeight()); + Value weight = LLVM::ConstantOp::create( + rewriter, loc, rewriter.getI32Type(), adaptor.getWeight()); // Bound variables unsigned numDecls = op.getBody().getNumArguments(); - Value numDeclsVal = - rewriter.create(loc, rewriter.getI32Type(), numDecls); + Value numDeclsVal = LLVM::ConstantOp::create( + rewriter, loc, rewriter.getI32Type(), numDecls); // We replace the block arguments with constant symbolic values and inform // the quantifier API call which constants it should treat as bound @@ -970,11 +970,11 @@ struct QuantifierLowering : public SMTLoweringPattern { for (auto [i, arg] : llvm::enumerate(op.getBody().getArguments())) { Value newArg; if (adaptor.getBoundVarNames().has_value()) - newArg = rewriter.create( - loc, arg.getType(), + newArg = smt::DeclareFunOp::create( + rewriter, loc, arg.getType(), cast((*adaptor.getBoundVarNames())[i])); else - newArg = rewriter.create(loc, arg.getType()); + newArg = smt::DeclareFunOp::create(rewriter, loc, arg.getType()); repl.push_back(typeConverter->materializeTargetConversion( rewriter, loc, typeConverter->convertType(arg.getType()), newArg)); } @@ -994,8 +994,8 @@ struct QuantifierLowering : public SMTLoweringPattern { // Patterns unsigned numPatterns = adaptor.getPatterns().size(); - Value numPatternsVal = rewriter.create( - loc, rewriter.getI32Type(), numPatterns); + Value numPatternsVal = LLVM::ConstantOp::create( + rewriter, loc, rewriter.getI32Type(), numPatterns); Value patternStorage; if (numPatterns > 0) { @@ -1015,8 +1015,8 @@ struct QuantifierLowering : public SMTLoweringPattern { rewriter.inlineBlockBefore(&patternRegion->front(), op, repl); rewriter.setInsertionPoint(op); - Value numTerms = rewriter.create( - loc, rewriter.getI32Type(), patternTerms.size()); + Value numTerms = LLVM::ConstantOp::create( + rewriter, loc, rewriter.getI32Type(), patternTerms.size()); Value patternTermStorage = createStorageForValueList(patternList, loc, rewriter); Value pattern = buildPtrAPICall(rewriter, loc, "Z3_mk_pattern", @@ -1028,7 +1028,7 @@ struct QuantifierLowering : public SMTLoweringPattern { } else { // If we set the num_patterns parameter to 0, we can just pass a nullptr // as storage. - patternStorage = rewriter.create(loc, ptrTy); + patternStorage = LLVM::ZeroOp::create(rewriter, loc, ptrTy); } StringRef apiCallName = "Z3_mk_forall_const"; @@ -1054,8 +1054,8 @@ struct RepeatOpLowering : public SMTLoweringPattern { LogicalResult matchAndRewrite(RepeatOp op, OpAdaptor adaptor, ConversionPatternRewriter &rewriter) const final { - Value count = rewriter.create( - op.getLoc(), rewriter.getI32Type(), op.getCount()); + Value count = LLVM::ConstantOp::create( + rewriter, op.getLoc(), rewriter.getI32Type(), op.getCount()); rewriter.replaceOp(op, buildPtrAPICall(rewriter, op.getLoc(), "Z3_mk_repeat", {count, adaptor.getInput()})); @@ -1077,11 +1077,11 @@ struct ExtractOpLowering : public SMTLoweringPattern { matchAndRewrite(ExtractOp op, OpAdaptor adaptor, ConversionPatternRewriter &rewriter) const final { Location loc = op.getLoc(); - Value low = rewriter.create(loc, rewriter.getI32Type(), - adaptor.getLowBit()); - Value high = rewriter.create( - loc, rewriter.getI32Type(), - adaptor.getLowBit() + op.getType().getWidth() - 1); + Value low = LLVM::ConstantOp::create(rewriter, loc, rewriter.getI32Type(), + adaptor.getLowBit()); + Value high = LLVM::ConstantOp::create(rewriter, loc, rewriter.getI32Type(), + adaptor.getLowBit() + + op.getType().getWidth() - 1); rewriter.replaceOp(op, buildPtrAPICall(rewriter, loc, "Z3_mk_extract", {high, low, adaptor.getInput()})); return success(); @@ -1149,8 +1149,8 @@ struct IntConstantOpLowering : public SMTLoweringPattern { Location loc = op.getLoc(); Value type = buildPtrAPICall(rewriter, loc, "Z3_mk_int_sort"); if (adaptor.getValue().getBitWidth() <= 64) { - Value val = rewriter.create( - loc, rewriter.getI64Type(), adaptor.getValue().getSExtValue()); + Value val = LLVM::ConstantOp::create(rewriter, loc, rewriter.getI64Type(), + adaptor.getValue().getSExtValue()); rewriter.replaceOp( op, buildPtrAPICall(rewriter, loc, "Z3_mk_int64", {val, type})); return success(); @@ -1204,8 +1204,8 @@ struct Int2BVOpLowering : public SMTLoweringPattern { matchAndRewrite(Int2BVOp op, OpAdaptor adaptor, ConversionPatternRewriter &rewriter) const final { Value widthConst = - rewriter.create(op->getLoc(), rewriter.getI32Type(), - op.getResult().getType().getWidth()); + LLVM::ConstantOp::create(rewriter, op->getLoc(), rewriter.getI32Type(), + op.getResult().getType().getWidth()); rewriter.replaceOp(op, buildPtrAPICall(rewriter, op.getLoc(), "Z3_mk_int2bv", {widthConst, adaptor.getInput()})); @@ -1225,8 +1225,8 @@ struct BV2IntOpLowering : public SMTLoweringPattern { ConversionPatternRewriter &rewriter) const final { // FIXME: ideally we don't want to use i1 here, since bools can sometimes be // compiled to wider widths in LLVM - Value isSignedConst = rewriter.create( - op->getLoc(), rewriter.getI1Type(), op.getIsSigned()); + Value isSignedConst = LLVM::ConstantOp::create( + rewriter, op->getLoc(), rewriter.getI1Type(), op.getIsSigned()); rewriter.replaceOp(op, buildPtrAPICall(rewriter, op.getLoc(), "Z3_mk_bv2int", {adaptor.getInput(), isSignedConst})); @@ -1263,11 +1263,11 @@ struct IntAbsOpLowering : public SMTLoweringPattern { matchAndRewrite(IntAbsOp op, OpAdaptor adaptor, ConversionPatternRewriter &rewriter) const final { Location loc = op.getLoc(); - Value zero = rewriter.create( - loc, rewriter.getIntegerAttr(rewriter.getI1Type(), 0)); - Value cmp = rewriter.create(loc, IntPredicate::lt, - adaptor.getInput(), zero); - Value neg = rewriter.create(loc, zero, adaptor.getInput()); + Value zero = IntConstantOp::create( + rewriter, loc, rewriter.getIntegerAttr(rewriter.getI1Type(), 0)); + Value cmp = IntCmpOp::create(rewriter, loc, IntPredicate::lt, + adaptor.getInput(), zero); + Value neg = IntSubOp::create(rewriter, loc, zero, adaptor.getInput()); rewriter.replaceOpWithNewOp(op, cmp, neg, adaptor.getInput()); return success(); } diff --git a/lib/Conversion/SeqToSV/FirMemLowering.cpp b/lib/Conversion/SeqToSV/FirMemLowering.cpp index e8c745fb6f..3778848560 100644 --- a/lib/Conversion/SeqToSV/FirMemLowering.cpp +++ b/lib/Conversion/SeqToSV/FirMemLowering.cpp @@ -131,8 +131,8 @@ FlatSymbolRefAttr FirMemLowering::getOrCreateSchema() { "readUnderWrite", "writeUnderWrite", "writeClockIDs", "initFilename", "initIsBinary", "initIsInline"}; - schemaOp = builder.create( - circuit.getLoc(), "FIRRTLMem", "FIRRTL_Memory", + schemaOp = hw::HWGeneratorSchemaOp::create( + builder, circuit.getLoc(), "FIRRTLMem", "FIRRTL_Memory", builder.getStrArrayAttr(schemaFields)); } } @@ -292,8 +292,9 @@ FirMemLowering::createMemoryModule(FirMemConfig &mem, } // Create the module. - auto genOp = builder.create( - loc, schemaSymRef, name, ports, StringRef{}, ArrayAttr{}, genAttrs); + auto genOp = + hw::HWModuleGeneratedOp::create(builder, loc, schemaSymRef, name, ports, + StringRef{}, ArrayAttr{}, genAttrs); if (mem.outputFile) genOp->setAttr("output_file", mem.outputFile); @@ -313,8 +314,8 @@ void FirMemLowering::lowerMemoriesInModule( auto it = constOneOps.try_emplace(width, Value{}); if (it.second) { auto builder = OpBuilder::atBlockBegin(module.getBodyBlock()); - it.first->second = builder.create( - module.getLoc(), builder.getIntegerType(width), 1); + it.first->second = hw::ConstantOp::create( + builder, module.getLoc(), builder.getIntegerType(width), 1); } return it.first->second; }; @@ -374,9 +375,9 @@ void FirMemLowering::lowerMemoriesInModule( if (auto name = memOp.getName(); name && !name->empty()) memName = *name; ImplicitLocOpBuilder builder(memOp.getLoc(), memOp); - auto instOp = builder.create( - genOp, builder.getStringAttr(memName + "_ext"), inputs, ArrayAttr{}, - memOp.getInnerSymAttr()); + auto instOp = hw::InstanceOp::create( + builder, genOp, builder.getStringAttr(memName + "_ext"), inputs, + ArrayAttr{}, memOp.getInnerSymAttr()); for (auto [oldOutput, newOutput] : llvm::zip(outputs, instOp.getResults())) oldOutput.replaceAllUsesWith(newOutput); diff --git a/lib/Conversion/SeqToSV/FirRegLowering.cpp b/lib/Conversion/SeqToSV/FirRegLowering.cpp index 0e6b19f896..735c4eb743 100644 --- a/lib/Conversion/SeqToSV/FirRegLowering.cpp +++ b/lib/Conversion/SeqToSV/FirRegLowering.cpp @@ -104,7 +104,7 @@ void FirRegLowering::addToIfBlock(OpBuilder &builder, Value cond, // later. This way we don't have to build a new if and replace it. if (!op) { auto newIfOp = - builder.create(cond.getLoc(), cond, trueSide, falseSide); + sv::IfOp::create(builder, cond.getLoc(), cond, trueSide, falseSide); ifCache.insert({{builder.getBlock(), cond}, newIfOp}); } else { OpBuilder::InsertionGuard guard(builder); @@ -213,7 +213,7 @@ static hw::HierPathOp getHierPathTo(OpBuilder &builder, Namespace &ns, builder.setInsertionPoint(entry.reg->getParentOfType()); auto path = builder.getArrayAttr({entry.ref}); - return builder.create(entry.reg.getLoc(), name, path); + return hw::HierPathOp::create(builder, entry.reg.getLoc(), name, path); } FirRegLowering::PathTable FirRegLowering::createPaths(mlir::ModuleOp top) { @@ -296,8 +296,8 @@ SmallVector FirRegLowering::createRandomizationVector(OpBuilder &builder, // Create randomization vector SmallVector randValues; auto numRandomCalls = (maxBit + 31) / 32; - auto logic = builder.create( - loc, + auto logic = sv::LogicOp::create( + builder, loc, hw::UnpackedArrayType::get(builder.getIntegerType(32), numRandomCalls), "_RANDOM"); // Indvar's width must be equal to `ceil(log2(numRandomCalls + @@ -308,21 +308,23 @@ SmallVector FirRegLowering::createRandomizationVector(OpBuilder &builder, auto ub = getOrCreateConstant(loc, APInt(inducionVariableWidth, numRandomCalls)); auto step = getOrCreateConstant(loc, APInt(inducionVariableWidth, 1)); - auto forLoop = builder.create( - loc, lb, ub, step, "i", [&](BlockArgument iter) { - auto rhs = builder.create( - loc, builder.getIntegerType(32), "RANDOM"); + auto forLoop = sv::ForOp::create( + builder, loc, lb, ub, step, "i", [&](BlockArgument iter) { + auto rhs = sv::MacroRefExprSEOp::create( + builder, loc, builder.getIntegerType(32), "RANDOM"); Value iterValue = iter; if (!iter.getType().isInteger(arrayIndexWith)) - iterValue = builder.create(loc, iterValue, 0, - arrayIndexWith); - auto lhs = builder.create(loc, logic, iterValue); - builder.create(loc, lhs, rhs); + iterValue = comb::ExtractOp::create(builder, loc, iterValue, 0, + arrayIndexWith); + auto lhs = + sv::ArrayIndexInOutOp::create(builder, loc, logic, iterValue); + sv::BPAssignOp::create(builder, loc, lhs, rhs); }); builder.setInsertionPointAfter(forLoop); for (uint64_t x = 0; x < numRandomCalls; ++x) { - auto lhs = builder.create( - loc, logic, getOrCreateConstant(loc, APInt(arrayIndexWith, x))); + auto lhs = sv::ArrayIndexInOutOp::create( + builder, loc, logic, + getOrCreateConstant(loc, APInt(arrayIndexWith, x))); randValues.push_back(lhs.getResult()); } @@ -334,11 +336,11 @@ void FirRegLowering::createRandomInitialization(ImplicitLocOpBuilder &builder) { sv::MacroIdentAttr::get(builder.getContext(), "RANDOMIZE_REG_INIT"); if (!randomInitRegs.empty()) { - builder.create("INIT_RANDOM_PROLOG_", [&] { - builder.create("`INIT_RANDOM_PROLOG_"); + sv::IfDefProceduralOp::create(builder, "INIT_RANDOM_PROLOG_", [&] { + sv::VerbatimOp::create(builder, "`INIT_RANDOM_PROLOG_"); }); - builder.create(randInitRef, [&] { + sv::IfDefProceduralOp::create(builder, randInitRef, [&] { auto randValues = createRandomizationVector(builder, builder.getLoc()); for (auto &svReg : randomInitRegs) initialize(builder, svReg, randValues); @@ -356,9 +358,9 @@ void FirRegLowering::createPresetInitialization(ImplicitLocOpBuilder &builder) { if (cst.getType() == elemTy) rhs = cst; else - rhs = builder.create(loc, elemTy, cst); + rhs = hw::BitcastOp::create(builder, loc, elemTy, cst); - builder.create(loc, svReg.reg, rhs); + sv::BPAssignOp::create(builder, loc, svReg.reg, rhs); } } @@ -371,10 +373,10 @@ void FirRegLowering::createAsyncResetInitialization( // if (reset) begin // .. // end - builder.create(reset.first, [&] { + sv::IfOp::create(builder, reset.first, [&] { for (auto ® : reset.second) - builder.create(reg.reg.getLoc(), reg.reg, - reg.asyncResetValue); + sv::BPAssignOp::create(builder, reg.reg.getLoc(), reg.reg, + reg.asyncResetValue); }); } } @@ -401,20 +403,20 @@ void FirRegLowering::createInitialBlock() { auto builder = ImplicitLocOpBuilder::atBlockTerminator(loc, module.getBodyBlock()); - builder.create("ENABLE_INITIAL_REG_", [&] { - builder.create([&] { - builder.create("FIRRTL_BEFORE_INITIAL", [&] { - builder.create("`FIRRTL_BEFORE_INITIAL"); + sv::IfDefOp::create(builder, "ENABLE_INITIAL_REG_", [&] { + sv::OrderedOutputOp::create(builder, [&] { + sv::IfDefOp::create(builder, "FIRRTL_BEFORE_INITIAL", [&] { + sv::VerbatimOp::create(builder, "`FIRRTL_BEFORE_INITIAL"); }); - builder.create([&] { + sv::InitialOp::create(builder, [&] { createRandomInitialization(builder); createPresetInitialization(builder); createAsyncResetInitialization(builder); }); - builder.create("FIRRTL_AFTER_INITIAL", [&] { - builder.create("`FIRRTL_AFTER_INITIAL"); + sv::IfDefOp::create(builder, "FIRRTL_AFTER_INITIAL", [&] { + sv::VerbatimOp::create(builder, "`FIRRTL_AFTER_INITIAL"); }); }); }); @@ -566,7 +568,7 @@ void FirRegLowering::createTree(OpBuilder &builder, Value reg, Value term, // Create an array index op just after `reg`. OpBuilder::InsertionGuard guard(builder); builder.setInsertionPointAfterValue(reg); - return builder.create(reg.getLoc(), reg, idx); + return sv::ArrayIndexInOutOp::create(builder, reg.getLoc(), reg, idx); }; SmallVector opsToDelete; @@ -588,7 +590,7 @@ void FirRegLowering::createTree(OpBuilder &builder, Value reg, Value term, if (mux && mux.getTwoState() && reachableMuxes->isMuxReachableFrom(firReg, mux)) { if (counter >= limit) { - builder.create(term.getLoc(), reg, next); + sv::PAssignOp::create(builder, term.getLoc(), reg, next); continue; } addToIfBlock( @@ -614,7 +616,7 @@ void FirRegLowering::createTree(OpBuilder &builder, Value reg, Value term, // recursive calls. Add the value to `opsToDelete` so that it can // be deleted afterwards. auto termElement = - builder.create(term.getLoc(), term, index); + hw::ArrayGetOp::create(builder, term.getLoc(), term, index); opsToDelete.push_back(termElement); addToWorklist(nextReg, termElement, trueValue); }, @@ -642,14 +644,14 @@ void FirRegLowering::createTree(OpBuilder &builder, Value reg, Value term, // recursive calls. Add the value to `opsToDelete` so that it can // be deleted afterwards. auto termElement = - builder.create(term.getLoc(), term, idxVal); + hw::ArrayGetOp::create(builder, term.getLoc(), term, idxVal); opsToDelete.push_back(termElement); addToWorklist(index, termElement, value); } continue; } - builder.create(term.getLoc(), reg, next); + sv::PAssignOp::create(builder, term.getLoc(), reg, next); } while (!opsToDelete.empty()) { @@ -671,7 +673,7 @@ void FirRegLowering::lowerReg(FirRegOp reg) { ImplicitLocOpBuilder builder(reg.getLoc(), reg); RegLowerInfo svReg{nullptr, path, reg.getPresetAttr(), nullptr, nullptr, -1, 0}; - svReg.reg = builder.create(loc, regTy, reg.getNameAttr()); + svReg.reg = sv::RegOp::create(builder, loc, regTy, reg.getNameAttr()); svReg.width = hw::getBitWidth(regTy); if (auto attr = reg->getAttrOfType("firrtl.random_init_start")) @@ -686,7 +688,7 @@ void FirRegLowering::lowerReg(FirRegOp reg) { if (auto innerSymAttr = reg.getInnerSymAttr()) svReg.reg.setInnerSymAttr(innerSymAttr); - auto regVal = builder.create(loc, svReg.reg); + auto regVal = sv::ReadInOutOp::create(builder, loc, svReg.reg); if (reg.hasReset()) { addToAlwaysBlock( @@ -695,14 +697,14 @@ void FirRegLowering::lowerReg(FirRegOp reg) { // If this is an AsyncReset, ensure that we emit a self connect to // avoid erroneously creating a latch construct. if (reg.getIsAsync() && areEquivalentValues(reg, reg.getNext())) - b.create(reg.getLoc(), svReg.reg, reg); + sv::PAssignOp::create(b, reg.getLoc(), svReg.reg, reg); else createTree(b, svReg.reg, reg, reg.getNext()); }, reg.getIsAsync() ? sv::ResetType::AsyncReset : sv::ResetType::SyncReset, sv::EventControl::AtPosEdge, reg.getReset(), [&](OpBuilder &builder) { - builder.create(loc, svReg.reg, reg.getResetValue()); + sv::PAssignOp::create(builder, loc, svReg.reg, reg.getResetValue()); }); if (reg.getIsAsync()) { svReg.asyncResetSignal = reg.getReset(); @@ -749,19 +751,19 @@ void FirRegLowering::initializeRegisterElements(Location loc, pos -= intTy.getWidth(); auto elem = builder.createOrFold(loc, randomSource, pos, intTy.getWidth()); - builder.create(loc, reg, elem); + sv::BPAssignOp::create(builder, loc, reg, elem); } else if (auto array = hw::type_dyn_cast(type)) { for (unsigned i = 0, e = array.getNumElements(); i < e; ++i) { auto index = getOrCreateConstant(loc, APInt(llvm::Log2_64_Ceil(e), i)); initializeRegisterElements( - loc, builder, builder.create(loc, reg, index), + loc, builder, sv::ArrayIndexInOutOp::create(builder, loc, reg, index), randomSource, pos); } } else if (auto structType = hw::type_dyn_cast(type)) { for (auto e : structType.getElements()) initializeRegisterElements( loc, builder, - builder.create(loc, reg, e.name), + sv::StructFieldInOutOp::create(builder, loc, reg, e.name), randomSource, pos); } else { assert(false && "unsupported type"); @@ -780,14 +782,14 @@ void FirRegLowering::buildRegConditions(OpBuilder &b, sv::RegOp reg) { for (auto &condition : conditions) { auto kind = condition.getKind(); if (kind == RegCondition::IfDefThen) { - auto ifDef = b.create( - reg.getLoc(), condition.getMacro(), []() {}); + auto ifDef = sv::IfDefProceduralOp::create(b, reg.getLoc(), + condition.getMacro(), []() {}); b.setInsertionPointToEnd(ifDef.getThenBlock()); continue; } if (kind == RegCondition::IfDefElse) { - auto ifDef = b.create( - reg.getLoc(), condition.getMacro(), []() {}, []() {}); + auto ifDef = sv::IfDefProceduralOp::create( + b, reg.getLoc(), condition.getMacro(), []() {}, []() {}); b.setInsertionPointToEnd(ifDef.getElseBlock()); continue; @@ -800,7 +802,7 @@ static Value buildXMRTo(OpBuilder &builder, HierPathOp path, Location loc, Type type) { auto name = path.getSymNameAttr(); auto ref = mlir::FlatSymbolRefAttr::get(name); - return builder.create(loc, type, ref); + return sv::XMRRefOp::create(builder, loc, type, ref); } void FirRegLowering::initialize(OpBuilder &builder, RegLowerInfo reg, @@ -830,7 +832,7 @@ void FirRegLowering::initialize(OpBuilder &builder, RegLowerInfo reg, auto index = offset / 32; auto start = offset % 32; auto nwidth = std::min(32 - start, width); - auto elemVal = builder.create(loc, rands[index]); + auto elemVal = sv::ReadInOutOp::create(builder, loc, rands[index]); auto elem = builder.createOrFold(loc, elemVal, start, nwidth); nibbles.push_back(elem); @@ -877,24 +879,24 @@ void FirRegLowering::addToAlwaysBlock( auto createIfOp = [&]() { // It is weird but intended. Here we want to create an empty sv.if // with an else block. - insideIfOp = builder.create( - reset, []() {}, []() {}); + insideIfOp = sv::IfOp::create( + builder, reset, []() {}, []() {}); }; if (resetStyle == sv::ResetType::AsyncReset) { sv::EventControl events[] = {clockEdge, resetEdge}; Value clocks[] = {clock, reset}; - alwaysOp = builder.create(events, clocks, [&]() { + alwaysOp = sv::AlwaysOp::create(builder, events, clocks, [&]() { if (resetEdge == sv::EventControl::AtNegEdge) llvm_unreachable("negative edge for reset is not expected"); createIfOp(); }); } else { - alwaysOp = builder.create(clockEdge, clock, createIfOp); + alwaysOp = sv::AlwaysOp::create(builder, clockEdge, clock, createIfOp); } } else { assert(!resetBody); - alwaysOp = builder.create(clockEdge, clock); + alwaysOp = sv::AlwaysOp::create(builder, clockEdge, clock); insideIfOp = nullptr; } } diff --git a/lib/Conversion/SeqToSV/SeqToSV.cpp b/lib/Conversion/SeqToSV/SeqToSV.cpp index ac361b2b97..c27f0e5eb0 100644 --- a/lib/Conversion/SeqToSV/SeqToSV.cpp +++ b/lib/Conversion/SeqToSV/SeqToSV.cpp @@ -102,7 +102,7 @@ LogicalResult ModuleLoweringState::ImmutableValueLowering::lower(seq::InitialOp initialOp) { OpBuilder builder = OpBuilder::atBlockBegin(module.getBodyBlock()); if (!svInitialOp) - svInitialOp = builder.create(initialOp->getLoc()); + svInitialOp = sv::InitialOp::create(builder, initialOp->getLoc()); // Initial ops are merged to single one and must not have operands. assert(initialOp.getNumOperands() == 0 && "initial op should have no operands"); @@ -115,9 +115,8 @@ ModuleLoweringState::ImmutableValueLowering::lower(seq::InitialOp initialOp) { for (auto [result, operand] : llvm::zip(initialOp.getResults(), yieldOp->getOperands())) { auto placeholder = - builder - .create( - loc, ArrayRef{result.getType()}, ArrayRef{}) + mlir::UnrealizedConversionCastOp::create( + builder, loc, ArrayRef{result.getType()}, ArrayRef{}) ->getResult(0); result.replaceAllUsesWith(placeholder); mapping.insert( @@ -154,20 +153,20 @@ public: auto regTy = ConversionPattern::getTypeConverter()->convertType(reg.getType()); - auto svReg = rewriter.create(loc, regTy, reg.getNameAttr(), - reg.getInnerSymAttr()); + auto svReg = sv::RegOp::create(rewriter, loc, regTy, reg.getNameAttr(), + reg.getInnerSymAttr()); svReg->setDialectAttrs(reg->getDialectAttrs()); circt::sv::setSVAttributes(svReg, circt::sv::getSVAttributes(reg)); - auto regVal = rewriter.create(loc, svReg); + auto regVal = sv::ReadInOutOp::create(rewriter, loc, svReg); auto assignValue = [&] { createAssign(rewriter, reg.getLoc(), svReg, reg); }; auto assignReset = [&] { - rewriter.create(loc, svReg, adaptor.getResetValue()); + sv::PAssignOp::create(rewriter, loc, svReg, adaptor.getResetValue()); }; // Registers written in an `always_ff` process may not have any assignments @@ -177,24 +176,24 @@ public: if (adaptor.getReset() && adaptor.getResetValue()) { if (mayLowerToAlwaysFF) { - rewriter.create( - loc, sv::EventControl::AtPosEdge, adaptor.getClk(), - sv::ResetType::SyncReset, sv::EventControl::AtPosEdge, - adaptor.getReset(), assignValue, assignReset); + sv::AlwaysFFOp::create(rewriter, loc, sv::EventControl::AtPosEdge, + adaptor.getClk(), sv::ResetType::SyncReset, + sv::EventControl::AtPosEdge, adaptor.getReset(), + assignValue, assignReset); } else { - rewriter.create( - loc, sv::EventControl::AtPosEdge, adaptor.getClk(), [&] { - rewriter.create(loc, adaptor.getReset(), assignReset, - assignValue); + sv::AlwaysOp::create( + rewriter, loc, sv::EventControl::AtPosEdge, adaptor.getClk(), [&] { + sv::IfOp::create(rewriter, loc, adaptor.getReset(), assignReset, + assignValue); }); } } else { if (mayLowerToAlwaysFF) { - rewriter.create(loc, sv::EventControl::AtPosEdge, - adaptor.getClk(), assignValue); + sv::AlwaysFFOp::create(rewriter, loc, sv::EventControl::AtPosEdge, + adaptor.getClk(), assignValue); } else { - rewriter.create(loc, sv::EventControl::AtPosEdge, - adaptor.getClk(), assignValue); + sv::AlwaysOp::create(rewriter, loc, sv::EventControl::AtPosEdge, + adaptor.getClk(), assignValue); } } @@ -216,7 +215,7 @@ public: OpBuilder::InsertionGuard guard(rewriter); auto in = initial.getSVInitial(); rewriter.setInsertionPointToEnd(in.getBodyBlock()); - rewriter.create(reg->getLoc(), svReg, initialValue); + sv::BPAssignOp::create(rewriter, reg->getLoc(), svReg, initialValue); } } @@ -238,15 +237,15 @@ template <> void CompRegLower::createAssign(ConversionPatternRewriter &rewriter, Location loc, sv::RegOp svReg, OpAdaptor reg) const { - rewriter.create(loc, svReg, reg.getInput()); + sv::PAssignOp::create(rewriter, loc, svReg, reg.getInput()); } /// Create the assign inside of an if block. template <> void CompRegLower::createAssign( ConversionPatternRewriter &rewriter, Location loc, sv::RegOp svReg, OpAdaptor reg) const { - rewriter.create(loc, reg.getClockEnable(), [&]() { - rewriter.create(loc, svReg, reg.getInput()); + sv::IfOp::create(rewriter, loc, reg.getClockEnable(), [&]() { + sv::PAssignOp::create(rewriter, loc, svReg, reg.getInput()); }); } @@ -268,9 +267,9 @@ public: auto regTy = ConversionPattern::getTypeConverter()->convertType( fromImmutableOp.getType()); - auto svReg = rewriter.create(loc, regTy); + auto svReg = sv::RegOp::create(rewriter, loc, regTy); - auto regVal = rewriter.create(loc, svReg); + auto regVal = sv::ReadInOutOp::create(rewriter, loc, svReg); // Lower initial values. auto module = fromImmutableOp->template getParentOfType(); @@ -283,8 +282,8 @@ public: OpBuilder::InsertionGuard guard(rewriter); auto in = initial.getSVInitial(); rewriter.setInsertionPointToEnd(in.getBodyBlock()); - rewriter.create(fromImmutableOp->getLoc(), svReg, - initialValue); + sv::BPAssignOp::create(rewriter, fromImmutableOp->getLoc(), svReg, + initialValue); rewriter.replaceOp(fromImmutableOp, regVal); return success(); @@ -308,25 +307,26 @@ public: // enable in Value enable = adaptor.getEnable(); if (auto te = adaptor.getTestEnable()) - enable = rewriter.create(loc, enable, te); + enable = comb::OrOp::create(rewriter, loc, enable, te); // Enable latch. - Value enableLatch = rewriter.create( - loc, rewriter.getI1Type(), rewriter.getStringAttr("cg_en_latch")); + Value enableLatch = + sv::RegOp::create(rewriter, loc, rewriter.getI1Type(), + rewriter.getStringAttr("cg_en_latch")); // Latch the enable signal using an always @* block. - rewriter.create( - loc, llvm::SmallVector{}, llvm::SmallVector{}, - [&]() { - rewriter.create( - loc, comb::createOrFoldNot(loc, clk, rewriter), [&]() { - rewriter.create(loc, enableLatch, enable); + sv::AlwaysOp::create( + rewriter, loc, llvm::SmallVector{}, + llvm::SmallVector{}, [&]() { + sv::IfOp::create( + rewriter, loc, comb::createOrFoldNot(loc, clk, rewriter), [&]() { + sv::PAssignOp::create(rewriter, loc, enableLatch, enable); }); }); // Create the gated clock signal. rewriter.replaceOpWithNewOp( - clockGate, clk, rewriter.create(loc, enableLatch)); + clockGate, clk, sv::ReadInOutOp::create(rewriter, loc, enableLatch)); return success(); } }; @@ -344,7 +344,7 @@ public: Value clk = adaptor.getInput(); StringAttr name = op->getAttrOfType("sv.namehint"); - Value one = rewriter.create(loc, APInt(1, 1)); + Value one = hw::ConstantOp::create(rewriter, loc, APInt(1, 1)); auto newOp = rewriter.replaceOpWithNewOp(op, clk, one); if (name) rewriter.modifyOpInPlace(newOp, @@ -408,8 +408,8 @@ struct SeqToSVTypeConverter : public TypeConverter { mlir::Location loc) -> mlir::Value { if (inputs.size() != 1) return Value(); - return builder - .create(loc, resultType, inputs[0]) + return mlir::UnrealizedConversionCastOp::create(builder, loc, resultType, + inputs[0]) ->getResult(0); }); @@ -418,8 +418,8 @@ struct SeqToSVTypeConverter : public TypeConverter { mlir::Location loc) -> mlir::Value { if (inputs.size() != 1) return Value(); - return builder - .create(loc, resultType, inputs[0]) + return mlir::UnrealizedConversionCastOp::create(builder, loc, resultType, + inputs[0]) ->getResult(0); }); } @@ -498,33 +498,33 @@ public: Value one; if (clockDiv.getPow2()) { - one = rewriter.create(loc, APInt(1, 1)); + one = hw::ConstantOp::create(rewriter, loc, APInt(1, 1)); } Value output = clockDiv.getInput(); SmallVector regs; for (unsigned i = 0; i < clockDiv.getPow2(); ++i) { - Value reg = rewriter.create( - loc, rewriter.getI1Type(), + Value reg = sv::RegOp::create( + rewriter, loc, rewriter.getI1Type(), rewriter.getStringAttr("clock_out_" + std::to_string(i))); regs.push_back(reg); - rewriter.create( - loc, sv::EventControl::AtPosEdge, output, [&] { - Value outputVal = rewriter.create(loc, reg); - Value inverted = rewriter.create(loc, outputVal, one); - rewriter.create(loc, reg, inverted); + sv::AlwaysOp::create( + rewriter, loc, sv::EventControl::AtPosEdge, output, [&] { + Value outputVal = sv::ReadInOutOp::create(rewriter, loc, reg); + Value inverted = comb::XorOp::create(rewriter, loc, outputVal, one); + sv::BPAssignOp::create(rewriter, loc, reg, inverted); }); - output = rewriter.create(loc, reg); + output = sv::ReadInOutOp::create(rewriter, loc, reg); } if (!regs.empty()) { - Value zero = rewriter.create(loc, APInt(1, 0)); - rewriter.create(loc, [&] { + Value zero = hw::ConstantOp::create(rewriter, loc, APInt(1, 0)); + sv::InitialOp::create(rewriter, loc, [&] { for (Value reg : regs) { - rewriter.create(loc, reg, zero); + sv::BPAssignOp::create(rewriter, loc, reg, zero); } }); } @@ -719,20 +719,20 @@ void SeqToSVPass::runOnOperation() { auto loc = UnknownLoc::get(context); auto b = ImplicitLocOpBuilder::atBlockBegin(loc, circuit.getBody()); if (needsRegRandomization || needsMemRandomization) { - b.create("ENABLE_INITIAL_REG_"); - b.create("ENABLE_INITIAL_MEM_"); + sv::MacroDeclOp::create(b, "ENABLE_INITIAL_REG_"); + sv::MacroDeclOp::create(b, "ENABLE_INITIAL_MEM_"); if (needsRegRandomization) { - b.create("FIRRTL_BEFORE_INITIAL"); - b.create("FIRRTL_AFTER_INITIAL"); + sv::MacroDeclOp::create(b, "FIRRTL_BEFORE_INITIAL"); + sv::MacroDeclOp::create(b, "FIRRTL_AFTER_INITIAL"); } if (needsMemRandomization) - b.create("RANDOMIZE_MEM_INIT"); - b.create("RANDOMIZE_REG_INIT"); - b.create("RANDOMIZE"); - b.create("RANDOMIZE_DELAY"); - b.create("RANDOM"); - b.create("INIT_RANDOM"); - b.create("INIT_RANDOM_PROLOG_"); + sv::MacroDeclOp::create(b, "RANDOMIZE_MEM_INIT"); + sv::MacroDeclOp::create(b, "RANDOMIZE_REG_INIT"); + sv::MacroDeclOp::create(b, "RANDOMIZE"); + sv::MacroDeclOp::create(b, "RANDOMIZE_DELAY"); + sv::MacroDeclOp::create(b, "RANDOM"); + sv::MacroDeclOp::create(b, "INIT_RANDOM"); + sv::MacroDeclOp::create(b, "INIT_RANDOM_PROLOG_"); } bool hasRegRandomization = needsRegRandomization && !disableRegRandomization; @@ -755,9 +755,9 @@ void SeqToSVPass::runOnOperation() { for (auto sym : circuit.getOps()) symbols.insert(sym.getName()); if (!symbols.count("SYNTHESIS")) - b.create("SYNTHESIS"); + sv::MacroDeclOp::create(b, "SYNTHESIS"); if (!symbols.count("VERILATOR")) - b.create("VERILATOR"); + sv::MacroDeclOp::create(b, "VERILATOR"); } // TODO: We could have an operation for macros and uses of them, and @@ -767,66 +767,66 @@ void SeqToSVPass::runOnOperation() { StringRef defineFalse = StringRef()) { if (!defineFalse.data()) { assert(defineTrue.data() && "didn't define anything"); - b.create( - guard, [&]() { b.create(defName, defineTrue); }); + sv::IfDefOp::create( + b, guard, [&]() { sv::MacroDefOp::create(b, defName, defineTrue); }); } else { - b.create( - guard, + sv::IfDefOp::create( + b, guard, [&]() { if (defineTrue.data()) - b.create(defName, defineTrue); + sv::MacroDefOp::create(b, defName, defineTrue); }, - [&]() { b.create(defName, defineFalse); }); + [&]() { sv::MacroDefOp::create(b, defName, defineFalse); }); } }; // Helper function to emit #ifndef guard. auto emitGuard = [&](const char *guard, llvm::function_ref body) { - b.create( - guard, []() {}, body); + sv::IfDefOp::create( + b, guard, []() {}, body); }; - b.create(randomInitFragmentName.getAttr(), [&] { - b.create( - "// Standard header to adapt well known macros for " - "register randomization."); + emit::FragmentOp::create(b, randomInitFragmentName.getAttr(), [&] { + sv::VerbatimOp::create(b, + "// Standard header to adapt well known macros for " + "register randomization."); - b.create( - "\n// RANDOM may be set to an expression that produces a 32-bit " - "random unsigned value."); + sv::VerbatimOp::create( + b, "\n// RANDOM may be set to an expression that produces a 32-bit " + "random unsigned value."); emitGuardedDefine("RANDOM", "RANDOM", StringRef(), "$random"); - b.create( - "\n// Users can define INIT_RANDOM as general code that gets " - "injected " - "into the\n// initializer block for modules with registers."); + sv::VerbatimOp::create( + b, "\n// Users can define INIT_RANDOM as general code that gets " + "injected " + "into the\n// initializer block for modules with registers."); emitGuardedDefine("INIT_RANDOM", "INIT_RANDOM", StringRef(), ""); - b.create( - "\n// If using random initialization, you can also define " - "RANDOMIZE_DELAY to\n// customize the delay used, otherwise 0.002 " - "is used."); + sv::VerbatimOp::create( + b, "\n// If using random initialization, you can also define " + "RANDOMIZE_DELAY to\n// customize the delay used, otherwise 0.002 " + "is used."); emitGuardedDefine("RANDOMIZE_DELAY", "RANDOMIZE_DELAY", StringRef(), "0.002"); - b.create( - "\n// Define INIT_RANDOM_PROLOG_ for use in our modules below."); + sv::VerbatimOp::create( + b, "\n// Define INIT_RANDOM_PROLOG_ for use in our modules below."); emitGuard("INIT_RANDOM_PROLOG_", [&]() { - b.create( - "RANDOMIZE", + sv::IfDefOp::create( + b, "RANDOMIZE", [&]() { emitGuardedDefine("VERILATOR", "INIT_RANDOM_PROLOG_", "`INIT_RANDOM", "`INIT_RANDOM #`RANDOMIZE_DELAY begin end"); }, - [&]() { b.create("INIT_RANDOM_PROLOG_", ""); }); + [&]() { sv::MacroDefOp::create(b, "INIT_RANDOM_PROLOG_", ""); }); }); }); if (hasMemRandomization) { - b.create(randomInitMemFragmentName.getAttr(), [&] { - b.create("\n// Include rmemory initializers in init " - "blocks unless synthesis is set"); + emit::FragmentOp::create(b, randomInitMemFragmentName.getAttr(), [&] { + sv::VerbatimOp::create(b, "\n// Include rmemory initializers in init " + "blocks unless synthesis is set"); emitGuard("RANDOMIZE", [&]() { emitGuardedDefine("RANDOMIZE_MEM_INIT", "RANDOMIZE"); }); @@ -834,14 +834,14 @@ void SeqToSVPass::runOnOperation() { emitGuardedDefine("ENABLE_INITIAL_MEM_", "ENABLE_INITIAL_MEM_", StringRef(), ""); }); - b.create(""); + sv::VerbatimOp::create(b, ""); }); } if (hasRegRandomization) { - b.create(randomInitRegFragmentName.getAttr(), [&] { - b.create("\n// Include register initializers in init " - "blocks unless synthesis is set"); + emit::FragmentOp::create(b, randomInitRegFragmentName.getAttr(), [&] { + sv::VerbatimOp::create(b, "\n// Include register initializers in init " + "blocks unless synthesis is set"); emitGuard("RANDOMIZE", [&]() { emitGuardedDefine("RANDOMIZE_REG_INIT", "RANDOMIZE"); }); @@ -849,7 +849,7 @@ void SeqToSVPass::runOnOperation() { emitGuardedDefine("ENABLE_INITIAL_REG_", "ENABLE_INITIAL_REG_", StringRef(), ""); }); - b.create(""); + sv::VerbatimOp::create(b, ""); }); } } diff --git a/lib/Conversion/SimToSV/SimToSV.cpp b/lib/Conversion/SimToSV/SimToSV.cpp index e854e4cc46..4bcae887ac 100644 --- a/lib/Conversion/SimToSV/SimToSV.cpp +++ b/lib/Conversion/SimToSV/SimToSV.cpp @@ -65,13 +65,13 @@ public: ConversionPatternRewriter &rewriter) const final { auto loc = op.getLoc(); auto resultType = rewriter.getIntegerType(1); - auto str = rewriter.create(loc, op.getFormatString()); - auto reg = rewriter.create(loc, resultType, - rewriter.getStringAttr("_pargs")); - rewriter.create(loc, [&] { - auto call = rewriter.create( - loc, resultType, "test$plusargs", ArrayRef{str}); - rewriter.create(loc, reg, call); + auto str = sv::ConstantStrOp::create(rewriter, loc, op.getFormatString()); + auto reg = sv::RegOp::create(rewriter, loc, resultType, + rewriter.getStringAttr("_pargs")); + sv::InitialOp::create(rewriter, loc, [&] { + auto call = sv::SystemFunctionOp::create( + rewriter, loc, resultType, "test$plusargs", ArrayRef{str}); + sv::BPAssignOp::create(rewriter, loc, reg, call); }); rewriter.replaceOpWithNewOp(op, reg); @@ -93,18 +93,18 @@ public: auto i1ty = rewriter.getIntegerType(1); auto type = op.getResult().getType(); - auto wirev = rewriter.create( - loc, type, rewriter.getStringAttr("_pargs_v")); - auto wiref = rewriter.create( - loc, i1ty, rewriter.getStringAttr("_pargs_f")); + auto wirev = sv::WireOp::create(rewriter, loc, type, + rewriter.getStringAttr("_pargs_v")); + auto wiref = sv::WireOp::create(rewriter, loc, i1ty, + rewriter.getStringAttr("_pargs_f")); state.usedSynthesisMacro = true; - rewriter.create( - loc, "SYNTHESIS", + sv::IfDefOp::create( + rewriter, loc, "SYNTHESIS", [&]() { - auto cstFalse = rewriter.create(loc, APInt(1, 0)); - auto cstZ = rewriter.create(loc, type); - auto assignZ = rewriter.create(loc, wirev, cstZ); + auto cstFalse = hw::ConstantOp::create(rewriter, loc, APInt(1, 0)); + auto cstZ = sv::ConstantZOp::create(rewriter, loc, type); + auto assignZ = sv::AssignOp::create(rewriter, loc, wirev, cstZ); circt::sv::setSVAttributes( assignZ, sv::SVAttributeAttr::get( @@ -112,33 +112,34 @@ public: "This dummy assignment exists to avoid undriven lint " "warnings (e.g., Verilator UNDRIVEN).", /*emitAsComment=*/true)); - rewriter.create(loc, wiref, cstFalse); + sv::AssignOp::create(rewriter, loc, wiref, cstFalse); }, [&]() { auto i32ty = rewriter.getIntegerType(32); - auto regf = rewriter.create( - loc, i32ty, rewriter.getStringAttr("_found")); - auto regv = rewriter.create( - loc, type, rewriter.getStringAttr("_value")); - rewriter.create(loc, [&] { + auto regf = sv::RegOp::create(rewriter, loc, i32ty, + rewriter.getStringAttr("_found")); + auto regv = sv::RegOp::create(rewriter, loc, type, + rewriter.getStringAttr("_value")); + sv::InitialOp::create(rewriter, loc, [&] { auto str = - rewriter.create(loc, op.getFormatString()); - auto call = rewriter.create( - loc, i32ty, "value$plusargs", ArrayRef{str, regv}); - rewriter.create(loc, regf, call); + sv::ConstantStrOp::create(rewriter, loc, op.getFormatString()); + auto call = sv::SystemFunctionOp::create( + rewriter, loc, i32ty, "value$plusargs", + ArrayRef{str, regv}); + sv::BPAssignOp::create(rewriter, loc, regf, call); }); - Value readRegF = rewriter.create(loc, regf); - Value readRegV = rewriter.create(loc, regv); - auto cstTrue = rewriter.create(loc, i32ty, 1); + Value readRegF = sv::ReadInOutOp::create(rewriter, loc, regf); + Value readRegV = sv::ReadInOutOp::create(rewriter, loc, regv); + auto cstTrue = hw::ConstantOp::create(rewriter, loc, i32ty, 1); // Squash any X coming from the regf to 0. - auto cmp = rewriter.create( - loc, comb::ICmpPredicate::ceq, readRegF, cstTrue); - rewriter.create(loc, wiref, cmp); - rewriter.create(loc, wirev, readRegV); + auto cmp = comb::ICmpOp::create( + rewriter, loc, comb::ICmpPredicate::ceq, readRegF, cstTrue); + sv::AssignOp::create(rewriter, loc, wiref, cmp); + sv::AssignOp::create(rewriter, loc, wirev, readRegV); }); - Value readf = rewriter.create(loc, wiref); - Value readv = rewriter.create(loc, wirev); + Value readf = sv::ReadInOutOp::create(rewriter, loc, wiref); + Value readv = sv::ReadInOutOp::create(rewriter, loc, wirev); rewriter.replaceOp(op, {readf, readv}); return success(); @@ -155,16 +156,16 @@ public: ConversionPatternRewriter &rewriter) const final { auto loc = op.getLoc(); - Value clockCast = rewriter.create(loc, adaptor.getClk()); + Value clockCast = seq::FromClockOp::create(rewriter, loc, adaptor.getClk()); this->state.usedSynthesisMacro = true; - rewriter.create( - loc, "SYNTHESIS", [&] {}, + sv::IfDefOp::create( + rewriter, loc, "SYNTHESIS", [&] {}, [&] { - rewriter.create( - loc, sv::EventControl::AtPosEdge, clockCast, [&] { - rewriter.create(loc, adaptor.getCond(), - [&] { rewriter.create(loc); }); + sv::AlwaysOp::create( + rewriter, loc, sv::EventControl::AtPosEdge, clockCast, [&] { + sv::IfOp::create(rewriter, loc, adaptor.getCond(), + [&] { ToOp::create(rewriter, loc); }); }); }); @@ -192,49 +193,50 @@ public: SmallVector reads; for (auto [type, result] : llvm::zip(op.getResultTypes(), op.getResults())) { - temporaries.push_back(rewriter.create(op.getLoc(), type)); + temporaries.push_back(sv::RegOp::create(rewriter, op.getLoc(), type)); reads.push_back( - rewriter.create(op.getLoc(), temporaries.back())); + sv::ReadInOutOp::create(rewriter, op.getLoc(), temporaries.back())); } auto emitCall = [&]() { - auto call = rewriter.create( - op.getLoc(), op.getResultTypes(), op.getCalleeAttr(), + auto call = sv::FuncCallProceduralOp::create( + rewriter, op.getLoc(), op.getResultTypes(), op.getCalleeAttr(), adaptor.getInputs()); for (auto [lhs, rhs] : llvm::zip(temporaries, call.getResults())) { if (isClockedCall) - rewriter.create(op.getLoc(), lhs, rhs); + sv::PAssignOp::create(rewriter, op.getLoc(), lhs, rhs); else - rewriter.create(op.getLoc(), lhs, rhs); + sv::BPAssignOp::create(rewriter, op.getLoc(), lhs, rhs); } }; if (isClockedCall) { Value clockCast = - rewriter.create(loc, adaptor.getClock()); - rewriter.create( - loc, ArrayRef{sv::EventControl::AtPosEdge}, + seq::FromClockOp::create(rewriter, loc, adaptor.getClock()); + sv::AlwaysOp::create( + rewriter, loc, + ArrayRef{sv::EventControl::AtPosEdge}, ArrayRef{clockCast}, [&]() { if (!hasEnable) return emitCall(); - rewriter.create(op.getLoc(), adaptor.getEnable(), - emitCall); + sv::IfOp::create(rewriter, op.getLoc(), adaptor.getEnable(), + emitCall); }); } else { // Unclocked call is lowered into always_comb. // TODO: If there is a return value and no output argument, use an // unclocked call op. - rewriter.create(loc, [&]() { + sv::AlwaysCombOp::create(rewriter, loc, [&]() { if (!hasEnable) return emitCall(); auto assignXToResults = [&] { for (auto lhs : temporaries) { - auto xValue = rewriter.create( - op.getLoc(), lhs.getType().getElementType()); - rewriter.create(op.getLoc(), lhs, xValue); + auto xValue = sv::ConstantXOp::create( + rewriter, op.getLoc(), lhs.getType().getElementType()); + sv::BPAssignOp::create(rewriter, op.getLoc(), lhs, xValue); } }; - rewriter.create(op.getLoc(), adaptor.getEnable(), emitCall, - assignXToResults); + sv::IfOp::create(rewriter, op.getLoc(), adaptor.getEnable(), emitCall, + assignXToResults); }); } @@ -269,24 +271,25 @@ void LowerDPIFunc::lower(sim::DPIFuncOp func) { } auto svFuncDecl = - builder.create(func.getSymNameAttr(), func.getModuleType(), - func.getPerArgumentAttrsAttr(), inputLocsAttr, - outputLocsAttr, func.getVerilogNameAttr()); + sv::FuncOp::create(builder, func.getSymNameAttr(), func.getModuleType(), + func.getPerArgumentAttrsAttr(), inputLocsAttr, + outputLocsAttr, func.getVerilogNameAttr()); // DPI function is a declaration so it must be a private function. svFuncDecl.setPrivate(); auto name = builder.getStringAttr(nameSpace.newName( func.getSymNameAttr().getValue(), "dpi_import_fragument")); // Add include guards to avoid duplicate declarations. See Issue 7458. - auto macroDecl = builder.create(nameSpace.newName( - "__CIRCT_DPI_IMPORT", func.getSymNameAttr().getValue().upper())); - builder.create(name, [&]() { - builder.create( - macroDecl.getSymNameAttr(), []() {}, + auto macroDecl = sv::MacroDeclOp::create( + builder, nameSpace.newName("__CIRCT_DPI_IMPORT", + func.getSymNameAttr().getValue().upper())); + emit::FragmentOp::create(builder, name, [&]() { + sv::IfDefOp::create( + builder, macroDecl.getSymNameAttr(), []() {}, [&]() { - builder.create(func.getSymNameAttr(), - StringAttr()); - builder.create(macroDecl.getSymNameAttr(), ""); + sv::FuncDPIImportOp::create(builder, func.getSymNameAttr(), + StringAttr()); + sv::MacroDefOp::create(builder, macroDecl.getSymNameAttr(), ""); }); }); @@ -369,7 +372,7 @@ struct SimToSVPass : public circt::impl::LowerSimToSVBase { } else { auto builder = ImplicitLocOpBuilder::atBlockBegin( UnknownLoc::get(context), circuit.getBody()); - builder.create("SYNTHESIS"); + sv::MacroDeclOp::create(builder, "SYNTHESIS"); } } } diff --git a/lib/Conversion/VerifToSMT/VerifToSMT.cpp b/lib/Conversion/VerifToSMT/VerifToSMT.cpp index 2142140640..9ae8c57a71 100644 --- a/lib/Conversion/VerifToSMT/VerifToSMT.cpp +++ b/lib/Conversion/VerifToSMT/VerifToSMT.cpp @@ -47,7 +47,7 @@ struct VerifAssertOpConversion : OpConversionPattern { Value cond = typeConverter->materializeTargetConversion( rewriter, op.getLoc(), smt::BoolType::get(getContext()), adaptor.getProperty()); - Value notCond = rewriter.create(op.getLoc(), cond); + Value notCond = smt::NotOp::create(rewriter, op.getLoc(), cond); rewriter.replaceOpWithNewOp(op, notCond); return success(); } @@ -89,7 +89,7 @@ protected: Value o2 = typeConverter->materializeTargetConversion( rewriter, loc, typeConverter->convertType(out1.getType()), out2); outputsDifferent.emplace_back( - rewriter.create(loc, o1, o2)); + smt::DistinctOp::create(rewriter, loc, o1, o2)); } } @@ -101,32 +101,32 @@ protected: // the result type of the operation and yield the result of the check // operation. if (op.getNumResults() == 0) { - auto checkOp = rewriter.create(loc, TypeRange{}); + auto checkOp = smt::CheckOp::create(rewriter, loc, TypeRange{}); rewriter.createBlock(&checkOp.getSatRegion()); - rewriter.create(loc); + smt::YieldOp::create(rewriter, loc); rewriter.createBlock(&checkOp.getUnknownRegion()); - rewriter.create(loc); + smt::YieldOp::create(rewriter, loc); rewriter.createBlock(&checkOp.getUnsatRegion()); - rewriter.create(loc); + smt::YieldOp::create(rewriter, loc); rewriter.setInsertionPointAfter(checkOp); - rewriter.create(loc); + smt::YieldOp::create(rewriter, loc); // Erase as operation is replaced by an operator without a return value. rewriter.eraseOp(op); } else { Value falseVal = - rewriter.create(loc, rewriter.getBoolAttr(false)); + arith::ConstantOp::create(rewriter, loc, rewriter.getBoolAttr(false)); Value trueVal = - rewriter.create(loc, rewriter.getBoolAttr(true)); - auto checkOp = rewriter.create(loc, rewriter.getI1Type()); + arith::ConstantOp::create(rewriter, loc, rewriter.getBoolAttr(true)); + auto checkOp = smt::CheckOp::create(rewriter, loc, rewriter.getI1Type()); rewriter.createBlock(&checkOp.getSatRegion()); - rewriter.create(loc, falseVal); + smt::YieldOp::create(rewriter, loc, falseVal); rewriter.createBlock(&checkOp.getUnknownRegion()); - rewriter.create(loc, falseVal); + smt::YieldOp::create(rewriter, loc, falseVal); rewriter.createBlock(&checkOp.getUnsatRegion()); - rewriter.create(loc, trueVal); + smt::YieldOp::create(rewriter, loc, trueVal); rewriter.setInsertionPointAfter(checkOp); - rewriter.create(loc, checkOp->getResults()); + smt::YieldOp::create(rewriter, loc, checkOp->getResults()); rewriter.replaceOp(op, solver->getResults()); } @@ -157,8 +157,8 @@ struct LogicEquivalenceCheckingOpConversion if (hasNoResult) { rewriter.eraseOp(op); } else { - Value trueVal = - rewriter.create(loc, rewriter.getBoolAttr(true)); + Value trueVal = arith::ConstantOp::create(rewriter, loc, + rewriter.getBoolAttr(true)); rewriter.replaceOp(op, trueVal); } return success(); @@ -168,10 +168,10 @@ struct LogicEquivalenceCheckingOpConversion // value. smt::SolverOp solver; if (hasNoResult) - solver = rewriter.create(loc, TypeRange{}, ValueRange{}); + solver = smt::SolverOp::create(rewriter, loc, TypeRange{}, ValueRange{}); else - solver = rewriter.create(loc, rewriter.getI1Type(), - ValueRange{}); + solver = smt::SolverOp::create(rewriter, loc, rewriter.getI1Type(), + ValueRange{}); rewriter.createBlock(&solver.getBodyRegion()); // First, convert the block arguments of the miter bodies. @@ -185,7 +185,7 @@ struct LogicEquivalenceCheckingOpConversion // Second, create the symbolic values we replace the block arguments with SmallVector inputs; for (auto arg : adaptor.getFirstCircuit().getArguments()) - inputs.push_back(rewriter.create(loc, arg.getType())); + inputs.push_back(smt::DeclareFunOp::create(rewriter, loc, arg.getType())); // Third, inline the blocks // Note: the argument value replacement does not happen immediately, but @@ -212,9 +212,9 @@ struct LogicEquivalenceCheckingOpConversion if (outputsDifferent.size() == 1) toAssert = outputsDifferent[0]; else - toAssert = rewriter.create(loc, outputsDifferent); + toAssert = smt::OrOp::create(rewriter, loc, outputsDifferent); - rewriter.create(loc, toAssert); + smt::AssertOp::create(rewriter, loc, toAssert); // Fifth, check for satisfiablility and report the result back. replaceOpWithSatCheck(op, loc, rewriter, solver); @@ -251,8 +251,8 @@ struct RefinementCheckingOpConversion // If there is no non-determinism in the source circuit, the // refinement check becomes an equivalence check, which does not // need quantified expressions. - auto eqOp = rewriter.create( - op.getLoc(), op.getNumResults() != 0); + auto eqOp = verif::LogicEquivalenceCheckingOp::create( + rewriter, op.getLoc(), op.getNumResults() != 0); rewriter.moveBlockBefore(&op.getFirstCircuit().front(), &eqOp.getFirstCircuit(), eqOp.getFirstCircuit().end()); @@ -274,8 +274,8 @@ struct RefinementCheckingOpConversion if (hasNoResult) { rewriter.eraseOp(op); } else { - Value trueVal = - rewriter.create(loc, rewriter.getBoolAttr(true)); + Value trueVal = arith::ConstantOp::create(rewriter, loc, + rewriter.getBoolAttr(true)); rewriter.replaceOp(op, trueVal); } return success(); @@ -285,10 +285,10 @@ struct RefinementCheckingOpConversion // value. smt::SolverOp solver; if (hasNoResult) - solver = rewriter.create(loc, TypeRange{}, ValueRange{}); + solver = smt::SolverOp::create(rewriter, loc, TypeRange{}, ValueRange{}); else - solver = rewriter.create(loc, rewriter.getI1Type(), - ValueRange{}); + solver = smt::SolverOp::create(rewriter, loc, rewriter.getI1Type(), + ValueRange{}); rewriter.createBlock(&solver.getBodyRegion()); // Convert the block arguments of the miter bodies. @@ -302,7 +302,7 @@ struct RefinementCheckingOpConversion // Create the symbolic values we replace the block arguments with SmallVector inputs; for (auto arg : adaptor.getFirstCircuit().getArguments()) - inputs.push_back(rewriter.create(loc, arg.getType())); + inputs.push_back(smt::DeclareFunOp::create(rewriter, loc, arg.getType())); // Inline the target circuit. Free variables remain free variables. rewriter.mergeBlocks(&adaptor.getSecondCircuit().front(), solver.getBody(), @@ -311,8 +311,8 @@ struct RefinementCheckingOpConversion // Create the universally quantified expression containing the source // circuit. Free variables in the circuit's body become bound variables. - auto forallOp = rewriter.create( - op.getLoc(), TypeRange(srcNonDetValues), + auto forallOp = smt::ForallOp::create( + rewriter, op.getLoc(), TypeRange(srcNonDetValues), [&](OpBuilder &builder, auto, ValueRange args) -> Value { // Inline the source circuit Block *body = builder.getBlock(); @@ -340,7 +340,7 @@ struct RefinementCheckingOpConversion // Assert the quantified expression rewriter.setInsertionPointAfter(forallOp); - rewriter.create(op.getLoc(), forallOp.getResult()); + smt::AssertOp::create(rewriter, op.getLoc(), forallOp.getResult()); // Check for satisfiability and report the result back. replaceOpWithSatCheck(op, loc, rewriter, solver); @@ -403,16 +403,16 @@ struct VerifBoundedModelCheckingOpConversion OpBuilder::InsertionGuard guard(rewriter); rewriter.setInsertionPointToEnd( op->getParentOfType().getBody()); - initFuncOp = rewriter.create(loc, names.newName("bmc_init"), - initFuncTy); + initFuncOp = func::FuncOp::create(rewriter, loc, + names.newName("bmc_init"), initFuncTy); rewriter.inlineRegionBefore(op.getInit(), initFuncOp.getFunctionBody(), initFuncOp.end()); - loopFuncOp = rewriter.create(loc, names.newName("bmc_loop"), - loopFuncTy); + loopFuncOp = func::FuncOp::create(rewriter, loc, + names.newName("bmc_loop"), loopFuncTy); rewriter.inlineRegionBefore(op.getLoop(), loopFuncOp.getFunctionBody(), loopFuncOp.end()); - circuitFuncOp = rewriter.create( - loc, names.newName("bmc_circuit"), circuitFuncTy); + circuitFuncOp = func::FuncOp::create( + rewriter, loc, names.newName("bmc_circuit"), circuitFuncTy); rewriter.inlineRegionBefore(op.getCircuit(), circuitFuncOp.getFunctionBody(), circuitFuncOp.end()); @@ -427,20 +427,20 @@ struct VerifBoundedModelCheckingOpConversion for (unsigned i = 0; i < outputTy.size(); ++i) toReturn.push_back(typeConverter->materializeTargetConversion( rewriter, loc, outputTy[i], operands[i])); - rewriter.create(loc, toReturn); + func::ReturnOp::create(rewriter, loc, toReturn); } } - auto solver = - rewriter.create(loc, rewriter.getI1Type(), ValueRange{}); + auto solver = smt::SolverOp::create(rewriter, loc, rewriter.getI1Type(), + ValueRange{}); rewriter.createBlock(&solver.getBodyRegion()); // Call init func to get initial clock values ValueRange initVals = - rewriter.create(loc, initFuncOp)->getResults(); + func::CallOp::create(rewriter, loc, initFuncOp)->getResults(); // Initial push - rewriter.create(loc, 1); + smt::PushOp::create(rewriter, loc, 1); // InputDecls order should be // @@ -463,11 +463,12 @@ struct VerifBoundedModelCheckingOpConversion assert(cstInt.getBitWidth() == cast(newTy).getWidth() && "Width mismatch between initial value and target type"); - inputDecls.push_back(rewriter.create(loc, cstInt)); + inputDecls.push_back( + smt::BVConstantOp::create(rewriter, loc, cstInt)); continue; } } - inputDecls.push_back(rewriter.create(loc, newTy)); + inputDecls.push_back(smt::DeclareFunOp::create(rewriter, loc, newTy)); } auto numStateArgs = initVals.size() - initIndex; @@ -476,33 +477,32 @@ struct VerifBoundedModelCheckingOpConversion inputDecls.push_back(initVals[initIndex]); Value lowerBound = - rewriter.create(loc, rewriter.getI32IntegerAttr(0)); + arith::ConstantOp::create(rewriter, loc, rewriter.getI32IntegerAttr(0)); Value step = - rewriter.create(loc, rewriter.getI32IntegerAttr(1)); + arith::ConstantOp::create(rewriter, loc, rewriter.getI32IntegerAttr(1)); Value upperBound = - rewriter.create(loc, adaptor.getBoundAttr()); + arith::ConstantOp::create(rewriter, loc, adaptor.getBoundAttr()); Value constFalse = - rewriter.create(loc, rewriter.getBoolAttr(false)); + arith::ConstantOp::create(rewriter, loc, rewriter.getBoolAttr(false)); Value constTrue = - rewriter.create(loc, rewriter.getBoolAttr(true)); + arith::ConstantOp::create(rewriter, loc, rewriter.getBoolAttr(true)); inputDecls.push_back(constFalse); // wasViolated? // TODO: swapping to a whileOp here would allow early exit once the property // is violated // Perform model check up to the provided bound - auto forOp = rewriter.create( - loc, lowerBound, upperBound, step, inputDecls, + auto forOp = scf::ForOp::create( + rewriter, loc, lowerBound, upperBound, step, inputDecls, [&](OpBuilder &builder, Location loc, Value i, ValueRange iterArgs) { // Drop existing assertions - builder.create(loc, 1); - builder.create(loc, 1); + smt::PopOp::create(builder, loc, 1); + smt::PushOp::create(builder, loc, 1); // Execute the circuit ValueRange circuitCallOuts = - builder - .create( - loc, circuitFuncOp, - iterArgs.take_front(circuitFuncOp.getNumArguments())) + func::CallOp::create( + builder, loc, circuitFuncOp, + iterArgs.take_front(circuitFuncOp.getNumArguments())) ->getResults(); // If we have a cycle up to which we ignore assertions, we need an @@ -516,41 +516,43 @@ struct VerifBoundedModelCheckingOpConversion auto ignoreAssertionsUntil = op->getAttrOfType("ignore_asserts_until"); if (ignoreAssertionsUntil) { - auto ignoreUntilConstant = builder.create( - loc, rewriter.getI32IntegerAttr( - ignoreAssertionsUntil.getValue().getZExtValue())); - auto shouldIgnore = builder.create( - loc, arith::CmpIPredicate::ult, i, ignoreUntilConstant); - auto ifShouldIgnore = builder.create( - loc, builder.getI1Type(), shouldIgnore, true); + auto ignoreUntilConstant = arith::ConstantOp::create( + builder, loc, + rewriter.getI32IntegerAttr( + ignoreAssertionsUntil.getValue().getZExtValue())); + auto shouldIgnore = + arith::CmpIOp::create(builder, loc, arith::CmpIPredicate::ult, + i, ignoreUntilConstant); + auto ifShouldIgnore = scf::IfOp::create( + builder, loc, builder.getI1Type(), shouldIgnore, true); // If we should ignore, yield the existing value builder.setInsertionPointToEnd( &ifShouldIgnore.getThenRegion().front()); - builder.create(loc, ValueRange(iterArgs.back())); + scf::YieldOp::create(builder, loc, ValueRange(iterArgs.back())); builder.setInsertionPointToEnd( &ifShouldIgnore.getElseRegion().front()); yieldedValue = ifShouldIgnore.getResult(0); } auto checkOp = - rewriter.create(loc, builder.getI1Type()); + smt::CheckOp::create(rewriter, loc, builder.getI1Type()); { OpBuilder::InsertionGuard guard(builder); builder.createBlock(&checkOp.getSatRegion()); - builder.create(loc, constTrue); + smt::YieldOp::create(builder, loc, constTrue); builder.createBlock(&checkOp.getUnknownRegion()); - builder.create(loc, constTrue); + smt::YieldOp::create(builder, loc, constTrue); builder.createBlock(&checkOp.getUnsatRegion()); - builder.create(loc, constFalse); + smt::YieldOp::create(builder, loc, constFalse); } - Value violated = builder.create( - loc, checkOp.getResult(0), iterArgs.back()); + Value violated = arith::OrIOp::create( + builder, loc, checkOp.getResult(0), iterArgs.back()); // If we've packaged everything in an IfOp, we need to yield the // new violated value if (ignoreAssertionsUntil) { - builder.create(loc, violated); + scf::YieldOp::create(builder, loc, violated); // Replace the variable with the yielded value violated = yieldedValue; } @@ -567,7 +569,7 @@ struct VerifBoundedModelCheckingOpConversion for (auto stateArg : iterArgs.drop_back().take_back(numStateArgs)) loopCallInputs.push_back(stateArg); ValueRange loopVals = - builder.create(loc, loopFuncOp, loopCallInputs) + func::CallOp::create(builder, loc, loopFuncOp, loopCallInputs) ->getResults(); size_t loopIndex = 0; @@ -579,7 +581,8 @@ struct VerifBoundedModelCheckingOpConversion if (isa(oldTy)) newDecls.push_back(loopVals[loopIndex++]); else - newDecls.push_back(builder.create(loc, newTy)); + newDecls.push_back( + smt::DeclareFunOp::create(builder, loc, newTy)); } // Only update the registers on a clock posedge unless in rising @@ -598,13 +601,13 @@ struct VerifBoundedModelCheckingOpConversion // The clock is necessarily the first value returned by the loop // region auto newClock = loopVals[0]; - auto oldClockLow = builder.create(loc, oldClock); + auto oldClockLow = smt::BVNotOp::create(builder, loc, oldClock); auto isPosedgeBV = - builder.create(loc, oldClockLow, newClock); + smt::BVAndOp::create(builder, loc, oldClockLow, newClock); // Convert posedge bv<1> to bool - auto trueBV = builder.create(loc, 1, 1); + auto trueBV = smt::BVConstantOp::create(builder, loc, 1, 1); auto isPosedge = - builder.create(loc, isPosedgeBV, trueBV); + smt::EqOp::create(builder, loc, isPosedgeBV, trueBV); auto regStates = iterArgs.take_front(circuitFuncOp.getNumArguments()) .take_back(numRegs); @@ -614,8 +617,8 @@ struct VerifBoundedModelCheckingOpConversion // Create an ITE to calculate the next reg state // TODO: we create a lot of ITEs here that will slow things down // - these could be avoided by making init/loop regions concrete - nextRegStates.push_back(builder.create( - loc, isPosedge, regInput, regState)); + nextRegStates.push_back(smt::IteOp::create( + builder, loc, isPosedge, regInput, regState)); } newDecls.append(nextRegStates); } @@ -627,12 +630,12 @@ struct VerifBoundedModelCheckingOpConversion newDecls.push_back(violated); - builder.create(loc, newDecls); + scf::YieldOp::create(builder, loc, newDecls); }); - Value res = rewriter.create(loc, forOp->getResults().back(), - constTrue); - rewriter.create(loc, res); + Value res = arith::XOrIOp::create(rewriter, loc, forOp->getResults().back(), + constTrue); + smt::YieldOp::create(rewriter, loc, res); rewriter.replaceOp(op, solver.getResults()); return success(); } diff --git a/lib/Conversion/VerifToSV/VerifToSV.cpp b/lib/Conversion/VerifToSV/VerifToSV.cpp index 62007af45b..238b561291 100644 --- a/lib/Conversion/VerifToSV/VerifToSV.cpp +++ b/lib/Conversion/VerifToSV/VerifToSV.cpp @@ -45,7 +45,7 @@ struct PrintOpConversionPattern : public OpConversionPattern { // Printf's will be emitted to stdout (32'h8000_0001 in IEEE Std 1800-2012). Value fdStdout = - rewriter.create(op.getLoc(), APInt(32, 0x80000001)); + hw::ConstantOp::create(rewriter, op.getLoc(), APInt(32, 0x80000001)); auto fstrOp = dyn_cast_or_null(op.getString().getDefiningOp()); @@ -66,13 +66,13 @@ struct HasBeenResetConversion : public OpConversionPattern { matchAndRewrite(HasBeenResetOp op, OpAdaptor operands, ConversionPatternRewriter &rewriter) const override { auto i1 = rewriter.getI1Type(); - auto constOne = rewriter.create(op.getLoc(), i1, 1); - auto constZero = rewriter.create(op.getLoc(), i1, 0); - auto constX = rewriter.create(op.getLoc(), i1); + auto constOne = hw::ConstantOp::create(rewriter, op.getLoc(), i1, 1); + auto constZero = hw::ConstantOp::create(rewriter, op.getLoc(), i1, 0); + auto constX = sv::ConstantXOp::create(rewriter, op.getLoc(), i1); // Declare the register that will track the reset state. - auto reg = rewriter.create( - op.getLoc(), i1, rewriter.getStringAttr("hasBeenResetReg")); + auto reg = sv::RegOp::create(rewriter, op.getLoc(), i1, + rewriter.getStringAttr("hasBeenResetReg")); auto clock = operands.getClock(); auto reset = operands.getReset(); @@ -84,15 +84,15 @@ struct HasBeenResetConversion : public OpConversionPattern { // In case the reset is async, check if the reset is already active during // the `initial` block and immediately set the register to 1. Otherwise // initialize to X. - rewriter.create(op.getLoc(), [&] { + sv::InitialOp::create(rewriter, op.getLoc(), [&] { auto assignOne = [&] { - rewriter.create(op.getLoc(), reg, constOne); + sv::BPAssignOp::create(rewriter, op.getLoc(), reg, constOne); }; auto assignX = [&] { - rewriter.create(op.getLoc(), reg, constX); + sv::BPAssignOp::create(rewriter, op.getLoc(), reg, constX); }; if (op.getAsync()) - rewriter.create(op.getLoc(), reset, assignOne, assignX); + sv::IfOp::create(rewriter, op.getLoc(), reset, assignOne, assignX); else assignX(); }); @@ -101,20 +101,20 @@ struct HasBeenResetConversion : public OpConversionPattern { // reset is initiated. For async resets this happens at the reset's posedge; // for sync resets this happens on the clock's posedge if the reset is set. Value triggerOn = op.getAsync() ? reset : clock; - rewriter.create( - op.getLoc(), sv::EventControl::AtPosEdge, triggerOn, [&] { + sv::AlwaysOp::create( + rewriter, op.getLoc(), sv::EventControl::AtPosEdge, triggerOn, [&] { auto assignOne = [&] { - rewriter.create(op.getLoc(), reg, constOne); + sv::PAssignOp::create(rewriter, op.getLoc(), reg, constOne); }; if (op.getAsync()) assignOne(); else - rewriter.create(op.getLoc(), reset, assignOne); + sv::IfOp::create(rewriter, op.getLoc(), reset, assignOne); }); // Derive the actual result value: // hasBeenReset = (hasBeenResetReg === 1) && (reset === 0); - auto regRead = rewriter.create(op.getLoc(), reg); + auto regRead = sv::ReadInOutOp::create(rewriter, op.getLoc(), reg); auto regIsOne = rewriter.createOrFold( op.getLoc(), comb::ICmpPredicate::ceq, regRead, constOne); auto resetIsZero = rewriter.createOrFold( diff --git a/lib/Dialect/AIG/AIGOps.cpp b/lib/Dialect/AIG/AIGOps.cpp index 40607a870a..ecf497e8e1 100644 --- a/lib/Dialect/AIG/AIGOps.cpp +++ b/lib/Dialect/AIG/AIGOps.cpp @@ -87,7 +87,7 @@ LogicalResult AndInverterOp::canonicalize(AndInverterOp op, return failure(); if (!constValue.isAllOnes()) { - auto constOp = rewriter.create(op.getLoc(), constValue); + auto constOp = hw::ConstantOp::create(rewriter, op.getLoc(), constValue); uniqueInverts.push_back(false); uniqueValues.push_back(constOp); } diff --git a/lib/Dialect/AIG/Transforms/AIGERRunner.cpp b/lib/Dialect/AIG/Transforms/AIGERRunner.cpp index 7980bc17d7..77944c34c3 100644 --- a/lib/Dialect/AIG/Transforms/AIGERRunner.cpp +++ b/lib/Dialect/AIG/Transforms/AIGERRunner.cpp @@ -417,7 +417,7 @@ LogicalResult AIGERRunner::importFromAIGER(Converter &converter, mlir::OpBuilder builder(originalModule->getContext()); builder.setInsertionPointToStart(&temporaryBlock); auto temporaryModule = - builder.create(builder.getUnknownLoc()); + mlir::ModuleOp::create(builder, builder.getUnknownLoc()); // Import the AIGER file into the temporary module if (failed(circt::aiger::importAIGER(sourceMgr, originalModule->getContext(), diff --git a/lib/Dialect/AIG/Transforms/LowerVariadic.cpp b/lib/Dialect/AIG/Transforms/LowerVariadic.cpp index 8590fd06df..7a5f416487 100644 --- a/lib/Dialect/AIG/Transforms/LowerVariadic.cpp +++ b/lib/Dialect/AIG/Transforms/LowerVariadic.cpp @@ -42,12 +42,12 @@ static Value lowerVariadicAndInverterOp(AndInverterOp op, OperandRange operands, break; case 1: if (inverts[0]) - return rewriter.create(op.getLoc(), operands[0], true); + return AndInverterOp::create(rewriter, op.getLoc(), operands[0], true); else return operands[0]; case 2: - return rewriter.create(op.getLoc(), operands[0], operands[1], - inverts[0], inverts[1]); + return AndInverterOp::create(rewriter, op.getLoc(), operands[0], + operands[1], inverts[0], inverts[1]); default: auto firstHalf = operands.size() / 2; auto lhs = @@ -56,7 +56,7 @@ static Value lowerVariadicAndInverterOp(AndInverterOp op, OperandRange operands, auto rhs = lowerVariadicAndInverterOp(op, operands.drop_front(firstHalf), inverts.drop_front(firstHalf), rewriter); - return rewriter.create(op.getLoc(), lhs, rhs); + return AndInverterOp::create(rewriter, op.getLoc(), lhs, rhs); } return Value(); diff --git a/lib/Dialect/AIG/Transforms/LowerWordToBits.cpp b/lib/Dialect/AIG/Transforms/LowerWordToBits.cpp index c86b89b94b..ded5827d61 100644 --- a/lib/Dialect/AIG/Transforms/LowerWordToBits.cpp +++ b/lib/Dialect/AIG/Transforms/LowerWordToBits.cpp @@ -64,10 +64,10 @@ struct WordRewritePattern : public OpRewritePattern { } // Otherwise, we need to extract the bit. operands.push_back( - rewriter.create(op.getLoc(), operand, i, 1)); + comb::ExtractOp::create(rewriter, op.getLoc(), operand, i, 1)); } - results.push_back(rewriter.create(op.getLoc(), operands, - op.getInvertedAttr())); + results.push_back(AndInverterOp::create(rewriter, op.getLoc(), operands, + op.getInvertedAttr())); } rewriter.replaceOpWithNewOp(op, results); diff --git a/lib/Dialect/Arc/ArcDialect.cpp b/lib/Dialect/Arc/ArcDialect.cpp index fbe11b194e..25cf273d4e 100644 --- a/lib/Dialect/Arc/ArcDialect.cpp +++ b/lib/Dialect/Arc/ArcDialect.cpp @@ -66,7 +66,7 @@ Operation *ArcDialect::materializeConstant(OpBuilder &builder, Attribute value, // Integer constants. if (auto intType = dyn_cast(type)) if (auto attrValue = dyn_cast(value)) - return builder.create(loc, type, attrValue); + return hw::ConstantOp::create(builder, loc, type, attrValue); // Parameter expressions materialize into hw.param.value. auto *parentOp = builder.getBlock()->getParentOp(); @@ -74,7 +74,7 @@ Operation *ArcDialect::materializeConstant(OpBuilder &builder, Attribute value, if (!curModule) curModule = parentOp->getParentOfType(); if (curModule && isValidParameterExpression(value, curModule)) - return builder.create(loc, type, value); + return hw::ParamValueOp::create(builder, loc, type, value); return nullptr; } diff --git a/lib/Dialect/Arc/ArcFolds.cpp b/lib/Dialect/Arc/ArcFolds.cpp index 08f589face..379b922667 100644 --- a/lib/Dialect/Arc/ArcFolds.cpp +++ b/lib/Dialect/Arc/ArcFolds.cpp @@ -158,8 +158,8 @@ static bool removeUnusedClockDomainOutputs(ClockDomainOp op, rewriter.setInsertionPoint(op); - auto newDomain = rewriter.create( - op.getLoc(), resultTypes, op.getInputs(), op.getClock()); + auto newDomain = ClockDomainOp::create(rewriter, op.getLoc(), resultTypes, + op.getInputs(), op.getClock()); rewriter.inlineRegionBefore(op.getBody(), newDomain.getBody(), newDomain->getRegion(0).begin()); diff --git a/lib/Dialect/Arc/ArcReductions.cpp b/lib/Dialect/Arc/ArcReductions.cpp index a383996ec6..640dcd6cfe 100644 --- a/lib/Dialect/Arc/ArcReductions.cpp +++ b/lib/Dialect/Arc/ArcReductions.cpp @@ -29,9 +29,9 @@ struct StateElimination : public OpReduction { LogicalResult rewrite(StateOp stateOp) override { OpBuilder builder(stateOp); ValueRange results = - builder - .create(stateOp.getLoc(), stateOp->getResultTypes(), - stateOp.getArcAttr(), stateOp.getInputs()) + arc::CallOp::create(builder, stateOp.getLoc(), + stateOp->getResultTypes(), stateOp.getArcAttr(), + stateOp.getInputs()) ->getResults(); stateOp.replaceAllUsesWith(results); stateOp.erase(); diff --git a/lib/Dialect/Arc/Transforms/AddTaps.cpp b/lib/Dialect/Arc/Transforms/AddTaps.cpp index e043c05eb6..29f3c2abe7 100644 --- a/lib/Dialect/Arc/Transforms/AddTaps.cpp +++ b/lib/Dialect/Arc/Transforms/AddTaps.cpp @@ -66,7 +66,7 @@ struct AddTapsPass : public arc::impl::AddTapsBase { OpBuilder builder(wireOp); if (!readOp) - readOp = builder.create(wireOp.getLoc(), wireOp); + readOp = sv::ReadInOutOp::create(builder, wireOp.getLoc(), wireOp); buildTap(builder, readOp.getLoc(), readOp, wireOp.getName()); } @@ -95,7 +95,7 @@ struct AddTapsPass : public arc::impl::AddTapsBase { return; if (isa(value.getType())) value = builder.createOrFold(loc, value); - builder.create(loc, value, name); + arc::TapOp::create(builder, loc, value, name); } }; } // namespace diff --git a/lib/Dialect/Arc/Transforms/AllocateState.cpp b/lib/Dialect/Arc/Transforms/AllocateState.cpp index b8d61bf99b..c7626276f7 100644 --- a/lib/Dialect/Arc/Transforms/AllocateState.cpp +++ b/lib/Dialect/Arc/Transforms/AllocateState.cpp @@ -135,7 +135,7 @@ void AllocateStatePass::allocateOps(Value storage, Block *block, if (!getter || !result.getDefiningOp()) { ImplicitLocOpBuilder builder(result.getLoc(), user); getter = - builder.create(result.getType(), storage, offset); + StorageGetOp::create(builder, result.getType(), storage, offset); getters.push_back(getter); opOrder[getter] = userOrder; } else if (userOrder < opOrder.lookup(getter)) { @@ -152,8 +152,8 @@ void AllocateStatePass::allocateOps(Value storage, Block *block, storageOwner = cast(storage).getOwner()->getParentOp(); if (storageOwner->isProperAncestor(block->getParentOp())) { - auto substorage = builder.create( - block->getParentOp()->getLoc(), + auto substorage = AllocStorageOp::create( + builder, block->getParentOp()->getLoc(), StorageType::get(&getContext(), currentByte), storage); for (auto *op : ops) op->replaceUsesOfWith(storage, substorage); diff --git a/lib/Dialect/Arc/Transforms/ArcCanonicalizer.cpp b/lib/Dialect/Arc/Transforms/ArcCanonicalizer.cpp index 7797ef036f..9fac762137 100644 --- a/lib/Dialect/Arc/Transforms/ArcCanonicalizer.cpp +++ b/lib/Dialect/Arc/Transforms/ArcCanonicalizer.cpp @@ -358,13 +358,13 @@ LogicalResult MemWritePortEnableAndMaskCanonicalizer::matchAndRewrite( &newDefOp.getBody(), newDefOp.getBody().end(), newDefOp.getArgumentTypes(), SmallVector(newDefOp.getNumArguments(), defOp.getLoc())); - auto callOp = rewriter.create(newDefOp.getLoc(), newResultTypes, - newName, block->getArguments()); + auto callOp = CallOp::create(rewriter, newDefOp.getLoc(), newResultTypes, + newName, block->getArguments()); SmallVector results(callOp->getResults()); - Value constTrue = rewriter.create( - newDefOp.getLoc(), rewriter.getI1Type(), 1); + Value constTrue = hw::ConstantOp::create(rewriter, newDefOp.getLoc(), + rewriter.getI1Type(), 1); results.insert(results.begin() + op.getEnableIdx(), constTrue); - rewriter.create(newDefOp.getLoc(), results); + OutputOp::create(rewriter, newDefOp.getLoc(), results); // Remove the enable output from the current arc auto *terminator = defOp.getBodyBlock().getTerminator(); @@ -416,7 +416,7 @@ LogicalResult ICMPCanonicalizer::matchAndRewrite(comb::ICmpOp op, PatternRewriter &rewriter) const { auto getConstant = [&](const APInt &constant) -> Value { - return rewriter.create(op.getLoc(), constant); + return hw::ConstantOp::create(rewriter, op.getLoc(), constant); }; auto sameWidthIntegers = [](TypeRange types) -> std::optional { if (llvm::all_equal(types) && !types.empty()) @@ -425,9 +425,9 @@ ICMPCanonicalizer::matchAndRewrite(comb::ICmpOp op, return std::nullopt; }; auto negate = [&](Value input) -> Value { - auto constTrue = rewriter.create(op.getLoc(), APInt(1, 1)); - return rewriter.create(op.getLoc(), input, constTrue, - op.getTwoState()); + auto constTrue = hw::ConstantOp::create(rewriter, op.getLoc(), APInt(1, 1)); + return comb::XorOp::create(rewriter, op.getLoc(), input, constTrue, + op.getTwoState()); }; APInt rhs; @@ -438,8 +438,8 @@ ICMPCanonicalizer::matchAndRewrite(comb::ICmpOp op, if ((op.getPredicate() == comb::ICmpPredicate::eq || op.getPredicate() == comb::ICmpPredicate::ne) && rhs.isAllOnes()) { - Value andOp = rewriter.create( - op.getLoc(), concatOp.getInputs(), op.getTwoState()); + Value andOp = comb::AndOp::create( + rewriter, op.getLoc(), concatOp.getInputs(), op.getTwoState()); if (*optionalWidth == 1) { if (op.getPredicate() == comb::ICmpPredicate::ne) andOp = negate(andOp); @@ -457,8 +457,8 @@ ICMPCanonicalizer::matchAndRewrite(comb::ICmpOp op, if ((op.getPredicate() == comb::ICmpPredicate::ne || op.getPredicate() == comb::ICmpPredicate::eq) && rhs.isZero()) { - Value orOp = rewriter.create( - op.getLoc(), concatOp.getInputs(), op.getTwoState()); + Value orOp = comb::OrOp::create( + rewriter, op.getLoc(), concatOp.getInputs(), op.getTwoState()); if (*optionalWidth == 1) { if (op.getPredicate() == comb::ICmpPredicate::eq) orOp = negate(orOp); @@ -595,8 +595,8 @@ CompRegCanonicalizer::matchAndRewrite(seq::CompRegOp op, if (constant.isZero()) return failure(); - Value newInput = rewriter.create( - op->getLoc(), op.getReset(), op.getResetValue(), op.getInput()); + Value newInput = comb::MuxOp::create(rewriter, op->getLoc(), op.getReset(), + op.getResetValue(), op.getInput()); rewriter.modifyOpInPlace(op, [&]() { op.getInputMutable().set(newInput); op.getResetMutable().clear(); diff --git a/lib/Dialect/Arc/Transforms/FindInitialVectors.cpp b/lib/Dialect/Arc/Transforms/FindInitialVectors.cpp index 16665238c3..b5da827fc4 100644 --- a/lib/Dialect/Arc/Transforms/FindInitialVectors.cpp +++ b/lib/Dialect/Arc/Transforms/FindInitialVectors.cpp @@ -219,7 +219,7 @@ Vectorizer::vectorize(FindInitialVectorsPass::StatisticVars &stat) { // Now construct the `VectorizeOp` ImplicitLocOpBuilder builder(ops[0]->getLoc(), ops[0]); auto vectorizeOp = - builder.create(resultTypes, operandValueRanges); + VectorizeOp::create(builder, resultTypes, operandValueRanges); // Now we have the operands, results and attributes, now we need to get // the blocks. @@ -245,7 +245,7 @@ Vectorizer::vectorize(FindInitialVectorsPass::StatisticVars &stat) { auto *clonedOp = builder.clone(*ops[0], argMapping); // `VectorizeReturnOp` - builder.create(clonedOp->getResult(0)); + VectorizeReturnOp::create(builder, clonedOp->getResult(0)); // Now replace the original ops with the vectorized ops for (auto [op, result] : llvm::zip(ops, vectorizeOp->getResults())) { diff --git a/lib/Dialect/Arc/Transforms/InferMemories.cpp b/lib/Dialect/Arc/Transforms/InferMemories.cpp index 8279c55c05..ae0258cefc 100644 --- a/lib/Dialect/Arc/Transforms/InferMemories.cpp +++ b/lib/Dialect/Arc/Transforms/InferMemories.cpp @@ -115,7 +115,7 @@ void InferMemoriesPass::runOnOperation() { return signalPassFailure(); } auto memType = MemoryType::get(&getContext(), depth, wordType, addressTy); - auto memOp = builder.create(memType); + auto memOp = MemoryOp::create(builder, memType); if (tapMemories && !instOp.getInstanceName().empty()) memOp->setAttr("name", instOp.getInstanceNameAttr()); @@ -124,9 +124,9 @@ void InferMemoriesPass::runOnOperation() { auto applyLatency = [&](Value clock, Value data, unsigned latency) { for (unsigned i = 0; i < latency; ++i) - data = builder.create( - data, clock, builder.getStringAttr(""), Value{}, Value{}, Value{}, - hw::InnerSymAttr{}); + data = seq::CompRegOp::create(builder, data, clock, + builder.getStringAttr(""), Value{}, + Value{}, Value{}, hw::InnerSymAttr{}); return data; }; @@ -141,7 +141,7 @@ void InferMemoriesPass::runOnOperation() { auto tap = [&](Value value, const Twine &name) { auto prefixedName = builder.getStringAttr(tapPrefix + "_" + name); - builder.create(value, prefixedName); + arc::TapOp::create(builder, value, prefixedName); }; // Handle read ports. @@ -174,9 +174,10 @@ void InferMemoriesPass::runOnOperation() { // Read the underlying storage. (The result of a disabled read port is // undefined, currently we define it to be zero.) - Value readOp = builder.create(wordType, memOp, address); - Value zero = builder.create(wordType, 0); - readOp = builder.create(enable, readOp, zero); + Value readOp = + MemoryReadPortOp::create(builder, wordType, memOp, address); + Value zero = hw::ConstantOp::create(builder, wordType, 0); + readOp = comb::MuxOp::create(builder, enable, readOp, zero); // Apply the latency after the underlying storage was accessed. (If the // latency is 0, the memory read is combinatorial without any buffer.) @@ -216,9 +217,9 @@ void InferMemoriesPass::runOnOperation() { tap(readData, "rdata"); } - auto c1_i1 = builder.create(builder.getI1Type(), 1); - auto notWriteMode = builder.create(writeMode, c1_i1); - Value readEnable = builder.create(enable, notWriteMode); + auto c1_i1 = hw::ConstantOp::create(builder, builder.getI1Type(), 1); + auto notWriteMode = comb::XorOp::create(builder, writeMode, c1_i1); + Value readEnable = comb::AndOp::create(builder, enable, notWriteMode); // Apply the latency before the underlying storage is accessed. Value readAddress = applyLatency(clock, address, readPreLatency); @@ -227,21 +228,21 @@ void InferMemoriesPass::runOnOperation() { // Read the underlying storage. (The result of a disabled read port is // undefined, currently we define it to be zero.) Value readOp = - builder.create(wordType, memOp, readAddress); - Value zero = builder.create(wordType, 0); - readOp = builder.create(readEnable, readOp, zero); + MemoryReadPortOp::create(builder, wordType, memOp, readAddress); + Value zero = hw::ConstantOp::create(builder, wordType, 0); + readOp = comb::MuxOp::create(builder, readEnable, readOp, zero); if (writeMask) { unsigned maskWidth = cast(writeMask.getType()).getWidth(); SmallVector toConcat; for (unsigned i = 0; i < maskWidth; ++i) { - Value bit = builder.create(writeMask, i, 1); - Value replicated = builder.create(bit, maskGran); + Value bit = comb::ExtractOp::create(builder, writeMask, i, 1); + Value replicated = comb::ReplicateOp::create(builder, bit, maskGran); toConcat.push_back(replicated); } std::reverse(toConcat.begin(), toConcat.end()); // I hate concat writeMask = - builder.create(writeData.getType(), toConcat); + comb::ConcatOp::create(builder, writeData.getType(), toConcat); } // Apply the latency after the underlying storage was accessed. (If the @@ -249,7 +250,7 @@ void InferMemoriesPass::runOnOperation() { readOp = applyLatency(clock, readOp, readPostLatency); readData.replaceAllUsesWith(readOp); - auto writeEnable = builder.create(enable, writeMode); + auto writeEnable = comb::AndOp::create(builder, enable, writeMode); SmallVector inputs({address, writeData, writeEnable}); if (writeMask) inputs.push_back(writeMask); @@ -287,12 +288,12 @@ void InferMemoriesPass::runOnOperation() { unsigned maskWidth = cast(mask.getType()).getWidth(); SmallVector toConcat; for (unsigned i = 0; i < maskWidth; ++i) { - Value bit = builder.create(mask, i, 1); - Value replicated = builder.create(bit, maskGran); + Value bit = comb::ExtractOp::create(builder, mask, i, 1); + Value replicated = comb::ReplicateOp::create(builder, bit, maskGran); toConcat.push_back(replicated); } std::reverse(toConcat.begin(), toConcat.end()); // I hate concat - mask = builder.create(data.getType(), toConcat); + mask = comb::ConcatOp::create(builder, data.getType(), toConcat); } SmallVector inputs({address, data}); if (enable) @@ -308,16 +309,16 @@ void InferMemoriesPass::runOnOperation() { auto ipSave = builder.saveInsertionPoint(); TypeRange types = ValueRange(inputs).getTypes(); builder.setInsertionPointToStart(module.getBody()); - auto defOp = builder.create( - names.newName("mem_write"), builder.getFunctionType(types, types)); + auto defOp = DefineOp::create(builder, names.newName("mem_write"), + builder.getFunctionType(types, types)); auto &block = defOp.getBody().emplaceBlock(); auto args = block.addArguments( types, SmallVector(types.size(), builder.getLoc())); builder.setInsertionPointToEnd(&block); - builder.create(SmallVector(args)); + arc::OutputOp::create(builder, SmallVector(args)); builder.restoreInsertionPoint(ipSave); - builder.create(memOp, defOp.getName(), inputs, clock, - hasEnable, hasMask); + MemoryWritePortOp::create(builder, memOp, defOp.getName(), inputs, clock, + hasEnable, hasMask); } opsToDelete.push_back(instOp); diff --git a/lib/Dialect/Arc/Transforms/InferStateProperties.cpp b/lib/Dialect/Arc/Transforms/InferStateProperties.cpp index e4a9289fc2..7f4b1a40e8 100644 --- a/lib/Dialect/Arc/Transforms/InferStateProperties.cpp +++ b/lib/Dialect/Arc/Transforms/InferStateProperties.cpp @@ -148,10 +148,10 @@ static void setResetOperandOfStateOp(arc::StateOp stateOp, ImplicitLocOpBuilder builder(stateOp.getLoc(), stateOp); if (stateOp.getEnable()) - resetCond = builder.create(stateOp.getEnable(), resetCond); + resetCond = comb::AndOp::create(builder, stateOp.getEnable(), resetCond); if (stateOp.getReset()) - resetCond = builder.create(stateOp.getReset(), resetCond); + resetCond = comb::OrOp::create(builder, stateOp.getReset(), resetCond); stateOp.getResetMutable().assign(resetCond); } @@ -192,25 +192,24 @@ applyEnableTransformation(arc::DefineOp arcOp, arc::StateOp stateOp, Value enableCond = stateOp.getInputs()[enableInfos[0].condition.getArgNumber()]; - Value one = builder.create(builder.getI1Type(), -1); + Value one = hw::ConstantOp::create(builder, builder.getI1Type(), -1); if (enableInfos[0].isDisable) { inputs[enableInfos[0].condition.getArgNumber()] = - builder.create(builder.getI1Type(), 0); - enableCond = builder.create(enableCond, one); + hw::ConstantOp::create(builder, builder.getI1Type(), 0); + enableCond = comb::XorOp::create(builder, enableCond, one); } else { inputs[enableInfos[0].condition.getArgNumber()] = one; } if (stateOp.getEnable()) - enableCond = builder.create(stateOp.getEnable(), enableCond); + enableCond = comb::AndOp::create(builder, stateOp.getEnable(), enableCond); stateOp.getEnableMutable().assign(enableCond); for (size_t i = 0, e = outputOp.getOutputs().size(); i < e; ++i) { if (enableInfos[i].selfArg.hasOneUse()) - inputs[enableInfos[i].selfArg.getArgNumber()] = - builder.create(stateOp.getLoc(), - enableInfos[i].selfArg.getType(), 0); + inputs[enableInfos[i].selfArg.getArgNumber()] = hw::ConstantOp::create( + builder, stateOp.getLoc(), enableInfos[i].selfArg.getType(), 0); } stateOp.getInputsMutable().assign(inputs); diff --git a/lib/Dialect/Arc/Transforms/IsolateClocks.cpp b/lib/Dialect/Arc/Transforms/IsolateClocks.cpp index 6ad1c1bb0b..e6fe10f7ce 100644 --- a/lib/Dialect/Arc/Transforms/IsolateClocks.cpp +++ b/lib/Dialect/Arc/Transforms/IsolateClocks.cpp @@ -113,9 +113,9 @@ ClockDomainOp ClockDomain::materialize(OpBuilder &materializeBuilder, computeCrossingValues(inputs, outputs); // Add the terminator and clock domain outputs and rewire the SSA value uses - auto outputOp = builder.create(loc, outputs); - auto clockDomainOp = materializeBuilder.create( - loc, ValueRange(outputs).getTypes(), inputs, clock); + auto outputOp = arc::OutputOp::create(builder, loc, outputs); + auto clockDomainOp = ClockDomainOp::create( + materializeBuilder, loc, ValueRange(outputs).getTypes(), inputs, clock); for (auto [domainOutput, val] : llvm::zip(clockDomainOp.getOutputs(), outputOp->getOperands())) { val.replaceUsesWithIf(domainOutput, [&](OpOperand &operand) { diff --git a/lib/Dialect/Arc/Transforms/LowerArcsToFuncs.cpp b/lib/Dialect/Arc/Transforms/LowerArcsToFuncs.cpp index faaf7b666a..c358468391 100644 --- a/lib/Dialect/Arc/Transforms/LowerArcsToFuncs.cpp +++ b/lib/Dialect/Arc/Transforms/LowerArcsToFuncs.cpp @@ -42,8 +42,8 @@ struct DefineOpLowering : public OpConversionPattern { LogicalResult matchAndRewrite(arc::DefineOp op, OpAdaptor adaptor, ConversionPatternRewriter &rewriter) const final { - auto func = rewriter.create(op.getLoc(), op.getName(), - op.getFunctionType()); + auto func = mlir::func::FuncOp::create(rewriter, op.getLoc(), op.getName(), + op.getFunctionType()); func->setAttr( "llvm.linkage", LLVM::LinkageAttr::get(getContext(), LLVM::linkage::Linkage::Internal)); diff --git a/lib/Dialect/Arc/Transforms/LowerClocksToFuncs.cpp b/lib/Dialect/Arc/Transforms/LowerClocksToFuncs.cpp index af318ef325..40c08fc4d7 100644 --- a/lib/Dialect/Arc/Transforms/LowerClocksToFuncs.cpp +++ b/lib/Dialect/Arc/Transforms/LowerClocksToFuncs.cpp @@ -125,7 +125,7 @@ LogicalResult LowerClocksToFuncsPass::lowerClock(Operation *clockOp, // Add a return op to the end of the body. auto builder = OpBuilder::atBlockEnd(&clockRegion.front()); - builder.create(clockOp->getLoc()); + func::ReturnOp::create(builder, clockOp->getLoc()); // Pick a name for the clock function. SmallString<32> funcName; @@ -137,8 +137,8 @@ LogicalResult LowerClocksToFuncsPass::lowerClock(Operation *clockOp, else if (isa(clockOp)) funcName.append("_final"); - auto funcOp = funcBuilder.create( - clockOp->getLoc(), funcName, + auto funcOp = func::FuncOp::create( + funcBuilder, clockOp->getLoc(), funcName, builder.getFunctionType({modelStorageArg.getType()}, {})); symbolTable->insert(funcOp); // uniquifies the name LLVM_DEBUG(llvm::dbgs() << " - Created function `" << funcOp.getSymName() diff --git a/lib/Dialect/Arc/Transforms/LowerLUT.cpp b/lib/Dialect/Arc/Transforms/LowerLUT.cpp index ae51793dae..f7bd876bef 100644 --- a/lib/Dialect/Arc/Transforms/LowerLUT.cpp +++ b/lib/Dialect/Arc/Transforms/LowerLUT.cpp @@ -170,7 +170,7 @@ void LutCalculator::getTableEntriesAsConstValues( DenseMap map; for (auto entry : table) { if (!map.count(entry)) - map[entry] = builder.create(lut.getLoc(), entry); + map[entry] = hw::ConstantOp::create(builder, lut.getLoc(), entry); tableEntries.push_back(map[entry]); } @@ -225,26 +225,27 @@ struct LutToInteger : OpConversionPattern { result.insertBits(chunk, nextInsertion); } - Value table = rewriter.create(lut.getLoc(), result); + Value table = hw::ConstantOp::create(rewriter, lut.getLoc(), result); // Zero-extend the lookup/index value to the same bit-width as the table, // because the shift operation requires both operands to have the same // bit-width. - Value zextValue = rewriter.create( - lut->getLoc(), rewriter.getIntegerType(tableSize - inputBw), 0); - Value entryOffset = rewriter.create(lut.getLoc(), zextValue, - lut.getInputs()); - Value resultBitWidth = rewriter.create( - lut.getLoc(), entryOffset.getType(), + Value zextValue = + hw::ConstantOp::create(rewriter, lut->getLoc(), + rewriter.getIntegerType(tableSize - inputBw), 0); + Value entryOffset = comb::ConcatOp::create(rewriter, lut.getLoc(), + zextValue, lut.getInputs()); + Value resultBitWidth = hw::ConstantOp::create( + rewriter, lut.getLoc(), entryOffset.getType(), lut.getResult().getType().getIntOrFloatBitWidth()); - Value lookupValue = - rewriter.create(lut.getLoc(), entryOffset, resultBitWidth); + Value lookupValue = comb::MulOp::create(rewriter, lut.getLoc(), entryOffset, + resultBitWidth); // Shift the table and truncate to the bitwidth of the output value. Value shiftedTable = - rewriter.create(lut->getLoc(), table, lookupValue); - const Value extracted = rewriter.create( - lut.getLoc(), shiftedTable, 0, + comb::ShrUOp::create(rewriter, lut->getLoc(), table, lookupValue); + const Value extracted = comb::ExtractOp::create( + rewriter, lut.getLoc(), shiftedTable, 0, lut.getOutput().getType().getIntOrFloatBitWidth()); rewriter.replaceOp(lut, extracted); @@ -275,13 +276,15 @@ struct LutToArray : OpConversionPattern { if (tableSize <= 256) return failure(); - Value table = rewriter.create( - lut.getLoc(), hw::ArrayType::get(lut.getType(), constantAttrs.size()), + Value table = hw::AggregateConstantOp::create( + rewriter, lut.getLoc(), + hw::ArrayType::get(lut.getType(), constantAttrs.size()), rewriter.getArrayAttr(constantAttrs)); - Value lookupValue = rewriter.create( - lut.getLoc(), rewriter.getIntegerType(inputBw), lut.getInputs()); + Value lookupValue = comb::ConcatOp::create(rewriter, lut.getLoc(), + rewriter.getIntegerType(inputBw), + lut.getInputs()); const Value extracted = - rewriter.create(lut.getLoc(), table, lookupValue); + hw::ArrayGetOp::create(rewriter, lut.getLoc(), table, lookupValue); rewriter.replaceOp(lut, extracted); return success(); diff --git a/lib/Dialect/Arc/Transforms/LowerState.cpp b/lib/Dialect/Arc/Transforms/LowerState.cpp index 2871076315..c7d566a3c1 100644 --- a/lib/Dialect/Arc/Transforms/LowerState.cpp +++ b/lib/Dialect/Arc/Transforms/LowerState.cpp @@ -190,9 +190,9 @@ LogicalResult ModuleLowering::run() { // Create the replacement `ModelOp`. auto modelOp = - builder.create(moduleOp.getLoc(), moduleOp.getModuleNameAttr(), - TypeAttr::get(moduleOp.getModuleType()), - FlatSymbolRefAttr{}, FlatSymbolRefAttr{}); + ModelOp::create(builder, moduleOp.getLoc(), moduleOp.getModuleNameAttr(), + TypeAttr::get(moduleOp.getModuleType()), + FlatSymbolRefAttr{}, FlatSymbolRefAttr{}); auto &modelBlock = modelOp.getBody().emplaceBlock(); storageArg = modelBlock.addArgument( StorageType::get(builder.getContext(), {}), modelOp.getLoc()); @@ -200,11 +200,11 @@ LogicalResult ModuleLowering::run() { // Create the `arc.initial` op to contain the ops for the initialization // phase. - auto initialOp = builder.create(moduleOp.getLoc()); + auto initialOp = InitialOp::create(builder, moduleOp.getLoc()); initialBuilder.setInsertionPointToStart(&initialOp.getBody().emplaceBlock()); // Create the `arc.final` op to contain the ops for the finalization phase. - auto finalOp = builder.create(moduleOp.getLoc()); + auto finalOp = FinalOp::create(builder, moduleOp.getLoc()); finalBuilder.setInsertionPointToStart(&finalOp.getBody().emplaceBlock()); // Position the alloc builder such that allocation ops get inserted above the @@ -214,8 +214,9 @@ LogicalResult ModuleLowering::run() { // Allocate storage for the inputs. for (auto arg : moduleOp.getBodyBlock()->getArguments()) { auto name = moduleOp.getArgName(arg.getArgNumber()); - auto state = allocBuilder.create( - arg.getLoc(), StateType::get(arg.getType()), name, storageArg); + auto state = + RootInputOp::create(allocBuilder, arg.getLoc(), + StateType::get(arg.getType()), name, storageArg); allocatedInputs.push_back(state); } @@ -315,15 +316,17 @@ Value ModuleLowering::getAllocatedState(OpResult result) { // Handle memories. if (auto memOp = dyn_cast(result.getOwner())) { - auto alloc = allocBuilder.create( - memOp.getLoc(), memOp.getType(), storageArg, memOp->getAttrs()); + auto alloc = + AllocMemoryOp::create(allocBuilder, memOp.getLoc(), memOp.getType(), + storageArg, memOp->getAttrs()); allocatedStates.insert({result, alloc}); return alloc; } // Create the allocation op. - auto alloc = allocBuilder.create( - result.getLoc(), StateType::get(result.getType()), storageArg); + auto alloc = + AllocStateOp::create(allocBuilder, result.getLoc(), + StateType::get(result.getType()), storageArg); allocatedStates.insert({result, alloc}); // HACK: If the result comes from an instance op, add the instance and port @@ -351,20 +354,20 @@ Value ModuleLowering::getAllocatedState(OpResult result) { Value ModuleLowering::detectPosedge(Value clock) { auto loc = clock.getLoc(); if (isa(clock.getType())) - clock = builder.create(loc, clock); + clock = seq::FromClockOp::create(builder, loc, clock); // Allocate storage to store the previous clock value. - auto oldStorage = allocBuilder.create( - loc, StateType::get(builder.getI1Type()), storageArg); + auto oldStorage = AllocStateOp::create( + allocBuilder, loc, StateType::get(builder.getI1Type()), storageArg); // Read the old clock value from storage and write the new clock value to // storage. - auto oldClock = builder.create(loc, oldStorage); - builder.create(loc, oldStorage, clock, Value{}); + auto oldClock = StateReadOp::create(builder, loc, oldStorage); + StateWriteOp::create(builder, loc, oldStorage, clock, Value{}); // Detect a rising edge. - auto edge = builder.create(loc, oldClock, clock); - return builder.create(loc, edge, clock); + auto edge = comb::XorOp::create(builder, loc, oldClock, clock); + return comb::AndOp::create(builder, loc, edge, clock); } /// Get the builder appropriate for the given phase. @@ -402,7 +405,7 @@ static scf::IfOp createOrReuseIf(OpBuilder &builder, Value condition, if (auto ifOp = dyn_cast(*std::prev(ip))) if (ifOp.getCondition() == condition) return ifOp; - return builder.create(condition.getLoc(), condition, withElse); + return scf::IfOp::create(builder, condition.getLoc(), condition, withElse); } /// This function is called from the lowering worklist in order to perform a @@ -483,8 +486,8 @@ LogicalResult OpLowering::lower(StateOp op) { auto state = module.getAllocatedState(result); if (!state) return failure(); - module.initialBuilder.create(value.getLoc(), state, value, - Value{}); + StateWriteOp::create(module.initialBuilder, value.getLoc(), state, value, + Value{}); } return success(); } @@ -500,9 +503,9 @@ LogicalResult OpLowering::lower(StateOp op) { return lowerStateful(op.getClock(), op.getEnable(), op.getReset(), op.getInputs(), op.getResults(), [&](ValueRange inputs) { - return module.builder - .create(op.getLoc(), op.getResultTypes(), - op.getArc(), inputs) + return CallOp::create(module.builder, op.getLoc(), + op.getResultTypes(), op.getArc(), + inputs) .getResults(); }); } @@ -526,8 +529,9 @@ LogicalResult OpLowering::lower(sim::DPICallOp op) { return op.emitOpError() << "without clock cannot have an enable"; // Lower the op to a regular function call. - auto callOp = module.getBuilder(phase).create( - op.getLoc(), op.getCalleeAttr(), op.getResultTypes(), inputs); + auto callOp = + func::CallOp::create(module.getBuilder(phase), op.getLoc(), + op.getCalleeAttr(), op.getResultTypes(), inputs); for (auto [oldResult, newResult] : llvm::zip(op.getResults(), callOp.getResults())) module.loweredValues[{oldResult, phase}] = newResult; @@ -538,10 +542,10 @@ LogicalResult OpLowering::lower(sim::DPICallOp op) { return lowerStateful(op.getClock(), op.getEnable(), /*reset=*/{}, op.getInputs(), op.getResults(), [&](ValueRange inputs) { - return module.builder - .create(op.getLoc(), - op.getCalleeAttr(), - op.getResultTypes(), inputs) + return func::CallOp::create( + module.builder, op.getLoc(), + op.getCalleeAttr(), op.getResultTypes(), + inputs) .getResults(); }); } @@ -607,14 +611,14 @@ LogicalResult OpLowering::lowerStateful( // Generate the zero value writes. for (auto state : states) { auto type = cast(state.getType()).getType(); - Value value = module.builder.create( - loweredReset.getLoc(), + Value value = ConstantOp::create( + module.builder, loweredReset.getLoc(), module.builder.getIntegerType(hw::getBitWidth(type)), 0); if (value.getType() != type) - value = module.builder.create(loweredReset.getLoc(), type, - value); - module.builder.create(loweredReset.getLoc(), state, value, - Value{}); + value = BitcastOp::create(module.builder, loweredReset.getLoc(), type, + value); + StateWriteOp::create(module.builder, loweredReset.getLoc(), state, value, + Value{}); } module.builder.setInsertionPoint(ifResetOp.elseYield()); } @@ -649,14 +653,14 @@ LogicalResult OpLowering::lowerStateful( // Compute the transfer function and write its results to the state's storage. auto loweredResults = createMapping(loweredInputs); for (auto [state, value] : llvm::zip(states, loweredResults)) - module.builder.create(value.getLoc(), state, value, Value{}); + StateWriteOp::create(module.builder, value.getLoc(), state, value, Value{}); // Since we just wrote the new state value to storage, insert read ops just // before the if op that keep the old value around for any later ops that // still need it. module.builder.setInsertionPoint(ifClockOp); for (auto [state, result] : llvm::zip(states, results)) { - auto oldValue = module.builder.create(result.getLoc(), state); + auto oldValue = StateReadOp::create(module.builder, result.getLoc(), state); module.loweredValues[{result, Phase::Old}] = oldValue; } @@ -734,8 +738,9 @@ LogicalResult OpLowering::lower(MemoryOp op) { return failure(); inputs.push_back(lowered); } - auto callOp = module.builder.create( - write.getLoc(), write.getArcResultTypes(), write.getArc(), inputs); + auto callOp = + CallOp::create(module.builder, write.getLoc(), + write.getArcResultTypes(), write.getArc(), inputs); // If the write has an enable, wrap the remaining logic in an if op. if (write.getEnable()) { @@ -752,21 +757,22 @@ LogicalResult OpLowering::lower(MemoryOp op) { auto mask = callOp.getResult(write.getMaskIdx(write.getEnable())); auto maskInv = module.builder.createOrFold( write.getLoc(), mask, - module.builder.create(write.getLoc(), mask.getType(), -1), + ConstantOp::create(module.builder, write.getLoc(), mask.getType(), + -1), true); auto oldData = - module.builder.create(write.getLoc(), state, address); - auto oldMasked = module.builder.create( - write.getLoc(), maskInv, oldData, true); + MemoryReadOp::create(module.builder, write.getLoc(), state, address); + auto oldMasked = comb::AndOp::create(module.builder, write.getLoc(), + maskInv, oldData, true); auto newMasked = - module.builder.create(write.getLoc(), mask, data, true); - data = module.builder.create(write.getLoc(), oldMasked, - newMasked, true); + comb::AndOp::create(module.builder, write.getLoc(), mask, data, true); + data = comb::OrOp::create(module.builder, write.getLoc(), oldMasked, + newMasked, true); } // Actually write to the memory. - module.builder.create(write.getLoc(), state, address, - Value{}, data); + MemoryWriteOp::create(module.builder, write.getLoc(), state, address, + Value{}, data); } return success(); @@ -785,12 +791,13 @@ LogicalResult OpLowering::lower(TapOp op) { auto &state = module.allocatedTaps[op]; if (!state) { - auto alloc = module.allocBuilder.create( - op.getLoc(), StateType::get(value.getType()), module.storageArg, true); + auto alloc = AllocStateOp::create(module.allocBuilder, op.getLoc(), + StateType::get(value.getType()), + module.storageArg, true); alloc->setAttr("name", op.getNameAttr()); state = alloc; } - module.builder.create(op.getLoc(), state, value, Value{}); + StateWriteOp::create(module.builder, op.getLoc(), state, value, Value{}); return success(); } @@ -812,12 +819,13 @@ LogicalResult OpLowering::lower(InstanceOp op) { // Then allocate storage for each instance input and assign the corresponding // value. for (auto [value, name] : llvm::zip(values, op.getArgNames())) { - auto state = module.allocBuilder.create( - value.getLoc(), StateType::get(value.getType()), module.storageArg); + auto state = AllocStateOp::create(module.allocBuilder, value.getLoc(), + StateType::get(value.getType()), + module.storageArg); state->setAttr("name", module.builder.getStringAttr( op.getInstanceName() + "/" + cast(name).getValue())); - module.builder.create(value.getLoc(), state, value, Value{}); + StateWriteOp::create(module.builder, value.getLoc(), state, value, Value{}); } // HACK: Also ensure that storage has been allocated for all outputs. @@ -847,10 +855,10 @@ LogicalResult OpLowering::lower(hw::OutputOp op) { // Then allocate storage for each output and assign the corresponding value. for (auto [value, name] : llvm::zip(values, module.moduleOp.getOutputNames())) { - auto state = module.allocBuilder.create( - value.getLoc(), StateType::get(value.getType()), cast(name), - module.storageArg); - module.builder.create(value.getLoc(), state, value, Value{}); + auto state = RootOutputOp::create( + module.allocBuilder, value.getLoc(), StateType::get(value.getType()), + cast(name), module.storageArg); + StateWriteOp::create(module.builder, value.getLoc(), state, value, Value{}); } return success(); } @@ -947,12 +955,13 @@ LogicalResult OpLowering::lower(llhd::FinalOp op) { // Create a new `scf.execute_region` op and clone the entire `llhd.final` body // region into it. Replace `llhd.halt` ops with `scf.yield`. - auto executeOp = module.finalBuilder.create( - op.getLoc(), TypeRange{}); + auto executeOp = scf::ExecuteRegionOp::create(module.finalBuilder, + op.getLoc(), TypeRange{}); module.finalBuilder.cloneRegionBefore(op.getBody(), executeOp.getRegion(), executeOp.getRegion().begin(), mapping); executeOp.walk([&](llhd::HaltOp op) { - OpBuilder(op).create(op.getLoc()); + auto builder = OpBuilder(op); + scf::YieldOp::create(builder, op.getLoc()); op.erase(); }); @@ -988,7 +997,7 @@ Value OpLowering::lowerValue(Value value, Phase phase) { if (initial) return {}; auto state = module.allocatedInputs[arg.getArgNumber()]; - return module.getBuilder(phase).create(arg.getLoc(), state); + return StateReadOp::create(module.getBuilder(phase), arg.getLoc(), state); } // Check if the value has already been lowered. @@ -1031,7 +1040,7 @@ Value OpLowering::lowerValue(InstanceOp op, OpResult result, Phase phase) { if (initial) return {}; auto state = module.getAllocatedState(result); - return module.getBuilder(phase).create(result.getLoc(), state); + return StateReadOp::create(module.getBuilder(phase), result.getLoc(), state); } /// Handle uses of a state. This creates an `arc.state_read` op to read from the @@ -1053,7 +1062,7 @@ Value OpLowering::lowerValue(StateOp op, OpResult result, Phase phase) { "need old value but new value already written"); auto state = module.getAllocatedState(result); - return module.getBuilder(phase).create(result.getLoc(), state); + return StateReadOp::create(module.getBuilder(phase), result.getLoc(), state); } /// Handle uses of a DPI call. This creates an `arc.state_read` op to read from @@ -1075,7 +1084,7 @@ Value OpLowering::lowerValue(sim::DPICallOp op, OpResult result, Phase phase) { "need old value but new value already written"); auto state = module.getAllocatedState(result); - return module.getBuilder(phase).create(result.getLoc(), state); + return StateReadOp::create(module.getBuilder(phase), result.getLoc(), state); } /// Handle uses of a memory read operation. This creates an `arc.memory_read` op @@ -1109,8 +1118,8 @@ Value OpLowering::lowerValue(MemoryReadPortOp op, OpResult result, } auto state = module.getAllocatedState(memOp->getResult(0)); - return module.getBuilder(phase).create(result.getLoc(), state, - address); + return MemoryReadOp::create(module.getBuilder(phase), result.getLoc(), state, + address); } /// Handle uses of `seq.initial` values computed during the initial phase. This @@ -1137,16 +1146,17 @@ Value OpLowering::lowerValue(seq::InitialOp op, OpResult result, Phase phase) { // initial phase. auto &state = module.allocatedInitials[result]; if (!state) { - state = module.allocBuilder.create( - value.getLoc(), StateType::get(value.getType()), module.storageArg); + state = AllocStateOp::create(module.allocBuilder, value.getLoc(), + StateType::get(value.getType()), + module.storageArg); OpBuilder::InsertionGuard guard(module.initialBuilder); module.initialBuilder.setInsertionPointAfterValue(value); - module.initialBuilder.create(value.getLoc(), state, value, - Value{}); + StateWriteOp::create(module.initialBuilder, value.getLoc(), state, value, + Value{}); } // Read back the value computed during the initial phase. - return module.getBuilder(phase).create(state.getLoc(), state); + return StateReadOp::create(module.getBuilder(phase), state.getLoc(), state); } /// The `seq.from_immutable` cast is just a passthrough. diff --git a/lib/Dialect/Arc/Transforms/LowerVectorizations.cpp b/lib/Dialect/Arc/Transforms/LowerVectorizations.cpp index cd09a45fb2..a0dccfd66a 100644 --- a/lib/Dialect/Arc/Transforms/LowerVectorizations.cpp +++ b/lib/Dialect/Arc/Transforms/LowerVectorizations.cpp @@ -57,20 +57,20 @@ static VectorizeOp lowerBoundaryScalar(VectorizeOp op) { for (ValueRange range : op.getInputs()) { unsigned bw = range.front().getType().getIntOrFloatBitWidth(); - vectors.push_back(builder - .create( - builder.getIntegerType(bw * range.size()), range) - ->getResults()); + vectors.push_back( + comb::ConcatOp::create(builder, + builder.getIntegerType(bw * range.size()), range) + ->getResults()); } unsigned width = op->getResult(0).getType().getIntOrFloatBitWidth(); - VectorizeOp newOp = builder.create( - builder.getIntegerType(width * op->getNumResults()), vectors); + VectorizeOp newOp = VectorizeOp::create( + builder, builder.getIntegerType(width * op->getNumResults()), vectors); newOp.getBody().takeBody(op.getBody()); for (OpResult res : op.getResults()) { - Value newRes = builder.create( - newOp.getResult(0), width * res.getResultNumber(), width); + Value newRes = comb::ExtractOp::create( + builder, newOp.getResult(0), width * res.getResultNumber(), width); res.replaceAllUsesWith(newRes); } @@ -119,21 +119,22 @@ static VectorizeOp lowerBoundaryVector(VectorizeOp op) { range.front().getType()); if (llvm::all_equal(range)) { vectors.push_back( - builder.create(type, range.front()) + vector::BroadcastOp::create(builder, type, range.front()) ->getResults()); continue; } // Otherwise do a gather. ValueRange vector = - builder - .create(DenseElementsAttr::get( + arith::ConstantOp::create( + builder, + DenseElementsAttr::get( type, SmallVector( range.size(), builder.getIntegerAttr(type.getElementType(), 0)))) ->getResults(); for (auto [i, element] : llvm::enumerate(range)) - vector = builder.create(element, vector.front(), i) + vector = vector::InsertOp::create(builder, element, vector.front(), i) ->getResults(); vectors.push_back(vector); @@ -141,12 +142,12 @@ static VectorizeOp lowerBoundaryVector(VectorizeOp op) { VectorType resType = VectorType::get( SmallVector(1, op->getNumResults()), op.getResult(0).getType()); - VectorizeOp newOp = builder.create(resType, vectors); + VectorizeOp newOp = VectorizeOp::create(builder, resType, vectors); newOp.getBody().takeBody(op.getBody()); for (OpResult res : op.getResults()) - res.replaceAllUsesWith(builder.create( - newOp.getResult(0), res.getResultNumber())); + res.replaceAllUsesWith(vector::ExtractOp::create( + builder, newOp.getResult(0), res.getResultNumber())); op->erase(); return newOp; diff --git a/lib/Dialect/Arc/Transforms/LowerVerifSimulations.cpp b/lib/Dialect/Arc/Transforms/LowerVerifSimulations.cpp index 34c9dea30f..acd239df79 100644 --- a/lib/Dialect/Arc/Transforms/LowerVerifSimulations.cpp +++ b/lib/Dialect/Arc/Transforms/LowerVerifSimulations.cpp @@ -59,8 +59,9 @@ void LowerVerifSimulationsPass::runOnOperation() { return signalPassFailure(); } } else { - auto func = builder.create( - getOperation().getLoc(), builder.getStringAttr("exit"), exitFuncType); + auto func = + func::FuncOp::create(builder, getOperation().getLoc(), + builder.getStringAttr("exit"), exitFuncType); SymbolTable::setSymbolVisibility(func, SymbolTable::Visibility::Private); } @@ -108,7 +109,7 @@ void LowerVerifSimulationsPass::lowerSimulation(verif::SimulationOp op, // Replace the `verif.yield` operation with an `hw.output`. OpBuilder builder(yieldOp); - builder.create(yieldOp->getLoc(), yieldOp->getOperands()); + hw::OutputOp::create(builder, yieldOp->getLoc(), yieldOp->getOperands()); yieldOp->erase(); // Move the body of the simulation into a separate HW module. @@ -116,25 +117,25 @@ void LowerVerifSimulationsPass::lowerSimulation(verif::SimulationOp op, auto implName = StringAttr::get(context, Twine("verif.simulation.impl.") + op.getSymName()); auto loc = op.getLoc(); - auto implOp = builder.create(loc, implName, implPorts); + auto implOp = hw::HWModuleOp::create(builder, loc, implName, implPorts); symbolTable.insert(implOp); implOp.getBody().takeBody(op.getBodyRegion()); // Create a new function for the verification op. auto funcType = builder.getFunctionType({}, {}); auto funcOp = - builder.create(loc, op.getSymNameAttr(), funcType); + func::FuncOp::create(builder, loc, op.getSymNameAttr(), funcType); auto *funcBody = builder.createBlock(&funcOp.getBody()); - auto falseOp = builder.create(loc, i1Type, 0); - auto trueOp = builder.create(loc, i1Type, 1); - auto lowOp = builder.create(loc, falseOp); - auto highOp = builder.create(loc, trueOp); + auto falseOp = hw::ConstantOp::create(builder, loc, i1Type, 0); + auto trueOp = hw::ConstantOp::create(builder, loc, i1Type, 1); + auto lowOp = seq::ToClockOp::create(builder, loc, falseOp); + auto highOp = seq::ToClockOp::create(builder, loc, trueOp); // Instantiate the implementation module. auto instType = SimModelInstanceType::get( context, FlatSymbolRefAttr::get(implOp.getSymNameAttr())); - auto instOp = builder.create(loc); + auto instOp = SimInstantiateOp::create(builder, loc); auto *instBody = builder.createBlock(&instOp.getBody(), {}, {instType}, {loc}); auto instArg = instBody->getArgument(0); @@ -142,57 +143,57 @@ void LowerVerifSimulationsPass::lowerSimulation(verif::SimulationOp op, // Create an `scf.execute_region` op inside such that we can use simple // control flow in the `arc.sim.instantiate` op body. This is simpler than // setting up an `scf.while` op. - auto execOp = builder.create(loc, TypeRange{}); + auto execOp = scf::ExecuteRegionOp::create(builder, loc, TypeRange{}); builder.setInsertionPointToEnd(&execOp.getRegion().emplaceBlock()); // Apply the initial clock tick to the design. - builder.create(loc, instArg, clockName, lowOp); - builder.create(loc, instArg, initName, trueOp); - builder.create(loc, instArg); - builder.create(loc, instArg, clockName, highOp); - builder.create(loc, instArg); - builder.create(loc, instArg, clockName, lowOp); - builder.create(loc, instArg, initName, falseOp); - builder.create(loc, instArg); + SimSetInputOp::create(builder, loc, instArg, clockName, lowOp); + SimSetInputOp::create(builder, loc, instArg, initName, trueOp); + SimStepOp::create(builder, loc, instArg); + SimSetInputOp::create(builder, loc, instArg, clockName, highOp); + SimStepOp::create(builder, loc, instArg); + SimSetInputOp::create(builder, loc, instArg, clockName, lowOp); + SimSetInputOp::create(builder, loc, instArg, initName, falseOp); + SimStepOp::create(builder, loc, instArg); // Create the block that will perform a single clock tick. auto &loopBlock = execOp.getRegion().emplaceBlock(); - builder.create(loc, &loopBlock); + cf::BranchOp::create(builder, loc, &loopBlock); builder.setInsertionPointToEnd(&loopBlock); // Sample the done and success signals. auto doneSample = - builder.create(loc, i1Type, instArg, doneName); + SimGetPortOp::create(builder, loc, i1Type, instArg, doneName); auto successSample = - builder.create(loc, i1Type, instArg, successName); + SimGetPortOp::create(builder, loc, i1Type, instArg, successName); // Apply a full clock cycle to the design. - builder.create(loc, instArg, clockName, highOp); - builder.create(loc, instArg); - builder.create(loc, instArg, clockName, lowOp); - builder.create(loc, instArg); + SimSetInputOp::create(builder, loc, instArg, clockName, highOp); + SimStepOp::create(builder, loc, instArg); + SimSetInputOp::create(builder, loc, instArg, clockName, lowOp); + SimStepOp::create(builder, loc, instArg); // If done, exit the loop. auto &exitBlock = execOp.getRegion().emplaceBlock(); - builder.create(loc, doneSample, &exitBlock, &loopBlock); + cf::CondBranchOp::create(builder, loc, doneSample, &exitBlock, &loopBlock); builder.setInsertionPointToEnd(&exitBlock); // Convert the i1 success signal into an i32 failure signal that can be used // as an exit code. auto i32Type = builder.getI32Type(); - auto failureI32 = builder.create( - loc, i32Type, - builder.create( - loc, successSample, builder.create(loc, i1Type, 1))); + auto failureI32 = arith::ExtUIOp::create( + builder, loc, i32Type, + arith::XOrIOp::create(builder, loc, successSample, + hw::ConstantOp::create(builder, loc, i1Type, 1))); // Call exit with the computed exit code. - builder.create(loc, TypeRange{}, builder.getStringAttr("exit"), - ValueRange{failureI32}); - builder.create(loc); + func::CallOp::create(builder, loc, TypeRange{}, builder.getStringAttr("exit"), + ValueRange{failureI32}); + scf::YieldOp::create(builder, loc); // Create the final function return. builder.setInsertionPointToEnd(funcBody); - builder.create(loc); + func::ReturnOp::create(builder, loc); // Get rid of the original simulation op. op.erase(); diff --git a/lib/Dialect/Arc/Transforms/MakeTables.cpp b/lib/Dialect/Arc/Transforms/MakeTables.cpp index 49a2f093bf..9a13d57bd6 100644 --- a/lib/Dialect/Arc/Transforms/MakeTables.cpp +++ b/lib/Dialect/Arc/Transforms/MakeTables.cpp @@ -119,7 +119,7 @@ void MakeTablesPass::runOnArc(DefineOp defineOp) { SmallVector inputsToConcat(defineOp.getArguments()); std::reverse(inputsToConcat.begin(), inputsToConcat.end()); auto concatInputs = inputsToConcat.size() > 1 - ? builder.create(inputsToConcat) + ? comb::ConcatOp::create(builder, inputsToConcat) : inputsToConcat[0]; // Compute a lookup table for every output. @@ -170,10 +170,10 @@ void MakeTablesPass::runOnArc(DefineOp defineOp) { // Create the table lookup ops. for (auto [table, outputOperand] : llvm::zip(tables, outputOp->getOpOperands())) { - auto array = builder.create( - ArrayType::get(outputOperand.get().getType(), numTableEntries), + auto array = hw::AggregateConstantOp::create( + builder, ArrayType::get(outputOperand.get().getType(), numTableEntries), builder.getArrayAttr(table)); - outputOperand.set(builder.create(array, concatInputs)); + outputOperand.set(hw::ArrayGetOp::create(builder, array, concatInputs)); } for (auto *op : tabularizedOps) { diff --git a/lib/Dialect/Arc/Transforms/MuxToControlFlow.cpp b/lib/Dialect/Arc/Transforms/MuxToControlFlow.cpp index 90b5071102..8652c535e8 100644 --- a/lib/Dialect/Arc/Transforms/MuxToControlFlow.cpp +++ b/lib/Dialect/Arc/Transforms/MuxToControlFlow.cpp @@ -185,13 +185,13 @@ static void doConversion(Operation *op, BranchInfo info, // Build the scf.if operation with the scf.yields inside. ImplicitLocOpBuilder builder(op->getLoc(), op); - mlir::scf::IfOp ifOp = builder.create( - info.condition, + mlir::scf::IfOp ifOp = mlir::scf::IfOp::create( + builder, info.condition, [&](OpBuilder &builder, Location loc) { - builder.create(loc, info.trueValue); + mlir::scf::YieldOp::create(builder, loc, info.trueValue); }, [&](OpBuilder &builder, Location loc) { - builder.create(loc, info.falseValue); + mlir::scf::YieldOp::create(builder, loc, info.falseValue); }); op->getResult(0).replaceAllUsesWith(ifOp.getResult(0)); diff --git a/lib/Dialect/Arc/Transforms/SplitFuncs.cpp b/lib/Dialect/Arc/Transforms/SplitFuncs.cpp index 0efdaa798a..82271797d3 100644 --- a/lib/Dialect/Arc/Transforms/SplitFuncs.cpp +++ b/lib/Dialect/Arc/Transforms/SplitFuncs.cpp @@ -112,7 +112,7 @@ LogicalResult SplitFuncsPass::lowerFunc(FuncOp funcOp) { outValues.push_back(el); }); opBuilder.setInsertionPointToEnd(currentBlock); - opBuilder.create(funcOp->getLoc(), outValues); + ReturnOp::create(opBuilder, funcOp->getLoc(), outValues); } // Create and populate new FuncOps for (long unsigned i = 0; i < blocks.size() - 1; ++i) { @@ -132,8 +132,8 @@ LogicalResult SplitFuncsPass::lowerFunc(FuncOp funcOp) { funcName.append("_split_func"); funcName.append(std::to_string(i)); auto newFunc = - opBuilder.create(funcOp->getLoc(), funcName, - opBuilder.getFunctionType(argTypes, outTypes)); + FuncOp::create(opBuilder, funcOp->getLoc(), funcName, + opBuilder.getFunctionType(argTypes, outTypes)); ++numFuncsCreated; symbolTable->insert(newFunc); auto *funcBlock = newFunc.addEntryBlock(); @@ -150,8 +150,8 @@ LogicalResult SplitFuncsPass::lowerFunc(FuncOp funcOp) { for (auto pair : argMap) replaceAllUsesInRegionWith(pair.first, pair.second, newFunc.getRegion()); opBuilder.setInsertionPointToStart(blocks[i + 1]); - Operation *callOp = opBuilder.create( - funcOp->getLoc(), outTypes, funcName, args); + Operation *callOp = func::CallOp::create(opBuilder, funcOp->getLoc(), + outTypes, funcName, args); auto callResults = callOp->getResults(); argMap.clear(); for (unsigned long k = 0; k < outValues.size(); ++k) diff --git a/lib/Dialect/Arc/Transforms/SplitLoops.cpp b/lib/Dialect/Arc/Transforms/SplitLoops.cpp index 85d23fccde..9fe2d6bfdd 100644 --- a/lib/Dialect/Arc/Transforms/SplitLoops.cpp +++ b/lib/Dialect/Arc/Transforms/SplitLoops.cpp @@ -161,7 +161,7 @@ void Splitter::run(Block &block, DenseMap &coloring) { // Create the final `arc.output` op for each of the splits. for (auto &split : splits) - split->builder.create(loc, split->exportedValues); + arc::OutputOp::create(split->builder, loc, split->exportedValues); } /// Get or create the split for a given operation color. @@ -291,10 +291,11 @@ void SplitLoopsPass::splitArc(Namespace &arcNamespace, DefineOp defOp, if (splitter.splits.size() > 1) splitName = arcNamespace.newName(defOp.getSymName() + "_split_" + Twine(split->index)); - auto splitArc = builder.create( - splitName, builder.getFunctionType( - split->block->getArgumentTypes(), - split->block->getTerminator()->getOperandTypes())); + auto splitArc = + DefineOp::create(builder, splitName, + builder.getFunctionType( + split->block->getArgumentTypes(), + split->block->getTerminator()->getOperandTypes())); splitArc.getBody().push_back(split->block.release()); splitArcs.push_back(splitArc); ++numArcsCreated; @@ -365,7 +366,7 @@ void SplitLoopsPass::replaceArcUse(CallOpInterface arcUse, if (!getMappedValuesOrSchedule(split->importedValues, operands)) continue; - auto newUse = builder.create(splitDef, operands); + auto newUse = CallOp::create(builder, splitDef, operands); allArcUses.insert(newUse); newUses[split->index] = newUse; diff --git a/lib/Dialect/Arc/Transforms/StripSV.cpp b/lib/Dialect/Arc/Transforms/StripSV.cpp index db0de71ac8..298389da34 100644 --- a/lib/Dialect/Arc/Transforms/StripSV.cpp +++ b/lib/Dialect/Arc/Transforms/StripSV.cpp @@ -138,9 +138,8 @@ void StripSVPass::runOnOperation() { Value next; // Note: this register will have an sync reset regardless. if (reg.hasReset()) - next = builder.create(reg.getLoc(), reg.getReset(), - reg.getResetValue(), reg.getNext(), - false); + next = comb::MuxOp::create(builder, reg.getLoc(), reg.getReset(), + reg.getResetValue(), reg.getNext(), false); else next = reg.getNext(); @@ -154,9 +153,9 @@ void StripSVPass::runOnOperation() { IntegerAttr::get(reg.getType(), *reg.getPreset())); } - Value compReg = builder.create( - reg.getLoc(), next.getType(), next, reg.getClk(), reg.getNameAttr(), - Value{}, Value{}, /*initialValue*/ presetValue, + Value compReg = seq::CompRegOp::create( + builder, reg.getLoc(), next.getType(), next, reg.getClk(), + reg.getNameAttr(), Value{}, Value{}, /*initialValue*/ presetValue, reg.getInnerSymAttr()); reg.replaceAllUsesWith(compReg); opsToDelete.push_back(reg); @@ -169,9 +168,9 @@ void StripSVPass::runOnOperation() { auto modName = instOp.getModuleNameAttr().getAttr(); ImplicitLocOpBuilder builder(instOp.getLoc(), instOp); if (clockGateModuleNames.contains(modName)) { - auto gated = builder.create( - instOp.getOperand(0), instOp.getOperand(1), instOp.getOperand(2), - hw::InnerSymAttr{}); + auto gated = seq::ClockGateOp::create( + builder, instOp.getOperand(0), instOp.getOperand(1), + instOp.getOperand(2), hw::InnerSymAttr{}); instOp.replaceAllUsesWith(gated); opsToDelete.push_back(instOp); } diff --git a/lib/Dialect/Calyx/CalyxOps.cpp b/lib/Dialect/Calyx/CalyxOps.cpp index 8d464e1162..1293274a73 100644 --- a/lib/Dialect/Calyx/CalyxOps.cpp +++ b/lib/Dialect/Calyx/CalyxOps.cpp @@ -601,9 +601,9 @@ static void buildComponentLike(OpBuilder &builder, OperationState &result, // Insert the WiresOp and ControlOp. IRRewriter::InsertionGuard guard(builder); builder.setInsertionPointToStart(body); - builder.create(result.location); + WiresOp::create(builder, result.location); if (!combinational) - builder.create(result.location); + ControlOp::create(builder, result.location); } //===----------------------------------------------------------------------===// @@ -2437,12 +2437,12 @@ static LogicalResult commonTailPatternWithSeq(IfOpTy ifOp, // this IfOp is nested in a ParOp. This avoids unintentionally // parallelizing the pulled out EnableOps. rewriter.setInsertionPointAfter(ifOp); - SeqOpTy seqOp = rewriter.create(ifOp.getLoc()); + SeqOpTy seqOp = SeqOpTy::create(rewriter, ifOp.getLoc()); Block *body = seqOp.getBodyBlock(); ifOp->remove(); body->push_back(ifOp); rewriter.setInsertionPointToEnd(body); - rewriter.create(seqOp.getLoc(), lastThenEnableOp->getGroupName()); + EnableOp::create(rewriter, seqOp.getLoc(), lastThenEnableOp->getGroupName()); // Erase the common EnableOp from the Then and Else regions. rewriter.eraseOp(*lastThenEnableOp); @@ -2496,7 +2496,7 @@ static LogicalResult commonTailPatternWithPar(OpTy controlOp, // the pulled out EnableOps. rewriter.setInsertionPointAfter(controlOp); - ParOpTy parOp = rewriter.create(controlOp.getLoc()); + ParOpTy parOp = ParOpTy::create(rewriter, controlOp.getLoc()); Block *body = parOp.getBodyBlock(); controlOp->remove(); body->push_back(controlOp); @@ -2504,7 +2504,7 @@ static LogicalResult commonTailPatternWithPar(OpTy controlOp, // counterparts in the Then and Else regions. rewriter.setInsertionPointToEnd(body); for (StringRef groupName : groupNames) - rewriter.create(parOp.getLoc(), groupName); + EnableOp::create(rewriter, parOp.getLoc(), groupName); return success(); } diff --git a/lib/Dialect/Calyx/Transforms/AffineParallelUnroll.cpp b/lib/Dialect/Calyx/Transforms/AffineParallelUnroll.cpp index 63f017da53..7abc8e2a1e 100644 --- a/lib/Dialect/Calyx/Transforms/AffineParallelUnroll.cpp +++ b/lib/Dialect/Calyx/Transforms/AffineParallelUnroll.cpp @@ -260,8 +260,8 @@ struct AffineParallelUnroll : public OpRewritePattern { rewriter.getContext()); AffineMap ubMap = AffineMap::get(0, 0, rewriter.getAffineConstantExpr(1), rewriter.getContext()); - auto newParallelOp = rewriter.create( - loc, /*resultTypes=*/TypeRange(), + auto newParallelOp = AffineParallelOp::create( + rewriter, loc, /*resultTypes=*/TypeRange(), /*reductions=*/SmallVector(), /*lowerBoundsMap=*/lbMap, /*lowerBoundsOperands=*/SmallVector(), /*upperBoundsMap=*/ubMap, /*upperBoundsOperands=*/SmallVector(), @@ -294,7 +294,7 @@ struct AffineParallelUnroll : public OpRewritePattern { // Create an `scf.execute_region` to wrap each unrolled block since // `affine.parallel` requires only one block in the body region. auto executeRegionOp = - insideBuilder.create(loc, TypeRange{}); + scf::ExecuteRegionOp::create(insideBuilder, loc, TypeRange{}); Region &executeRegionRegion = executeRegionOp.getRegion(); Block *executeRegionBlock = &executeRegionRegion.emplaceBlock(); @@ -307,7 +307,7 @@ struct AffineParallelUnroll : public OpRewritePattern { // Map induction variables to constant indices for (unsigned i = 0; i < indices.size(); ++i) { Value ivConstant = - regionBuilder.create(loc, indices[i]); + arith::ConstantIndexOp::create(regionBuilder, loc, indices[i]); operandMap.map(pLoopIVs[i], ivConstant); } @@ -316,7 +316,7 @@ struct AffineParallelUnroll : public OpRewritePattern { regionBuilder.clone(*it, operandMap); // A terminator should always be inserted in `scf.execute_region`'s block. - regionBuilder.create(loc); + scf::YieldOp::create(regionBuilder, loc); // Increment indices using `step`. bool done = false; diff --git a/lib/Dialect/Calyx/Transforms/AffinePloopUnparallelize.cpp b/lib/Dialect/Calyx/Transforms/AffinePloopUnparallelize.cpp index cab1325850..af1c9a9405 100644 --- a/lib/Dialect/Calyx/Transforms/AffinePloopUnparallelize.cpp +++ b/lib/Dialect/Calyx/Transforms/AffinePloopUnparallelize.cpp @@ -79,8 +79,8 @@ public: SmallVector simplifiableIndexSwitchOps = collectSimplifiableIndexSwitchOps(affineParallelOp, factor); - auto outerLoop = rewriter.create( - loc, lowerBound, rewriter.getDimIdentityMap(), upperBound, + auto outerLoop = affine::AffineForOp::create( + rewriter, loc, lowerBound, rewriter.getDimIdentityMap(), upperBound, rewriter.getDimIdentityMap(), step * factor); rewriter.setInsertionPointToStart(outerLoop.getBody()); @@ -89,8 +89,8 @@ public: /*results=*/rewriter.getAffineConstantExpr(0), rewriter.getContext()); AffineMap ubMap = AffineMap::get( 0, 0, rewriter.getAffineConstantExpr(factor), rewriter.getContext()); - auto innerParallel = rewriter.create( - loc, /*resultTypes=*/TypeRange(), + auto innerParallel = affine::AffineParallelOp::create( + rewriter, loc, /*resultTypes=*/TypeRange(), /*reductions=*/SmallVector(), /*lowerBoundsMap=*/lbMap, /*lowerBoundsOperands=*/SmallVector(), /*upperBoundsMap=*/ubMap, /*upperBoundsOperands=*/SmallVector(), @@ -109,8 +109,8 @@ public: 2, 0, rewriter.getAffineDimExpr(0) + rewriter.getAffineDimExpr(1), rewriter.getContext()); - auto newIndex = rewriter.create( - loc, addMap, + auto newIndex = affine::AffineApplyOp::create( + rewriter, loc, addMap, ValueRange{outerLoop.getInductionVar(), innerParallel.getIVs()[0]}); Block *srcBlock = affineParallelOp.getBody(); @@ -133,7 +133,7 @@ public: }); rewriter.setInsertionPointToEnd(destBlock); - rewriter.create(loc); + affine::AffineYieldOp::create(rewriter, loc); for (auto indexSwitchOp : simplifiableIndexSwitchOps) { indexSwitchOp.setOperand(innerParallel.getIVs().front()); diff --git a/lib/Dialect/Calyx/Transforms/AffineToSCF.cpp b/lib/Dialect/Calyx/Transforms/AffineToSCF.cpp index e58d1ea0e1..a1659c2283 100644 --- a/lib/Dialect/Calyx/Transforms/AffineToSCF.cpp +++ b/lib/Dialect/Calyx/Transforms/AffineToSCF.cpp @@ -56,7 +56,7 @@ public: Location loc = affineParallelOp.getLoc(); SmallVector steps; for (int64_t step : affineParallelSteps) - steps.push_back(rewriter.create(loc, step)); + steps.push_back(arith::ConstantIndexOp::create(rewriter, loc, step)); auto upperBoundTuple = mlir::affine::expandAffineMap( rewriter, loc, affineParallelOp.getUpperBoundsMap(), @@ -69,8 +69,8 @@ public: auto affineParallelTerminator = cast( affineParallelOp.getBody()->getTerminator()); - scf::ParallelOp scfParallelOp = rewriter.create( - loc, *lowerBoundTuple, *upperBoundTuple, steps, + scf::ParallelOp scfParallelOp = scf::ParallelOp::create( + rewriter, loc, *lowerBoundTuple, *upperBoundTuple, steps, /*bodyBuilderFn=*/nullptr); scfParallelOp->setAttr("calyx.unroll", affineParallelOp->getAttr("calyx.unroll")); diff --git a/lib/Dialect/Calyx/Transforms/CalyxHelpers.cpp b/lib/Dialect/Calyx/Transforms/CalyxHelpers.cpp index cd5befee0b..7a8bdeebaf 100644 --- a/lib/Dialect/Calyx/Transforms/CalyxHelpers.cpp +++ b/lib/Dialect/Calyx/Transforms/CalyxHelpers.cpp @@ -24,7 +24,7 @@ calyx::RegisterOp createRegister(Location loc, OpBuilder &builder, Twine prefix) { OpBuilder::InsertionGuard guard(builder); builder.setInsertionPointToStart(component.getBodyBlock()); - return builder.create(loc, (prefix + "_reg").str(), width); + return RegisterOp::create(builder, loc, (prefix + "_reg").str(), width); } hw::ConstantOp createConstant(Location loc, OpBuilder &builder, @@ -32,8 +32,8 @@ hw::ConstantOp createConstant(Location loc, OpBuilder &builder, size_t value) { OpBuilder::InsertionGuard g(builder); builder.setInsertionPointToStart(component.getBodyBlock()); - return builder.create( - loc, APInt(width, value, /*isSigned=*/false)); + return hw::ConstantOp::create(builder, loc, + APInt(width, value, /*isSigned=*/false)); } calyx::InstanceOp createInstance(Location loc, OpBuilder &builder, @@ -43,8 +43,8 @@ calyx::InstanceOp createInstance(Location loc, OpBuilder &builder, StringRef componentName) { OpBuilder::InsertionGuard g(builder); builder.setInsertionPointToStart(component.getBodyBlock()); - return builder.create(loc, resultTypes, instanceName, - componentName); + return InstanceOp::create(builder, loc, resultTypes, instanceName, + componentName); } std::string getInstanceName(mlir::func::CallOp callOp) { diff --git a/lib/Dialect/Calyx/Transforms/CalyxLoweringUtils.cpp b/lib/Dialect/Calyx/Transforms/CalyxLoweringUtils.cpp index 55dd018ef0..f99f6273d7 100644 --- a/lib/Dialect/Calyx/Transforms/CalyxLoweringUtils.cpp +++ b/lib/Dialect/Calyx/Transforms/CalyxLoweringUtils.cpp @@ -174,10 +174,10 @@ void buildAssignmentsForRegisterWrite(OpBuilder &builder, mlir::IRRewriter::InsertionGuard guard(builder); auto loc = inputValue.getLoc(); builder.setInsertionPointToEnd(groupOp.getBodyBlock()); - builder.create(loc, reg.getIn(), inputValue); - builder.create( - loc, reg.getWriteEn(), createConstant(loc, builder, componentOp, 1, 1)); - builder.create(loc, reg.getDone()); + calyx::AssignOp::create(builder, loc, reg.getIn(), inputValue); + calyx::AssignOp::create(builder, loc, reg.getWriteEn(), + createConstant(loc, builder, componentOp, 1, 1)); + calyx::GroupDoneOp::create(builder, loc, reg.getDone()); } //===----------------------------------------------------------------------===// @@ -610,13 +610,13 @@ MultipleGroupDonePattern::matchAndRewrite(calyx::GroupOp groupOp, SmallVector doneOpSrcs; llvm::transform(groupDoneOps, std::back_inserter(doneOpSrcs), [](calyx::GroupDoneOp op) { return op.getSrc(); }); - Value allDone = rewriter.create(groupDoneOps.front().getLoc(), - doneOpSrcs, false); + Value allDone = comb::AndOp::create(rewriter, groupDoneOps.front().getLoc(), + doneOpSrcs, false); /// Create a group done op with the complex expression as a guard. - rewriter.create( - groupOp.getLoc(), - rewriter.create(groupOp.getLoc(), APInt(1, 1)), allDone); + calyx::GroupDoneOp::create( + rewriter, groupOp.getLoc(), + hw::ConstantOp::create(rewriter, groupOp.getLoc(), APInt(1, 1)), allDone); for (auto groupDoneOp : groupDoneOps) rewriter.eraseOp(groupDoneOp); @@ -775,8 +775,8 @@ RewriteMemoryAccesses::partiallyLower(calyx::AssignOp assignOp, rewriter.setInsertionPoint(assignOp->getBlock(), assignOp->getBlock()->begin()); - rewriter.create(assignOp->getLoc(), newOp->getResult(0), - src); + calyx::AssignOp::create(rewriter, assignOp->getLoc(), newOp->getResult(0), + src); assignOp.setOperand(1, newOp->getResult(1)); return success(); @@ -828,8 +828,8 @@ BuildReturnRegs::partiallyLowerFuncToComp(mlir::func::FuncOp funcOp, rewriter.setInsertionPointToStart( getComponent().getWiresOp().getBodyBlock()); - rewriter.create( - funcOp->getLoc(), + calyx::AssignOp::create( + rewriter, funcOp->getLoc(), calyx::getComponentOutput( getComponent(), getState().getFuncOpResultMapping(argType.index())), reg.getOut()); diff --git a/lib/Dialect/Calyx/Transforms/ClkResetInsertion.cpp b/lib/Dialect/Calyx/Transforms/ClkResetInsertion.cpp index 7afbcc2c77..91df6ae320 100644 --- a/lib/Dialect/Calyx/Transforms/ClkResetInsertion.cpp +++ b/lib/Dialect/Calyx/Transforms/ClkResetInsertion.cpp @@ -45,7 +45,7 @@ static void doPortPassthrough(ComponentOp comp, Value fromPort, for (auto port : cell.getInputPorts()) { if (!cell.portInfo(port).hasAttribute(portID)) continue; - builder.create(cell.getLoc(), port, fromPort); + AssignOp::create(builder, cell.getLoc(), port, fromPort); } } } diff --git a/lib/Dialect/Calyx/Transforms/CompileControl.cpp b/lib/Dialect/Calyx/Transforms/CompileControl.cpp index 056506936a..59a69e1e3b 100644 --- a/lib/Dialect/Calyx/Transforms/CompileControl.cpp +++ b/lib/Dialect/Calyx/Transforms/CompileControl.cpp @@ -94,7 +94,7 @@ void CompileControlVisitor::visit(SeqOp seq, ComponentOp &component) { // Create the new compilation group to replace this SeqOp. builder.setInsertionPointToEnd(wiresBody); auto seqGroup = - builder.create(wires->getLoc(), builder.getStringAttr("seq")); + GroupOp::create(builder, wires->getLoc(), builder.getStringAttr("seq")); // Guarantees a unique SymbolName for the group. auto &symTable = am.getChildAnalysis(wires); @@ -118,25 +118,25 @@ void CompileControlVisitor::visit(SeqOp seq, ComponentOp &component) { auto guard = groupOp.getDoneOp().getGuard(); Value source = groupOp.getDoneOp().getSrc(); auto doneOpValue = !guard ? source - : builder.create( - wires->getLoc(), guard, source, false); + : comb::AndOp::create(builder, wires->getLoc(), + guard, source, false); // Build the Guard for the `go` signal of the current group being walked. // The group should begin when: // (1) the current step in the fsm is reached, and // (2) the done signal of this group is not high. auto eqCmp = - builder.create(wires->getLoc(), comb::ICmpPredicate::eq, - fsmOut, fsmCurrentState, false); + comb::ICmpOp::create(builder, wires->getLoc(), comb::ICmpPredicate::eq, + fsmOut, fsmCurrentState, false); auto notDone = comb::createOrFoldNot(wires->getLoc(), doneOpValue, builder); auto groupGoGuard = - builder.create(wires->getLoc(), eqCmp, notDone, false); + comb::AndOp::create(builder, wires->getLoc(), eqCmp, notDone, false); // Guard for the `in` and `write_en` signal of the fsm register. These are // driven when the group has completed. builder.setInsertionPoint(seqGroup); - auto groupDoneGuard = - builder.create(wires->getLoc(), eqCmp, doneOpValue, false); + auto groupDoneGuard = comb::AndOp::create(builder, wires->getLoc(), eqCmp, + doneOpValue, false); // Directly update the GroupGoOp of the current group being walked. auto goOp = groupOp.getGoOp(); @@ -147,10 +147,10 @@ void CompileControlVisitor::visit(SeqOp seq, ComponentOp &component) { fsmNextState = createConstant(wires->getLoc(), builder, component, fsmBitWidth, fsmIndex + 1); builder.setInsertionPointToEnd(seqGroup.getBodyBlock()); - builder.create(wires->getLoc(), fsmIn, fsmNextState, - groupDoneGuard); - builder.create(wires->getLoc(), fsmWriteEn, oneConstant, - groupDoneGuard); + AssignOp::create(builder, wires->getLoc(), fsmIn, fsmNextState, + groupDoneGuard); + AssignOp::create(builder, wires->getLoc(), fsmWriteEn, oneConstant, + groupDoneGuard); // Increment the fsm index for the next group. ++fsmIndex; }); @@ -158,27 +158,27 @@ void CompileControlVisitor::visit(SeqOp seq, ComponentOp &component) { // Build the final guard for the new Seq group's GroupDoneOp. This is // defined by the fsm's final state. builder.setInsertionPoint(seqGroup); - auto isFinalState = builder.create( - wires->getLoc(), comb::ICmpPredicate::eq, fsmOut, fsmNextState, false); + auto isFinalState = + comb::ICmpOp::create(builder, wires->getLoc(), comb::ICmpPredicate::eq, + fsmOut, fsmNextState, false); // Insert the respective GroupDoneOp. builder.setInsertionPointToEnd(seqGroup.getBodyBlock()); - builder.create(seqGroup->getLoc(), oneConstant, isFinalState); + GroupDoneOp::create(builder, seqGroup->getLoc(), oneConstant, isFinalState); // Add continuous wires to reset the `in` and `write_en` ports of the fsm // when the SeqGroup is finished executing. builder.setInsertionPointToEnd(wiresBody); auto zeroConstant = createConstant(wires->getLoc(), builder, component, fsmBitWidth, 0); - builder.create(wires->getLoc(), fsmIn, zeroConstant, isFinalState); - builder.create(wires->getLoc(), fsmWriteEn, oneConstant, - isFinalState); + AssignOp::create(builder, wires->getLoc(), fsmIn, zeroConstant, isFinalState); + AssignOp::create(builder, wires->getLoc(), fsmWriteEn, oneConstant, + isFinalState); // Replace the SeqOp with an EnableOp. builder.setInsertionPoint(seq); - builder.create( - seq->getLoc(), seqGroup.getSymName(), - ArrayAttr::get(builder.getContext(), compiledGroups)); + EnableOp::create(builder, seq->getLoc(), seqGroup.getSymName(), + ArrayAttr::get(builder.getContext(), compiledGroups)); seq->erase(); } diff --git a/lib/Dialect/Calyx/Transforms/GoInsertion.cpp b/lib/Dialect/Calyx/Transforms/GoInsertion.cpp index 433db67245..223fc1d558 100644 --- a/lib/Dialect/Calyx/Transforms/GoInsertion.cpp +++ b/lib/Dialect/Calyx/Transforms/GoInsertion.cpp @@ -43,13 +43,13 @@ void GoInsertionPass::runOnOperation() { OpBuilder builder(wiresOp->getRegion(0)); auto undefinedOp = - builder.create(wiresOp->getLoc(), builder.getI1Type()); + UndefinedOp::create(builder, wiresOp->getLoc(), builder.getI1Type()); wiresOp.walk([&](GroupOp group) { OpBuilder builder(group->getRegion(0)); // Since the source of a GroupOp's go signal isn't set until the // the Compile Control pass, use an undefined value. - auto goOp = builder.create(group->getLoc(), undefinedOp); + auto goOp = GroupGoOp::create(builder, group->getLoc(), undefinedOp); updateGroupAssignmentGuards(builder, group, goOp); }); diff --git a/lib/Dialect/Calyx/Transforms/RemoveCombGroups.cpp b/lib/Dialect/Calyx/Transforms/RemoveCombGroups.cpp index b777b52da9..7f48c82278 100644 --- a/lib/Dialect/Calyx/Transforms/RemoveCombGroups.cpp +++ b/lib/Dialect/Calyx/Transforms/RemoveCombGroups.cpp @@ -98,8 +98,8 @@ static calyx::RegisterOp createReg(ComponentOp component, Twine prefix, size_t width) { IRRewriter::InsertionGuard guard(rewriter); rewriter.setInsertionPointToStart(component.getBodyBlock()); - return rewriter.create(loc, (prefix + "_reg").str(), - width); + return calyx::RegisterOp::create(rewriter, loc, (prefix + "_reg").str(), + width); } // Wraps the provided 'op' inside a newly created TOp operation, and @@ -108,7 +108,7 @@ template static TOp wrapInsideOp(OpBuilder &builder, Operation *op) { OpBuilder::InsertionGuard g(builder); builder.setInsertionPoint(op); - auto newOp = builder.create(op->getLoc()); + auto newOp = TOp::create(builder, op->getLoc()); op->moveBefore(newOp.getBodyBlock(), newOp.getBodyBlock()->begin()); return newOp; } @@ -125,8 +125,8 @@ struct RemoveCombGroupsPattern : public OpRewritePattern { PatternRewriter &rewriter) const override { auto component = combGroup->getParentOfType(); - auto group = rewriter.create(combGroup.getLoc(), - combGroup.getName()); + auto group = calyx::GroupOp::create(rewriter, combGroup.getLoc(), + combGroup.getName()); rewriter.mergeBlocks(combGroup.getBodyBlock(), group.getBodyBlock()); rewriter.replaceOp(combGroup, group); @@ -139,8 +139,9 @@ struct RemoveCombGroupsPattern : public OpRewritePattern { } rewriter.setInsertionPointToStart(group.getBodyBlock()); - auto oneConstant = rewriter.create( - group.getLoc(), APInt(1, 1, /*isSigned=*/true, /*implicitTrunc=*/true)); + auto oneConstant = hw::ConstantOp::create( + rewriter, group.getLoc(), + APInt(1, 1, /*isSigned=*/true, /*implicitTrunc=*/true)); // Maintain the set of cell results which have already been assigned to // its register within this group. @@ -177,11 +178,10 @@ struct RemoveCombGroupsPattern : public OpRewritePattern { // Assign the cell result register - a register should only be // assigned once within a group. if (!alreadyAssignedResults.contains(combRes)) { - rewriter.create(combRes.getLoc(), - combResReg->second.getIn(), combRes); - rewriter.create(combRes.getLoc(), - combResReg->second.getWriteEn(), - oneConstant); + AssignOp::create(rewriter, combRes.getLoc(), + combResReg->second.getIn(), combRes); + AssignOp::create(rewriter, combRes.getLoc(), + combResReg->second.getWriteEn(), oneConstant); alreadyAssignedResults.insert(combRes); } @@ -196,11 +196,11 @@ struct RemoveCombGroupsPattern : public OpRewritePattern { assert(!registerDoneSigs.empty() && "No registers assigned in the combinational group?"); rewriter.setInsertionPointToEnd(group.getBodyBlock()); - rewriter.create( - group.getLoc(), - rewriter.create(group.getLoc(), APInt(1, 1)), - rewriter.create(combGroup.getLoc(), rewriter.getI1Type(), - registerDoneSigs.takeVector())); + calyx::GroupDoneOp::create( + rewriter, group.getLoc(), + hw::ConstantOp::create(rewriter, group.getLoc(), APInt(1, 1)), + comb::AndOp::create(rewriter, combGroup.getLoc(), rewriter.getI1Type(), + registerDoneSigs.takeVector())); return success(); } @@ -223,7 +223,7 @@ struct RemoveCombGroupsPass // Ensure that we're inside a sequential control composition. wrapInsideOp(builder, ifOp); builder.setInsertionPoint(ifOp); - builder.create(ifOp.getLoc(), groupName.value()); + EnableOp::create(builder, ifOp.getLoc(), groupName.value()); ifOp.removeGroupNameAttr(); }); } @@ -237,16 +237,16 @@ struct RemoveCombGroupsPass // Ensure that we're inside a sequential control composition. wrapInsideOp(builder, whileOp); builder.setInsertionPoint(whileOp); - builder.create(whileOp.getLoc(), groupName); + EnableOp::create(builder, whileOp.getLoc(), groupName); whileOp.removeGroupNameAttr(); // Also schedule the group at the end of the while body. auto &curWhileBodyOp = whileOp.getBodyBlock()->front(); builder.setInsertionPointToStart(whileOp.getBodyBlock()); - auto newSeqBody = builder.create(curWhileBodyOp.getLoc()); + auto newSeqBody = SeqOp::create(builder, curWhileBodyOp.getLoc()); builder.setInsertionPointToStart(newSeqBody.getBodyBlock()); auto condEnable = - builder.create(curWhileBodyOp.getLoc(), groupName); + EnableOp::create(builder, curWhileBodyOp.getLoc(), groupName); curWhileBodyOp.moveBefore(condEnable); }); } diff --git a/lib/Dialect/Calyx/Transforms/RemoveGroups.cpp b/lib/Dialect/Calyx/Transforms/RemoveGroups.cpp index 8778e2b2de..7331c0ce30 100644 --- a/lib/Dialect/Calyx/Transforms/RemoveGroups.cpp +++ b/lib/Dialect/Calyx/Transforms/RemoveGroups.cpp @@ -54,8 +54,8 @@ static void modifyGroupOperations(ComponentOp component) { // Replace `calyx.group_done %0, %1 ? : i1` // with `calyx.assign %done, %0, %1 ? : i1` auto assignOp = - builder.create(group->getLoc(), component.getDonePort(), - groupDone.getSrc(), groupDone.getGuard()); + AssignOp::create(builder, group->getLoc(), component.getDonePort(), + groupDone.getSrc(), groupDone.getGuard()); groupDone->replaceAllUsesWith(assignOp); } else { // Replace calyx.group_go's uses with its guard, e.g. diff --git a/lib/Dialect/Comb/CombDialect.cpp b/lib/Dialect/Comb/CombDialect.cpp index 3561d64999..3576ce8ac7 100644 --- a/lib/Dialect/Comb/CombDialect.cpp +++ b/lib/Dialect/Comb/CombDialect.cpp @@ -44,15 +44,15 @@ Operation *CombDialect::materializeConstant(OpBuilder &builder, Attribute value, // Integer constants. if (auto intType = dyn_cast(type)) if (auto attrValue = dyn_cast(value)) - return builder.create(loc, type, attrValue); + return hw::ConstantOp::create(builder, loc, type, attrValue); // Parameter expressions materialize into hw.param.value. - auto parentOp = builder.getBlock()->getParentOp(); + auto *parentOp = builder.getBlock()->getParentOp(); auto curModule = dyn_cast(parentOp); if (!curModule) curModule = parentOp->getParentOfType(); if (curModule && isValidParameterExpression(value, curModule)) - return builder.create(loc, type, value); + return hw::ParamValueOp::create(builder, loc, type, value); return nullptr; } diff --git a/lib/Dialect/Comb/CombFolds.cpp b/lib/Dialect/Comb/CombFolds.cpp index 46df438a6e..a9ca5f5e49 100644 --- a/lib/Dialect/Comb/CombFolds.cpp +++ b/lib/Dialect/Comb/CombFolds.cpp @@ -227,7 +227,7 @@ static bool narrowOperationWidth(OpTy op, bool narrowTrailingBits, args.push_back(rewriter.createOrFold(inop.getLoc(), newType, inop, range.first)); } - auto newop = rewriter.create(op.getLoc(), newType, args); + auto newop = OpTy::create(rewriter, op.getLoc(), newType, args); newop->setDialectAttrs(op->getDialectAttrs()); if (op.getTwoState()) newop.setTwoState(true); @@ -236,13 +236,14 @@ static bool narrowOperationWidth(OpTy op, bool narrowTrailingBits, if (range.first) newResult = rewriter.createOrFold( op.getLoc(), newResult, - rewriter.create(op.getLoc(), - APInt::getZero(range.first))); + hw::ConstantOp::create(rewriter, op.getLoc(), + APInt::getZero(range.first))); if (range.second + 1 < opType.getWidth()) newResult = rewriter.createOrFold( op.getLoc(), - rewriter.create( - op.getLoc(), APInt::getZero(opType.getWidth() - range.second - 1)), + hw::ConstantOp::create( + rewriter, op.getLoc(), + APInt::getZero(opType.getWidth() - range.second - 1)), newResult); rewriter.replaceOp(op, newResult); return true; @@ -333,11 +334,11 @@ LogicalResult ShlOp::canonicalize(ShlOp op, PatternRewriter &rewriter) { return failure(); auto zeros = - rewriter.create(op.getLoc(), APInt::getZero(shift)); + hw::ConstantOp::create(rewriter, op.getLoc(), APInt::getZero(shift)); // Remove the high bits which would be removed by the Shl. auto extract = - rewriter.create(op.getLoc(), op.getLhs(), 0, width - shift); + ExtractOp::create(rewriter, op.getLoc(), op.getLhs(), 0, width - shift); replaceOpWithNewOpAndCopyNamehint(rewriter, op, extract, zeros); return success(); @@ -371,11 +372,11 @@ LogicalResult ShrUOp::canonicalize(ShrUOp op, PatternRewriter &rewriter) { return failure(); auto zeros = - rewriter.create(op.getLoc(), APInt::getZero(shift)); + hw::ConstantOp::create(rewriter, op.getLoc(), APInt::getZero(shift)); // Remove the low bits which would be removed by the Shr. - auto extract = rewriter.create(op.getLoc(), op.getLhs(), shift, - width - shift); + auto extract = ExtractOp::create(rewriter, op.getLoc(), op.getLhs(), shift, + width - shift); replaceOpWithNewOpAndCopyNamehint(rewriter, op, zeros, extract); return success(); @@ -408,8 +409,8 @@ LogicalResult ShrSOp::canonicalize(ShrSOp op, PatternRewriter &rewriter) { return success(); } - auto extract = rewriter.create(op.getLoc(), op.getLhs(), shift, - width - shift); + auto extract = ExtractOp::create(rewriter, op.getLoc(), op.getLhs(), shift, + width - shift); replaceOpWithNewOpAndCopyNamehint(rewriter, op, sext, extract); return success(); @@ -498,7 +499,7 @@ static LogicalResult extractConcatToConcatExtract(ExtractOp op, } else { auto resultType = IntegerType::get(rewriter.getContext(), widthToConsume); reverseConcatArgs.push_back( - rewriter.create(op.getLoc(), resultType, *it, extractLo)); + ExtractOp::create(rewriter, op.getLoc(), resultType, *it, extractLo)); } widthRemaining -= widthToConsume; @@ -608,14 +609,14 @@ LogicalResult ExtractOp::canonicalize(ExtractOp op, PatternRewriter &rewriter) { auto resultTy = rewriter.getIntegerType(pop); SmallVector resultElts; if (lz) - resultElts.push_back(rewriter.create( - op.getLoc(), APInt::getZero(lz))); + resultElts.push_back(hw::ConstantOp::create(rewriter, op.getLoc(), + APInt::getZero(lz))); resultElts.push_back(rewriter.createOrFold( op.getLoc(), resultTy, inputOp->getOperand(0), op.getLowBit() + tz)); if (tz) - resultElts.push_back(rewriter.create( - op.getLoc(), APInt::getZero(tz))); + resultElts.push_back(hw::ConstantOp::create(rewriter, op.getLoc(), + APInt::getZero(tz))); replaceOpWithNewOpAndCopyNamehint(rewriter, op, resultElts); return success(); } @@ -631,8 +632,8 @@ LogicalResult ExtractOp::canonicalize(ExtractOp op, PatternRewriter &rewriter) { if (shlOp->hasOneUse()) if (auto lhsCst = shlOp.getLhs().getDefiningOp()) if (lhsCst.getValue().isOne()) { - auto newCst = rewriter.create( - shlOp.getLoc(), + auto newCst = hw::ConstantOp::create( + rewriter, shlOp.getLoc(), APInt(lhsCst.getValue().getBitWidth(), op.getLowBit())); replaceOpWithNewOpAndCopyNamehint( rewriter, op, ICmpPredicate::eq, shlOp->getOperand(1), newCst, @@ -731,15 +732,16 @@ static bool canonicalizeLogicalCstWithConcat(Operation *logicalOp, size_t operandWidth = operand.getType().getIntOrFloatBitWidth(); nextOperandBit -= operandWidth; // Take a slice of the constant. - auto eltCst = rewriter.create( - logicalOp->getLoc(), cst.lshr(nextOperandBit).trunc(operandWidth)); + auto eltCst = + hw::ConstantOp::create(rewriter, logicalOp->getLoc(), + cst.lshr(nextOperandBit).trunc(operandWidth)); newConcatOperands.push_back(createLogicalOp({operand, eltCst})); } // Create the concat, and the rest of the logical op if we need it. Value newResult = - rewriter.create(concatOp.getLoc(), newConcatOperands); + ConcatOp::create(rewriter, concatOp.getLoc(), newConcatOperands); // If we had a variadic logical op on the top level, then recreate it with the // new concat and without the constant operand. @@ -949,7 +951,7 @@ LogicalResult AndOp::canonicalize(AndOp op, PatternRewriter &rewriter) { // folding APInt value2; if (matchPattern(inputs[size - 2], m_ConstantInt(&value2))) { - auto cst = rewriter.create(op.getLoc(), value & value2); + auto cst = hw::ConstantOp::create(rewriter, op.getLoc(), value & value2); SmallVector newOperands(inputs.drop_back(/*n=*/2)); newOperands.push_back(cst); replaceOpWithNewOpAndCopyNamehint(rewriter, op, op.getType(), @@ -972,14 +974,15 @@ LogicalResult AndOp::canonicalize(AndOp op, PatternRewriter &rewriter) { // Don't add zero bit constants unnecessarily. SmallVector concatOperands; if (trailingZeros != resultWidth - 1) { - auto highZeros = rewriter.create( - op.getLoc(), APInt::getZero(resultWidth - trailingZeros - 1)); + auto highZeros = hw::ConstantOp::create( + rewriter, op.getLoc(), + APInt::getZero(resultWidth - trailingZeros - 1)); concatOperands.push_back(highZeros); } concatOperands.push_back(replicateOperand); if (trailingZeros != 0) { - auto lowZeros = rewriter.create( - op.getLoc(), APInt::getZero(trailingZeros)); + auto lowZeros = hw::ConstantOp::create( + rewriter, op.getLoc(), APInt::getZero(trailingZeros)); concatOperands.push_back(lowZeros); } replaceOpWithNewOpAndCopyNamehint( @@ -1007,7 +1010,7 @@ LogicalResult AndOp::canonicalize(AndOp op, PatternRewriter &rewriter) { if (!smallMask.isAllOnes()) { auto loc = inputs.back().getLoc(); smallElt = rewriter.createOrFold( - loc, smallElt, rewriter.create(loc, smallMask), + loc, smallElt, hw::ConstantOp::create(rewriter, loc, smallMask), false); } @@ -1015,12 +1018,12 @@ LogicalResult AndOp::canonicalize(AndOp op, PatternRewriter &rewriter) { // along with the smaller extracted value. SmallVector resultElts; if (lz) - resultElts.push_back( - rewriter.create(op.getLoc(), APInt::getZero(lz))); + resultElts.push_back(hw::ConstantOp::create(rewriter, op.getLoc(), + APInt::getZero(lz))); resultElts.push_back(smallElt); if (tz) - resultElts.push_back( - rewriter.create(op.getLoc(), APInt::getZero(tz))); + resultElts.push_back(hw::ConstantOp::create(rewriter, op.getLoc(), + APInt::getZero(tz))); replaceOpWithNewOpAndCopyNamehint(rewriter, op, resultElts); return success(); } @@ -1043,7 +1046,7 @@ LogicalResult AndOp::canonicalize(AndOp op, PatternRewriter &rewriter) { // and(a[0], a[1], ..., a[n]) -> icmp eq(a, -1) if (auto source = getCommonOperand(op)) { auto cmpAgainst = - rewriter.create(op.getLoc(), APInt::getAllOnes(size)); + hw::ConstantOp::create(rewriter, op.getLoc(), APInt::getAllOnes(size)); replaceOpWithNewOpAndCopyNamehint(rewriter, op, ICmpPredicate::eq, source, cmpAgainst); return success(); @@ -1128,7 +1131,7 @@ LogicalResult OrOp::canonicalize(OrOp op, PatternRewriter &rewriter) { // or(..., c1, c2) -> or(..., c3) where c3 = c1 | c2 -- constant folding APInt value2; if (matchPattern(inputs[size - 2], m_ConstantInt(&value2))) { - auto cst = rewriter.create(op.getLoc(), value | value2); + auto cst = hw::ConstantOp::create(rewriter, op.getLoc(), value | value2); SmallVector newOperands(inputs.drop_back(/*n=*/2)); newOperands.push_back(cst); replaceOpWithNewOpAndCopyNamehint(rewriter, op, op.getType(), @@ -1153,7 +1156,7 @@ LogicalResult OrOp::canonicalize(OrOp op, PatternRewriter &rewriter) { // or(a[0], a[1], ..., a[n]) -> icmp ne(a, 0) if (auto source = getCommonOperand(op)) { auto cmpAgainst = - rewriter.create(op.getLoc(), APInt::getZero(size)); + hw::ConstantOp::create(rewriter, op.getLoc(), APInt::getZero(size)); replaceOpWithNewOpAndCopyNamehint(rewriter, op, ICmpPredicate::ne, source, cmpAgainst); return success(); @@ -1177,7 +1180,7 @@ LogicalResult OrOp::canonicalize(OrOp op, PatternRewriter &rewriter) { firstMux.getFalseValue() == mux.getFalseValue(); }; if (llvm::all_of(op.getOperands().drop_front(), check)) { - auto cond = rewriter.create(op.getLoc(), conditions, true); + auto cond = comb::OrOp::create(rewriter, op.getLoc(), conditions, true); replaceOpWithNewOpAndCopyNamehint( rewriter, op, cond, firstMux.getTrueValue(), firstMux.getFalseValue(), true); @@ -1227,8 +1230,8 @@ static void canonicalizeXorIcmpTrue(XorOp op, unsigned icmpOperand, auto negatedPred = ICmpOp::getNegatedPredicate(icmp.getPredicate()); Value result = - rewriter.create(icmp.getLoc(), negatedPred, icmp.getOperand(0), - icmp.getOperand(1), icmp.getTwoState()); + ICmpOp::create(rewriter, icmp.getLoc(), negatedPred, icmp.getOperand(0), + icmp.getOperand(1), icmp.getTwoState()); // If the xor had other operands, rebuild it. if (op.getNumOperands() > 2) { @@ -1236,7 +1239,8 @@ static void canonicalizeXorIcmpTrue(XorOp op, unsigned icmpOperand, newOperands.pop_back(); newOperands.erase(newOperands.begin() + icmpOperand); newOperands.push_back(result); - result = rewriter.create(op.getLoc(), newOperands, op.getTwoState()); + result = + XorOp::create(rewriter, op.getLoc(), newOperands, op.getTwoState()); } replaceOpAndCopyNamehint(rewriter, op, result); @@ -1269,7 +1273,7 @@ LogicalResult XorOp::canonicalize(XorOp op, PatternRewriter &rewriter) { // xor(..., c1, c2) -> xor(..., c3) where c3 = c1 ^ c2. APInt value2; if (matchPattern(inputs[size - 2], m_ConstantInt(&value2))) { - auto cst = rewriter.create(op.getLoc(), value ^ value2); + auto cst = hw::ConstantOp::create(rewriter, op.getLoc(), value ^ value2); SmallVector newOperands(inputs.drop_back(/*n=*/2)); newOperands.push_back(cst); replaceOpWithNewOpAndCopyNamehint(rewriter, op, op.getType(), @@ -1351,7 +1355,7 @@ LogicalResult SubOp::canonicalize(SubOp op, PatternRewriter &rewriter) { // sub(x, cst) -> add(x, -cst) APInt value; if (matchPattern(op.getRhs(), m_ConstantInt(&value))) { - auto negCst = rewriter.create(op.getLoc(), -value); + auto negCst = hw::ConstantOp::create(rewriter, op.getLoc(), -value); replaceOpWithNewOpAndCopyNamehint(rewriter, op, op.getLhs(), negCst, false); return success(); @@ -1392,7 +1396,7 @@ LogicalResult AddOp::canonicalize(AddOp op, PatternRewriter &rewriter) { // add(..., c1, c2) -> add(..., c3) where c3 = c1 + c2 -- constant folding if (matchPattern(inputs[size - 1], m_ConstantInt(&value)) && matchPattern(inputs[size - 2], m_ConstantInt(&value2))) { - auto cst = rewriter.create(op.getLoc(), value + value2); + auto cst = hw::ConstantOp::create(rewriter, op.getLoc(), value + value2); SmallVector newOperands(inputs.drop_back(/*n=*/2)); newOperands.push_back(cst); replaceOpWithNewOpAndCopyNamehint(rewriter, op, op.getType(), @@ -1404,9 +1408,9 @@ LogicalResult AddOp::canonicalize(AddOp op, PatternRewriter &rewriter) { if (inputs[size - 1] == inputs[size - 2]) { SmallVector newOperands(inputs.drop_back(/*n=*/2)); - auto one = rewriter.create(op.getLoc(), op.getType(), 1); + auto one = hw::ConstantOp::create(rewriter, op.getLoc(), op.getType(), 1); auto shiftLeftOp = - rewriter.create(op.getLoc(), inputs.back(), one, false); + comb::ShlOp::create(rewriter, op.getLoc(), inputs.back(), one, false); newOperands.push_back(shiftLeftOp); replaceOpWithNewOpAndCopyNamehint(rewriter, op, op.getType(), @@ -1421,10 +1425,10 @@ LogicalResult AddOp::canonicalize(AddOp op, PatternRewriter &rewriter) { APInt one(/*numBits=*/value.getBitWidth(), 1, /*isSigned=*/false); auto rhs = - rewriter.create(op.getLoc(), (one << value) + one); + hw::ConstantOp::create(rewriter, op.getLoc(), (one << value) + one); std::array factors = {shlOp.getLhs(), rhs}; - auto mulOp = rewriter.create(op.getLoc(), factors, false); + auto mulOp = comb::MulOp::create(rewriter, op.getLoc(), factors, false); SmallVector newOperands(inputs.drop_back(/*n=*/2)); newOperands.push_back(mulOp); @@ -1440,9 +1444,9 @@ LogicalResult AddOp::canonicalize(AddOp op, PatternRewriter &rewriter) { matchPattern(mulOp.getInputs()[1], m_ConstantInt(&value))) { APInt one(/*numBits=*/value.getBitWidth(), 1, /*isSigned=*/false); - auto rhs = rewriter.create(op.getLoc(), value + one); + auto rhs = hw::ConstantOp::create(rewriter, op.getLoc(), value + one); std::array factors = {mulOp.getInputs()[0], rhs}; - auto newMulOp = rewriter.create(op.getLoc(), factors, false); + auto newMulOp = comb::MulOp::create(rewriter, op.getLoc(), factors, false); SmallVector newOperands(inputs.drop_back(/*n=*/2)); newOperands.push_back(newMulOp); @@ -1465,7 +1469,7 @@ LogicalResult AddOp::canonicalize(AddOp op, PatternRewriter &rewriter) { matchPattern(addOp.getInputs()[1], m_ConstantInt(&value2)) && inputs.size() == 2 && matchPattern(inputs[1], m_ConstantInt(&value))) { - auto rhs = rewriter.create(op.getLoc(), value + value2); + auto rhs = hw::ConstantOp::create(rewriter, op.getLoc(), value + value2); replaceOpWithNewOpAndCopyNamehint( rewriter, op, op.getType(), ArrayRef{addOp.getInputs()[0], rhs}, /*twoState=*/op.getTwoState() && addOp.getTwoState()); @@ -1512,10 +1516,10 @@ LogicalResult MulOp::canonicalize(MulOp op, PatternRewriter &rewriter) { // mul(x, c) -> shl(x, log2(c)), where c is a power of two. if (size == 2 && matchPattern(inputs.back(), m_ConstantInt(&value)) && value.isPowerOf2()) { - auto shift = rewriter.create(op.getLoc(), op.getType(), - value.exactLogBase2()); + auto shift = hw::ConstantOp::create(rewriter, op.getLoc(), op.getType(), + value.exactLogBase2()); auto shlOp = - rewriter.create(op.getLoc(), inputs[0], shift, false); + comb::ShlOp::create(rewriter, op.getLoc(), inputs[0], shift, false); replaceOpWithNewOpAndCopyNamehint(rewriter, op, op.getType(), ArrayRef(shlOp), false); @@ -1532,7 +1536,7 @@ LogicalResult MulOp::canonicalize(MulOp op, PatternRewriter &rewriter) { // mul(..., c1, c2) -> mul(..., c3) where c3 = c1 * c2 -- constant folding if (matchPattern(inputs[size - 1], m_ConstantInt(&value)) && matchPattern(inputs[size - 2], m_ConstantInt(&value2))) { - auto cst = rewriter.create(op.getLoc(), value * value2); + auto cst = hw::ConstantOp::create(rewriter, op.getLoc(), value * value2); SmallVector newOperands(inputs.drop_back(/*n=*/2)); newOperands.push_back(cst); replaceOpWithNewOpAndCopyNamehint(rewriter, op, op.getType(), @@ -1677,7 +1681,7 @@ LogicalResult ConcatOp::canonicalize(ConcatOp op, PatternRewriter &rewriter) { resultCst |= prevCst.getValue().zext(prevWidth + thisWidth) << thisWidth; Value replacement = - rewriter.create(op.getLoc(), resultCst); + hw::ConstantOp::create(rewriter, op.getLoc(), resultCst); return flattenConcat(i - 1, i, replacement); } } @@ -1727,9 +1731,9 @@ LogicalResult ConcatOp::canonicalize(ConcatOp op, PatternRewriter &rewriter) { if (prevExtract.getLowBit() == extract.getLowBit() + thisWidth) { auto prevWidth = prevExtract.getType().getIntOrFloatBitWidth(); auto resType = rewriter.getIntegerType(thisWidth + prevWidth); - Value replacement = rewriter.create( - op.getLoc(), resType, extract.getInput(), - extract.getLowBit()); + Value replacement = + ExtractOp::create(rewriter, op.getLoc(), resType, + extract.getInput(), extract.getLowBit()); return flattenConcat(i - 1, i, replacement); } } @@ -1770,11 +1774,11 @@ LogicalResult ConcatOp::canonicalize(ConcatOp op, PatternRewriter &rewriter) { .getElementType(), extractOpt->width + prevExtractOpt->width); auto resIntType = rewriter.getIntegerType(hw::getBitWidth(resType)); - Value replacement = rewriter.create( - op.getLoc(), resIntType, - rewriter.create(op.getLoc(), resType, - prevExtractOpt->input, - extractOpt->index)); + Value replacement = hw::BitcastOp::create( + rewriter, op.getLoc(), resIntType, + hw::ArraySliceOp::create(rewriter, op.getLoc(), resType, + prevExtractOpt->input, + extractOpt->index)); return flattenConcat(i - 1, i, replacement); } } @@ -1976,7 +1980,7 @@ static bool foldMuxChain(MuxOp rootMux, bool isFalseSide, // Build the array_create and the array_get. auto fusedLoc = rewriter.getFusedLoc(locationsFound); - auto array = rewriter.create(fusedLoc, table); + auto array = hw::ArrayCreateOp::create(rewriter, fusedLoc, table); replaceOpWithNewOpAndCopyNamehint(rewriter, rootMux, array, indexValue); return true; @@ -2245,9 +2249,9 @@ static bool foldMuxOfUniformArrays(MuxOp op, PatternRewriter &rewriter) { if (!trueVec.isUniform() || !falseVec.isUniform()) return false; - auto mux = rewriter.create( - op.getLoc(), op.getCond(), trueVec.getUniformElement(), - falseVec.getUniformElement(), op.getTwoState()); + auto mux = MuxOp::create(rewriter, op.getLoc(), op.getCond(), + trueVec.getUniformElement(), + falseVec.getUniformElement(), op.getTwoState()); SmallVector values(trueVec.getInputs().size(), mux); rewriter.replaceOpWithNewOp(op, values); @@ -2268,7 +2272,7 @@ static bool assumeMuxCondInOperand(Value muxCond, Value muxValue, OpBuilder::InsertionGuard guard(rewriter); rewriter.setInsertionPoint(op); auto condValue = - rewriter.create(muxCond.getLoc(), APInt(1, constCond)); + hw::ConstantOp::create(rewriter, muxCond.getLoc(), APInt(1, constCond)); rewriter.modifyOpInPlace(op, [&] { for (auto &use : op->getOpOperands()) if (use.get() == muxCond) @@ -2461,8 +2465,8 @@ LogicalResult MuxRewriter::matchAndRewrite(MuxOp op, trueMux && falseMux && trueMux.getCond() == falseMux.getCond() && trueMux.getTrueValue() == falseMux.getTrueValue() && trueMux != op && falseMux != op) { - auto subMux = rewriter.create( - rewriter.getFusedLoc({trueMux.getLoc(), falseMux.getLoc()}), + auto subMux = MuxOp::create( + rewriter, rewriter.getFusedLoc({trueMux.getLoc(), falseMux.getLoc()}), op.getCond(), trueMux.getFalseValue(), falseMux.getFalseValue()); replaceOpWithNewOpAndCopyNamehint(rewriter, op, trueMux.getCond(), trueMux.getTrueValue(), subMux, @@ -2476,8 +2480,8 @@ LogicalResult MuxRewriter::matchAndRewrite(MuxOp op, trueMux && falseMux && trueMux.getCond() == falseMux.getCond() && trueMux.getFalseValue() == falseMux.getFalseValue() && trueMux != op && falseMux != op) { - auto subMux = rewriter.create( - rewriter.getFusedLoc({trueMux.getLoc(), falseMux.getLoc()}), + auto subMux = MuxOp::create( + rewriter, rewriter.getFusedLoc({trueMux.getLoc(), falseMux.getLoc()}), op.getCond(), trueMux.getTrueValue(), falseMux.getTrueValue()); replaceOpWithNewOpAndCopyNamehint(rewriter, op, trueMux.getCond(), subMux, trueMux.getFalseValue(), @@ -2492,10 +2496,11 @@ LogicalResult MuxRewriter::matchAndRewrite(MuxOp op, trueMux.getTrueValue() == falseMux.getTrueValue() && trueMux.getFalseValue() == falseMux.getFalseValue() && trueMux != op && falseMux != op) { - auto subMux = rewriter.create( - rewriter.getFusedLoc( - {op.getLoc(), trueMux.getLoc(), falseMux.getLoc()}), - op.getCond(), trueMux.getCond(), falseMux.getCond()); + auto subMux = + MuxOp::create(rewriter, + rewriter.getFusedLoc( + {op.getLoc(), trueMux.getLoc(), falseMux.getLoc()}), + op.getCond(), trueMux.getCond(), falseMux.getCond()); replaceOpWithNewOpAndCopyNamehint( rewriter, op, subMux, trueMux.getTrueValue(), trueMux.getFalseValue(), op.getTwoStateAttr()); @@ -2580,8 +2585,8 @@ static bool foldArrayOfMuxes(hw::ArrayCreateOp op, PatternRewriter &rewriter) { // Replace the create with an aggregate operation. Push the create op // into the operands of the aggregate operation. auto arrayTy = op.getType(); - auto trueValues = rewriter.create(loc, arrayTy, trues); - auto falseValues = rewriter.create(loc, arrayTy, falses); + auto trueValues = hw::ArrayCreateOp::create(rewriter, loc, arrayTy, trues); + auto falseValues = hw::ArrayCreateOp::create(rewriter, loc, arrayTy, falses); rewriter.replaceOpWithNewOp(op, arrayTy, first.getCond(), trueValues, falseValues, isTwoState); return true; @@ -2787,8 +2792,8 @@ static LogicalResult matchAndRewriteCompareConcat(ICmpOp op, Operation *lhs, Value signBit = rewriter.createOrFold( op.getLoc(), firstNonEmptyValue, firstNonEmptyElemWidth - 1, 1); - auto newLhs = rewriter.create(lhs->getLoc(), signBit, lhsOnly); - auto newRhs = rewriter.create(rhs->getLoc(), signBit, rhsOnly); + auto newLhs = ConcatOp::create(rewriter, lhs->getLoc(), signBit, lhsOnly); + auto newRhs = ConcatOp::create(rewriter, rhs->getLoc(), signBit, rhsOnly); return replaceWith(op.getPredicate(), newLhs, newRhs); }; @@ -2894,8 +2899,8 @@ static void combineEqualityICmpWithKnownBitsAndConstant( rewriter.createOrFold(operand.getLoc(), newConcatOperands); // Form the comparison against the smaller constant. - auto newConstantOp = rewriter.create( - cmpOp.getOperand(1).getLoc(), newConstant); + auto newConstantOp = hw::ConstantOp::create( + rewriter, cmpOp.getOperand(1).getLoc(), newConstant); replaceOpWithNewOpAndCopyNamehint(rewriter, cmpOp, cmpOp.getPredicate(), concatResult, @@ -2910,14 +2915,14 @@ static void combineEqualityICmpWithXorOfConstant(ICmpOp cmpOp, XorOp xorOp, rewriter.setInsertionPoint(xorOp); auto xorRHS = xorOp.getOperands().back().getDefiningOp(); - auto newRHS = rewriter.create(xorRHS->getLoc(), - xorRHS.getValue() ^ rhs); + auto newRHS = hw::ConstantOp::create(rewriter, xorRHS->getLoc(), + xorRHS.getValue() ^ rhs); Value newLHS; switch (xorOp.getNumOperands()) { case 1: // This isn't common but is defined so we need to handle it. - newLHS = rewriter.create(xorOp.getLoc(), - APInt::getZero(rhs.getBitWidth())); + newLHS = hw::ConstantOp::create(rewriter, xorOp.getLoc(), + APInt::getZero(rhs.getBitWidth())); break; case 2: // The binary case is the most common. @@ -2927,7 +2932,7 @@ static void combineEqualityICmpWithXorOfConstant(ICmpOp cmpOp, XorOp xorOp, // The general case forces us to form a new xor with the remaining operands. SmallVector newOperands(xorOp.getOperands()); newOperands.pop_back(); - newLHS = rewriter.create(xorOp.getLoc(), newOperands, false); + newLHS = XorOp::create(rewriter, xorOp.getLoc(), newOperands, false); break; } @@ -2961,7 +2966,7 @@ LogicalResult ICmpOp::canonicalize(ICmpOp op, PatternRewriter &rewriter) { // Canonicalize with RHS constant if (matchPattern(op.getRhs(), m_ConstantInt(&rhs))) { auto getConstant = [&](APInt constant) -> Value { - return rewriter.create(op.getLoc(), std::move(constant)); + return hw::ConstantOp::create(rewriter, op.getLoc(), std::move(constant)); }; auto replaceWith = [&](ICmpPredicate predicate, Value lhs, @@ -3018,8 +3023,8 @@ LogicalResult ICmpOp::canonicalize(ICmpOp op, PatternRewriter &rewriter) { if (rhs.countLeadingOnes() + rhs.countTrailingZeros() == rhs.getBitWidth()) { auto numOnes = rhs.countLeadingOnes(); - auto smaller = rewriter.create( - op.getLoc(), op.getLhs(), rhs.getBitWidth() - numOnes, numOnes); + auto smaller = ExtractOp::create(rewriter, op.getLoc(), op.getLhs(), + rhs.getBitWidth() - numOnes, numOnes); return replaceWith(ICmpPredicate::ne, smaller, getConstant(APInt::getAllOnes(numOnes))); } @@ -3041,8 +3046,8 @@ LogicalResult ICmpOp::canonicalize(ICmpOp op, PatternRewriter &rewriter) { if ((rhs + 1).isPowerOf2()) { auto numOnes = rhs.countTrailingOnes(); auto newWidth = rhs.getBitWidth() - numOnes; - auto smaller = rewriter.create(op.getLoc(), op.getLhs(), - numOnes, newWidth); + auto smaller = ExtractOp::create(rewriter, op.getLoc(), op.getLhs(), + numOnes, newWidth); return replaceWith(ICmpPredicate::ne, smaller, getConstant(APInt::getZero(newWidth))); } @@ -3136,9 +3141,10 @@ LogicalResult ICmpOp::canonicalize(ICmpOp op, PatternRewriter &rewriter) { if (auto replicateOp = op.getLhs().getDefiningOp()) if (rhs.isAllOnes() || rhs.isZero()) { auto width = replicateOp.getInput().getType().getIntOrFloatBitWidth(); - auto cst = rewriter.create( - op.getLoc(), rhs.isAllOnes() ? APInt::getAllOnes(width) - : APInt::getZero(width)); + auto cst = + hw::ConstantOp::create(rewriter, op.getLoc(), + rhs.isAllOnes() ? APInt::getAllOnes(width) + : APInt::getZero(width)); replaceOpWithNewOpAndCopyNamehint( rewriter, op, op.getPredicate(), replicateOp.getInput(), cst, op.getTwoState()); diff --git a/lib/Dialect/Comb/CombOps.cpp b/lib/Dialect/Comb/CombOps.cpp index c68888bbbb..dba50b2abe 100644 --- a/lib/Dialect/Comb/CombOps.cpp +++ b/lib/Dialect/Comb/CombOps.cpp @@ -32,8 +32,8 @@ Value comb::createZExt(OpBuilder &builder, Location loc, Value value, return value; // Create a zero constant for the upper bits. - auto zeros = builder.create( - loc, builder.getIntegerType(targetWidth - inputWidth), 0); + auto zeros = hw::ConstantOp::create( + builder, loc, builder.getIntegerType(targetWidth - inputWidth), 0); return builder.createOrFold(loc, zeros, value); } @@ -64,7 +64,7 @@ Value comb::createOrFoldSExt(Value value, Type destTy, Value comb::createOrFoldNot(Location loc, Value value, OpBuilder &builder, bool twoState) { - auto allOnes = builder.create(loc, value.getType(), -1); + auto allOnes = hw::ConstantOp::create(builder, loc, value.getType(), -1); return builder.createOrFold(loc, value, allOnes, twoState); } @@ -170,8 +170,8 @@ Value comb::createDynamicInject(OpBuilder &builder, Location loc, Value value, // Zero-extend the offset and clear the value bits we are replacing. offset = createZExt(builder, loc, offset, largeWidth); - Value mask = builder.create( - loc, APInt::getLowBitsSet(largeWidth, smallWidth)); + Value mask = hw::ConstantOp::create( + builder, loc, APInt::getLowBitsSet(largeWidth, smallWidth)); mask = builder.createOrFold(loc, mask, offset); mask = createOrFoldNot(loc, mask, builder, true); value = builder.createOrFold(loc, value, mask, twoState); @@ -205,14 +205,15 @@ Value comb::createInject(OpBuilder &builder, Location loc, Value value, auto end = offset + smallWidth; if (end < largeWidth) fragments.push_back( - builder.create(loc, value, end, largeWidth - end)); + comb::ExtractOp::create(builder, loc, value, end, largeWidth - end)); if (end <= largeWidth) fragments.push_back(replacement); else - fragments.push_back(builder.create(loc, replacement, 0, - largeWidth - offset)); + fragments.push_back(comb::ExtractOp::create(builder, loc, replacement, 0, + largeWidth - offset)); if (offset > 0) - fragments.push_back(builder.create(loc, value, 0, offset)); + fragments.push_back( + comb::ExtractOp::create(builder, loc, value, 0, offset)); return builder.createOrFold(loc, fragments); } @@ -237,7 +238,7 @@ SmallVector comb::wallaceReduction(OpBuilder &builder, Location loc, size_t width, size_t targetAddends, SmallVector> &addends) { - auto falseValue = builder.create(loc, APInt(1, 0)); + auto falseValue = hw::ConstantOp::create(builder, loc, APInt(1, 0)); SmallVector> newAddends; newAddends.reserve(addends.size()); // Continue reduction until we have only two rows. The length of @@ -285,11 +286,11 @@ comb::wallaceReduction(OpBuilder &builder, Location loc, size_t width, for (auto &addend : addends) { // Reverse the order of the bits std::reverse(addend.begin(), addend.end()); - carrySave.push_back(builder.create(loc, addend)); + carrySave.push_back(comb::ConcatOp::create(builder, loc, addend)); } // Pad with zeros - auto zero = builder.create(loc, APInt(width, 0)); + auto zero = hw::ConstantOp::create(builder, loc, APInt(width, 0)); while (carrySave.size() < targetAddends) carrySave.push_back(zero); diff --git a/lib/Dialect/Comb/Transforms/IntRangeOptimizations.cpp b/lib/Dialect/Comb/Transforms/IntRangeOptimizations.cpp index 0dcaa8e4f6..2cc1b0f6fe 100644 --- a/lib/Dialect/Comb/Transforms/IntRangeOptimizations.cpp +++ b/lib/Dialect/Comb/Transforms/IntRangeOptimizations.cpp @@ -89,16 +89,16 @@ struct CombOpNarrow : public OpRewritePattern { // Extract the lsbs from each operand auto extractLhsOp = - rewriter.create(loc, replaceType, lhs, 0); + comb::ExtractOp::create(rewriter, loc, replaceType, lhs, 0); auto extractRhsOp = - rewriter.create(loc, replaceType, rhs, 0); - auto narrowOp = rewriter.create(loc, extractLhsOp, extractRhsOp); + comb::ExtractOp::create(rewriter, loc, replaceType, rhs, 0); + auto narrowOp = CombOpTy::create(rewriter, loc, extractLhsOp, extractRhsOp); // Concatenate zeros to match the original operator width auto zero = - rewriter.create(loc, APInt::getZero(removeWidth)); - auto replaceOp = rewriter.create( - loc, op.getType(), ValueRange{zero, narrowOp}); + hw::ConstantOp::create(rewriter, loc, APInt::getZero(removeWidth)); + auto replaceOp = comb::ConcatOp::create(rewriter, loc, op.getType(), + ValueRange{zero, narrowOp}); rewriter.replaceOp(op, replaceOp); return success(); diff --git a/lib/Dialect/Comb/Transforms/LowerComb.cpp b/lib/Dialect/Comb/Transforms/LowerComb.cpp index e45a8a55af..92318f2861 100644 --- a/lib/Dialect/Comb/Transforms/LowerComb.cpp +++ b/lib/Dialect/Comb/Transforms/LowerComb.cpp @@ -42,7 +42,7 @@ private: getMux(loc, b, t, f, table.drop_front(half), inputs.drop_front()); Value if0 = getMux(loc, b, t, f, table.drop_back(half), inputs.drop_front()); - return b.create(loc, inputs.front(), if1, if0, false); + return MuxOp::create(b, loc, inputs.front(), if1, if0, false); } public: @@ -52,8 +52,10 @@ public: SmallVector table( llvm::map_range(op.getLookupTableAttr().getAsValueRange(), [](const APInt &a) { return !a.isZero(); })); - Value t = b.create(loc, b.getIntegerAttr(b.getI1Type(), 1)); - Value f = b.create(loc, b.getIntegerAttr(b.getI1Type(), 0)); + Value t = + hw::ConstantOp::create(b, loc, b.getIntegerAttr(b.getI1Type(), 1)); + Value f = + hw::ConstantOp::create(b, loc, b.getIntegerAttr(b.getI1Type(), 0)); Value tree = getMux(loc, b, t, f, table, op.getInputs()); b.modifyOpInPlace(tree.getDefiningOp(), [&]() { diff --git a/lib/Dialect/DC/DCOps.cpp b/lib/Dialect/DC/DCOps.cpp index 00c48c18cd..714ba79fb2 100644 --- a/lib/Dialect/DC/DCOps.cpp +++ b/lib/Dialect/DC/DCOps.cpp @@ -83,7 +83,7 @@ struct JoinOnBranchPattern : public OpRewritePattern { // Unpack the !dc.value input to the branch op auto unpacked = - rewriter.create(op.getLoc(), branch.getCondition()); + UnpackOp::create(rewriter, op.getLoc(), branch.getCondition()); rewriter.modifyOpInPlace(op, [&]() { op->eraseOperands(operandInfo.indices); op.getTokensMutable().append({unpacked.getToken()}); @@ -219,8 +219,8 @@ public: // adding more outputs to the current fork. size_t totalForks = fork.getNumResults() + userFork.getNumResults(); - auto newFork = rewriter.create(fork.getLoc(), - fork.getToken(), totalForks); + auto newFork = dc::ForkOp::create(rewriter, fork.getLoc(), + fork.getToken(), totalForks); rewriter.replaceOp( fork, newFork.getResults().take_front(fork.getNumResults())); rewriter.replaceOp( @@ -252,7 +252,7 @@ public: // each output. llvm::SmallVector sources; for (size_t i = 0; i < fork.getNumResults(); ++i) - sources.push_back(rewriter.create(fork.getLoc())); + sources.push_back(dc::SourceOp::create(rewriter, fork.getLoc())); rewriter.replaceOp(fork, sources); return success(); @@ -276,8 +276,8 @@ struct EliminateUnusedForkResultsPattern : mlir::OpRewritePattern { // Create a new fork op, dropping the unused results. rewriter.setInsertionPoint(op); auto operand = op.getOperand(); - auto newFork = rewriter.create( - op.getLoc(), operand, op.getNumResults() - unusedIndexes.size()); + auto newFork = ForkOp::create(rewriter, op.getLoc(), operand, + op.getNumResults() - unusedIndexes.size()); unsigned i = 0; for (auto oldRes : llvm::enumerate(op.getResults())) if (unusedIndexes.count(oldRes.index()) == 0) @@ -414,11 +414,10 @@ public: rewriter.replaceOpWithNewOp( select, llvm::SmallVector{ - rewriter.create(select.getLoc(), select.getCondition()) + UnpackOp::create(rewriter, select.getLoc(), select.getCondition()) .getToken(), - rewriter - .create(branchInput.getLoc(), - branchInput.getCondition()) + UnpackOp::create(rewriter, branchInput.getLoc(), + branchInput.getCondition()) .getToken()}); return success(); diff --git a/lib/Dialect/DC/Transforms/DCMaterialization.cpp b/lib/Dialect/DC/Transforms/DCMaterialization.cpp index 9ccef06796..5ae05769a1 100644 --- a/lib/Dialect/DC/Transforms/DCMaterialization.cpp +++ b/lib/Dialect/DC/Transforms/DCMaterialization.cpp @@ -43,10 +43,10 @@ static void insertSink(Value v, OpBuilder &rewriter) { rewriter.setInsertionPointAfterValue(v); if (isa(v.getType())) { // Unpack before sinking - v = rewriter.create(v.getLoc(), v).getToken(); + v = UnpackOp::create(rewriter, v.getLoc(), v).getToken(); } - rewriter.create(v.getLoc(), v); + SinkOp::create(rewriter, v.getLoc(), v); } // Adds a fork of the provided token or value-typed Value `result`. @@ -61,14 +61,14 @@ static void insertFork(Value result, OpBuilder &rewriter) { Value token = result; Value value; if (isValue) { - auto unpack = rewriter.create(result.getLoc(), result); + auto unpack = UnpackOp::create(rewriter, result.getLoc(), result); token = unpack.getToken(); value = unpack.getOutput(); } // Insert fork after op auto forkSize = opsToProcess.size(); - auto newFork = rewriter.create(token.getLoc(), token, forkSize); + auto newFork = ForkOp::create(rewriter, token.getLoc(), token, forkSize); // Modify operands of successor // opsToProcess may have multiple instances of same operand @@ -76,8 +76,8 @@ static void insertFork(Value result, OpBuilder &rewriter) { for (auto [op, forkOutput] : llvm::zip(opsToProcess, newFork->getResults())) { Value forkRes = forkOutput; if (isValue) - forkRes = - rewriter.create(forkRes.getLoc(), forkRes, value).getOutput(); + forkRes = PackOp::create(rewriter, forkRes.getLoc(), forkRes, value) + .getOutput(); replaceFirstUse(op, result, forkRes); } } diff --git a/lib/Dialect/Datapath/DatapathFolds.cpp b/lib/Dialect/Datapath/DatapathFolds.cpp index 87905f32cd..ec980c7328 100644 --- a/lib/Dialect/Datapath/DatapathFolds.cpp +++ b/lib/Dialect/Datapath/DatapathFolds.cpp @@ -158,8 +158,8 @@ struct FoldAddIntoCompress : public OpRewritePattern { return failure(); // Create a new CompressOp with all collected operands - auto newCompressOp = rewriter.create( - addOp.getLoc(), newCompressOperands, 2); + auto newCompressOp = datapath::CompressOp::create(rewriter, addOp.getLoc(), + newCompressOperands, 2); // Replace the original AddOp with a new add(compress(inputs)) rewriter.replaceOpWithNewOp(addOp, newCompressOp.getResults(), @@ -235,11 +235,11 @@ struct ReduceNumPartialProducts : public OpRewritePattern { maxNonZeroBits = std::max(maxNonZeroBits, nonZeroBits); } - auto newPP = rewriter.create( - op.getLoc(), op.getOperands(), maxNonZeroBits); + auto newPP = datapath::PartialProductOp::create( + rewriter, op.getLoc(), op.getOperands(), maxNonZeroBits); - auto zero = rewriter.create(op.getLoc(), - APInt::getZero(inputWidth)); + auto zero = hw::ConstantOp::create(rewriter, op.getLoc(), + APInt::getZero(inputWidth)); // Collect newPP results and pad with zeros if needed SmallVector newResults(newPP.getResults().begin(), diff --git a/lib/Dialect/ESI/ESIDialect.cpp b/lib/Dialect/ESI/ESIDialect.cpp index 4fcc95bca8..f504d03d2a 100644 --- a/lib/Dialect/ESI/ESIDialect.cpp +++ b/lib/Dialect/ESI/ESIDialect.cpp @@ -42,7 +42,7 @@ void ESIDialect::initialize() { Operation *ESIDialect::materializeConstant(OpBuilder &builder, Attribute value, Type type, Location loc) { if (isa(value)) - return builder.create(loc, builder.getI1Type(), 1); + return hw::ConstantOp::create(builder, loc, builder.getI1Type(), 1); return builder.getContext() ->getOrLoadDialect() ->materializeConstant(builder, value, type, loc); diff --git a/lib/Dialect/ESI/ESIFolds.cpp b/lib/Dialect/ESI/ESIFolds.cpp index 11505d81b7..41f37eb45c 100644 --- a/lib/Dialect/ESI/ESIFolds.cpp +++ b/lib/Dialect/ESI/ESIFolds.cpp @@ -21,7 +21,7 @@ LogicalResult WrapValidReadyOp::fold(FoldAdaptor, return failure(); OpBuilder builder(getContext()); results.push_back( - builder.create(getLoc(), getChanOutput().getType()) + NullSourceOp::create(builder, getLoc(), getChanOutput().getType()) .getOut()); results.push_back(IntegerAttr::get(IntegerType::get(getContext(), 1), 1)); return success(); @@ -51,7 +51,7 @@ LogicalResult WrapFIFOOp::fold(FoldAdaptor, OpBuilder builder(getContext()); results.push_back( - builder.create(getLoc(), getChanOutput().getType()) + NullSourceOp::create(builder, getLoc(), getChanOutput().getType()) .getOut()); results.push_back(IntegerAttr::get( IntegerType::get(getContext(), 1, IntegerType::Signless), 0)); diff --git a/lib/Dialect/ESI/ESIServices.cpp b/lib/Dialect/ESI/ESIServices.cpp index 1f03c93630..08343d84ab 100644 --- a/lib/Dialect/ESI/ESIServices.cpp +++ b/lib/Dialect/ESI/ESIServices.cpp @@ -107,15 +107,15 @@ instantiateCosimEndpointOps(ServiceImplementReqOp implReq, fromHostType = b.getType(fromHostType.getInner(), ChannelSignaling::ValidReady, fromHostType.getDataDelay()); - auto cosim = b.create( - loc, fromHostType, clk, rst, + auto cosim = CosimFromHostEndpointOp::create( + b, loc, fromHostType, clk, rst, toStringAttr(req.getRelativeAppIDPathAttr(), ch.name)); mlir::TypedValue fromHost = cosim.getFromHost(); if (fromHostType.getSignaling() == ChannelSignaling::FIFO) - fromHost = b.create( - loc, ch.type, clk, rst, fromHost, - /*stages=*/b.getIntegerAttr(b.getI64Type(), 1), - /*name=*/StringAttr()) + fromHost = ChannelBufferOp::create( + b, loc, ch.type, clk, rst, fromHost, + /*stages=*/b.getIntegerAttr(b.getI64Type(), 1), + /*name=*/StringAttr()) .getOutput(); toServerValues.push_back(fromHost); channelAssignments.push_back(getAssignment(ch.name, cosim.getIdAttr())); @@ -123,7 +123,7 @@ instantiateCosimEndpointOps(ServiceImplementReqOp implReq, } auto pack = - b.create(implReq.getLoc(), bundleType, toServerValues); + PackBundleOp::create(b, implReq.getLoc(), bundleType, toServerValues); implReq.getResult(toClientResultNum[req]) .replaceAllUsesWith(pack.getBundle()); @@ -136,23 +136,23 @@ instantiateCosimEndpointOps(ServiceImplementReqOp implReq, auto cosimType = b.getType(chType.getInner(), ChannelSignaling::ValidReady, chType.getDataDelay()); - fromChannel = b.create( - loc, cosimType, clk, rst, fromChannel, - /*stages=*/b.getIntegerAttr(b.getI64Type(), 1), - /*name=*/StringAttr()) + fromChannel = ChannelBufferOp::create( + b, loc, cosimType, clk, rst, fromChannel, + /*stages=*/b.getIntegerAttr(b.getI64Type(), 1), + /*name=*/StringAttr()) .getOutput(); } - auto cosim = b.create( - loc, clk, rst, fromChannel, + auto cosim = CosimToHostEndpointOp::create( + b, loc, clk, rst, fromChannel, toStringAttr(req.getRelativeAppIDPathAttr(), ch.name)); channelAssignments.push_back(getAssignment(ch.name, cosim.getIdAttr())); } } - implRecords.create( - req.getLoc(), req.getRelativeAppIDPathAttr(), req.getServicePortAttr(), - TypeAttr::get(bundleType), b.getDictionaryAttr(channelAssignments), - DictionaryAttr()); + ServiceImplClientRecordOp::create( + implRecords, req.getLoc(), req.getRelativeAppIDPathAttr(), + req.getServicePortAttr(), TypeAttr::get(bundleType), + b.getDictionaryAttr(channelAssignments), DictionaryAttr()); } // Erase the generation request. @@ -186,10 +186,10 @@ instantiateSystemVerilogMemory(ServiceImplementReqOp implReq, auto rst = implReq.getOperand(1); auto write = b.getStringAttr("write"); auto read = b.getStringAttr("read"); - auto none = b.create( - APInt(/*numBits*/ 0, /*val*/ 0, /*isSigned*/ false)); + auto none = hw::ConstantOp::create( + b, APInt(/*numBits*/ 0, /*val*/ 0, /*isSigned*/ false)); auto i1 = b.getI1Type(); - auto c0 = b.create(i1, 0); + auto c0 = hw::ConstantOp::create(b, i1, 0); // List of reqs which have a result. SmallVector toClientReqs( @@ -211,7 +211,7 @@ instantiateSystemVerilogMemory(ServiceImplementReqOp implReq, hw::UnpackedArrayType memType = hw::UnpackedArrayType::get(ramDecl.getInnerType(), ramDecl.getDepth()); auto mem = - b.create(memType, implReq.getServiceSymbolAttr().getAttr()) + sv::RegOp::create(b, memType, implReq.getServiceSymbolAttr().getAttr()) .getResult(); // Do everything which doesn't actually write to the memory, store the signals @@ -226,30 +226,30 @@ instantiateSystemVerilogMemory(ServiceImplementReqOp implReq, // Construct the response channel. auto doneValid = bb.get(i1); - auto ackChannel = b.create(none, doneValid); + auto ackChannel = WrapValidReadyOp::create(b, none, doneValid); auto pack = - b.create(implReq.getLoc(), req.getToClient().getType(), - ackChannel.getChanOutput()); + PackBundleOp::create(b, implReq.getLoc(), req.getToClient().getType(), + ackChannel.getChanOutput()); Value toServer = pack.getFromChannels()[RandomAccessMemoryDeclOp::ReqDirChannelIdx]; toClientResp = pack.getBundle(); // Unwrap the write request and 'explode' the struct. auto unwrap = - b.create(toServer, ackChannel.getReady()); + UnwrapValidReadyOp::create(b, toServer, ackChannel.getReady()); - Value address = b.create(unwrap.getRawOutput(), - b.getStringAttr("address")); - Value data = b.create(unwrap.getRawOutput(), - b.getStringAttr("data")); + Value address = hw::StructExtractOp::create(b, unwrap.getRawOutput(), + b.getStringAttr("address")); + Value data = hw::StructExtractOp::create(b, unwrap.getRawOutput(), + b.getStringAttr("data")); // Determine if the write should occur this cycle. - auto go = b.create(unwrap.getValid(), unwrap.getReady()); + auto go = comb::AndOp::create(b, unwrap.getValid(), unwrap.getReady()); go->setAttr("sv.namehint", b.getStringAttr("write_go")); // Register the 'go' signal and use it as the done message. doneValid.setValue( - b.create(go, clk, rst, c0, "write_done")); + seq::CompRegOp::create(b, go, clk, rst, c0, "write_done")); // Store the necessary data for the 'always' memory writing block. writeGoAddressData.push_back(std::make_tuple(go, address, data)); @@ -259,24 +259,24 @@ instantiateSystemVerilogMemory(ServiceImplementReqOp implReq, // Construct the response channel. auto dataValid = bb.get(i1); auto data = bb.get(ramDecl.getInnerType()); - auto dataChannel = b.create(data, dataValid); + auto dataChannel = WrapValidReadyOp::create(b, data, dataValid); auto pack = - b.create(implReq.getLoc(), req.getToClient().getType(), - dataChannel.getChanOutput()); + PackBundleOp::create(b, implReq.getLoc(), req.getToClient().getType(), + dataChannel.getChanOutput()); Value toServer = pack.getFromChannels()[RandomAccessMemoryDeclOp::RespDirChannelIdx]; toClientResp = pack.getBundle(); // Unwrap the requested address and read from that memory location. auto addressUnwrap = - b.create(toServer, dataChannel.getReady()); + UnwrapValidReadyOp::create(b, toServer, dataChannel.getReady()); Value unsignedAddress = addressUnwrap.getRawOutput(); - Value signlessAddress = b.create( - b.getIntegerType(llvm::Log2_64_Ceil(ramDecl.getDepth())), + Value signlessAddress = hw::BitcastOp::create( + b, b.getIntegerType(llvm::Log2_64_Ceil(ramDecl.getDepth())), unsignedAddress); - Value memLoc = b.create(mem, signlessAddress); - auto readData = b.create(memLoc); + Value memLoc = sv::ArrayIndexInOutOp::create(b, mem, signlessAddress); + auto readData = sv::ReadInOutOp::create(b, memLoc); // Set the data on the response. data.setValue(readData); @@ -289,19 +289,19 @@ instantiateSystemVerilogMemory(ServiceImplementReqOp implReq, } // Now construct the memory writes. - auto hwClk = b.create(clk); - b.create( - sv::EventControl::AtPosEdge, hwClk, sv::ResetType::SyncReset, + auto hwClk = seq::FromClockOp::create(b, clk); + sv::AlwaysFFOp::create( + b, sv::EventControl::AtPosEdge, hwClk, sv::ResetType::SyncReset, sv::EventControl::AtPosEdge, rst, [&] { for (auto [go, address, data] : writeGoAddressData) { Value a = address, d = data; // So the lambda can capture. // If we're told to go, do the write. - b.create(go, [&] { - Value signlessAddress = b.create( - b.getIntegerType(llvm::Log2_64_Ceil(ramDecl.getDepth())), a); + sv::IfOp::create(b, go, [&] { + Value signlessAddress = hw::BitcastOp::create( + b, b.getIntegerType(llvm::Log2_64_Ceil(ramDecl.getDepth())), a); Value memLoc = - b.create(mem, signlessAddress); - b.create(memLoc, d); + sv::ArrayIndexInOutOp::create(b, mem, signlessAddress); + sv::PAssignOp::create(b, memLoc, d); }); } }); @@ -330,8 +330,8 @@ ServiceGeneratorDispatcher::generate(ServiceImplementReqOp req, // Since we always need a record of generation, create it here then pass it to // the generator for possible modification. OpBuilder b(req); - auto implRecord = b.create( - req.getLoc(), req.getAppID(), /*isEngine=*/false, + auto implRecord = ServiceImplRecordOp::create( + b, req.getLoc(), req.getAppID(), /*isEngine=*/false, req.getServiceSymbolAttr(), req.getStdServiceAttr(), req.getImplTypeAttr(), b.getDictionaryAttr({})); implRecord.getReqDetails().emplaceBlock(); @@ -491,15 +491,15 @@ StringAttr ESIConnectServicesPass::getStdService(FlatSymbolRefAttr svcSym) { void ESIConnectServicesPass::convertReq(RequestConnectionOp req) { OpBuilder b(req); - auto newReq = b.create( - req.getLoc(), req.getToClient().getType(), req.getServicePortAttr(), + auto newReq = ServiceImplementConnReqOp::create( + b, req.getLoc(), req.getToClient().getType(), req.getServicePortAttr(), ArrayAttr::get(&getContext(), {req.getAppIDAttr()})); newReq->setDialectAttrs(req->getDialectAttrs()); req.getToClient().replaceAllUsesWith(newReq.getToClient()); // Emit a record of the original request. - b.create( - req.getLoc(), req.getAppID(), req.getServicePortAttr(), + ServiceRequestRecordOp::create( + b, req.getLoc(), req.getAppID(), req.getServicePortAttr(), getStdService(req.getServicePortAttr().getModuleRef()), req.getToClient().getType()); req.erase(); @@ -523,7 +523,7 @@ LogicalResult ESIConnectServicesPass::process(hw::HWModuleLike mod) { // location of the values), get the pointer to the default service instance, // if any. llvm::SetVector *anyServiceInst = nullptr; - if (auto defaultService = localImplReqs.find(SymbolRefAttr()); + if (auto *defaultService = localImplReqs.find(SymbolRefAttr()); defaultService != localImplReqs.end()) anyServiceInst = &defaultService->second; @@ -532,7 +532,7 @@ LogicalResult ESIConnectServicesPass::process(hw::HWModuleLike mod) { for (auto req : llvm::make_early_inc_range( mod.getBodyBlock()->getOps())) { auto service = req.getServicePort().getModuleRef(); - auto reqListIter = localImplReqs.find(service); + auto *reqListIter = localImplReqs.find(service); if (reqListIter != localImplReqs.end()) reqListIter->second.insert(req); else if (anyServiceInst) @@ -590,8 +590,8 @@ LogicalResult ESIConnectServicesPass::replaceInst( // Create the generation request op. OpBuilder b(instOp); - auto implOp = b.create( - instOp.getLoc(), resultTypes, instOp.getAppIDAttr(), + auto implOp = ServiceImplementReqOp::create( + b, instOp.getLoc(), resultTypes, instOp.getAppIDAttr(), instOp.getServiceSymbolAttr(), instOp.getImplTypeAttr(), getStdService(declSym), instOp.getImplOptsAttr(), instOp.getOperands()); implOp->setDialectAttrs(instOp->getDialectAttrs()); @@ -691,9 +691,9 @@ ESIConnectServicesPass::surfaceReqs(hw::HWMutableModuleLike mod, appIDPath = prependNamePart(appIDPath, instAppID); // Clone the request. - auto clone = b.create( - req.getLoc(), req.getToClient().getType(), req.getServicePortAttr(), - appIDPath); + auto clone = ServiceImplementConnReqOp::create( + b, req.getLoc(), req.getToClient().getType(), + req.getServicePortAttr(), appIDPath); clone->setDialectAttrs(req->getDialectAttrs()); newOperands.push_back(clone.getToClient()); } diff --git a/lib/Dialect/ESI/Passes/ESIAppIDHier.cpp b/lib/Dialect/ESI/Passes/ESIAppIDHier.cpp index 662d5b5130..d89fc17443 100644 --- a/lib/Dialect/ESI/Passes/ESIAppIDHier.cpp +++ b/lib/Dialect/ESI/Passes/ESIAppIDHier.cpp @@ -41,19 +41,19 @@ private: // Check if we need to create a root node. if (path.getPath().empty()) { - auto rootOp = OpBuilder::atBlockEnd(getOperation().getBody()) - .create(UnknownLoc::get(&getContext()), - path.getRoot()); + auto builder = OpBuilder::atBlockEnd(getOperation().getBody()); + auto rootOp = AppIDHierRootOp::create( + builder, UnknownLoc::get(&getContext()), path.getRoot()); block = &rootOp.getChildren().emplaceBlock(); } else { Block *parentBlock = getBlock(path.getParent(), opStack.drop_back()); Operation *op = opStack.back(); if (auto inst = dyn_cast(op)) { // Create a normal node underneath the parent AppID. - auto node = OpBuilder::atBlockEnd(parentBlock) - .create(UnknownLoc::get(&getContext()), - path.getPath().back(), - inst.getModuleNameAttr()); + auto builder = OpBuilder::atBlockEnd(parentBlock); + auto node = AppIDHierNodeOp::create( + builder, UnknownLoc::get(&getContext()), path.getPath().back(), + inst.getModuleNameAttr()); block = &node.getChildren().emplaceBlock(); } else { block = parentBlock; diff --git a/lib/Dialect/ESI/Passes/ESIBuildManifest.cpp b/lib/Dialect/ESI/Passes/ESIBuildManifest.cpp index f18c706c3a..e39caaf046 100644 --- a/lib/Dialect/ESI/Passes/ESIBuildManifest.cpp +++ b/lib/Dialect/ESI/Passes/ESIBuildManifest.cpp @@ -123,8 +123,8 @@ void ESIBuildManifestPass::runOnOperation() { ->getRegion(0) .front() .getTerminator()); - b.create(b.getUnknownLoc(), - BlobAttr::get(ctxt, compressedManifest)); + CompressedManifestOp::create(b, b.getUnknownLoc(), + BlobAttr::get(ctxt, compressedManifest)); } else { mod->emitWarning() << "zlib not available but required for manifest support"; diff --git a/lib/Dialect/ESI/Passes/ESILowerBundles.cpp b/lib/Dialect/ESI/Passes/ESILowerBundles.cpp index b5b71b2480..2cf5edd801 100644 --- a/lib/Dialect/ESI/Passes/ESILowerBundles.cpp +++ b/lib/Dialect/ESI/Passes/ESILowerBundles.cpp @@ -85,8 +85,8 @@ void BundlePort::mapInputSignals(OpBuilder &b, Operation *inst, Value, })); SmallVector toChannelTypes(llvm::map_range( newInputChannels, [](hw::PortInfo port) { return port.type; })); - auto unpack = b.create( - origPort.loc, + auto unpack = UnpackBundleOp::create( + b, origPort.loc, /*bundle=*/inst->getOperand(origPort.argNum), fromChannels); // Connect the new instance inputs to the results of the unpack. @@ -106,8 +106,8 @@ void BundlePort::mapOutputSignals(OpBuilder &b, Operation *inst, Value, })); SmallVector fromChannelTypes(llvm::map_range( newInputChannels, [](hw::PortInfo port) { return port.type; })); - auto pack = b.create( - origPort.loc, cast(origPort.type), toChannels); + auto pack = PackBundleOp::create( + b, origPort.loc, cast(origPort.type), toChannels); // Feed the fromChannels into the new instance. for (auto [idx, inPort] : llvm::enumerate(newInputChannels)) @@ -141,7 +141,7 @@ void BundlePort::buildInputSignals() { PackBundleOp pack; if (body) { ImplicitLocOpBuilder b(origPort.loc, body, body->begin()); - pack = b.create(bundleType, newInputValues); + pack = PackBundleOp::create(b, bundleType, newInputValues); body->getArgument(origPort.argNum).replaceAllUsesWith(pack.getBundle()); } @@ -179,10 +179,12 @@ void BundlePort::buildOutputSignals() { // For an output port, the original bundle must be unpacked into the // individual channel ports. UnpackBundleOp unpack; - if (body) - unpack = OpBuilder::atBlockTerminator(body).create( - origPort.loc, body->getTerminator()->getOperand(origPort.argNum), - unpackChannels); + if (body) { + auto builder = OpBuilder::atBlockTerminator(body); + unpack = UnpackBundleOp::create( + builder, origPort.loc, + body->getTerminator()->getOperand(origPort.argNum), unpackChannels); + } // Build new ports and put the new port info directly into the member // variable. diff --git a/lib/Dialect/ESI/Passes/ESILowerPhysical.cpp b/lib/Dialect/ESI/Passes/ESILowerPhysical.cpp index ce61396e22..1640524e05 100644 --- a/lib/Dialect/ESI/Passes/ESILowerPhysical.cpp +++ b/lib/Dialect/ESI/Passes/ESILowerPhysical.cpp @@ -64,16 +64,17 @@ LogicalResult ChannelBufferLowering::matchAndRewrite( Backedge rdEn = bb.get(rewriter.getI1Type()); Backedge valid = bb.get(rewriter.getI1Type()); - auto unwrap = rewriter.create(loc, stageInput, rdEn); - auto wrap = rewriter.create(loc, unwrap.getData(), valid); + auto unwrap = UnwrapFIFOOp::create(rewriter, loc, stageInput, rdEn); + auto wrap = + WrapValidReadyOp::create(rewriter, loc, unwrap.getData(), valid); stageInput = wrap.getChanOutput(); // rdEn = valid && ready - rdEn.setValue(rewriter.create(loc, wrap.getReady(), valid)); + rdEn.setValue(comb::AndOp::create(rewriter, loc, wrap.getReady(), valid)); // valid = !empty - valid.setValue(rewriter.create( - loc, unwrap.getEmpty(), - rewriter.create(loc, rewriter.getBoolAttr(true)))); + valid.setValue(comb::XorOp::create( + rewriter, loc, unwrap.getEmpty(), + hw::ConstantOp::create(rewriter, loc, rewriter.getBoolAttr(true)))); } // Expand 'abstract' buffer into 'physical' stages. @@ -86,8 +87,8 @@ LogicalResult ChannelBufferLowering::matchAndRewrite( for (uint64_t i = 0; i < numStages; ++i) { // Create the stages, connecting them up as we build. - auto stage = rewriter.create(loc, buffer.getClk(), - buffer.getRst(), stageInput); + auto stage = PipelineStageOp::create(rewriter, loc, buffer.getClk(), + buffer.getRst(), stageInput); if (bufferName) { SmallString<64> stageName( {bufferName.getValue(), "_stage", std::to_string(i)}); @@ -104,15 +105,15 @@ LogicalResult ChannelBufferLowering::matchAndRewrite( Backedge ready = bb.get(rewriter.getI1Type()); Backedge empty = bb.get(rewriter.getI1Type()); - auto unwrap = rewriter.create(loc, stageInput, ready); - auto wrap = rewriter.create( - loc, TypeRange{outputType, rewriter.getI1Type()}, unwrap.getRawOutput(), - empty); + auto unwrap = UnwrapValidReadyOp::create(rewriter, loc, stageInput, ready); + auto wrap = WrapFIFOOp::create(rewriter, loc, + TypeRange{outputType, rewriter.getI1Type()}, + unwrap.getRawOutput(), empty); ready.setValue(wrap.getRden()); - empty.setValue(rewriter.create( - loc, unwrap.getValid(), - rewriter.create(loc, rewriter.getBoolAttr(true)))); + empty.setValue(comb::XorOp::create( + rewriter, loc, unwrap.getValid(), + hw::ConstantOp::create(rewriter, loc, rewriter.getBoolAttr(true)))); output = wrap.getChanOutput(); } @@ -142,8 +143,8 @@ FIFOLowering::matchAndRewrite(FIFOOp op, OpAdaptor adaptor, auto outputType = op.getType(); BackedgeBuilder bb(rewriter, loc); auto i1 = rewriter.getI1Type(); - auto c1 = rewriter.create(loc, rewriter.getI1Type(), - rewriter.getBoolAttr(true)); + auto c1 = hw::ConstantOp::create(rewriter, loc, rewriter.getI1Type(), + rewriter.getBoolAttr(true)); mlir::TypedValue chanInput = op.getInput(); if (chanInput.getType().getDataDelay() != 0) return op.emitOpError( @@ -154,14 +155,14 @@ FIFOLowering::matchAndRewrite(FIFOOp op, OpAdaptor adaptor, Value dataNotAvailable; if (chanInput.getType().getSignaling() == ChannelSignaling::ValidReady) { auto unwrapValidReady = - rewriter.create(loc, chanInput, inputEn); + UnwrapValidReadyOp::create(rewriter, loc, chanInput, inputEn); rawData = unwrapValidReady.getRawOutput(); dataNotAvailable = comb::createOrFoldNot(loc, unwrapValidReady.getValid(), rewriter, /*twoState=*/true); dataNotAvailable.getDefiningOp()->setAttr( "sv.namehint", rewriter.getStringAttr("dataNotAvailable")); } else if (chanInput.getType().getSignaling() == ChannelSignaling::FIFO) { - auto unwrapPull = rewriter.create(loc, chanInput, inputEn); + auto unwrapPull = UnwrapFIFOOp::create(rewriter, loc, chanInput, inputEn); rawData = unwrapPull.getData(); dataNotAvailable = unwrapPull.getEmpty(); } else { @@ -170,39 +171,39 @@ FIFOLowering::matchAndRewrite(FIFOOp op, OpAdaptor adaptor, } Backedge outputRdEn = bb.get(i1); - auto seqFifo = rewriter.create( - loc, outputType.getInner(), i1, i1, Type(), Type(), rawData, outputRdEn, - inputEn, op.getClk(), op.getRst(), op.getDepthAttr(), + auto seqFifo = seq::FIFOOp::create( + rewriter, loc, outputType.getInner(), i1, i1, Type(), Type(), rawData, + outputRdEn, inputEn, op.getClk(), op.getRst(), op.getDepthAttr(), rewriter.getI64IntegerAttr(outputType.getDataDelay()), IntegerAttr(), IntegerAttr()); - auto inputNotEmpty = rewriter.create(loc, dataNotAvailable, c1); + auto inputNotEmpty = comb::XorOp::create(rewriter, loc, dataNotAvailable, c1); inputNotEmpty->setAttr("sv.namehint", rewriter.getStringAttr("inputNotEmpty")); auto seqFifoNotFull = - rewriter.create(loc, seqFifo.getFull(), c1); + comb::XorOp::create(rewriter, loc, seqFifo.getFull(), c1); seqFifoNotFull->setAttr("sv.namehint", rewriter.getStringAttr("seqFifoNotFull")); inputEn.setValue( - rewriter.create(loc, inputNotEmpty, seqFifoNotFull)); + comb::AndOp::create(rewriter, loc, inputNotEmpty, seqFifoNotFull)); static_cast(inputEn).getDefiningOp()->setAttr( "sv.namehint", rewriter.getStringAttr("inputEn")); Value output; if (outputType.getSignaling() == ChannelSignaling::ValidReady) { - auto wrap = rewriter.create( - loc, mlir::TypeRange{outputType, i1}, seqFifo.getOutput(), + auto wrap = WrapValidReadyOp::create( + rewriter, loc, mlir::TypeRange{outputType, i1}, seqFifo.getOutput(), comb::createOrFoldNot(loc, seqFifo.getEmpty(), rewriter, /*twoState=*/true)); output = wrap.getChanOutput(); outputRdEn.setValue( - rewriter.create(loc, wrap.getValid(), wrap.getReady())); + comb::AndOp::create(rewriter, loc, wrap.getValid(), wrap.getReady())); static_cast(outputRdEn) .getDefiningOp() ->setAttr("sv.namehint", rewriter.getStringAttr("outputRdEn")); } else if (outputType.getSignaling() == ChannelSignaling::FIFO) { auto wrap = - rewriter.create(loc, mlir::TypeRange{outputType, i1}, - seqFifo.getOutput(), seqFifo.getEmpty()); + WrapFIFOOp::create(rewriter, loc, mlir::TypeRange{outputType, i1}, + seqFifo.getOutput(), seqFifo.getEmpty()); output = wrap.getChanOutput(); outputRdEn.setValue(wrap.getRden()); } else { @@ -277,8 +278,9 @@ PureModuleLowering::matchAndRewrite(ESIPureModuleOp pureMod, OpAdaptor adaptor, } // Create the replacement `hw.module`. - auto hwMod = rewriter.create( - loc, pureMod.getNameAttr(), ports, ArrayAttr::get(getContext(), params)); + auto hwMod = + hw::HWModuleOp::create(rewriter, loc, pureMod.getNameAttr(), ports, + ArrayAttr::get(getContext(), params)); hwMod->setDialectAttrs(pureMod->getDialectAttrs()); rewriter.eraseBlock(hwMod.getBodyBlock()); rewriter.inlineRegionBefore(*body->getParent(), hwMod.getBodyRegion(), @@ -302,7 +304,7 @@ PureModuleLowering::matchAndRewrite(ESIPureModuleOp pureMod, OpAdaptor adaptor, rewriter.eraseOp(output); } rewriter.setInsertionPointToEnd(body); - rewriter.create(pureMod.getLoc(), hwOutputOperands); + hw::OutputOp::create(rewriter, pureMod.getLoc(), hwOutputOperands); // Erase the original op. rewriter.eraseOp(pureMod); diff --git a/lib/Dialect/ESI/Passes/ESILowerPorts.cpp b/lib/Dialect/ESI/Passes/ESILowerPorts.cpp index c074a54c3b..c2a4804188 100644 --- a/lib/Dialect/ESI/Passes/ESILowerPorts.cpp +++ b/lib/Dialect/ESI/Passes/ESILowerPorts.cpp @@ -141,7 +141,7 @@ void ValidReady::buildInputSignals() { ImplicitLocOpBuilder b(origPort.loc, body, body->begin()); // Build the ESI wrap operation to translate the lowered signals to what // they were. (A later pass takes care of eliminating the ESI ops.) - auto wrap = b.create(data, valid); + auto wrap = WrapValidReadyOp::create(b, data, valid); ready = wrap.getReady(); // Replace uses of the old ESI port argument with the new one from the // wrap. @@ -159,9 +159,9 @@ void ValidReady::buildInputSignals() { void ValidReady::mapInputSignals(OpBuilder &b, Operation *inst, Value instValue, SmallVectorImpl &newOperands, ArrayRef newResults) { - auto unwrap = b.create(inst->getLoc(), - inst->getOperand(origPort.argNum), - newResults[readyPort.argNum]); + auto unwrap = UnwrapValidReadyOp::create(b, inst->getLoc(), + inst->getOperand(origPort.argNum), + newResults[readyPort.argNum]); newOperands[dataPort.argNum] = unwrap.getRawOutput(); newOperands[validPort.argNum] = unwrap.getValid(); } @@ -181,8 +181,8 @@ void ValidReady::buildOutputSignals() { auto *terminator = body->getTerminator(); ImplicitLocOpBuilder b(origPort.loc, terminator); - auto unwrap = b.create( - terminator->getOperand(origPort.argNum), ready); + auto unwrap = UnwrapValidReadyOp::create( + b, terminator->getOperand(origPort.argNum), ready); data = unwrap.getRawOutput(); valid = unwrap.getValid(); } @@ -204,8 +204,8 @@ void ValidReady::mapOutputSignals(OpBuilder &b, Operation *inst, SmallVectorImpl &newOperands, ArrayRef newResults) { auto wrap = - b.create(inst->getLoc(), newResults[dataPort.argNum], - newResults[validPort.argNum]); + WrapValidReadyOp::create(b, inst->getLoc(), newResults[dataPort.argNum], + newResults[validPort.argNum]); inst->getResult(origPort.argNum).replaceAllUsesWith(wrap.getChanOutput()); newOperands[readyPort.argNum] = wrap.getReady(); } @@ -235,8 +235,8 @@ void FIFO::buildInputSignals() { ImplicitLocOpBuilder b(origPort.loc, body, body->begin()); // Build the ESI wrap operation to translate the lowered signals to what // they were. (A later pass takes care of eliminating the ESI ops.) - auto wrap = b.create(ArrayRef({chanTy, b.getI1Type()}), - data, empty); + auto wrap = WrapFIFOOp::create(b, ArrayRef({chanTy, b.getI1Type()}), + data, empty); rden = wrap.getRden(); // Replace uses of the old ESI port argument with the new one from the // wrap. @@ -251,8 +251,8 @@ void FIFO::mapInputSignals(OpBuilder &b, Operation *inst, Value instValue, SmallVectorImpl &newOperands, ArrayRef newResults) { auto unwrap = - b.create(inst->getLoc(), inst->getOperand(origPort.argNum), - newResults[rdenPort.argNum]); + UnwrapFIFOOp::create(b, inst->getLoc(), inst->getOperand(origPort.argNum), + newResults[rdenPort.argNum]); newOperands[dataPort.argNum] = unwrap.getData(); newOperands[emptyPort.argNum] = unwrap.getEmpty(); } @@ -276,7 +276,7 @@ void FIFO::buildOutputSignals() { ImplicitLocOpBuilder b(origPort.loc, terminator); auto unwrap = - b.create(terminator->getOperand(origPort.argNum), rden); + UnwrapFIFOOp::create(b, terminator->getOperand(origPort.argNum), rden); data = unwrap.getData(); empty = unwrap.getEmpty(); } @@ -292,8 +292,8 @@ void FIFO::buildOutputSignals() { void FIFO::mapOutputSignals(OpBuilder &b, Operation *inst, Value instValue, SmallVectorImpl &newOperands, ArrayRef newResults) { - auto wrap = b.create( - inst->getLoc(), ArrayRef({origPort.type, b.getI1Type()}), + auto wrap = WrapFIFOOp::create( + b, inst->getLoc(), ArrayRef({origPort.type, b.getI1Type()}), newResults[dataPort.argNum], newResults[emptyPort.argNum]); inst->getResult(origPort.argNum).replaceAllUsesWith(wrap.getChanOutput()); newOperands[rdenPort.argNum] = wrap.getRden(); @@ -503,17 +503,17 @@ void ESIPortsPass::updateInstance(HWModuleExternOp mod, InstanceOp inst) { // Build a gasket by instantiating an interface, connecting one end to an // `esi.unwrap.iface` and the other end to the instance. auto ifaceInst = - instBuilder.create(iface.getInterfaceType()); + InterfaceInstanceOp::create(instBuilder, iface.getInterfaceType()); nameStringBuffer.clear(); ifaceInst->setAttr( "name", StringAttr::get(mod.getContext(), constructInstanceName(op, iface, nameStringBuffer))); GetModportOp sinkModport = - instBuilder.create(ifaceInst, ESIHWBuilder::sinkStr); - instBuilder.create(op, sinkModport); + GetModportOp::create(instBuilder, ifaceInst, ESIHWBuilder::sinkStr); + UnwrapSVInterfaceOp::create(instBuilder, op, sinkModport); GetModportOp sourceModport = - instBuilder.create(ifaceInst, ESIHWBuilder::sourceStr); + GetModportOp::create(instBuilder, ifaceInst, ESIHWBuilder::sourceStr); // Finally, add the correct modport to the list of operands. newOperands.push_back(sourceModport); } @@ -550,29 +550,29 @@ void ESIPortsPass::updateInstance(HWModuleExternOp mod, InstanceOp inst) { // `esi.wrap.iface` and the other end to the instance. Append it to the // operand list. auto ifaceInst = - instBuilder.create(iface.getInterfaceType()); + InterfaceInstanceOp::create(instBuilder, iface.getInterfaceType()); nameStringBuffer.clear(); ifaceInst->setAttr( "name", StringAttr::get(mod.getContext(), constructInstanceName(res, iface, nameStringBuffer))); GetModportOp sourceModport = - instBuilder.create(ifaceInst, ESIHWBuilder::sourceStr); + GetModportOp::create(instBuilder, ifaceInst, ESIHWBuilder::sourceStr); auto newChannel = - instBuilder.create(res.getType(), sourceModport); + WrapSVInterfaceOp::create(instBuilder, res.getType(), sourceModport); // Connect all the old users of the output channel with the newly // wrapped replacement channel. res.replaceAllUsesWith(newChannel); GetModportOp sinkModport = - instBuilder.create(ifaceInst, ESIHWBuilder::sinkStr); + GetModportOp::create(instBuilder, ifaceInst, ESIHWBuilder::sinkStr); // And add the modport on the other side to the new operand list. newOperands.push_back(sinkModport); } // Create the new instance! - auto newInst = instBuilder.create( - mod, inst.getInstanceNameAttr(), newOperands, inst.getParameters(), - inst.getInnerSymAttr()); + auto newInst = hw::InstanceOp::create( + instBuilder, mod, inst.getInstanceNameAttr(), newOperands, + inst.getParameters(), inst.getInnerSymAttr()); // Go through the old list of non-ESI result values, and replace them with // the new non-ESI results. diff --git a/lib/Dialect/ESI/Passes/ESILowerToHW.cpp b/lib/Dialect/ESI/Passes/ESILowerToHW.cpp index 200e6bf9f4..8615f62990 100644 --- a/lib/Dialect/ESI/Passes/ESILowerToHW.cpp +++ b/lib/Dialect/ESI/Passes/ESILowerToHW.cpp @@ -80,7 +80,7 @@ LogicalResult PipelineStageLowering::matchAndRewrite( circt::BackedgeBuilder back(rewriter, loc); circt::Backedge wrapReady = back.get(rewriter.getI1Type()); auto unwrap = - rewriter.create(loc, stage.getInput(), wrapReady); + UnwrapValidReadyOp::create(rewriter, loc, stage.getInput(), wrapReady); StringRef pipeStageName = "pipelineStage"; if (auto name = stage->getAttrOfType("name")) @@ -92,8 +92,8 @@ LogicalResult PipelineStageLowering::matchAndRewrite( operands.push_back(unwrap.getRawOutput()); operands.push_back(unwrap.getValid()); operands.push_back(stageReady); - auto stageInst = rewriter.create( - loc, stageModule, pipeStageName, operands, stageParams); + auto stageInst = hw::InstanceOp::create(rewriter, loc, stageModule, + pipeStageName, operands, stageParams); auto stageInstResults = stageInst.getResults(); // Set a_ready (from the unwrap) back edge correctly to its output from @@ -104,8 +104,8 @@ LogicalResult PipelineStageLowering::matchAndRewrite( xValid = stageInstResults[2]; // Wrap up the output of the HW stage module. - auto wrap = rewriter.create( - loc, chPort, rewriter.getI1Type(), x, xValid); + auto wrap = WrapValidReadyOp::create(rewriter, loc, chPort, + rewriter.getI1Type(), x, xValid); // Set the stages x_ready backedge correctly. stageReady.setValue(wrap.getReady()); @@ -134,12 +134,12 @@ LogicalResult NullSourceOpLowering::matchAndRewrite( if (width == -1) return rewriter.notifyMatchFailure( nullop, "NullOp lowering only supports hw types"); - auto valid = - rewriter.create(nullop.getLoc(), rewriter.getI1Type(), 0); + auto valid = hw::ConstantOp::create(rewriter, nullop.getLoc(), + rewriter.getI1Type(), 0); auto zero = - rewriter.create(loc, rewriter.getIntegerType(width), 0); - auto typedZero = rewriter.create(loc, innerType, zero); - auto wrap = rewriter.create(loc, typedZero, valid); + hw::ConstantOp::create(rewriter, loc, rewriter.getIntegerType(width), 0); + auto typedZero = hw::BitcastOp::create(rewriter, loc, innerType, zero); + auto wrap = WrapValidReadyOp::create(rewriter, loc, typedZero, valid); wrap->setAttr("name", rewriter.getStringAttr("nullsource")); rewriter.replaceOp(nullop, {wrap.getChanOutput()}); return success(); @@ -160,8 +160,8 @@ public: UnwrapValidReadyOp unwrap = dyn_cast(op); if (wrap) { if (ChannelType::hasNoConsumers(wrap.getChanOutput())) { - auto c1 = rewriter.create(wrap.getLoc(), - rewriter.getI1Type(), 1); + auto c1 = hw::ConstantOp::create(rewriter, wrap.getLoc(), + rewriter.getI1Type(), 1); rewriter.replaceOp(wrap, {nullptr, c1}); return success(); } @@ -276,8 +276,8 @@ public: "Could not find 'unwrap'."); // Create transaction signal as valid AND ready - auto validAndReady = rewriter.create( - op.getLoc(), wrapVR.getValid(), unwrapVR.getReady()); + auto validAndReady = comb::AndOp::create( + rewriter, op.getLoc(), wrapVR.getValid(), unwrapVR.getReady()); rewriter.replaceOp(op, {validAndReady, wrapVR.getRawInput()}); return success(); @@ -298,12 +298,12 @@ public: "Could not find 'unwrap'."); // Create transaction signal as !empty AND rden - auto notEmpty = rewriter.create( - op.getLoc(), wrapFIFO.getEmpty(), - rewriter.create(op.getLoc(), - rewriter.getBoolAttr(true))); - auto transaction = rewriter.create(op.getLoc(), notEmpty, - unwrapFIFO.getRden()); + auto notEmpty = comb::XorOp::create( + rewriter, op.getLoc(), wrapFIFO.getEmpty(), + hw::ConstantOp::create(rewriter, op.getLoc(), + rewriter.getBoolAttr(true))); + auto transaction = comb::AndOp::create(rewriter, op.getLoc(), notEmpty, + unwrapFIFO.getRden()); rewriter.replaceOp(op, {transaction, wrapFIFO.getData()}); return success(); @@ -370,14 +370,15 @@ WrapInterfaceLower::matchAndRewrite(WrapSVInterfaceOp wrap, OpAdaptor adaptor, return failure(); auto loc = wrap.getLoc(); - auto validSignal = rewriter.create( - loc, ifaceInstance, ESIHWBuilder::validStr); + auto validSignal = ReadInterfaceSignalOp::create(rewriter, loc, ifaceInstance, + ESIHWBuilder::validStr); Value dataSignal; - dataSignal = rewriter.create(loc, ifaceInstance, - ESIHWBuilder::dataStr); - auto wrapVR = rewriter.create(loc, dataSignal, validSignal); - rewriter.create( - loc, ifaceInstance, ESIHWBuilder::readyStr, wrapVR.getReady()); + dataSignal = ReadInterfaceSignalOp::create(rewriter, loc, ifaceInstance, + ESIHWBuilder::dataStr); + auto wrapVR = + WrapValidReadyOp::create(rewriter, loc, dataSignal, validSignal); + AssignInterfaceSignalOp::create(rewriter, loc, ifaceInstance, + ESIHWBuilder::readyStr, wrapVR.getReady()); rewriter.replaceOp(wrap, {wrapVR.getChanOutput()}); return success(); } @@ -415,15 +416,16 @@ LogicalResult UnwrapInterfaceLower::matchAndRewrite( return failure(); auto loc = unwrap.getLoc(); - auto readySignal = rewriter.create( - loc, ifaceInstance, ESIHWBuilder::readyStr); + auto readySignal = ReadInterfaceSignalOp::create(rewriter, loc, ifaceInstance, + ESIHWBuilder::readyStr); auto unwrapVR = - rewriter.create(loc, operands[0], readySignal); - rewriter.create( - loc, ifaceInstance, ESIHWBuilder::validStr, unwrapVR.getValid()); + UnwrapValidReadyOp::create(rewriter, loc, operands[0], readySignal); + AssignInterfaceSignalOp::create(rewriter, loc, ifaceInstance, + ESIHWBuilder::validStr, unwrapVR.getValid()); - rewriter.create( - loc, ifaceInstance, ESIHWBuilder::dataStr, unwrapVR.getRawOutput()); + AssignInterfaceSignalOp::create(rewriter, loc, ifaceInstance, + ESIHWBuilder::dataStr, + unwrapVR.getRawOutput()); rewriter.eraseOp(unwrap); return success(); } @@ -468,14 +470,15 @@ LogicalResult CosimToHostLowering::matchAndRewrite( // Set up the egest route to drive the EP's toHost ports. auto sendReady = bb.get(rewriter.getI1Type()); UnwrapValidReadyOp unwrapSend = - rewriter.create(loc, toHost, sendReady); + UnwrapValidReadyOp::create(rewriter, loc, toHost, sendReady); Value castedSendData; if (width > 0) - castedSendData = rewriter.create( - loc, rewriter.getIntegerType(width), unwrapSend.getRawOutput()); + castedSendData = + hw::BitcastOp::create(rewriter, loc, rewriter.getIntegerType(width), + unwrapSend.getRawOutput()); else - castedSendData = rewriter.create( - loc, rewriter.getIntegerType(1), rewriter.getBoolAttr(false)); + castedSendData = hw::ConstantOp::create( + rewriter, loc, rewriter.getIntegerType(1), rewriter.getBoolAttr(false)); // Build or get the cached Cosim Endpoint module parameterization. Operation *symTable = ep->getParentWithTrait(); @@ -489,8 +492,9 @@ LogicalResult CosimToHostLowering::matchAndRewrite( unwrapSend.getValid(), castedSendData, }; - auto cosimEpModule = rewriter.create( - loc, endpoint, ep.getIdAttr(), operands, ArrayAttr::get(ctxt, params)); + auto cosimEpModule = + hw::InstanceOp::create(rewriter, loc, endpoint, ep.getIdAttr(), operands, + ArrayAttr::get(ctxt, params)); sendReady.setValue(cosimEpModule.getResult(0)); // Replace the CosimEndpointOp op. @@ -547,22 +551,23 @@ LogicalResult CosimFromHostLowering::matchAndRewrite( // Create replacement Cosim_Endpoint instance. Value operands[] = {adaptor.getClk(), adaptor.getRst(), recvReady}; - auto cosimEpModule = rewriter.create( - loc, endpoint, ep.getIdAttr(), operands, ArrayAttr::get(ctxt, params)); + auto cosimEpModule = + hw::InstanceOp::create(rewriter, loc, endpoint, ep.getIdAttr(), operands, + ArrayAttr::get(ctxt, params)); // Set up the injest path. Value recvDataFromCosim = cosimEpModule.getResult(1); Value recvValidFromCosim = cosimEpModule.getResult(0); Value castedRecvData; if (width > 0) - castedRecvData = - rewriter.create(loc, type.getInner(), recvDataFromCosim); + castedRecvData = hw::BitcastOp::create(rewriter, loc, type.getInner(), + recvDataFromCosim); else - castedRecvData = rewriter.create( - loc, rewriter.getIntegerType(0), + castedRecvData = hw::ConstantOp::create( + rewriter, loc, rewriter.getIntegerType(0), rewriter.getIntegerAttr(rewriter.getIntegerType(0), 0)); - WrapValidReadyOp wrapRecv = rewriter.create( - loc, castedRecvData, recvValidFromCosim); + WrapValidReadyOp wrapRecv = WrapValidReadyOp::create( + rewriter, loc, castedRecvData, recvValidFromCosim); recvReady.setValue(wrapRecv.getReady()); // Replace the CosimEndpointOp op. @@ -615,8 +620,8 @@ LogicalResult ManifestRomLowering::createRomModule( {{rewriter.getStringAttr("data"), rewriter.getI64Type(), ModulePort::Direction::Output}}, }; - auto rom = rewriter.create( - loc, rewriter.getStringAttr(manifestRomName), ports); + auto rom = HWModuleOp::create(rewriter, loc, + rewriter.getStringAttr(manifestRomName), ports); Block *romBody = rom.getBodyBlock(); rewriter.setInsertionPointToStart(romBody); Value clk = romBody->getArgument(0); @@ -647,25 +652,26 @@ LogicalResult ManifestRomLowering::createRomModule( SmallVector wordAttrs; for (uint64_t word : words) wordAttrs.push_back(rewriter.getI64IntegerAttr(word)); - auto manifestConstant = rewriter.create( - loc, hw::UnpackedArrayType::get(rewriter.getI64Type(), words.size()), + auto manifestConstant = hw::AggregateConstantOp::create( + rewriter, loc, + hw::UnpackedArrayType::get(rewriter.getI64Type(), words.size()), rewriter.getArrayAttr(wordAttrs)); auto manifestReg = - rewriter.create(loc, manifestConstant.getType()); - rewriter.create(loc, manifestReg, manifestConstant); + sv::RegOp::create(rewriter, loc, manifestConstant.getType()); + sv::AssignOp::create(rewriter, loc, manifestReg, manifestConstant); // Slim down the address, register it, do the lookup, and register the output. size_t addrBits = llvm::Log2_64_Ceil(words.size()); auto slimmedIdx = - rewriter.create(loc, inputAddress, 0, addrBits); - Value inputAddresReg = rewriter.create(loc, slimmedIdx, clk); + comb::ExtractOp::create(rewriter, loc, inputAddress, 0, addrBits); + Value inputAddresReg = seq::CompRegOp::create(rewriter, loc, slimmedIdx, clk); auto readIdx = - rewriter.create(loc, manifestReg, inputAddresReg); - auto readData = rewriter.create(loc, readIdx); - Value readDataReg = rewriter.create(loc, readData, clk); + sv::ArrayIndexInOutOp::create(rewriter, loc, manifestReg, inputAddresReg); + auto readData = sv::ReadInOutOp::create(rewriter, loc, readIdx); + Value readDataReg = seq::CompRegOp::create(rewriter, loc, readData, clk); if (auto *term = romBody->getTerminator()) rewriter.eraseOp(term); - rewriter.create(loc, ValueRange{readDataReg}); + hw::OutputOp::create(rewriter, loc, ValueRange{readDataReg}); return success(); } @@ -717,38 +723,38 @@ LogicalResult CosimManifestLowering::matchAndRewrite( }; rewriter.setInsertionPointToEnd( op->getParentOfType().getBody()); - auto cosimManifestExternModule = rewriter.create( - loc, rewriter.getStringAttr("Cosim_Manifest"), ports, "Cosim_Manifest", - ArrayAttr::get(ctxt, params)); + auto cosimManifestExternModule = HWModuleExternOp::create( + rewriter, loc, rewriter.getStringAttr("Cosim_Manifest"), ports, + "Cosim_Manifest", ArrayAttr::get(ctxt, params)); hw::ModulePortInfo portInfo({}); - auto manifestMod = rewriter.create( - loc, rewriter.getStringAttr("__ESIManifest"), portInfo, + auto manifestMod = hw::HWModuleOp::create( + rewriter, loc, rewriter.getStringAttr("__ESIManifest"), portInfo, [&](OpBuilder &rewriter, const hw::HWModulePortAccessor &) { // Assemble the manifest data into a constant. SmallVector bytes; for (uint8_t b : op.getCompressedManifest().getData()) bytes.push_back(rewriter.getI8IntegerAttr(b)); - auto manifestConstant = rewriter.create( - loc, hw::ArrayType::get(rewriter.getI8Type(), bytes.size()), + auto manifestConstant = hw::AggregateConstantOp::create( + rewriter, loc, + hw::ArrayType::get(rewriter.getI8Type(), bytes.size()), rewriter.getArrayAttr(bytes)); auto manifestLogic = - rewriter.create(loc, manifestConstant.getType()); - rewriter.create(loc, manifestLogic, manifestConstant); - auto manifest = rewriter.create(loc, manifestLogic); + sv::LogicOp::create(rewriter, loc, manifestConstant.getType()); + sv::AssignOp::create(rewriter, loc, manifestLogic, manifestConstant); + auto manifest = sv::ReadInOutOp::create(rewriter, loc, manifestLogic); // Then instantiate the external module. - rewriter.create( - loc, cosimManifestExternModule, "__manifest", - ArrayRef({manifest}), - rewriter.getArrayAttr({ParamDeclAttr::get( - "COMPRESSED_MANIFEST_SIZE", - rewriter.getI32IntegerAttr(bytes.size()))})); + hw::InstanceOp::create(rewriter, loc, cosimManifestExternModule, + "__manifest", ArrayRef({manifest}), + rewriter.getArrayAttr({ParamDeclAttr::get( + "COMPRESSED_MANIFEST_SIZE", + rewriter.getI32IntegerAttr(bytes.size()))})); }); rewriter.setInsertionPoint(op); - rewriter.create(loc, manifestMod, "__manifest", - ArrayRef({})); + hw::InstanceOp::create(rewriter, loc, manifestMod, "__manifest", + ArrayRef({})); rewriter.eraseOp(op); return success(); diff --git a/lib/Dialect/ESI/Passes/ESILowerTypes.cpp b/lib/Dialect/ESI/Passes/ESILowerTypes.cpp index 44a4aaeb69..b4cc7a27cf 100644 --- a/lib/Dialect/ESI/Passes/ESILowerTypes.cpp +++ b/lib/Dialect/ESI/Passes/ESILowerTypes.cpp @@ -56,7 +56,7 @@ private: ValueRange inputs, Location loc) { if (inputs.size() != 1) return mlir::Value(); - auto wrap = b.create(loc, resultType, inputs[0]); + auto wrap = WrapWindow::create(b, loc, resultType, inputs[0]); return wrap.getWindow(); } @@ -65,7 +65,7 @@ private: ValueRange inputs, Location loc) { if (inputs.size() != 1 || !isa(inputs[0].getType())) return mlir::Value(); - auto unwrap = b.create(loc, resultType, inputs[0]); + auto unwrap = UnwrapWindow::create(b, loc, resultType, inputs[0]); return unwrap.getFrame(); } }; diff --git a/lib/Dialect/FIRRTL/FIRRTLAnnotationHelper.cpp b/lib/Dialect/FIRRTL/FIRRTLAnnotationHelper.cpp index 5066c7b2d2..847b14d929 100644 --- a/lib/Dialect/FIRRTL/FIRRTLAnnotationHelper.cpp +++ b/lib/Dialect/FIRRTL/FIRRTLAnnotationHelper.cpp @@ -405,8 +405,8 @@ HierPathCache::HierPathCache(Operation *op, SymbolTable &symbolTable) hw::HierPathOp HierPathCache::getOpFor(ArrayAttr attr) { auto &op = cache[attr]; if (!op) { - op = builder.create(UnknownLoc::get(builder.getContext()), - "nla", attr); + op = hw::HierPathOp::create(builder, UnknownLoc::get(builder.getContext()), + "nla", attr); symbolTable.insert(op); op.setVisibility(SymbolTable::Visibility::Private); } @@ -475,10 +475,9 @@ static Value lowerInternalPathAnno(AnnoPathValue &srcTarget, // RefSendOp. Store into an op to ensure we have stable reference, // so future tapping won't invalidate this Value. sendVal = modInstance.getResults().back(); - sendVal = - builder - .create(sendVal.getType(), sendVal) - ->getResult(0); + sendVal = mlir::UnrealizedConversionCastOp::create(builder, sendVal.getType(), + sendVal) + ->getResult(0); // Now set the instance as the source for the final datatap xmr. srcTarget = AnnoPathValue(modInstance); @@ -495,9 +494,10 @@ static Value lowerInternalPathAnno(AnnoPathValue &srcTarget, } else if (auto intMod = dyn_cast((Operation *)mod)) { auto builder = ImplicitLocOpBuilder::atBlockEnd( intMod.getLoc(), &intMod.getBody().getBlocks().back()); - auto pathStr = builder.create( - portRefType.getType(), internalPathAttr.getValue(), ValueRange{}); - auto sendPath = builder.create(pathStr); + auto pathStr = + VerbatimExprOp::create(builder, portRefType.getType(), + internalPathAttr.getValue(), ValueRange{}); + auto sendPath = RefSendOp::create(builder, pathStr); emitConnect(builder, intMod.getArguments().back(), sendPath.getResult()); } @@ -647,7 +647,7 @@ LogicalResult circt::firrtl::applyGCTDataTaps(const AnnoPathValue &target, lastInst->getBlock()); builder.setInsertionPointAfter(lastInst); // Instance port cannot be used as an annotation target, so use a NodeOp. - auto node = builder.create(lastInst.getResult(portNo)); + auto node = NodeOp::create(builder, lastInst.getResult(portNo)); AnnotationSet::addDontTouch(node); srcTarget->ref = AnnoTarget(circt::firrtl::detail::AnnoTargetImpl(node)); } @@ -692,17 +692,17 @@ LogicalResult circt::firrtl::applyGCTDataTaps(const AnnoPathValue &target, valType.getWidthlessType() != wireType.getWidthlessType()) { // Helper: create a wire, cast it with callback, connect cast to sink. auto addWireWithCast = [&](auto createCast) { - auto wire = - sinkBuilder.create(valType, tapName.getValue()).getResult(); + auto wire = WireOp::create(sinkBuilder, valType, tapName.getValue()) + .getResult(); emitConnect(sinkBuilder, sink, createCast(wire)); sink = wire; }; if (isa(wireType)) addWireWithCast( - [&](auto v) { return sinkBuilder.create(v); }); + [&](auto v) { return AsUIntPrimOp::create(sinkBuilder, v); }); else if (isa(wireType)) addWireWithCast( - [&](auto v) { return sinkBuilder.create(v); }); + [&](auto v) { return AsAsyncResetPrimOp::create(sinkBuilder, v); }); } state.wiringProblems.push_back( @@ -814,19 +814,20 @@ LogicalResult circt::firrtl::applyGCTMemTaps(const AnnoPathValue &target, SmallVector data; Type uintType = builder.getType(); for (uint64_t i = 0, e = combMem.getType().getNumElements(); i != e; ++i) { - auto port = builder.create( - combMem.getType().getElementType(), + auto port = chirrtl::MemoryPortOp::create( + builder, combMem.getType().getElementType(), CMemoryPortType::get(builder.getContext()), combMem.getResult(), MemDirAttr::Read, builder.getStringAttr("memTap_" + Twine(i)), builder.getArrayAttr({})); - builder.create( - port.getPort(), - builder.create(uintType, APSInt::getUnsigned(i)), clock); + chirrtl::MemoryPortAccessOp::create( + builder, port.getPort(), + ConstantOp::create(builder, uintType, APSInt::getUnsigned(i)), clock); data.push_back(port.getData()); } // Package up all the reads into a vector. - auto sendVal = builder.create( + auto sendVal = VectorCreateOp::create( + builder, FVectorType::get(combMem.getType().getElementType(), combMem.getType().getNumElements()), data); @@ -844,10 +845,9 @@ LogicalResult circt::firrtl::applyGCTMemTaps(const AnnoPathValue &target, auto debugType = RefType::get(FVectorType::get( combMem.getType().getElementType(), combMem.getType().getNumElements())); Value memDbgPort = - builder - .create( - debugType, combMem, - state.getNamespace(srcTarget->ref.getModule()).newName("memTap")) + chirrtl::MemoryDebugPortOp::create( + builder, debugType, combMem, + state.getNamespace(srcTarget->ref.getModule()).newName("memTap")) .getResult(); auto sendVal = memDbgPort; diff --git a/lib/Dialect/FIRRTL/FIRRTLDialect.cpp b/lib/Dialect/FIRRTL/FIRRTLDialect.cpp index 9472bcd893..6b203c24ff 100644 --- a/lib/Dialect/FIRRTL/FIRRTLDialect.cpp +++ b/lib/Dialect/FIRRTL/FIRRTLDialect.cpp @@ -58,39 +58,40 @@ Operation *FIRRTLDialect::materializeConstant(OpBuilder &builder, // important that this goes first. if (auto attrValue = dyn_cast(value)) { if (isa(type)) - return builder.create(loc, type, attrValue); + return BoolConstantOp::create(builder, loc, type, attrValue); assert((isa(type) && "BoolAttrs can only be materialized for special constant types.")); - return builder.create(loc, type, attrValue); + return SpecialConstantOp::create(builder, loc, type, attrValue); } // Integer constants. if (auto attrValue = dyn_cast(value)) { if (isa(type)) - return builder.create(loc, type, attrValue); + return FIntegerConstantOp::create(builder, loc, type, attrValue); // Integer attributes (ui1) might still be special constant types. if (attrValue.getValue().getBitWidth() == 1 && isa(type)) - return builder.create( - loc, type, builder.getBoolAttr(attrValue.getValue().isAllOnes())); + return SpecialConstantOp::create( + builder, loc, type, + builder.getBoolAttr(attrValue.getValue().isAllOnes())); assert((!type_cast(type).hasWidth() || (unsigned)type_cast(type).getWidthOrSentinel() == attrValue.getValue().getBitWidth()) && "type/value width mismatch materializing constant"); - return builder.create(loc, type, attrValue); + return ConstantOp::create(builder, loc, type, attrValue); } // Aggregate constants. if (auto arrayAttr = dyn_cast(value)) { if (isa(type)) - return builder.create(loc, type, arrayAttr); + return AggregateConstantOp::create(builder, loc, type, arrayAttr); } // String constants. if (auto stringAttr = dyn_cast(value)) { if (type_isa(type)) - return builder.create(loc, type, stringAttr); + return StringConstantOp::create(builder, loc, type, stringAttr); } return nullptr; diff --git a/lib/Dialect/FIRRTL/FIRRTLFolds.cpp b/lib/Dialect/FIRRTL/FIRRTLFolds.cpp index 60b4d0ed70..dc8ae78563 100644 --- a/lib/Dialect/FIRRTL/FIRRTLFolds.cpp +++ b/lib/Dialect/FIRRTL/FIRRTLFolds.cpp @@ -331,14 +331,14 @@ static LogicalResult canonicalizePrimOp( // Insert a pad if the type widths disagree. if (width != type_cast(resultValue.getType()).getBitWidthOrSentinel()) - resultValue = rewriter.create(op->getLoc(), resultValue, width); + resultValue = PadPrimOp::create(rewriter, op->getLoc(), resultValue, width); // Insert a cast if this is a uint vs. sint or vice versa. if (type_isa(type) && type_isa(resultValue.getType())) - resultValue = rewriter.create(op->getLoc(), resultValue); + resultValue = AsSIntPrimOp::create(rewriter, op->getLoc(), resultValue); else if (type_isa(type) && type_isa(resultValue.getType())) - resultValue = rewriter.create(op->getLoc(), resultValue); + resultValue = AsUIntPrimOp::create(rewriter, op->getLoc(), resultValue); assert(type == resultValue.getType() && "canonicalization changed type"); replaceOpAndCopyName(rewriter, op, resultValue); @@ -873,20 +873,20 @@ LogicalResult EQPrimOp::canonicalize(EQPrimOp op, PatternRewriter &rewriter) { // eq(x, 0) -> not(x) when x is 1 bit. if (rhsCst->isZero() && op.getLhs().getType() == op.getType() && op.getRhs().getType() == op.getType()) { - return rewriter.create(op.getLoc(), op.getLhs()) + return NotPrimOp::create(rewriter, op.getLoc(), op.getLhs()) .getResult(); } // eq(x, 0) -> not(orr(x)) when x is >1 bit if (rhsCst->isZero() && width > 1) { - auto orrOp = rewriter.create(op.getLoc(), op.getLhs()); - return rewriter.create(op.getLoc(), orrOp).getResult(); + auto orrOp = OrRPrimOp::create(rewriter, op.getLoc(), op.getLhs()); + return NotPrimOp::create(rewriter, op.getLoc(), orrOp).getResult(); } // eq(x, ~0) -> andr(x) when x is >1 bit if (rhsCst->isAllOnes() && width > 1 && op.getLhs().getType() == op.getRhs().getType()) { - return rewriter.create(op.getLoc(), op.getLhs()) + return AndRPrimOp::create(rewriter, op.getLoc(), op.getLhs()) .getResult(); } } @@ -923,21 +923,22 @@ LogicalResult NEQPrimOp::canonicalize(NEQPrimOp op, PatternRewriter &rewriter) { // neq(x, 1) -> not(x) when x is 1 bit if (rhsCst->isAllOnes() && op.getLhs().getType() == op.getType() && op.getRhs().getType() == op.getType()) { - return rewriter.create(op.getLoc(), op.getLhs()) + return NotPrimOp::create(rewriter, op.getLoc(), op.getLhs()) .getResult(); } // neq(x, 0) -> orr(x) when x is >1 bit if (rhsCst->isZero() && width > 1) { - return rewriter.create(op.getLoc(), op.getLhs()) + return OrRPrimOp::create(rewriter, op.getLoc(), op.getLhs()) .getResult(); } // neq(x, ~0) -> not(andr(x))) when x is >1 bit if (rhsCst->isAllOnes() && width > 1 && op.getLhs().getType() == op.getRhs().getType()) { - auto andrOp = rewriter.create(op.getLoc(), op.getLhs()); - return rewriter.create(op.getLoc(), andrOp).getResult(); + auto andrOp = + AndRPrimOp::create(rewriter, op.getLoc(), op.getLhs()); + return NotPrimOp::create(rewriter, op.getLoc(), andrOp).getResult(); } } @@ -1422,7 +1423,7 @@ public: auto castToUIntIfSigned = [&](Value value) -> Value { if (type_isa(value.getType())) return value; - return rewriter.create(value.getLoc(), value); + return AsUIntPrimOp::create(rewriter, value.getLoc(), value); }; assert(operands.size() >= 1 && "zero width cast must be rejected"); @@ -1481,7 +1482,7 @@ public: operands.push_back(cst); } else { // Folded. - operands.push_back(rewriter.create(cat.getLoc(), value)); + operands.push_back(ConstantOp::create(rewriter, cat.getLoc(), value)); } i = j - 1; @@ -1585,7 +1586,7 @@ static void replaceWithBits(Operation *op, Value value, unsigned hiBit, unsigned loBit, PatternRewriter &rewriter) { auto resType = type_cast(op->getResult(0).getType()); if (type_cast(value.getType()).getWidth() != resType.getWidth()) - value = rewriter.create(op->getLoc(), value, hiBit, loBit); + value = BitsPrimOp::create(rewriter, op->getLoc(), value, hiBit, loBit); if (resType.isSigned() && !type_cast(value.getType()).isSigned()) { value = rewriter.createOrFold(op->getLoc(), resType, value); @@ -1677,8 +1678,8 @@ public: type_cast(input.getType()).getBitWidthOrSentinel(); if (inputWidth < 0 || width == inputWidth) return input; - return rewriter - .create(mux.getLoc(), mux.getType(), input, width) + return PadPrimOp::create(rewriter, mux.getLoc(), mux.getType(), input, + width) .getResult(); }; @@ -1714,9 +1715,8 @@ public: return {}; } rewriter.setInsertionPointAfter(mux); - return rewriter - .create(mux.getLoc(), mux.getType(), - ValueRange{mux.getSel(), high, low}) + return MuxPrimOp::create(rewriter, mux.getLoc(), mux.getType(), + ValueRange{mux.getSel(), high, low}) .getResult(); } @@ -2060,8 +2060,7 @@ MatchingConnectOp firrtl::getSingleConnectUserOf(Value value) { if (!matchingConnect || (connect && connect != matchingConnect) || matchingConnect->getBlock() != value.getParentBlock()) return {}; - else - connect = matchingConnect; + connect = matchingConnect; } } return connect; @@ -2178,7 +2177,7 @@ LogicalResult AttachOp::canonicalize(AttachOp op, PatternRewriter &rewriter) { for (auto newOperand : attach.getOperands()) if (newOperand != operand) // Don't add operand twice. newOperands.push_back(newOperand); - rewriter.create(op->getLoc(), newOperands); + AttachOp::create(rewriter, op->getLoc(), newOperands); rewriter.eraseOp(attach); rewriter.eraseOp(op); return success(); @@ -2196,7 +2195,7 @@ LogicalResult AttachOp::canonicalize(AttachOp op, PatternRewriter &rewriter) { if (newOperand != operand) // Don't the add wire. newOperands.push_back(newOperand); - rewriter.create(op->getLoc(), newOperands); + AttachOp::create(rewriter, op->getLoc(), newOperands); rewriter.eraseOp(op); rewriter.eraseOp(wire); return success(); @@ -2674,8 +2673,9 @@ static void erasePort(PatternRewriter &rewriter, Value port) { Value clock; auto getClock = [&] { if (!clock) - clock = rewriter.create( - port.getLoc(), ClockType::get(rewriter.getContext()), false); + clock = SpecialConstantOp::create(rewriter, port.getLoc(), + ClockType::get(rewriter.getContext()), + false); return clock; }; @@ -2687,7 +2687,7 @@ static void erasePort(PatternRewriter &rewriter, Value port) { auto subfield = dyn_cast(op); if (!subfield) { auto ty = port.getType(); - auto reg = rewriter.create(port.getLoc(), ty, getClock()); + auto reg = RegOp::create(rewriter, port.getLoc(), ty, getClock()); rewriter.replaceAllUsesWith(port, reg.getResult()); return; } @@ -2714,7 +2714,7 @@ static void erasePort(PatternRewriter &rewriter, Value port) { // Replace read values with a register that is never written, handing off // the canonicalization of such a register to another canonicalizer. auto ty = access.getType(); - auto reg = rewriter.create(access.getLoc(), ty, getClock()); + auto reg = RegOp::create(rewriter, access.getLoc(), ty, getClock()); rewriter.replaceOp(access, reg.getResult()); } assert(port.use_empty() && "port should have no remaining uses"); @@ -2752,10 +2752,10 @@ struct FoldZeroWidthMemory : public mlir::RewritePattern { .getResult(); if (fieldName.ends_with("data")) { // Make sure to write data ports. - auto zero = rewriter.create( - wire.getLoc(), firrtl::type_cast(wire.getType()), - APInt::getZero(0)); - rewriter.create(wire.getLoc(), wire, zero); + auto zero = firrtl::ConstantOp::create( + rewriter, wire.getLoc(), + firrtl::type_cast(wire.getType()), APInt::getZero(0)); + MatchingConnectOp::create(rewriter, wire.getLoc(), wire, zero); } } } @@ -2857,8 +2857,8 @@ struct FoldUnusedPorts : public mlir::RewritePattern { MemOp newOp; if (!resultTypes.empty()) - newOp = rewriter.create( - mem.getLoc(), resultTypes, mem.getReadLatency(), + newOp = MemOp::create( + rewriter, mem.getLoc(), resultTypes, mem.getReadLatency(), mem.getWriteLatency(), mem.getDepth(), mem.getRuw(), rewriter.getStrArrayAttr(portNames), mem.getName(), mem.getNameKind(), mem.getAnnotations(), rewriter.getArrayAttr(portAnnotations), @@ -2918,12 +2918,12 @@ struct FoldReadWritePorts : public mlir::RewritePattern { portAnnotations.push_back(mem.getPortAnnotation(i)); } - auto newOp = rewriter.create( - mem.getLoc(), resultTypes, mem.getReadLatency(), mem.getWriteLatency(), - mem.getDepth(), mem.getRuw(), rewriter.getStrArrayAttr(portNames), - mem.getName(), mem.getNameKind(), mem.getAnnotations(), - rewriter.getArrayAttr(portAnnotations), mem.getInnerSymAttr(), - mem.getInitAttr(), mem.getPrefixAttr()); + auto newOp = MemOp::create( + rewriter, mem.getLoc(), resultTypes, mem.getReadLatency(), + mem.getWriteLatency(), mem.getDepth(), mem.getRuw(), + rewriter.getStrArrayAttr(portNames), mem.getName(), mem.getNameKind(), + mem.getAnnotations(), rewriter.getArrayAttr(portAnnotations), + mem.getInnerSymAttr(), mem.getInitAttr(), mem.getPrefixAttr()); for (unsigned i = 0, n = mem.getNumResults(); i < n; ++i) { auto result = mem.getResult(i); @@ -2937,8 +2937,8 @@ struct FoldReadWritePorts : public mlir::RewritePattern { auto fromFieldIndex = resultPortTy.getElementIndex(fromName); assert(fromFieldIndex && "missing enable flag on memory port"); - auto toField = rewriter.create(newResult.getLoc(), - newResult, toName); + auto toField = SubfieldOp::create(rewriter, newResult.getLoc(), + newResult, toName); for (auto *op : llvm::make_early_inc_range(result.getUsers())) { auto fromField = cast(op); if (fromFieldIndex != fromField.getFieldIndex()) @@ -3119,7 +3119,7 @@ struct FoldUnusedBits : public mlir::RewritePattern { rewriter.setInsertionPointAfter(newMem); auto newPortAccess = - rewriter.create(port.getLoc(), port, field); + SubfieldOp::create(rewriter, port.getLoc(), port, field); for (auto *op : llvm::make_early_inc_range(port.getUsers())) { auto portAccess = cast(op); @@ -3263,7 +3263,7 @@ struct FoldRegMems : public mlir::RewritePattern { // Create a new wire where the memory used to be. This wire will dominate // all readers of the memory. Reads should be made through this wire. rewriter.setInsertionPointAfter(mem); - auto memWire = rewriter.create(loc, ty).getResult(); + auto memWire = WireOp::create(rewriter, loc, ty).getResult(); // The memory is replaced by a register, which we place at the end of the // block, so that any value driven to the original memory will dominate the @@ -3271,10 +3271,10 @@ struct FoldRegMems : public mlir::RewritePattern { // after the register. rewriter.setInsertionPointToEnd(block); auto memReg = - rewriter.create(loc, ty, clock, mem.getName()).getResult(); + RegOp::create(rewriter, loc, ty, clock, mem.getName()).getResult(); // Connect the output of the register to the wire. - rewriter.create(loc, memWire, memReg); + MatchingConnectOp::create(rewriter, loc, memWire, memReg); // Helper to insert a given number of pipeline stages through registers. // The pipelines are placed at the end of the block. @@ -3286,11 +3286,10 @@ struct FoldRegMems : public mlir::RewritePattern { llvm::raw_string_ostream os(regName); os << mem.getName() << "_" << name << "_" << i; } - auto reg = rewriter - .create(mem.getLoc(), value.getType(), clock, - rewriter.getStringAttr(regName)) + auto reg = RegOp::create(rewriter, mem.getLoc(), value.getType(), clock, + rewriter.getStringAttr(regName)) .getResult(); - rewriter.create(value.getLoc(), reg, value); + MatchingConnectOp::create(rewriter, value.getLoc(), reg, value); value = reg; } return value; @@ -3341,7 +3340,7 @@ struct FoldRegMems : public mlir::RewritePattern { Value en = getPortFieldValue(port, "en"); Value wmode = getPortFieldValue(port, "wmode"); - auto wen = rewriter.create(port.getLoc(), en, wmode); + auto wen = AndPrimOp::create(rewriter, port.getLoc(), en, wmode); auto wenPipelined = pipeline(wen, portClock, name + "_wen", writeStages); writes.emplace_back(wdata, wenPipelined, wmask); @@ -3367,16 +3366,16 @@ struct FoldRegMems : public mlir::RewritePattern { auto dataPart = rewriter.createOrFold(loc, data, hi, lo); auto nextPart = rewriter.createOrFold(loc, next, hi, lo); auto bit = rewriter.createOrFold(loc, mask, i, i); - auto chunk = rewriter.create(loc, bit, dataPart, nextPart); + auto chunk = MuxPrimOp::create(rewriter, loc, bit, dataPart, nextPart); chunks.push_back(chunk); } std::reverse(chunks.begin(), chunks.end()); masked = rewriter.createOrFold(loc, chunks); - next = rewriter.create(next.getLoc(), en, masked, next); + next = MuxPrimOp::create(rewriter, next.getLoc(), en, masked, next); } Value typedNext = rewriter.createOrFold(next.getLoc(), ty, next); - rewriter.create(memReg.getLoc(), memReg, typedNext); + MatchingConnectOp::create(rewriter, memReg.getLoc(), memReg, typedNext); // Delete the fields and their associated connects. for (Operation *conn : connects) @@ -3566,8 +3565,8 @@ LogicalResult InvalidValueOp::canonicalize(InvalidValueOp op, type_cast(op->user_begin()->getOperand(0).getType()) .getBitWidthOrSentinel() > 0))) { auto *modop = *op->user_begin(); - auto inv = rewriter.create(op.getLoc(), - modop->getResult(0).getType()); + auto inv = InvalidValueOp::create(rewriter, op.getLoc(), + modop->getResult(0).getType()); rewriter.replaceAllOpUsesWith(modop, inv); rewriter.eraseOp(modop); rewriter.eraseOp(op); diff --git a/lib/Dialect/FIRRTL/FIRRTLIntrinsics.cpp b/lib/Dialect/FIRRTL/FIRRTLIntrinsics.cpp index 1d692509fa..a56c21f6b2 100644 --- a/lib/Dialect/FIRRTL/FIRRTLIntrinsics.cpp +++ b/lib/Dialect/FIRRTL/FIRRTLIntrinsics.cpp @@ -181,7 +181,7 @@ FailureOr IntrinsicLowerings::lower(FModuleOp mod, !isTypeLarger(resultType, inputType)) return {}; - auto w = builder.create(loc, resultType).getResult(); + auto w = WireOp::create(builder, loc, resultType).getResult(); emitConnect(builder, loc, w, inputs.front()); return w; }; @@ -265,8 +265,8 @@ public: void convert(GenericIntrinsic gi, GenericIntrinsicOpAdaptor adaptor, PatternRewriter &rewriter) override { auto bty = gi.getOutputBundle().getType(); - auto newop = rewriter.create( - gi.op.getLoc(), bty.getElementTypePreservingConst(0), + auto newop = PlusArgsValueIntrinsicOp::create( + rewriter, gi.op.getLoc(), bty.getElementTypePreservingConst(0), bty.getElementTypePreservingConst(1), gi.getParamValue("FORMAT")); rewriter.replaceOpWithNewOp( diff --git a/lib/Dialect/FIRRTL/FIRRTLOps.cpp b/lib/Dialect/FIRRTL/FIRRTLOps.cpp index a362bbe19b..982dfe336f 100644 --- a/lib/Dialect/FIRRTL/FIRRTLOps.cpp +++ b/lib/Dialect/FIRRTL/FIRRTLOps.cpp @@ -2051,7 +2051,7 @@ void ClassOp::build(::mlir::OpBuilder &odsBuilder, auto args = body.getArguments(); auto loc = odsState.location; for (unsigned i = 0, e = ports.size(); i != e; i += 2) - odsBuilder.create(loc, args[i + 1], args[i]); + PropAssignOp::create(odsBuilder, loc, args[i + 1], args[i]); odsBuilder.restoreInsertionPoint(prevLoc); } @@ -2413,11 +2413,11 @@ InstanceOp InstanceOp::erasePorts(OpBuilder &builder, SmallVector newPortAnnotations = removeElementsAtIndices(getPortAnnotations().getValue(), portIndices); - auto newOp = builder.create( - getLoc(), newResultTypes, getModuleName(), getName(), getNameKind(), - newPortDirections, newPortNames, getAnnotations().getValue(), - newPortAnnotations, getLayers(), getLowerToBind(), getDoNotPrint(), - getInnerSymAttr()); + auto newOp = InstanceOp::create( + builder, getLoc(), newResultTypes, getModuleName(), getName(), + getNameKind(), newPortDirections, newPortNames, + getAnnotations().getValue(), newPortAnnotations, getLayers(), + getLowerToBind(), getDoNotPrint(), getInnerSymAttr()); for (unsigned oldIdx = 0, newIdx = 0, numOldPorts = getNumResults(); oldIdx != numOldPorts; ++oldIdx) { @@ -2487,11 +2487,12 @@ InstanceOp::cloneAndInsertPorts(ArrayRef> ports) { } // Create a new instance op with the reset inserted. - return OpBuilder(*this).create( - getLoc(), newPortTypes, getModuleName(), getName(), getNameKind(), - newPortDirections, newPortNames, getAnnotations().getValue(), - newPortAnnos, getLayers(), getLowerToBind(), getDoNotPrint(), - getInnerSymAttr()); + OpBuilder builder(*this); + return InstanceOp::create(builder, getLoc(), newPortTypes, getModuleName(), + getName(), getNameKind(), newPortDirections, + newPortNames, getAnnotations().getValue(), + newPortAnnos, getLayers(), getLowerToBind(), + getDoNotPrint(), getInnerSymAttr()); } LogicalResult InstanceOp::verifySymbolUses(SymbolTableCollection &symbolTable) { @@ -2910,9 +2911,10 @@ InstanceChoiceOp::erasePorts(OpBuilder &builder, SmallVector newPortAnnotations = removeElementsAtIndices(getPortAnnotations().getValue(), portIndices); - auto newOp = builder.create( - getLoc(), newResultTypes, getModuleNames(), getCaseNames(), getName(), - getNameKind(), direction::packAttribute(getContext(), newPortDirections), + auto newOp = InstanceChoiceOp::create( + builder, getLoc(), newResultTypes, getModuleNames(), getCaseNames(), + getName(), getNameKind(), + direction::packAttribute(getContext(), newPortDirections), ArrayAttr::get(getContext(), newPortNames), getAnnotationsAttr(), ArrayAttr::get(getContext(), newPortAnnotations), getLayers(), getInnerSymAttr()); diff --git a/lib/Dialect/FIRRTL/FIRRTLReductions.cpp b/lib/Dialect/FIRRTL/FIRRTLReductions.cpp index 693c09d767..3dd8193f44 100644 --- a/lib/Dialect/FIRRTL/FIRRTLReductions.cpp +++ b/lib/Dialect/FIRRTL/FIRRTLReductions.cpp @@ -193,8 +193,8 @@ struct FIRRTLModuleExternalizer : public OpReduction { LogicalResult rewrite(firrtl::FModuleOp module) override { nlaRemover.markNLAsInOperation(module); OpBuilder builder(module); - builder.create( - module->getLoc(), + firrtl::FExtModuleOp::create( + builder, module->getLoc(), module->getAttrOfType(SymbolTable::getSymbolAttrName()), module.getConventionAttr(), module.getPorts(), ArrayAttr(), StringRef(), module.getAnnotationsAttr()); @@ -249,10 +249,10 @@ static void invalidateOutputs(ImplicitLocOpBuilder &builder, Value value, return; Value invalid = invalidCache.lookup(type); if (!invalid) { - invalid = builder.create(type); + invalid = firrtl::InvalidValueOp::create(builder, type); invalidCache.insert({type, invalid}); } - builder.create(value, invalid); + firrtl::ConnectOp::create(builder, value, invalid); } /// Connect a value to every leave of a destination value. @@ -264,13 +264,13 @@ static void connectToLeafs(ImplicitLocOpBuilder &builder, Value dest, if (auto bundleType = dyn_cast(type)) { for (auto element : llvm::enumerate(bundleType.getElements())) connectToLeafs(builder, - builder.create(dest, element.index()), + firrtl::SubfieldOp::create(builder, dest, element.index()), value); return; } if (auto vectorType = dyn_cast(type)) { for (unsigned i = 0, e = vectorType.getNumElements(); i != e; ++i) - connectToLeafs(builder, builder.create(dest, i), + connectToLeafs(builder, firrtl::SubindexOp::create(builder, dest, i), value); return; } @@ -280,14 +280,14 @@ static void connectToLeafs(ImplicitLocOpBuilder &builder, Value dest, auto destWidth = type.getBitWidthOrSentinel(); auto valueWidth = valueType ? valueType.getBitWidthOrSentinel() : -1; if (destWidth >= 0 && valueWidth >= 0 && destWidth < valueWidth) - value = builder.create(value, destWidth); + value = firrtl::HeadPrimOp::create(builder, value, destWidth); if (!isa(type)) { if (isa(type)) - value = builder.create(value); + value = firrtl::AsSIntPrimOp::create(builder, value); else return; } - builder.create(dest, value); + firrtl::ConnectOp::create(builder, dest, value); } /// Reduce all leaf fields of a value through an XOR tree. @@ -310,7 +310,7 @@ static void reduceXor(ImplicitLocOpBuilder &builder, Value &into, Value value) { } if (!isa(type)) { if (isa(type)) - value = builder.create(value); + value = firrtl::AsUIntPrimOp::create(builder, value); else return; } @@ -376,10 +376,9 @@ struct InstanceStubber : public OpReduction { auto name = builder.getStringAttr(Twine(instOp.getName()) + "_" + instOp.getPortNameStr(i)); auto wire = - builder - .create(result.getType(), name, - firrtl::NameKindEnum::DroppableName, - instOp.getPortAnnotation(i), StringAttr{}) + firrtl::WireOp::create(builder, result.getType(), name, + firrtl::NameKindEnum::DroppableName, + instOp.getPortAnnotation(i), StringAttr{}) .getResult(); invalidateOutputs(builder, wire, invalidCache, instOp.getPortDirection(i) == firrtl::Direction::In); @@ -426,10 +425,9 @@ struct MemoryStubber : public OpReduction { auto name = builder.getStringAttr(Twine(memOp.getName()) + "_" + memOp.getPortNameStr(i)); auto wire = - builder - .create(result.getType(), name, - firrtl::NameKindEnum::DroppableName, - memOp.getPortAnnotation(i), StringAttr{}) + firrtl::WireOp::create(builder, result.getType(), name, + firrtl::NameKindEnum::DroppableName, + memOp.getPortAnnotation(i), StringAttr{}) .getResult(); invalidateOutputs(builder, wire, invalidCache, true); result.replaceAllUsesWith(wire); @@ -556,8 +554,9 @@ struct FIRRTLConstantifier : public Reduction { auto width = type.getBitWidthOrSentinel(); if (width == -1) width = 64; - auto newOp = builder.create( - op->getLoc(), type, APSInt(width, isa(type))); + auto newOp = + firrtl::ConstantOp::create(builder, op->getLoc(), type, + APSInt(width, isa(type))); op->replaceAllUsesWith(newOp); reduce::pruneUnusedOps(op, *this); return success(); @@ -582,7 +581,7 @@ struct ConnectInvalidator : public Reduction { auto rhs = op->getOperand(1); OpBuilder builder(op); auto invOp = - builder.create(rhs.getLoc(), rhs.getType()); + firrtl::InvalidValueOp::create(builder, rhs.getLoc(), rhs.getType()); auto *rhsOp = rhs.getDefiningOp(); op->setOperand(1, invOp); if (rhsOp) @@ -670,15 +669,13 @@ struct ExtmoduleInstanceRemover : public OpReduction { ImplicitLocOpBuilder builder(instOp.getLoc(), instOp); SmallVector replacementWires; for (firrtl::PortInfo info : portInfo) { - auto wire = - builder - .create( - info.type, - (Twine(instOp.getName()) + "_" + info.getName()).str()) - .getResult(); + auto wire = firrtl::WireOp::create( + builder, info.type, + (Twine(instOp.getName()) + "_" + info.getName()).str()) + .getResult(); if (info.isOutput()) { - auto inv = builder.create(info.type); - builder.create(wire, inv); + auto inv = firrtl::InvalidValueOp::create(builder, info.type); + firrtl::ConnectOp::create(builder, wire, inv); } replacementWires.push_back(wire); } @@ -786,27 +783,25 @@ struct ConnectSourceOperandForwarder : public Reduction { ImplicitLocOpBuilder builder(destOp->getLoc(), destOp); Value newDest; if (auto wire = dyn_cast(destOp)) - newDest = builder - .create(forwardedOperand.getType(), - wire.getName()) + newDest = firrtl::WireOp::create(builder, forwardedOperand.getType(), + wire.getName()) .getResult(); else { auto regName = destOp->getAttrOfType("name"); // We can promote the register into a wire but we wouldn't do here because // the error might be caused by the register. auto clock = destOp->getOperand(0); - newDest = builder - .create(forwardedOperand.getType(), clock, - regName ? regName.str() : "") + newDest = firrtl::RegOp::create(builder, forwardedOperand.getType(), + clock, regName ? regName.str() : "") .getResult(); } // Create new connection between a new wire and the forwarded operand. builder.setInsertionPointAfter(op); if (isa(op)) - builder.create(newDest, forwardedOperand); + firrtl::ConnectOp::create(builder, newDest, forwardedOperand); else - builder.create(newDest, forwardedOperand); + firrtl::MatchingConnectOp::create(builder, newDest, forwardedOperand); // Remove the old connection and destination. We don't have to replace them // because destination has only one use. @@ -848,17 +843,17 @@ struct DetachSubaccesses : public Reduction { bool isWire = isa(op); Value invalidClock; if (!isWire) - invalidClock = builder.create( - op->getLoc(), firrtl::ClockType::get(op->getContext())); + invalidClock = firrtl::InvalidValueOp::create( + builder, op->getLoc(), firrtl::ClockType::get(op->getContext())); for (Operation *user : llvm::make_early_inc_range(op->getUsers())) { builder.setInsertionPoint(user); auto type = user->getResult(0).getType(); Operation *replOp; if (isWire) - replOp = builder.create(user->getLoc(), type); + replOp = firrtl::WireOp::create(builder, user->getLoc(), type); else replOp = - builder.create(user->getLoc(), type, invalidClock); + firrtl::RegOp::create(builder, user->getLoc(), type, invalidClock); user->replaceAllUsesWith(replOp); opsToErase.insert(user); } @@ -914,10 +909,9 @@ struct EagerInliner : public OpReduction { auto name = builder.getStringAttr(Twine(instOp.getName()) + "_" + instOp.getPortNameStr(i)); auto wire = - builder - .create(result.getType(), name, - firrtl::NameKindEnum::DroppableName, - instOp.getPortAnnotation(i), StringAttr{}) + firrtl::WireOp::create(builder, result.getType(), name, + firrtl::NameKindEnum::DroppableName, + instOp.getPortAnnotation(i), StringAttr{}) .getResult(); result.replaceAllUsesWith(wire); argReplacements.push_back(wire); diff --git a/lib/Dialect/FIRRTL/FIRRTLUtils.cpp b/lib/Dialect/FIRRTL/FIRRTLUtils.cpp index cd4198e87f..6a6b9421dc 100644 --- a/lib/Dialect/FIRRTL/FIRRTLUtils.cpp +++ b/lib/Dialect/FIRRTL/FIRRTLUtils.cpp @@ -42,29 +42,29 @@ void circt::firrtl::emitConnect(ImplicitLocOpBuilder &builder, Value dst, // References use ref.define. Add cast if types don't match. if (type_isa(dstFType)) { if (dstFType != srcFType) - src = builder.create(dstFType, src); - builder.create(dst, src); + src = RefCastOp::create(builder, dstFType, src); + RefDefineOp::create(builder, dst, src); } else if (type_isa(dstFType) && type_isa(srcFType)) { // Properties use propassign. - builder.create(dst, src); + PropAssignOp::create(builder, dst, src); } else { // Other types, give up and leave a connect - builder.create(dst, src); + ConnectOp::create(builder, dst, src); } return; } // More special connects if (isa(dstType)) { - builder.create(ArrayRef{dst, src}); + AttachOp::create(builder, ArrayRef{dst, src}); return; } // If the types are the exact same we can just connect them. if (dstType == srcType && dstType.isPassive() && !dstType.hasUninferredWidth()) { - builder.create(dst, src); + MatchingConnectOp::create(builder, dst, src); return; } @@ -75,12 +75,12 @@ void circt::firrtl::emitConnect(ImplicitLocOpBuilder &builder, Value dst, // connect and let the verifier catch it. auto srcBundle = type_dyn_cast(srcType); if (!srcBundle || numElements != srcBundle.getNumElements()) { - builder.create(dst, src); + ConnectOp::create(builder, dst, src); return; } for (size_t i = 0; i < numElements; ++i) { - auto dstField = builder.create(dst, i); - auto srcField = builder.create(src, i); + auto dstField = SubfieldOp::create(builder, dst, i); + auto srcField = SubfieldOp::create(builder, src, i); if (dstBundle.getElement(i).isFlip) std::swap(dstField, srcField); emitConnect(builder, dstField, srcField); @@ -95,12 +95,12 @@ void circt::firrtl::emitConnect(ImplicitLocOpBuilder &builder, Value dst, // connect and let the verifier catch it. auto srcVector = type_dyn_cast(srcType); if (!srcVector || numElements != srcVector.getNumElements()) { - builder.create(dst, src); + ConnectOp::create(builder, dst, src); return; } for (size_t i = 0; i < numElements; ++i) { - auto dstField = builder.create(dst, i); - auto srcField = builder.create(src, i); + auto dstField = SubindexOp::create(builder, dst, i); + auto srcField = SubindexOp::create(builder, src, i); emitConnect(builder, dstField, srcField); } return; @@ -109,7 +109,7 @@ void circt::firrtl::emitConnect(ImplicitLocOpBuilder &builder, Value dst, if ((dstType.hasUninferredReset() || srcType.hasUninferredReset()) && dstType != srcType) { srcType = dstType.getConstType(srcType.isConst()); - src = builder.create(srcType, src); + src = UninferredResetCastOp::create(builder, srcType, src); } // Handle passive types with possibly uninferred widths. @@ -124,10 +124,10 @@ void circt::firrtl::emitConnect(ImplicitLocOpBuilder &builder, Value dst, // can be const-cast'd, do so) if (dstType != srcType && dstType.getWidthlessType() != srcType && areTypesConstCastable(dstType.getWidthlessType(), srcType)) { - src = builder.create(dstType.getWidthlessType(), src); + src = ConstCastOp::create(builder, dstType.getWidthlessType(), src); } - builder.create(dst, src); + ConnectOp::create(builder, dst, src); return; } @@ -140,29 +140,29 @@ void circt::firrtl::emitConnect(ImplicitLocOpBuilder &builder, Value dst, if (isSignedDest) tmpType = UIntType::get(dstType.getContext(), dstWidth, srcType.isConst()); - src = builder.create(tmpType, src, srcWidth - dstWidth); + src = TailPrimOp::create(builder, tmpType, src, srcWidth - dstWidth); // Insert the cast back to signed if needed. if (isSignedDest) - src = builder.create( - dstType.getConstType(tmpType.isConst()), src); + src = AsSIntPrimOp::create(builder, + dstType.getConstType(tmpType.isConst()), src); } else if (srcWidth < dstWidth) { // Need to extend arg. - src = builder.create(src, dstWidth); + src = PadPrimOp::create(builder, src, dstWidth); } if (auto srcType = type_cast(src.getType()); srcType && dstType != srcType && areTypesConstCastable(dstType, srcType)) { - src = builder.create(dstType, src); + src = ConstCastOp::create(builder, dstType, src); } // Strict connect requires the types to be completely equal, including // connecting uint<1> to abstract reset types. if (dstType == src.getType() && dstType.isPassive() && !dstType.hasUninferredWidth()) { - builder.create(dst, src); + MatchingConnectOp::create(builder, dst, src); } else - builder.create(dst, src); + ConnectOp::create(builder, dst, src); } IntegerAttr circt::firrtl::getIntAttr(Type type, const APInt &value) { @@ -678,19 +678,19 @@ Value circt::firrtl::getValueByFieldID(ImplicitLocOpBuilder builder, FIRRTLTypeSwitch(value.getType()) .Case([&](auto bundle) { auto index = bundle.getIndexForFieldID(fieldID); - value = builder.create(value, index); + value = SubfieldOp::create(builder, value, index); fieldID -= bundle.getFieldID(index); }) .Case([&](auto vector) { auto index = vector.getIndexForFieldID(fieldID); - value = builder.create(value, index); + value = SubindexOp::create(builder, value, index); fieldID -= vector.getFieldID(index); }) .Case([&](auto reftype) { FIRRTLTypeSwitch(reftype.getType()) .template Case([&](auto type) { auto index = type.getIndexForFieldID(fieldID); - value = builder.create(value, index); + value = RefSubOp::create(builder, value, index); fieldID -= type.getFieldID(index); }) .Default([&](auto _) { @@ -1087,5 +1087,5 @@ PathOp circt::firrtl::createPathRef(Operation *op, hw::HierPathOp nla, } // Create the path operation. - return builderOM.create(kind, id); + return PathOp::create(builderOM, kind, id); } diff --git a/lib/Dialect/FIRRTL/Import/FIRParser.cpp b/lib/Dialect/FIRRTL/Import/FIRParser.cpp index ffd11163a5..480a476cda 100644 --- a/lib/Dialect/FIRRTL/Import/FIRParser.cpp +++ b/lib/Dialect/FIRRTL/Import/FIRParser.cpp @@ -1477,7 +1477,7 @@ struct FIRModuleContext : public FIRParser { } } - result = builder.create(type, std::forward(args)...); + result = OpTy::create(builder, type, std::forward(args)...); if (savedIP.isSet()) builder.setInsertionPoint(savedIP.getBlock(), savedIP.getPoint()); @@ -1996,7 +1996,7 @@ private: } // Create the operation. - auto op = builder.create(type, vals[Ms]..., ints[Ns]...); + auto op = T::create(builder, type, vals[Ms]..., ints[Ns]...); result = op.getResult(); return success(); } @@ -2096,7 +2096,7 @@ void FIRStmtParser::emitInvalidate(Value val, Flow flow) { if (props.isPassive && !props.containsAnalog) { if (flow == Flow::Source) return; - emitConnect(builder, val, builder.create(tpe)); + emitConnect(builder, val, InvalidValueOp::create(builder, tpe)); return; } @@ -2114,7 +2114,7 @@ void FIRStmtParser::emitInvalidate(Value val, Flow flow) { if (!subfield) { OpBuilder::InsertionGuard guard(builder); builder.setInsertionPointAfterValue(val); - subfield = builder.create(val, i); + subfield = SubfieldOp::create(builder, val, i); } emitInvalidate(subfield, tpe.getElement(i).isFlip ? swapFlow(flow) : flow); @@ -2127,7 +2127,7 @@ void FIRStmtParser::emitInvalidate(Value val, Flow flow) { if (!subindex) { OpBuilder::InsertionGuard guard(builder); builder.setInsertionPointAfterValue(val); - subindex = builder.create(tpex, val, i); + subindex = SubindexOp::create(builder, tpex, val, i); } emitInvalidate(subindex, flow); } @@ -2382,7 +2382,7 @@ ParseResult FIRStmtParser::parseExpImpl(Value &result, const Twine &message, // For FIRRTL versions earlier than 4.0.0, insert pad(_, 1) around any // unsigned shr This ensures the minimum width is 1 (but can be greater) if (version < FIRVersion(4, 0, 0) && type_isa(result.getType())) - result = builder.create(result, 1); + result = PadPrimOp::create(builder, result, 1); break; default: break; @@ -2453,7 +2453,7 @@ FIRStmtParser::emitCachedSubAccess(Value base, unsigned indexNo, SMLoc loc) { locationProcessor.setLoc(loc); OpBuilder::InsertionGuard guard(builder); builder.setInsertionPointAfterValue(base); - auto op = builder.create(resultType, base, indexNo); + auto op = subop::create(builder, resultType, base, indexNo); // Insert the newly created operation into the cache. return value = op.getResult(); @@ -2561,7 +2561,7 @@ ParseResult FIRStmtParser::parsePostFixDynamicSubscript(Value &result) { } // Create the result operation. - auto op = builder.create(resultType, result, index); + auto op = SubaccessOp::create(builder, resultType, result, index); result = op.getResult(); return success(); } @@ -2634,7 +2634,7 @@ ParseResult FIRStmtParser::parseListExp(Value &result) { return emitError(loc, "unexpected expression of type ") << operand.getType() << " in List expression of type " << elementType; - operand = builder.create(operand); + operand = ObjectAnyRefCastOp::create(builder, operand); } operands.push_back(operand); @@ -2643,7 +2643,7 @@ ParseResult FIRStmtParser::parseListExp(Value &result) { return failure(); locationProcessor.setLoc(loc); - result = builder.create(listType, operands); + result = ListCreateOp::create(builder, listType, operands); return success(); } @@ -2681,7 +2681,7 @@ ParseResult FIRStmtParser::parseListConcatExp(Value &result) { return emitError(loc, "need at least one List to concatenate"); locationProcessor.setLoc(loc); - result = builder.create(type, operands); + result = ListConcatOp::create(builder, type, operands); return success(); } @@ -2708,7 +2708,7 @@ ParseResult FIRStmtParser::parseCatExp(Value &result) { } locationProcessor.setLoc(loc); - result = builder.create(operands); + result = CatPrimOp::create(builder, operands); return success(); } @@ -2998,7 +2998,7 @@ ParseResult FIRStmtParser::parseAttach() { return failure(); locationProcessor.setLoc(startTok.getLoc()); - builder.create(operands); + AttachOp::create(builder, operands); return success(); } @@ -3045,15 +3045,15 @@ ParseResult FIRStmtParser::parseMemPort(MemDirAttr direction) { { OpBuilder::InsertionGuard guard(builder); builder.setInsertionPointAfterValue(memory); - auto memoryPortOp = builder.create( - resultType, CMemoryPortType::get(getContext()), memory, direction, id, - annotations); + auto memoryPortOp = MemoryPortOp::create( + builder, resultType, CMemoryPortType::get(getContext()), memory, + direction, id, annotations); memoryData = memoryPortOp.getResult(0); memoryPort = memoryPortOp.getResult(1); } // Create a memory port access in the current scope. - builder.create(memoryPort, indexExp, clock); + MemoryPortAccessOp::create(builder, memoryPort, indexExp, clock); return moduleContext.addSymbolEntry(id, memoryData, startLoc, true); } @@ -3144,9 +3144,9 @@ ParseResult FIRStmtParser::parseFormatString(SMLoc formatStringLoc, auto specialString = formatString.slice(start, i); if (specialString == "SimulationTime") { - operands.push_back(builder.create()); + operands.push_back(TimeOp::create(builder)); } else if (specialString == "HierarchicalModuleName") { - operands.push_back(builder.create()); + operands.push_back(HierarchicalModuleNameOp::create(builder)); } else { emitError(formatStringLoc) << "unknown printf substitution '" << specialString @@ -3206,8 +3206,8 @@ ParseResult FIRStmtParser::parsePrintf() { formatStrUnescaped, operands)) return failure(); - builder.create(clock, condition, formatStrUnescaped, operands, - name); + PrintFOp::create(builder, clock, condition, formatStrUnescaped, operands, + name); return success(); } @@ -3271,9 +3271,8 @@ ParseResult FIRStmtParser::parseFPrintf() { formatStrUnescaped, operands)) return failure(); - builder.create(clock, condition, outputFileNameStrUnescaped, - outputFileOperands, formatStrUnescaped, operands, - name); + FPrintFOp::create(builder, clock, condition, outputFileNameStrUnescaped, + outputFileOperands, formatStrUnescaped, operands, name); return success(); } @@ -3317,8 +3316,8 @@ ParseResult FIRStmtParser::parseFFlush() { parseOptionalInfo()) return failure(); - builder.create(clock, condition, outputFileNameStrUnescaped, - outputFileOperands); + FFlushOp::create(builder, clock, condition, outputFileNameStrUnescaped, + outputFileOperands); return success(); } @@ -3335,7 +3334,7 @@ ParseResult FIRStmtParser::parseSkip() { return failure(); locationProcessor.setLoc(startTok.getLoc()); - builder.create(); + SkipOp::create(builder); return success(); } @@ -3356,8 +3355,8 @@ ParseResult FIRStmtParser::parseStop() { return failure(); locationProcessor.setLoc(startTok.getLoc()); - builder.create(clock, condition, builder.getI32IntegerAttr(exitCode), - name); + StopOp::create(builder, clock, condition, builder.getI32IntegerAttr(exitCode), + name); return success(); } @@ -3391,8 +3390,8 @@ ParseResult FIRStmtParser::parseAssert() { locationProcessor.setLoc(startTok.getLoc()); auto formatStrUnescaped = FIRToken::getStringValue(formatString); - builder.create(clock, predicate, enable, formatStrUnescaped, - operands, name.getValue()); + AssertOp::create(builder, clock, predicate, enable, formatStrUnescaped, + operands, name.getValue()); return success(); } @@ -3426,8 +3425,8 @@ ParseResult FIRStmtParser::parseAssume() { locationProcessor.setLoc(startTok.getLoc()); auto formatStrUnescaped = FIRToken::getStringValue(formatString); - builder.create(clock, predicate, enable, formatStrUnescaped, - operands, name.getValue()); + AssumeOp::create(builder, clock, predicate, enable, formatStrUnescaped, + operands, name.getValue()); return success(); } @@ -3452,8 +3451,8 @@ ParseResult FIRStmtParser::parseCover() { locationProcessor.setLoc(startTok.getLoc()); auto messageUnescaped = FIRToken::getStringValue(message); - builder.create(clock, predicate, enable, messageUnescaped, - ValueRange{}, name.getValue()); + CoverOp::create(builder, clock, predicate, enable, messageUnescaped, + ValueRange{}, name.getValue()); return success(); } @@ -3475,7 +3474,7 @@ ParseResult FIRStmtParser::parseWhen(unsigned whenIndent) { locationProcessor.setLoc(startTok.getLoc()); // Create the IR representation for the when. - auto whenStmt = builder.create(condition, /*createElse*/ false); + auto whenStmt = WhenOp::create(builder, condition, /*createElse*/ false); // Parse the 'then' body into the 'then' region. if (parseSubBlock(whenStmt.getThenBlock(), whenIndent, layerSym)) @@ -3547,7 +3546,7 @@ ParseResult FIRStmtParser::parseEnumExp(Value &value) { auto type = IntType::get(builder.getContext(), false, 0, true); Type attrType = IntegerType::get(getContext(), 0, IntegerType::Unsigned); auto attr = builder.getIntegerAttr(attrType, APInt(0, 0, false)); - input = builder.create(type, attr); + input = ConstantOp::create(builder, type, attr); } else { // Otherwise we parse an expression. if (parseToken(FIRToken::comma, "expected ','") || @@ -3556,7 +3555,7 @@ ParseResult FIRStmtParser::parseEnumExp(Value &value) { return failure(); } - value = builder.create(enumType, tag, input); + value = FEnumCreateOp::create(builder, enumType, tag, input); return success(); } @@ -3650,7 +3649,7 @@ ParseResult FIRStmtParser::parseMatch(unsigned matchIndent) { return failure(); } - builder.create(input, ArrayAttr::get(getContext(), tags), regions); + MatchOp::create(builder, input, ArrayAttr::get(getContext(), tags), regions); return success(); } @@ -3774,8 +3773,9 @@ ParseResult FIRStmtParser::parseRWProbeStaticRefExp(FieldRef &refResult, locationProcessor.setLoc(loc); OpBuilder::InsertionGuard guard(builder); builder.setInsertionPoint(defining); - auto bounce = builder.create( - type, name, NameKindEnum::InterestingName, annotations, sym); + auto bounce = + WireOp::create(builder, type, name, NameKindEnum::InterestingName, + annotations, sym); auto bounceVal = bounce.getData(); // Replace instance result with reads from bounce wire. @@ -3915,8 +3915,8 @@ ParseResult FIRStmtParser::parseIntrinsic(Value &result, bool isStatement) { locationProcessor.setLoc(loc); - auto op = builder.create( - type, builder.getStringAttr(intrinsic), operands, parameters); + auto op = GenericIntrinsicOp::create( + builder, type, builder.getStringAttr(intrinsic), operands, parameters); if (type) result = op.getResult(); return success(); @@ -3962,8 +3962,8 @@ ParseResult FIRStmtParser::parsePathExp(Value &result) { "expected target string in path expression") || parseToken(FIRToken::r_paren, "expected ')' in path expression")) return failure(); - result = builder.create( - StringAttr::get(getContext(), FIRToken::getStringValue(target))); + result = UnresolvedPathOp::create( + builder, StringAttr::get(getContext(), FIRToken::getStringValue(target))); return success(); } @@ -4026,7 +4026,7 @@ ParseResult FIRStmtParser::parseRefRead(Value &result) { "expected reference-type expression in 'read', got ") << ref.getType(); - result = builder.create(ref); + result = RefResolveOp::create(builder, ref); return success(); } @@ -4056,7 +4056,7 @@ ParseResult FIRStmtParser::parseProbe(Value &result) { staticRef.getDefiningOp())) return emitError(startTok.getLoc(), "cannot probe memories or their ports"); - result = builder.create(staticRef); + result = RefSendOp::create(builder, staticRef); return success(); } @@ -4098,8 +4098,8 @@ ParseResult FIRStmtParser::parseRWProbe(Value &result) { << targetType; // Create the operation with a placeholder reference and add to fixup list. - auto op = builder.create(forceableType, - getConstants().placeholderInnerRef); + auto op = RWProbeOp::create(builder, forceableType, + getConstants().placeholderInnerRef); innerSymFixups.add(op, getTargetFor(staticRef)); result = op; return success(); @@ -4146,14 +4146,14 @@ ParseResult FIRStmtParser::parseRefForce() { // Try to cast destination to rwprobe of source type (dropping const). auto compatibleRWProbe = RefType::get(noConstSrcType, true, ref.getLayer()); if (areTypesRefCastable(compatibleRWProbe, ref)) - dest = builder.create(compatibleRWProbe, dest); + dest = RefCastOp::create(builder, compatibleRWProbe, dest); else return emitError(startTok.getLoc(), "incompatible force source of type ") << src.getType() << " cannot target destination " << dest.getType(); } - builder.create(clock, pred, dest, src); + RefForceOp::create(builder, clock, pred, dest, src); return success(); } @@ -4196,7 +4196,7 @@ ParseResult FIRStmtParser::parseRefForceInitial() { // Try to cast destination to rwprobe of source type (dropping const). auto compatibleRWProbe = RefType::get(noConstSrcType, true, ref.getLayer()); if (areTypesRefCastable(compatibleRWProbe, ref)) - dest = builder.create(compatibleRWProbe, dest); + dest = RefCastOp::create(builder, compatibleRWProbe, dest); else return emitError(startTok.getLoc(), "incompatible force_initial source of type ") @@ -4211,7 +4211,7 @@ ParseResult FIRStmtParser::parseRefForceInitial() { IntegerType::Unsigned), value); auto pred = moduleContext.getCachedConstant(builder, attr, type, attr); - builder.create(pred, dest, src); + RefForceInitialOp::create(builder, pred, dest, src); return success(); } @@ -4241,7 +4241,7 @@ ParseResult FIRStmtParser::parseRefRelease() { locationProcessor.setLoc(startTok.getLoc()); - builder.create(clock, pred, dest); + RefReleaseOp::create(builder, clock, pred, dest); return success(); } @@ -4274,7 +4274,7 @@ ParseResult FIRStmtParser::parseRefReleaseInitial() { IntegerType::Unsigned), value); auto pred = moduleContext.getCachedConstant(builder, attr, type, attr); - builder.create(pred, dest); + RefReleaseInitialOp::create(builder, pred, dest); return success(); } @@ -4326,12 +4326,12 @@ ParseResult FIRStmtParser::parsePropAssign() { if (lhsType != rhsType) { // If the lhs is anyref, and the rhs is a ClassType, insert a cast. if (isa(lhsType) && isa(rhsType)) - rhs = builder.create(rhs); + rhs = ObjectAnyRefCastOp::create(builder, rhs); else return emitError(loc, "cannot propassign non-equivalent type ") << rhsType << " to " << lhsType; } - builder.create(lhs, rhs); + PropAssignOp::create(builder, lhs, rhs); return success(); } @@ -4419,7 +4419,8 @@ ParseResult FIRStmtParser::parseLayerBlockOrGroup(unsigned indent) { nestedLayers.push_back(FlatSymbolRefAttr::get(builder.getContext(), id)); } - auto layerBlockOp = builder.create( + auto layerBlockOp = LayerBlockOp::create( + builder, SymbolRefAttr::get(builder.getContext(), rootLayer, nestedLayers)); layerBlockOp->getRegion(0).push_back(new Block()); @@ -4509,8 +4510,8 @@ ParseResult FIRStmtParser::parseInstance() { SmallVector portAnnotations(modulePorts.size(), annotations); hw::InnerSymAttr sym = {}; - auto result = builder.create( - referencedModule, id, NameKindEnum::InterestingName, + auto result = InstanceOp::create( + builder, referencedModule, id, NameKindEnum::InterestingName, annotations.getValue(), portAnnotations, false, false, sym); // Since we are implicitly unbundling the instance results, we need to keep @@ -4609,8 +4610,8 @@ ParseResult FIRStmtParser::parseInstanceChoice() { // Create an instance choice op. StringAttr sym; - auto result = builder.create( - defaultModule, caseModules, id, NameKindEnum::InterestingName, + auto result = InstanceChoiceOp::create( + builder, defaultModule, caseModules, id, NameKindEnum::InterestingName, annotations.getValue(), portAnnotations, sym); // Un-bundle the ports, identically to the regular instance operation. @@ -4668,7 +4669,7 @@ ParseResult FIRStmtParser::parseObject() { return emitError(startTok.getLoc(), "use of undefined class name '" + className + "' in object"); auto referencedClass = lookup->getSecond(); - auto result = builder.create(referencedClass, id); + auto result = ObjectOp::create(builder, referencedClass, id); return moduleContext.addSymbolEntry(id, result, startTok.getLoc()); } @@ -4698,8 +4699,8 @@ ParseResult FIRStmtParser::parseCombMem() { auto annotations = getConstants().emptyArrayAttr; StringAttr sym = {}; - auto result = builder.create( - vectorType.getElementType(), vectorType.getNumElements(), id, + auto result = CombMemOp::create( + builder, vectorType.getElementType(), vectorType.getNumElements(), id, NameKindEnum::InterestingName, annotations, sym); return moduleContext.addSymbolEntry(id, result, startTok.getLoc()); } @@ -4741,9 +4742,9 @@ ParseResult FIRStmtParser::parseSeqMem() { auto annotations = getConstants().emptyArrayAttr; StringAttr sym = {}; - auto result = builder.create( - vectorType.getElementType(), vectorType.getNumElements(), ruw, id, - NameKindEnum::InterestingName, annotations, sym); + auto result = SeqMemOp::create( + builder, vectorType.getElementType(), vectorType.getNumElements(), ruw, + id, NameKindEnum::InterestingName, annotations, sym); return moduleContext.addSymbolEntry(id, result, startTok.getLoc()); } @@ -4872,8 +4873,8 @@ ParseResult FIRStmtParser::parseMem(unsigned memIndent) { locationProcessor.setLoc(startTok.getLoc()); - auto result = builder.create( - resultTypes, readLatency, writeLatency, depth, ruw, + auto result = MemOp::create( + builder, resultTypes, readLatency, writeLatency, depth, ruw, builder.getArrayAttr(resultNames), id, NameKindEnum::InterestingName, annotations, builder.getArrayAttr(resultAnnotations), hw::InnerSymAttr(), MemoryInitAttr(), StringAttr()); @@ -4931,8 +4932,8 @@ ParseResult FIRStmtParser::parseNode() { auto annotations = getConstants().emptyArrayAttr; StringAttr sym = {}; - auto result = builder.create( - initializer, id, NameKindEnum::InterestingName, annotations, sym); + auto result = NodeOp::create(builder, initializer, id, + NameKindEnum::InterestingName, annotations, sym); return moduleContext.addSymbolEntry(id, result.getResult(), startTok.getLoc()); } @@ -4963,7 +4964,7 @@ ParseResult FIRStmtParser::parseWire() { ? NameKindEnum::DroppableName : NameKindEnum::InterestingName; - auto result = builder.create(type, id, namekind, annotations, sym); + auto result = WireOp::create(builder, type, id, namekind, annotations, sym); return moduleContext.addSymbolEntry(id, result.getResult(), startTok.getLoc()); } @@ -5063,14 +5064,12 @@ ParseResult FIRStmtParser::parseRegister(unsigned regIndent) { StringAttr sym = {}; if (resetSignal) result = - builder - .create(type, clock, resetSignal, resetValue, id, - NameKindEnum::InterestingName, annotations, sym) + RegResetOp::create(builder, type, clock, resetSignal, resetValue, id, + NameKindEnum::InterestingName, annotations, sym) .getResult(); else - result = builder - .create(type, clock, id, NameKindEnum::InterestingName, - annotations, sym) + result = RegOp::create(builder, type, clock, id, + NameKindEnum::InterestingName, annotations, sym) .getResult(); return moduleContext.addSymbolEntry(id, result, startTok.getLoc()); } @@ -5105,10 +5104,9 @@ ParseResult FIRStmtParser::parseRegisterWithReset() { locationProcessor.setLoc(startTok.getLoc()); auto result = - builder - .create(type, clock, resetSignal, resetValue, id, - NameKindEnum::InterestingName, - getConstants().emptyArrayAttr, StringAttr{}) + RegResetOp::create(builder, type, clock, resetSignal, resetValue, id, + NameKindEnum::InterestingName, + getConstants().emptyArrayAttr, StringAttr{}) .getResult(); return moduleContext.addSymbolEntry(id, result, startTok.getLoc()); @@ -5162,7 +5160,7 @@ ParseResult FIRStmtParser::parseContract(unsigned blockIndent) { // Add block arguments for each result and declare their names in a subscope // for the contract body. - auto contract = builder.create(types, values); + auto contract = ContractOp::create(builder, types, values); auto &block = contract.getBody().emplaceBlock(); // Parse the contract body. @@ -5642,7 +5640,7 @@ ParseResult FIRCircuitParser::parseClass(CircuitOp circuit, unsigned indent) { // build it auto builder = circuit.getBodyBuilder(); - auto classOp = builder.create(info.getLoc(), name, portList); + auto classOp = ClassOp::create(builder, info.getLoc(), name, portList); classOp.setPrivate(); deferredModules.emplace_back( DeferredModuleToParse{classOp, portLocs, getLexer().getCursor(), indent}); @@ -5680,7 +5678,7 @@ ParseResult FIRCircuitParser::parseExtClass(CircuitOp circuit, // Build it auto builder = circuit.getBodyBuilder(); - auto extClassOp = builder.create(info.getLoc(), name, portList); + auto extClassOp = ExtClassOp::create(builder, info.getLoc(), name, portList); // Stash the class name -> op in the constants, so we can resolve Inst types. getConstants().classMap[name.getValue()] = extClassOp; @@ -5736,9 +5734,9 @@ ParseResult FIRCircuitParser::parseExtModule(CircuitOp circuit, : Convention::Internal; auto conventionAttr = ConventionAttr::get(getContext(), convention); auto annotations = ArrayAttr::get(getContext(), {}); - auto extModuleOp = builder.create( - info.getLoc(), name, conventionAttr, portList, knownLayers, defName, - annotations, parameters, internalPaths, enabledLayers); + auto extModuleOp = FExtModuleOp::create( + builder, info.getLoc(), name, conventionAttr, portList, knownLayers, + defName, annotations, parameters, internalPaths, enabledLayers); auto visibility = isMainModule ? SymbolTable::Visibility::Public : SymbolTable::Visibility::Private; SymbolTable::setSymbolVisibility(extModuleOp, visibility); @@ -5774,9 +5772,8 @@ ParseResult FIRCircuitParser::parseIntModule(CircuitOp circuit, ArrayAttr annotations = getConstants().emptyArrayAttr; auto builder = circuit.getBodyBuilder(); - builder - .create(info.getLoc(), name, portList, intName, annotations, - parameters, internalPaths, enabledLayers) + FIntModuleOp::create(builder, info.getLoc(), name, portList, intName, + annotations, parameters, internalPaths, enabledLayers) .setPrivate(); return success(); } @@ -5825,8 +5822,8 @@ ParseResult FIRCircuitParser::parseModule(CircuitOp circuit, bool isPublic, auto conventionAttr = ConventionAttr::get(getContext(), convention); auto builder = circuit.getBodyBuilder(); auto moduleOp = - builder.create(info.getLoc(), name, conventionAttr, portList, - annotations, enabledLayers); + FModuleOp::create(builder, info.getLoc(), name, conventionAttr, portList, + annotations, enabledLayers); auto visibility = isPublic ? SymbolTable::Visibility::Public : SymbolTable::Visibility::Private; @@ -5905,8 +5902,8 @@ ParseResult FIRCircuitParser::parseFormalLike(CircuitOp circuit, } } - builder.create(info.getLoc(), id, moduleName, - params.getDictionary(getContext())); + Op::create(builder, info.getLoc(), id, moduleName, + params.getDictionary(getContext())); return success(); } @@ -6006,7 +6003,7 @@ ParseResult FIRCircuitParser::parseOptionDecl(CircuitOp circuit) { return failure(); auto builder = OpBuilder::atBlockEnd(circuit.getBodyBlock()); - auto optionOp = builder.create(info.getLoc(), id); + auto optionOp = OptionOp::create(builder, info.getLoc(), id); auto *block = new Block; optionOp.getBody().push_back(block); builder.setInsertionPointToEnd(block); @@ -6024,7 +6021,7 @@ ParseResult FIRCircuitParser::parseOptionDecl(CircuitOp circuit) { return emitError(loc) << "duplicate option case definition '" << id << "'"; - builder.create(caseInfo.getLoc(), id); + OptionCaseOp::create(builder, caseInfo.getLoc(), id); } return success(); @@ -6075,7 +6072,8 @@ ParseResult FIRCircuitParser::parseLayer(CircuitOp circuit) { return failure(); auto builder = OpBuilder::atBlockEnd(block); // Create the layer definition and give it an empty block. - auto layerOp = builder.create(info.getLoc(), id, *layerConvention); + auto layerOp = + LayerOp::create(builder, info.getLoc(), id, *layerConvention); layerOp->getRegion(0).push_back(new Block()); if (outputDir) layerOp->setAttr("output_file", outputDir); @@ -6217,7 +6215,7 @@ ParseResult FIRCircuitParser::parseCircuit( // Create the top-level circuit op in the MLIR module. OpBuilder b(mlirModule.getBodyRegion()); - auto circuit = b.create(info.getLoc(), name); + auto circuit = CircuitOp::create(b, info.getLoc(), name); // A timer to get execution time of annotation parsing. auto parseAnnotationTimer = ts.nest("Parse annotations"); diff --git a/lib/Dialect/FIRRTL/Transforms/AddSeqMemPorts.cpp b/lib/Dialect/FIRRTL/Transforms/AddSeqMemPorts.cpp index 7bc4765046..a4d0bf669b 100644 --- a/lib/Dialect/FIRRTL/Transforms/AddSeqMemPorts.cpp +++ b/lib/Dialect/FIRRTL/Transforms/AddSeqMemPorts.cpp @@ -305,8 +305,8 @@ LogicalResult AddSeqMemPortsPass::processModule(FModuleOp moduleOp) { if (it != invalids.end()) return it->getSecond(); return invalids - .insert({type, - builder.create(builder.getUnknownLoc(), type)}) + .insert({type, InvalidValueOp::create(builder, builder.getUnknownLoc(), + type)}) .first->getSecond(); }; @@ -325,15 +325,15 @@ LogicalResult AddSeqMemPortsPass::processModule(FModuleOp moduleOp) { if (port.direction == Direction::In) std::swap(modulePort, instPort); auto connectOp = - builder.create(port.loc, modulePort, instPort); + MatchingConnectOp::create(builder, port.loc, modulePort, instPort); instToInsertionPoint[instOp] = builder.saveInsertionPoint(); // If the connect was created inside a WhenOp, then the port needs to be // invalidated to make a legal circuit. if (port.direction == Direction::Out && connectOp->getParentOfType()) { builder.setInsertionPointToStart(moduleOp.getBodyBlock()); - builder.create(port.loc, modulePort, - getOrCreateInvalid(port.type)); + MatchingConnectOp::create(builder, port.loc, modulePort, + getOrCreateInvalid(port.type)); } } return success(); @@ -379,7 +379,7 @@ void AddSeqMemPortsPass::createOutputFile(igraph::ModuleOpInterface moduleOp) { auto loc = builder.getUnknownLoc(); // Put the information in a verbatim operation. - builder.create(loc, outputFile, [&] { + emit::FileOp::create(builder, loc, outputFile, [&] { for (auto instancePath : instancePaths) { // Note: Reverse instancepath to construct the NLA. SmallVector path(llvm::reverse(instancePath)); @@ -405,8 +405,8 @@ void AddSeqMemPortsPass::createOutputFile(igraph::ModuleOpInterface moduleOp) { os << "\n"; } - builder.create(loc, buffer, ValueRange{}, - builder.getArrayAttr(params)); + sv::VerbatimOp::create(builder, loc, buffer, ValueRange{}, + builder.getArrayAttr(params)); }); anythingChanged = true; } @@ -508,8 +508,8 @@ void AddSeqMemPortsPass::runOnOperation() { auto value = inst.getResult(firstResult + i); auto type = value.getType(); auto attr = getIntZerosAttr(type); - auto zero = builder.create(portInfo.loc, type, attr); - builder.create(portInfo.loc, value, zero); + auto zero = ConstantOp::create(builder, portInfo.loc, type, attr); + MatchingConnectOp::create(builder, portInfo.loc, value, zero); } } } diff --git a/lib/Dialect/FIRRTL/Transforms/BlackBoxReader.cpp b/lib/Dialect/FIRRTL/Transforms/BlackBoxReader.cpp index ef8c46918e..c835e5cecf 100644 --- a/lib/Dialect/FIRRTL/Transforms/BlackBoxReader.cpp +++ b/lib/Dialect/FIRRTL/Transforms/BlackBoxReader.cpp @@ -245,10 +245,10 @@ void BlackBoxReaderPass::runOnOperation() { auto fileName = ns.newName("blackbox_" + verilogName.getValue()); - auto fileOp = builder.create( - loc, annotationInfo.outputFileAttr.getFilename(), fileName, + auto fileOp = emit::FileOp::create( + builder, loc, annotationInfo.outputFileAttr.getFilename(), fileName, [&, text = annotationInfo.inlineText] { - builder.create(loc, text); + emit::VerbatimOp::create(builder, loc, text); }); if (!annotationInfo.outputFileAttr.getExcludeFromFilelist().getValue()) diff --git a/lib/Dialect/FIRRTL/Transforms/CreateCompanionAssume.cpp b/lib/Dialect/FIRRTL/Transforms/CreateCompanionAssume.cpp index 1bc482fc29..67eca4244b 100644 --- a/lib/Dialect/FIRRTL/Transforms/CreateCompanionAssume.cpp +++ b/lib/Dialect/FIRRTL/Transforms/CreateCompanionAssume.cpp @@ -49,15 +49,16 @@ struct CreateCompanionAssumePass // Copy messages once we confirmed that it works well with UNR tools. if (isUnrOnlyAssert) // If UNROnly, use UnclockedAssumeIntrinsicOp. - assume = builder.create( - assertOp.getLoc(), assertOp.getPredicate(), assertOp.getEnable(), - emptyMessage, ValueRange{}, assertOp.getName()); + assume = firrtl::UnclockedAssumeIntrinsicOp::create( + builder, assertOp.getLoc(), assertOp.getPredicate(), + assertOp.getEnable(), emptyMessage, ValueRange{}, + assertOp.getName()); else // Otherwise use concurrent assume. - assume = builder.create( - assertOp.getLoc(), assertOp.getClock(), assertOp.getPredicate(), - assertOp.getEnable(), emptyMessage, ValueRange{}, - assertOp.getName(), + assume = firrtl::AssumeOp::create( + builder, assertOp.getLoc(), assertOp.getClock(), + assertOp.getPredicate(), assertOp.getEnable(), emptyMessage, + ValueRange{}, assertOp.getName(), /*isConcurrent=*/true); // Add a guard "USE_PROPERTY_AS_CONSTRAINT" to companion assumes. diff --git a/lib/Dialect/FIRRTL/Transforms/CreateSiFiveMetadata.cpp b/lib/Dialect/FIRRTL/Transforms/CreateSiFiveMetadata.cpp index 1f97522e92..aa0d42731a 100644 --- a/lib/Dialect/FIRRTL/Transforms/CreateSiFiveMetadata.cpp +++ b/lib/Dialect/FIRRTL/Transforms/CreateSiFiveMetadata.cpp @@ -73,7 +73,7 @@ struct ObjectModelIR { } // Create the path operation. - return builderOM.create(kind, id); + return PathOp::create(builderOM, kind, id); } void createMemorySchema() { @@ -92,8 +92,8 @@ struct ObjectModelIR { }; StringRef extraPortFields[3] = {"name", "direction", "width"}; - extraPortsClass = builderOM.create( - "ExtraPortsMemorySchema", extraPortFields, extraPortsType); + extraPortsClass = ClassOp::create(builderOM, "ExtraPortsMemorySchema", + extraPortFields, extraPortsType); mlir::Type classFieldTypes[13] = { StringType::get(context), @@ -113,14 +113,14 @@ struct ObjectModelIR { ListType::get(context, cast(StringType::get(context))), }; - memorySchemaClass = builderOM.create( - "MemorySchema", memoryParamNames, classFieldTypes); + memorySchemaClass = ClassOp::create(builderOM, "MemorySchema", + memoryParamNames, classFieldTypes); // Now create the class that will instantiate metadata class with all the // memories of the circt. SmallVector mports; - memoryMetadataClass = builderOM.create( - builderOM.getStringAttr("MemoryMetadata"), mports); + memoryMetadataClass = ClassOp::create( + builderOM, builderOM.getStringAttr("MemoryMetadata"), mports); } void createRetimeModulesSchema() { @@ -128,12 +128,13 @@ struct ObjectModelIR { auto builderOM = mlir::ImplicitLocOpBuilder::atBlockEnd( unknownLoc, circtOp.getBodyBlock()); Type classFieldTypes[] = {StringType::get(context)}; - retimeModulesSchemaClass = builderOM.create( - "RetimeModulesSchema", retimeModulesParamNames, classFieldTypes); + retimeModulesSchemaClass = + ClassOp::create(builderOM, "RetimeModulesSchema", + retimeModulesParamNames, classFieldTypes); SmallVector mports; - retimeModulesMetadataClass = builderOM.create( - builderOM.getStringAttr("RetimeModulesMetadata"), mports); + retimeModulesMetadataClass = ClassOp::create( + builderOM, builderOM.getStringAttr("RetimeModulesMetadata"), mports); } void addRetimeModule(FModuleLike module) { @@ -144,12 +145,12 @@ struct ObjectModelIR { // Create the path operation. auto modEntry = - builderOM.create(module.getModuleNameAttr()); - auto object = builderOM.create(retimeModulesSchemaClass, - module.getModuleNameAttr()); + StringConstantOp::create(builderOM, module.getModuleNameAttr()); + auto object = ObjectOp::create(builderOM, retimeModulesSchemaClass, + module.getModuleNameAttr()); - auto inPort = builderOM.create(object, 0); - builderOM.create(inPort, modEntry); + auto inPort = ObjectSubfieldOp::create(builderOM, object, 0); + PropAssignOp::create(builderOM, inPort, modEntry); auto portIndex = retimeModulesMetadataClass.getNumPorts(); SmallVector> newPorts = { {portIndex, @@ -158,7 +159,7 @@ struct ObjectModelIR { retimeModulesMetadataClass.insertPorts(newPorts); auto blockarg = retimeModulesMetadataClass.getBodyBlock()->addArgument( object.getType(), module->getLoc()); - builderOM.create(blockarg, object); + PropAssignOp::create(builderOM, blockarg, object); } void addBlackBoxModulesSchema() { @@ -169,11 +170,11 @@ struct ObjectModelIR { StringType::get(context), BoolType::get(context), ListType::get(context, cast(StringType::get(context)))}; blackBoxModulesSchemaClass = - builderOM.create("SitestBlackBoxModulesSchema", - blackBoxModulesParamNames, classFieldTypes); + ClassOp::create(builderOM, "SitestBlackBoxModulesSchema", + blackBoxModulesParamNames, classFieldTypes); SmallVector mports; - blackBoxMetadataClass = builderOM.create( - builderOM.getStringAttr("SitestBlackBoxMetadata"), mports); + blackBoxMetadataClass = ClassOp::create( + builderOM, builderOM.getStringAttr("SitestBlackBoxMetadata"), mports); } void addBlackBoxModule(FExtModuleOp module, bool inDut, @@ -185,8 +186,9 @@ struct ObjectModelIR { return; auto builderOM = mlir::ImplicitLocOpBuilder::atBlockEnd( module.getLoc(), blackBoxMetadataClass.getBodyBlock()); - auto modEntry = builderOM.create(module.getDefnameAttr()); - auto inDutAttr = builderOM.create(inDut); + auto modEntry = + StringConstantOp::create(builderOM, module.getDefnameAttr()); + auto inDutAttr = BoolConstantOp::create(builderOM, inDut); SmallVector libValues; for (StringRef libName : libraries) { @@ -194,28 +196,29 @@ struct ObjectModelIR { if (libName == defName) { libNameAttr = modEntry; } else { - libNameAttr = builderOM.create( - builderOM.getStringAttr(libName)); + libNameAttr = StringConstantOp::create( + builderOM, builderOM.getStringAttr(libName)); } libValues.push_back(libNameAttr); } - auto blackBoxResourcesList = builderOM.create( + auto blackBoxResourcesList = ListCreateOp::create( + builderOM, ListType::get( builderOM.getContext(), cast(StringType::get(builderOM.getContext()))), libValues); - auto object = builderOM.create(blackBoxModulesSchemaClass, - module.getModuleNameAttr()); + auto object = ObjectOp::create(builderOM, blackBoxModulesSchemaClass, + module.getModuleNameAttr()); - auto inPortModuleName = builderOM.create(object, 0); - builderOM.create(inPortModuleName, modEntry); - auto inPortInDut = builderOM.create(object, 2); - builderOM.create(inPortInDut, inDutAttr); + auto inPortModuleName = ObjectSubfieldOp::create(builderOM, object, 0); + PropAssignOp::create(builderOM, inPortModuleName, modEntry); + auto inPortInDut = ObjectSubfieldOp::create(builderOM, object, 2); + PropAssignOp::create(builderOM, inPortInDut, inDutAttr); auto inPortBlackBoxResources = - builderOM.create(object, 4); - builderOM.create(inPortBlackBoxResources, - blackBoxResourcesList); + ObjectSubfieldOp::create(builderOM, object, 4); + PropAssignOp::create(builderOM, inPortBlackBoxResources, + blackBoxResourcesList); auto portIndex = blackBoxMetadataClass.getNumPorts(); SmallVector> newPorts = { {portIndex, @@ -224,7 +227,7 @@ struct ObjectModelIR { blackBoxMetadataClass.insertPorts(newPorts); auto blockarg = blackBoxMetadataClass.getBodyBlock()->addArgument( object.getType(), module->getLoc()); - builderOM.create(blockarg, object); + PropAssignOp::create(builderOM, blockarg, object); } void addMemory(FMemModuleOp mem) { @@ -234,11 +237,11 @@ struct ObjectModelIR { mem.getLoc(), memoryMetadataClass.getBodyBlock()); auto createConstField = [&](Attribute constVal) -> Value { if (auto boolConstant = dyn_cast_or_null(constVal)) - return builderOM.create(boolConstant); + return BoolConstantOp::create(builderOM, boolConstant); if (auto intConstant = dyn_cast_or_null(constVal)) - return builderOM.create(intConstant); + return FIntegerConstantOp::create(builderOM, intConstant); if (auto strConstant = dyn_cast_or_null(constVal)) - return builderOM.create(strConstant); + return StringConstantOp::create(builderOM, strConstant); return {}; }; auto nlaBuilder = OpBuilder::atBlockBegin(circtOp.getBodyBlock()); @@ -261,8 +264,8 @@ struct ObjectModelIR { for (auto memPath : memPaths) { { igraph::InstanceOpInterface finalInst = memPath.leaf(); - finalInstanceNames.emplace_back(builderOM.create( - finalInst.getInstanceNameAttr())); + finalInstanceNames.emplace_back(StringConstantOp::create( + builderOM, finalInst.getInstanceNameAttr())); } SmallVector namepath; bool foundDut = false; @@ -293,8 +296,8 @@ struct ObjectModelIR { PathOp pathRef; if (!namepath.empty()) { // This is a path that is in the design. - auto nla = nlaBuilder.create( - mem->getLoc(), + auto nla = hw::HierPathOp::create( + nlaBuilder, mem->getLoc(), nlaBuilder.getStringAttr(circtNamespace.newName("memNLA")), nlaBuilder.getArrayAttr(namepath)); nla.setVisibility(SymbolTable::Visibility::Private); @@ -310,15 +313,17 @@ struct ObjectModelIR { memoryHierPaths.push_back(pathRef); } } - auto finalInstNamesList = builderOM.create( + auto finalInstNamesList = ListCreateOp::create( + builderOM, ListType::get(context, cast(StringType::get(context))), finalInstanceNames); - auto hierpaths = builderOM.create( + auto hierpaths = ListCreateOp::create( + builderOM, ListType::get(context, cast(PathType::get(context))), memoryHierPaths); SmallVector memFields; - auto object = builderOM.create(memorySchemaClass, mem.getName()); + auto object = ObjectOp::create(builderOM, memorySchemaClass, mem.getName()); SmallVector extraPortsList; ClassType extraPortsType; for (auto attr : mem.getExtraPortsAttr()) { @@ -328,18 +333,18 @@ struct ObjectModelIR { auto direction = createConstField(port.getAs("direction")); auto width = createConstField(port.getAs("width")); auto extraPortsObj = - builderOM.create(extraPortsClass, "extraPorts"); + ObjectOp::create(builderOM, extraPortsClass, "extraPorts"); extraPortsType = extraPortsObj.getType(); - auto inPort = builderOM.create(extraPortsObj, 0); - builderOM.create(inPort, portName); - inPort = builderOM.create(extraPortsObj, 2); - builderOM.create(inPort, direction); - inPort = builderOM.create(extraPortsObj, 4); - builderOM.create(inPort, width); + auto inPort = ObjectSubfieldOp::create(builderOM, extraPortsObj, 0); + PropAssignOp::create(builderOM, inPort, portName); + inPort = ObjectSubfieldOp::create(builderOM, extraPortsObj, 2); + PropAssignOp::create(builderOM, inPort, direction); + inPort = ObjectSubfieldOp::create(builderOM, extraPortsObj, 4); + PropAssignOp::create(builderOM, inPort, width); extraPortsList.push_back(extraPortsObj); } - auto extraPorts = builderOM.create( - memorySchemaClass.getPortType(22), extraPortsList); + auto extraPorts = ListCreateOp::create( + builderOM, memorySchemaClass.getPortType(22), extraPortsList); for (auto field : llvm::enumerate(memoryParamNames)) { auto propVal = createConstField( llvm::StringSwitch(field.value()) @@ -371,8 +376,8 @@ struct ObjectModelIR { // The following `2*index` translates the index to the memory schema input // port number. auto inPort = - builderOM.create(object, 2 * field.index()); - builderOM.create(inPort, propVal); + ObjectSubfieldOp::create(builderOM, object, 2 * field.index()); + PropAssignOp::create(builderOM, inPort, propVal); } auto portIndex = memoryMetadataClass.getNumPorts(); SmallVector> newPorts = { @@ -381,7 +386,7 @@ struct ObjectModelIR { memoryMetadataClass.insertPorts(newPorts); auto blockarg = memoryMetadataClass.getBodyBlock()->addArgument( object.getType(), mem->getLoc()); - builderOM.create(blockarg, object); + PropAssignOp::create(builderOM, blockarg, object); } ObjectOp instantiateSifiveMetadata(FModuleOp topMod) { @@ -391,8 +396,8 @@ struct ObjectModelIR { auto builder = mlir::ImplicitLocOpBuilder::atBlockEnd( mlir::UnknownLoc::get(circtOp->getContext()), circtOp.getBodyBlock()); SmallVector mports; - auto sifiveMetadataClass = builder.create( - builder.getStringAttr("SiFive_Metadata"), mports); + auto sifiveMetadataClass = ClassOp::create( + builder, builder.getStringAttr("SiFive_Metadata"), mports); builder.setInsertionPointToStart(sifiveMetadataClass.getBodyBlock()); auto addPort = [&](Value obj, StringRef fieldName) { @@ -404,25 +409,23 @@ struct ObjectModelIR { sifiveMetadataClass.insertPorts(newPorts); auto blockarg = sifiveMetadataClass.getBodyBlock()->addArgument( obj.getType(), topMod->getLoc()); - builder.create(blockarg, obj); + PropAssignOp::create(builder, blockarg, obj); }; if (blackBoxMetadataClass) - addPort( - builder.create(blackBoxMetadataClass, - builder.getStringAttr("blackbox_metadata")), - "blackbox"); + addPort(ObjectOp::create(builder, blackBoxMetadataClass, + builder.getStringAttr("blackbox_metadata")), + "blackbox"); if (memoryMetadataClass) - addPort( - builder.create(memoryMetadataClass, - builder.getStringAttr("memory_metadata")), - "memory"); + addPort(ObjectOp::create(builder, memoryMetadataClass, + builder.getStringAttr("memory_metadata")), + "memory"); if (retimeModulesMetadataClass) - addPort(builder.create( - retimeModulesMetadataClass, - builder.getStringAttr("retime_modules_metadata")), - "retime"); + addPort( + ObjectOp::create(builder, retimeModulesMetadataClass, + builder.getStringAttr("retime_modules_metadata")), + "retime"); if (instanceInfo.hasDut()) { auto dutMod = instanceInfo.getDut(); @@ -447,8 +450,8 @@ struct ObjectModelIR { // actual DUT module!!). auto leafInst = dutPath.leaf(); auto nlaBuilder = OpBuilder::atBlockBegin(circtOp.getBodyBlock()); - auto nla = nlaBuilder.create( - dutMod->getLoc(), + auto nla = hw::HierPathOp::create( + nlaBuilder, dutMod->getLoc(), nlaBuilder.getStringAttr(circtNamespace.newName("dutNLA")), nlaBuilder.getArrayAttr(namepath)); nla.setVisibility(SymbolTable::Visibility::Private); @@ -456,15 +459,16 @@ struct ObjectModelIR { pathOpsToDut.emplace_back(createPathRef(leafInst, nla, builder)); } // Create the list of paths op and add it as a field of the class. - auto pathList = builder.create( + auto pathList = ListCreateOp::create( + builder, ListType::get(context, cast(PathType::get(context))), pathOpsToDut); addPort(pathList, "dutModulePath"); } builder.setInsertionPointToEnd(topMod.getBodyBlock()); - return builder.create(sifiveMetadataClass, - builder.getStringAttr("sifive_metadata")); + return ObjectOp::create(builder, sifiveMetadataClass, + builder.getStringAttr("sifive_metadata")); } /// Get the cached namespace for a module. @@ -699,9 +703,9 @@ CreateSiFiveMetadataPass::emitMemoryMetadata(ObjectModelIR &omir) { { SmallString<128> seqMemsJsonPath(metadataDir); llvm::sys::path::append(seqMemsJsonPath, "seq_mems.json"); - builder.create(seqMemsJsonPath, [&] { - builder.create(dutJsonBuffer, ValueRange{}, - builder.getArrayAttr(jsonSymbols)); + emit::FileOp::create(builder, seqMemsJsonPath, [&] { + sv::VerbatimOp::create(builder, dutJsonBuffer, ValueRange{}, + builder.getArrayAttr(jsonSymbols)); }); } @@ -714,9 +718,9 @@ CreateSiFiveMetadataPass::emitMemoryMetadata(ObjectModelIR &omir) { return failure(); } - builder.create(replSeqMemFile, [&] { - builder.create(seqMemConfStr, ValueRange{}, - builder.getArrayAttr(seqMemSymbols)); + emit::FileOp::create(builder, replSeqMemFile, [&] { + sv::VerbatimOp::create(builder, seqMemConfStr, ValueRange{}, + builder.getArrayAttr(seqMemSymbols)); }); } @@ -811,9 +815,9 @@ CreateSiFiveMetadataPass::emitRetimeModulesMetadata(ObjectModelIR &omir) { // Put the retime information in a verbatim operation. auto builder = ImplicitLocOpBuilder::atBlockEnd(UnknownLoc::get(context), circuitOp.getBodyBlock()); - builder.create(filename, [&] { - builder.create(builder.getStringAttr(buffer), ValueRange{}, - builder.getArrayAttr(symbols)); + emit::FileOp::create(builder, filename, [&] { + sv::VerbatimOp::create(builder, builder.getStringAttr(buffer), ValueRange{}, + builder.getArrayAttr(symbols)); }); return success(); } @@ -916,8 +920,8 @@ CreateSiFiveMetadataPass::emitSitestBlackboxMetadata(ObjectModelIR &omir) { auto builder = ImplicitLocOpBuilder::atBlockEnd(UnknownLoc::get(context), circuitOp.getBodyBlock()); - builder.create(filename, [&] { - builder.create(StringAttr::get(context, buffer)); + emit::FileOp::create(builder, filename, [&] { + emit::VerbatimOp::create(builder, StringAttr::get(context, buffer)); }); }; @@ -961,8 +965,9 @@ void CreateSiFiveMetadataPass::runOnOperation() { topMod.insertPorts(ports); auto builderOM = mlir::ImplicitLocOpBuilder::atBlockEnd( topMod->getLoc(), topMod.getBodyBlock()); - auto objectCast = builderOM.create(objectOp); - builderOM.create(topMod.getArgument(portIndex), objectCast); + auto objectCast = ObjectAnyRefCastOp::create(builderOM, objectOp); + PropAssignOp::create(builderOM, topMod.getArgument(portIndex), + objectCast); } // This pass modifies the hierarchy, InstanceGraph is not preserved. diff --git a/lib/Dialect/FIRRTL/Transforms/Dedup.cpp b/lib/Dialect/FIRRTL/Transforms/Dedup.cpp index be35536315..35087814b5 100644 --- a/lib/Dialect/FIRRTL/Transforms/Dedup.cpp +++ b/lib/Dialect/FIRRTL/Transforms/Dedup.cpp @@ -1061,8 +1061,8 @@ private: // Check the NLA cache to see if we already have this NLA. auto &cacheEntry = nlaCache[arrayAttr]; if (!cacheEntry) { - auto nla = OpBuilder::atBlockBegin(nlaBlock).create( - loc, "nla", arrayAttr); + auto builder = OpBuilder::atBlockBegin(nlaBlock); + auto nla = hw::HierPathOp::create(builder, loc, "nla", arrayAttr); // Insert it into the symbol table to get a unique name. symbolTable.insert(nla); // Store it in the cache. @@ -1560,8 +1560,8 @@ void fixupConnect(ImplicitLocOpBuilder &builder, Value dst, Value src) { auto dstBundle = type_cast(dstType); auto srcBundle = type_cast(srcType); for (unsigned i = 0; i < dstBundle.getNumElements(); ++i) { - auto dstField = builder.create(dst, i); - auto srcField = builder.create(src, i); + auto dstField = SubfieldOp::create(builder, dst, i); + auto srcField = SubfieldOp::create(builder, src, i); if (dstBundle.getElement(i).isFlip) { std::swap(srcBundle, dstBundle); std::swap(srcField, dstField); @@ -1609,7 +1609,7 @@ void fixupAllModules(InstanceGraph &instanceGraph) { // If the type changed we transform it back to the old type with an // intermediate wire. auto wire = - builder.create(oldType, inst.getPortName(i)).getResult(); + WireOp::create(builder, oldType, inst.getPortName(i)).getResult(); result.replaceAllUsesWith(wire); result.setType(newType); if (inst.getPortDirection(i) == Direction::Out) diff --git a/lib/Dialect/FIRRTL/Transforms/EliminateWires.cpp b/lib/Dialect/FIRRTL/Transforms/EliminateWires.cpp index e016bc22ee..9f1d005e6a 100644 --- a/lib/Dialect/FIRRTL/Transforms/EliminateWires.cpp +++ b/lib/Dialect/FIRRTL/Transforms/EliminateWires.cpp @@ -83,9 +83,9 @@ void EliminateWiresPass::runOnOperation() { for (auto [wire, writer] : worklist) { mlir::ImplicitLocOpBuilder builder(wire->getLoc(), writer); - auto node = builder.create( - writer.getSrc(), wire.getName(), wire.getNameKind(), - wire.getAnnotations(), wire.getInnerSymAttr(), wire.getForceable()); + auto node = NodeOp::create(builder, writer.getSrc(), wire.getName(), + wire.getNameKind(), wire.getAnnotations(), + wire.getInnerSymAttr(), wire.getForceable()); wire.replaceAllUsesWith(node); wire.erase(); writer.erase(); diff --git a/lib/Dialect/FIRRTL/Transforms/ExpandWhens.cpp b/lib/Dialect/FIRRTL/Transforms/ExpandWhens.cpp index 80be9e6237..08fe63e4f3 100644 --- a/lib/Dialect/FIRRTL/Transforms/ExpandWhens.cpp +++ b/lib/Dialect/FIRRTL/Transforms/ExpandWhens.cpp @@ -288,7 +288,7 @@ public: newValue = b.createOrFold(fusedLoc, cond, whenTrue, whenFalse); else if (trueIsInvalid) newValue = whenFalse; - return b.create(loc, dest, newValue); + return ConnectOp::create(b, loc, dest, newValue); } void visitDecl(WireOp op) { declareSinks(op.getResult(), Flow::Duplex); } @@ -301,14 +301,14 @@ public: .template Case([&](BundleType bundle) { for (auto i : llvm::seq(0u, (unsigned)bundle.getNumElements())) { auto subfield = - builder.create(value.getLoc(), value, i); + SubfieldOp::create(builder, value.getLoc(), value, i); foreachSubelement(builder, subfield, fn); } }) .template Case([&](FVectorType vector) { for (auto i : llvm::seq((size_t)0, vector.getNumElements())) { auto subindex = - builder.create(value.getLoc(), value, i); + SubindexOp::create(builder, value.getLoc(), value, i); foreachSubelement(builder, subindex, fn); } }) @@ -320,7 +320,7 @@ public: // aggergate type, connect each ground type element. auto builder = OpBuilder(op->getBlock(), ++Block::iterator(op)); auto fn = [&](Value value) { - auto connect = builder.create(value.getLoc(), value, value); + auto connect = ConnectOp::create(builder, value.getLoc(), value, value); driverMap[getFieldRefFromValue(value)] = connect; }; foreachSubelement(builder, op.getResult(), fn); @@ -331,7 +331,7 @@ public: // aggergate type, connect each ground type element. auto builder = OpBuilder(op->getBlock(), ++Block::iterator(op)); auto fn = [&](Value value) { - auto connect = builder.create(value.getLoc(), value, value); + auto connect = ConnectOp::create(builder, value.getLoc(), value, value); driverMap[getFieldRefFromValue(value)] = connect; }; foreachSubelement(builder, op.getResult(), fn); diff --git a/lib/Dialect/FIRRTL/Transforms/ExtractInstances.cpp b/lib/Dialect/FIRRTL/Transforms/ExtractInstances.cpp index d78c573ef3..248fdbaad8 100644 --- a/lib/Dialect/FIRRTL/Transforms/ExtractInstances.cpp +++ b/lib/Dialect/FIRRTL/Transforms/ExtractInstances.cpp @@ -113,7 +113,7 @@ struct ExtractInstancesPass if (inserted) { auto builder = ImplicitLocOpBuilder::atBlockEnd( UnknownLoc::get(&getContext()), getOperation().getBodyBlock()); - it->second = builder.create(fileName); + it->second = emit::FileOp::create(builder, fileName); } return it->second; } @@ -658,7 +658,7 @@ void ExtractInstancesPass::extractInstances() { auto src = newParentInst.getResult(numParentPorts + portIdx); if (newPorts[portIdx].second.direction == Direction::In) std::swap(src, dst); - builder.create(dst, src); + MatchingConnectOp::create(builder, dst, src); } // Move the wiring prefix from the old to the new instance. We just look @@ -980,8 +980,8 @@ void ExtractInstancesPass::groupInstances() { } // Create the wrapper module. - auto wrapper = builder.create( - builder.getUnknownLoc(), wrapperModuleName, + auto wrapper = FModuleOp::create( + builder, builder.getUnknownLoc(), wrapperModuleName, ConventionAttr::get(builder.getContext(), Convention::Internal), ports); SymbolTable::setSymbolVisibility(wrapper, SymbolTable::Visibility::Private); @@ -989,9 +989,9 @@ void ExtractInstancesPass::groupInstances() { // extracted instances' ports with the corresponding wrapper module ports. // This will essentially disconnect the extracted instances. builder.setInsertionPointToStart(parent.getBodyBlock()); - auto wrapperInst = builder.create( - wrapper.getLoc(), wrapper, wrapperName, NameKindEnum::DroppableName, - ArrayRef{}, + auto wrapperInst = InstanceOp::create( + builder, wrapper.getLoc(), wrapper, wrapperName, + NameKindEnum::DroppableName, ArrayRef{}, /*portAnnotations=*/ArrayRef{}, /*lowerToBind=*/false, /*doNotPrint=*/false, hw::InnerSymAttr::get(wrapperInstName)); unsigned portIdx = 0; @@ -1011,7 +1011,7 @@ void ExtractInstancesPass::groupInstances() { Value src = wrapper.getArgument(portIdx); if (ports[portIdx].direction == Direction::Out) std::swap(dst, src); - builder.create(result.getLoc(), dst, src); + MatchingConnectOp::create(builder, result.getLoc(), dst, src); ++portIdx; } } @@ -1051,7 +1051,7 @@ void ExtractInstancesPass::createTraceFiles(ClassOp &sifiveMetadataClass) { obj.getType(), Direction::Out)); auto blockarg = classOp.getBodyBlock()->addArgument(obj.getType(), obj.getLoc()); - builderOM.create(blockarg, obj); + PropAssignOp::create(builderOM, blockarg, obj); } classOp.insertPorts(newPorts); }; @@ -1102,11 +1102,11 @@ void ExtractInstancesPass::createTraceFiles(ClassOp &sifiveMetadataClass) { // Create the entry for this extracted instance in the metadata class. auto builderOM = mlir::ImplicitLocOpBuilder::atBlockEnd( inst.getLoc(), extractMetadataClass.getBodyBlock()); - auto prefixName = builderOM.create(prefix); - auto object = builderOM.create(schemaClass, prefix); + auto prefixName = StringConstantOp::create(builderOM, prefix); + auto object = ObjectOp::create(builderOM, schemaClass, prefix); auto fPrefix = - builderOM.create(object, prefixNameFieldId); - builderOM.create(fPrefix, prefixName); + ObjectSubfieldOp::create(builderOM, object, prefixNameFieldId); + PropAssignOp::create(builderOM, fPrefix, prefixName); auto targetInstance = innerRefToInstances[path.front()]; SmallVector pathOpAttr(llvm::reverse(path)); @@ -1114,18 +1114,18 @@ void ExtractInstancesPass::createTraceFiles(ClassOp &sifiveMetadataClass) { ArrayAttr::get(circuitOp->getContext(), pathOpAttr)); auto pathOp = createPathRef(targetInstance, nla, builderOM); - auto fPath = builderOM.create(object, pathFieldId); - builderOM.create(fPath, pathOp); + auto fPath = ObjectSubfieldOp::create(builderOM, object, pathFieldId); + PropAssignOp::create(builderOM, fPath, pathOp); auto fFile = - builderOM.create(object, fileNameFieldId); - auto fileNameOp = - builderOM.create(builder.getStringAttr(fileName)); - builderOM.create(fFile, fileNameOp); + ObjectSubfieldOp::create(builderOM, object, fileNameFieldId); + auto fileNameOp = StringConstantOp::create( + builderOM, builder.getStringAttr(fileName)); + PropAssignOp::create(builderOM, fFile, fileNameOp); auto finstName = - builderOM.create(object, instNameFieldId); - auto instNameOp = builderOM.create(origInstName); - builderOM.create(finstName, instNameOp); + ObjectSubfieldOp::create(builderOM, object, instNameFieldId); + auto instNameOp = StringConstantOp::create(builderOM, origInstName); + PropAssignOp::create(builderOM, finstName, instNameOp); // Now add this to the output field of the class. classFields.emplace_back(object, prefix + "_field"); @@ -1158,8 +1158,8 @@ void ExtractInstancesPass::createTraceFiles(ClassOp &sifiveMetadataClass) { } // Put the information in a verbatim operation. - builder.create(builder.getUnknownLoc(), buffer, - ValueRange{}, builder.getArrayAttr(symbols)); + sv::VerbatimOp::create(builder, builder.getUnknownLoc(), buffer, + ValueRange{}, builder.getArrayAttr(symbols)); } if (!classFields.empty()) { addPortsToClass(classFields, extractMetadataClass); @@ -1169,8 +1169,8 @@ void ExtractInstancesPass::createTraceFiles(ClassOp &sifiveMetadataClass) { auto builderOM = mlir::ImplicitLocOpBuilder::atBlockEnd( sifiveMetadataClass->getLoc(), sifiveMetadataClass.getBodyBlock()); SmallVector> classFields = { - {builderOM.create( - extractMetadataClass, + {ObjectOp::create( + builderOM, extractMetadataClass, builderOM.getStringAttr("extract_instances_metadata")), "extractedInstances_field"}}; @@ -1182,7 +1182,7 @@ void ExtractInstancesPass::createTraceFiles(ClassOp &sifiveMetadataClass) { "expected the class to be instantiated by an object op"); builderOM.setInsertionPoint(metadataObj); auto newObj = - builderOM.create(sifiveMetadataClass, metadataObj.getName()); + ObjectOp::create(builderOM, sifiveMetadataClass, metadataObj.getName()); metadataObj->replaceAllUsesWith(newObj); metadataObj->remove(); } @@ -1202,11 +1202,11 @@ void ExtractInstancesPass::createSchema() { }; StringRef portFields[] = {"name", "path", "filename", "inst_name"}; - schemaClass = builderOM.create("ExtractInstancesSchema", portFields, - portsType); + schemaClass = ClassOp::create(builderOM, "ExtractInstancesSchema", portFields, + portsType); // Now create the class that will instantiate the schema objects. SmallVector mports; - extractMetadataClass = builderOM.create( - builderOM.getStringAttr("ExtractInstancesMetadata"), mports); + extractMetadataClass = ClassOp::create( + builderOM, builderOM.getStringAttr("ExtractInstancesMetadata"), mports); } diff --git a/lib/Dialect/FIRRTL/Transforms/FlattenMemory.cpp b/lib/Dialect/FIRRTL/Transforms/FlattenMemory.cpp index 17de46884d..2da67137e8 100644 --- a/lib/Dialect/FIRRTL/Transforms/FlattenMemory.cpp +++ b/lib/Dialect/FIRRTL/Transforms/FlattenMemory.cpp @@ -121,8 +121,8 @@ struct FlattenMemoryPass } // Create the new flattened memory. - auto flatMem = builder.create( - ports, memOp.getReadLatency(), memOp.getWriteLatency(), + auto flatMem = MemOp::create( + builder, ports, memOp.getReadLatency(), memOp.getWriteLatency(), memOp.getDepth(), memOp.getRuw(), builder.getArrayAttr(portNames), memOp.getNameAttr(), memOp.getNameKind(), memOp.getAnnotations(), memOp.getPortAnnotations(), memOp.getInnerSymAttr(), @@ -136,11 +136,10 @@ struct FlattenMemoryPass // memory with the wire. We will be reconstructing the original type // in the wire from the bitvector of the flattened memory. auto result = memOp.getResult(index); - auto wire = builder - .create(result.getType(), - (memOp.getName() + "_" + - memOp.getPortName(index).getValue()) - .str()) + auto wire = WireOp::create(builder, result.getType(), + (memOp.getName() + "_" + + memOp.getPortName(index).getValue()) + .str()) .getResult(); result.replaceAllUsesWith(wire); result = wire; @@ -149,9 +148,9 @@ struct FlattenMemoryPass for (size_t fieldIndex = 0, fend = rType.getNumElements(); fieldIndex != fend; ++fieldIndex) { auto name = rType.getElement(fieldIndex).name; - auto oldField = builder.create(result, fieldIndex); + auto oldField = SubfieldOp::create(builder, result, fieldIndex); FIRRTLBaseValue newField = - builder.create(newResult, fieldIndex); + SubfieldOp::create(builder, newResult, fieldIndex); // data and mask depend on the memory type which was split. They can // also go both directions, depending on the port direction. if (!(name == "data" || name == "mask" || name == "wdata" || @@ -174,7 +173,7 @@ struct FlattenMemoryPass // newFieldType is of smaller bits than old. if (getBitWidth(newFieldType) != *oldFieldBitWidth) newFieldType = UIntType::get(context, *oldFieldBitWidth); - realOldField = builder.create(newFieldType, oldField); + realOldField = BitCastOp::create(builder, newFieldType, oldField); // Mask bits require special handling, since some of the mask bits // need to be repeated, direct bitcasting wouldn't work. Depending // on the mask granularity, some mask bits will be repeated. diff --git a/lib/Dialect/FIRRTL/Transforms/GrandCentral.cpp b/lib/Dialect/FIRRTL/Transforms/GrandCentral.cpp index 535e25d648..3cae3fbb7d 100644 --- a/lib/Dialect/FIRRTL/Transforms/GrandCentral.cpp +++ b/lib/Dialect/FIRRTL/Transforms/GrandCentral.cpp @@ -1123,7 +1123,7 @@ parseAugmentedType(ApplyState &state, DictionaryAttr augmentedType, auto sinkType = source->getType(); if (auto baseSinkType = type_dyn_cast(sinkType)) sinkType = baseSinkType.getPassiveType(); - auto sink = builder.create(sinkType, name); + auto sink = WireOp::create(builder, sinkType, name); state.targetCaches.insertOp(sink); AnnotationSet annotations(context); annotations.addAnnotations( @@ -2111,7 +2111,7 @@ void GrandCentralPass::runOnOperation() { for (auto port : instance->getResults()) { builder.setInsertionPointAfterValue(port); auto wire = - builder.create(port.getLoc(), port.getType()); + WireOp::create(builder, port.getLoc(), port.getType()); port.replaceAllUsesWith(wire.getResult()); } i->erase(); @@ -2391,8 +2391,8 @@ void GrandCentralPass::runOnOperation() { // Generate gathered XMR's. for (auto xmrElem : xmrElems) { auto uloc = companionBuilder.getUnknownLoc(); - companionBuilder.create(uloc, xmrElem.str, xmrElem.val, - xmrElem.syms); + sv::VerbatimOp::create(companionBuilder, uloc, xmrElem.str, xmrElem.val, + xmrElem.syms); } numXMRs += xmrElems.size(); @@ -2401,7 +2401,7 @@ void GrandCentralPass::runOnOperation() { auto builder = OpBuilder::atBlockEnd(getOperation().getBodyBlock()); auto loc = getOperation().getLoc(); sv::InterfaceOp iface = - builder.create(loc, ifaceBuilder.iFaceName); + sv::InterfaceOp::create(builder, loc, ifaceBuilder.iFaceName); if (!topIface) topIface = iface; ++numInterfaces; @@ -2429,8 +2429,9 @@ void GrandCentralPass::runOnOperation() { auto description = elem.description; if (description) { - auto descriptionOp = builder.create( - uloc, ("// " + cleanupDescription(description.getValue()))); + auto descriptionOp = sv::VerbatimOp::create( + builder, uloc, + ("// " + cleanupDescription(description.getValue()))); // If we need to generate a YAML representation of this interface, // then add an attribute indicating that this `sv::VerbatimOp` is @@ -2440,8 +2441,8 @@ void GrandCentralPass::runOnOperation() { builder.getStringAttr("description")); } if (auto *str = std::get_if(&elem.elemType)) { - auto instanceOp = builder.create( - uloc, str->toStr(elem.elemName.getValue())); + auto instanceOp = sv::VerbatimOp::create( + builder, uloc, str->toStr(elem.elemName.getValue())); // If we need to generate a YAML representation of the interface, then // add attributes that describe what this `sv::VerbatimOp` is. @@ -2463,8 +2464,8 @@ void GrandCentralPass::runOnOperation() { } auto tpe = std::get(elem.elemType); - builder.create(uloc, elem.elemName.getValue(), - tpe); + sv::InterfaceSignalOp::create(builder, uloc, elem.elemName.getValue(), + tpe); } } @@ -2475,8 +2476,8 @@ void GrandCentralPass::runOnOperation() { // Instantiate the interface inside the companion. builder.setInsertionPointToStart(companionModule.getBodyBlock()); - builder.create( - getOperation().getLoc(), topIface.getInterfaceType(), + sv::InterfaceInstanceOp::create( + builder, getOperation().getLoc(), topIface.getInterfaceType(), companionIDMap.lookup(bundle.getID()).name, hw::InnerSymAttr::get(builder.getStringAttr(symbolName))); @@ -2550,8 +2551,8 @@ void GrandCentralPass::runOnOperation() { // Generate gathered XMR's. for (auto xmrElem : xmrElems) - viewBuilder.create(xmrElem.str, xmrElem.val, - xmrElem.syms); + sv::VerbatimOp::create(viewBuilder, xmrElem.str, xmrElem.val, + xmrElem.syms); numXMRs += xmrElems.size(); sv::InterfaceOp topIface; @@ -2562,7 +2563,7 @@ void GrandCentralPass::runOnOperation() { auto builder = OpBuilder::atBlockEnd(getOperation().getBodyBlock()); auto loc = getOperation().getLoc(); sv::InterfaceOp iface = - builder.create(loc, ifaceBuilder.iFaceName); + sv::InterfaceOp::create(builder, loc, ifaceBuilder.iFaceName); if (!topIface) topIface = iface; ++numInterfaces; @@ -2584,8 +2585,9 @@ void GrandCentralPass::runOnOperation() { auto description = elem.description; if (description) { - auto descriptionOp = builder.create( - uloc, ("// " + cleanupDescription(description.getValue()))); + auto descriptionOp = sv::VerbatimOp::create( + builder, uloc, + ("// " + cleanupDescription(description.getValue()))); // If we need to generate a YAML representation of this interface, // then add an attribute indicating that this `sv::VerbatimOp` is @@ -2595,8 +2597,8 @@ void GrandCentralPass::runOnOperation() { builder.getStringAttr("description")); } if (auto *str = std::get_if(&elem.elemType)) { - auto instanceOp = builder.create( - uloc, str->toStr(elem.elemName.getValue())); + auto instanceOp = sv::VerbatimOp::create( + builder, uloc, str->toStr(elem.elemName.getValue())); // If we need to generate a YAML representation of the interface, then // add attributes that describe what this `sv::VerbatimOp` is. @@ -2618,8 +2620,8 @@ void GrandCentralPass::runOnOperation() { } auto tpe = std::get(elem.elemType); - builder.create(uloc, elem.elemName.getValue(), - tpe); + sv::InterfaceSignalOp::create(builder, uloc, elem.elemName.getValue(), + tpe); } } @@ -2631,8 +2633,8 @@ void GrandCentralPass::runOnOperation() { // Instantiate the interface before the view and the XMR's we inserted // above. viewBuilder.setInsertionPoint(view); - viewBuilder.create( - topIface.getInterfaceType(), view.getName(), + sv::InterfaceInstanceOp::create( + viewBuilder, topIface.getInterfaceType(), view.getName(), hw::InnerSymAttr::get(builder.getStringAttr(symbolName))); view.erase(); @@ -2659,7 +2661,7 @@ void GrandCentralPass::emitHierarchyYamlFile( yamlize(yout, intfs, true, yamlContext); auto builder = OpBuilder::atBlockBegin(circuitOp.getBodyBlock()); - builder.create(builder.getUnknownLoc(), yamlString) + sv::VerbatimOp::create(builder, builder.getUnknownLoc(), yamlString) ->setAttr("output_file", hw::OutputFileAttr::getFromFilename( &getContext(), yamlPath, /*excludeFromFileList=*/true)); diff --git a/lib/Dialect/FIRRTL/Transforms/IMConstProp.cpp b/lib/Dialect/FIRRTL/Transforms/IMConstProp.cpp index 1fdcfc0cef..308b5a4bc9 100644 --- a/lib/Dialect/FIRRTL/Transforms/IMConstProp.cpp +++ b/lib/Dialect/FIRRTL/Transforms/IMConstProp.cpp @@ -976,7 +976,7 @@ void IMConstPropPass::rewriteModuleBody(FModuleOp module) { // Separate the constants we insert from the instructions we are folding and // processing. Leave these as-is until we're done. - auto cursor = builder.create(module.getLoc(), APSInt(1)); + auto cursor = firrtl::ConstantOp::create(builder, module.getLoc(), APSInt(1)); builder.setInsertionPoint(cursor); // Unique constants per pair, inserted at entry @@ -1002,7 +1002,7 @@ void IMConstPropPass::rewriteModuleBody(FModuleOp module) { "Attempting to materialize rwprobe of constant, shouldn't happen"); auto inner = getConst(constantValue, refType.getType(), loc); assert(inner); - cst = builder.create(loc, inner); + cst = RefSendOp::create(builder, loc, inner); } else cst = module->getDialect()->materializeConstant(builder, constantValue, type, loc); diff --git a/lib/Dialect/FIRRTL/Transforms/IMDeadCodeElim.cpp b/lib/Dialect/FIRRTL/Transforms/IMDeadCodeElim.cpp index 3b69955253..54ba0992fa 100644 --- a/lib/Dialect/FIRRTL/Transforms/IMDeadCodeElim.cpp +++ b/lib/Dialect/FIRRTL/Transforms/IMDeadCodeElim.cpp @@ -307,7 +307,7 @@ void IMDeadCodeElimPass::forwardConstantOutputPort(FModuleOp module) { assert(ports[index].isOutput() && "must be an output port"); // Replace the port with the constant. - result.replaceAllUsesWith(builder.create(constant)); + result.replaceAllUsesWith(ConstantOp::create(builder, constant)); } } } @@ -629,15 +629,15 @@ void IMDeadCodeElimPass::rewriteModuleSignature(FModuleOp module) { if (isAssumedDead(result)) { // If the result is dead, replace the result with an unrealized conversion // cast which works as a dummy placeholder. - auto wire = builder - .create( - ArrayRef{result.getType()}, ArrayRef{}) - ->getResult(0); + auto wire = + mlir::UnrealizedConversionCastOp::create( + builder, ArrayRef{result.getType()}, ArrayRef{}) + ->getResult(0); result.replaceAllUsesWith(wire); return; } - Value wire = builder.create(result.getType()).getResult(); + Value wire = WireOp::create(builder, result.getType()).getResult(); result.replaceAllUsesWith(wire); // If a module port is dead but its instance result is alive, the port // is used as a temporary wire so make sure that a replaced wire is @@ -698,7 +698,7 @@ void IMDeadCodeElimPass::rewriteModuleSignature(FModuleOp module) { // Ok, this port is used only within its defined module. So we can replace // the port with a wire. - auto wire = builder.create(argument.getType()).getResult(); + auto wire = WireOp::create(builder, argument.getType()).getResult(); // Since `liveSet` contains the port, we have to erase it from the set. liveElements.erase(argument); @@ -710,10 +710,10 @@ void IMDeadCodeElimPass::rewriteModuleSignature(FModuleOp module) { // Replace the port with a dummy wire. This wire should be erased within // `rewriteModuleBody`. - Value wire = builder - .create( - ArrayRef{argument.getType()}, ArrayRef{}) - ->getResult(0); + Value wire = + mlir::UnrealizedConversionCastOp::create( + builder, ArrayRef{argument.getType()}, ArrayRef{}) + ->getResult(0); argument.replaceAllUsesWith(wire); assert(isAssumedDead(wire) && "dummy wire must be dead"); diff --git a/lib/Dialect/FIRRTL/Transforms/InferReadWrite.cpp b/lib/Dialect/FIRRTL/Transforms/InferReadWrite.cpp index e0020eb99f..402b5ed0b3 100644 --- a/lib/Dialect/FIRRTL/Transforms/InferReadWrite.cpp +++ b/lib/Dialect/FIRRTL/Transforms/InferReadWrite.cpp @@ -154,8 +154,8 @@ struct InferReadWritePass ImplicitLocOpBuilder builder(memOp.getLoc(), memOp); portAnnotations.push_back(builder.getArrayAttr(portAtts)); // Create the new rw memory. - auto rwMem = builder.create( - resultTypes, memOp.getReadLatency(), memOp.getWriteLatency(), + auto rwMem = MemOp::create( + builder, resultTypes, memOp.getReadLatency(), memOp.getWriteLatency(), memOp.getDepth(), RUWAttr::Undefined, builder.getArrayAttr(resultNames), memOp.getNameAttr(), memOp.getNameKind(), memOp.getAnnotations(), @@ -166,36 +166,36 @@ struct InferReadWritePass // Create the subfield access to all fields of the port. // The addr should be connected to read/write address depending on the // read/write mode. - auto addr = builder.create(rwPort, "addr"); + auto addr = SubfieldOp::create(builder, rwPort, "addr"); // Enable is high whenever the memory is written or read. - auto enb = builder.create(rwPort, "en"); + auto enb = SubfieldOp::create(builder, rwPort, "en"); // Read/Write clock. - auto clk = builder.create(rwPort, "clk"); - auto readData = builder.create(rwPort, "rdata"); + auto clk = SubfieldOp::create(builder, rwPort, "clk"); + auto readData = SubfieldOp::create(builder, rwPort, "rdata"); // wmode is high when the port is in write mode. That is this can be // connected to the write enable. - auto wmode = builder.create(rwPort, "wmode"); - auto writeData = builder.create(rwPort, "wdata"); - auto mask = builder.create(rwPort, "wmask"); + auto wmode = SubfieldOp::create(builder, rwPort, "wmode"); + auto writeData = SubfieldOp::create(builder, rwPort, "wdata"); + auto mask = SubfieldOp::create(builder, rwPort, "wmask"); // Temp wires to replace the original memory connects. auto rAddr = - builder.create(addr.getType(), "readAddr").getResult(); + WireOp::create(builder, addr.getType(), "readAddr").getResult(); auto wAddr = - builder.create(addr.getType(), "writeAddr").getResult(); + WireOp::create(builder, addr.getType(), "writeAddr").getResult(); auto wEnWire = - builder.create(enb.getType(), "writeEnable").getResult(); + WireOp::create(builder, enb.getType(), "writeEnable").getResult(); auto rEnWire = - builder.create(enb.getType(), "readEnable").getResult(); + WireOp::create(builder, enb.getType(), "readEnable").getResult(); auto writeClock = - builder.create(ClockType::get(enb.getContext())).getResult(); + WireOp::create(builder, ClockType::get(enb.getContext())).getResult(); // addr = Mux(WriteEnable, WriteAddress, ReadAddress). - builder.create( - addr, builder.create(wEnWire, wAddr, rAddr)); + MatchingConnectOp::create( + builder, addr, MuxPrimOp::create(builder, wEnWire, wAddr, rAddr)); // Enable = Or(WriteEnable, ReadEnable). - builder.create( - enb, builder.create(rEnWire, wEnWire)); + MatchingConnectOp::create(builder, enb, + OrPrimOp::create(builder, rEnWire, wEnWire)); builder.setInsertionPointToEnd(wmode->getBlock()); - builder.create(wmode, complementTerm); + MatchingConnectOp::create(builder, wmode, complementTerm); // Now iterate over the original memory read and write ports. size_t dbgsIndex = 0; for (const auto &portIt : llvm::enumerate(memOp.getResults())) { @@ -470,8 +470,8 @@ private: ImplicitLocOpBuilder builder(memOp.getLoc(), memOp); builder.setInsertionPointToStart( memOp->getParentOfType().getBodyBlock()); - auto constOne = builder.create( - UIntType::get(builder.getContext(), 1), APInt(1, 1)); + auto constOne = ConstantOp::create( + builder, UIntType::get(builder.getContext(), 1), APInt(1, 1)); setEnable(enableDriver, wmodeDriver, constOne); } } @@ -553,12 +553,13 @@ private: memOp.getPortKind(i), /*maskBits=*/1)); // Copy everything from old memory, except the result type. - auto newMem = builder.create( - resultTypes, memOp.getReadLatencyAttr(), memOp.getWriteLatencyAttr(), - memOp.getDepthAttr(), memOp.getRuwAttr(), memOp.getPortNamesAttr(), - memOp.getNameAttr(), memOp.getNameKindAttr(), - memOp.getAnnotationsAttr(), memOp.getPortAnnotationsAttr(), - memOp.getInnerSymAttr(), memOp.getInitAttr(), memOp.getPrefixAttr()); + auto newMem = MemOp::create( + builder, resultTypes, memOp.getReadLatencyAttr(), + memOp.getWriteLatencyAttr(), memOp.getDepthAttr(), memOp.getRuwAttr(), + memOp.getPortNamesAttr(), memOp.getNameAttr(), + memOp.getNameKindAttr(), memOp.getAnnotationsAttr(), + memOp.getPortAnnotationsAttr(), memOp.getInnerSymAttr(), + memOp.getInitAttr(), memOp.getPrefixAttr()); // Now replace the result of old memory with the new one. for (const auto &portIt : llvm::enumerate(memOp.getResults())) { // Old result. @@ -575,17 +576,19 @@ private: for (Operation *u : oldPort.getUsers()) { auto oldRes = dyn_cast(u); auto sf = - builder.create(newPortVal, oldRes.getFieldIndex()); + SubfieldOp::create(builder, newPortVal, oldRes.getFieldIndex()); auto fName = sf.getInput().getType().base().getElementName(sf.getFieldIndex()); // Replace all mask fields with a one bit constant 1. // Replace all other fields with the new port. if (fName.contains("mask")) { - WireOp dummy = builder.create(oldRes.getType()); + WireOp dummy = WireOp::create(builder, oldRes.getType()); oldRes->replaceAllUsesWith(dummy); - builder.create( - sf, builder.create( - UIntType::get(builder.getContext(), 1), APInt(1, 1))); + MatchingConnectOp::create( + builder, sf, + ConstantOp::create(builder, + UIntType::get(builder.getContext(), 1), + APInt(1, 1))); } else oldRes->replaceAllUsesWith(sf); diff --git a/lib/Dialect/FIRRTL/Transforms/InferResets.cpp b/lib/Dialect/FIRRTL/Transforms/InferResets.cpp index c42960f77f..3de43454c4 100644 --- a/lib/Dialect/FIRRTL/Transforms/InferResets.cpp +++ b/lib/Dialect/FIRRTL/Transforms/InferResets.cpp @@ -132,14 +132,14 @@ static Value createZeroValue(ImplicitLocOpBuilder &builder, FIRRTLBaseType type, auto value = FIRRTLTypeSwitch(type) .Case([&](auto type) { - return builder.create(nullBit()); + return AsClockPrimOp::create(builder, nullBit()); }) .Case([&](auto type) { - return builder.create(nullBit()); + return AsAsyncResetPrimOp::create(builder, nullBit()); }) .Case([&](auto type) { - return builder.create( - type, APInt::getZero(type.getWidth().value_or(1))); + return ConstantOp::create( + builder, type, APInt::getZero(type.getWidth().value_or(1))); }) .Case([&](auto type) -> Value { // There might not be a variant that corresponds to 0, in which case @@ -148,38 +148,39 @@ static Value createZeroValue(ImplicitLocOpBuilder &builder, FIRRTLBaseType type, type.getElement(0).value.getValue().isZero()) { const auto &element = type.getElement(0); auto value = createZeroValue(builder, element.type, cache); - return builder.create(type, element.name, value); + return FEnumCreateOp::create(builder, type, element.name, value); } - auto value = builder.create( - UIntType::get(builder.getContext(), type.getBitWidth(), - /*isConst=*/true), - APInt::getZero(type.getBitWidth())); - return builder.create(type, value); + auto value = ConstantOp::create(builder, + UIntType::get(builder.getContext(), + type.getBitWidth(), + /*isConst=*/true), + APInt::getZero(type.getBitWidth())); + return BitCastOp::create(builder, type, value); }) .Case([&](auto type) { - auto wireOp = builder.create(type); + auto wireOp = WireOp::create(builder, type); for (unsigned i = 0, e = type.getNumElements(); i < e; ++i) { auto fieldType = type.getElementTypePreservingConst(i); auto zero = createZeroValue(builder, fieldType, cache); auto acc = - builder.create(fieldType, wireOp.getResult(), i); + SubfieldOp::create(builder, fieldType, wireOp.getResult(), i); emitConnect(builder, acc, zero); } return wireOp.getResult(); }) .Case([&](auto type) { - auto wireOp = builder.create(type); + auto wireOp = WireOp::create(builder, type); auto zero = createZeroValue( builder, type.getElementTypePreservingConst(), cache); for (unsigned i = 0, e = type.getNumElements(); i < e; ++i) { - auto acc = builder.create(zero.getType(), - wireOp.getResult(), i); + auto acc = SubindexOp::create(builder, zero.getType(), + wireOp.getResult(), i); emitConnect(builder, acc, zero); } return wireOp.getResult(); }) .Case( - [&](auto type) { return builder.create(type); }) + [&](auto type) { return InvalidValueOp::create(builder, type); }) .Default([](auto) { llvm_unreachable("switch handles all types"); return Value{}; @@ -218,14 +219,14 @@ static bool insertResetMux(ImplicitLocOpBuilder &builder, Value target, return; LLVM_DEBUG(llvm::dbgs() << " - Insert mux into " << op << "\n"); auto muxOp = - builder.create(reset, resetValue, op.getSrc()); + MuxPrimOp::create(builder, reset, resetValue, op.getSrc()); op.getSrcMutable().assign(muxOp); resetValueUsed = true; }) // Look through subfields. .Case([&](auto op) { auto resetSubValue = - builder.create(resetValue, op.getFieldIndexAttr()); + SubfieldOp::create(builder, resetValue, op.getFieldIndexAttr()); if (insertResetMux(builder, op, reset, resetSubValue)) resetValueUsed = true; else @@ -234,7 +235,7 @@ static bool insertResetMux(ImplicitLocOpBuilder &builder, Value target, // Look through subindices. .Case([&](auto op) { auto resetSubValue = - builder.create(resetValue, op.getIndexAttr()); + SubindexOp::create(builder, resetValue, op.getIndexAttr()); if (insertResetMux(builder, op, reset, resetSubValue)) resetValueUsed = true; else @@ -245,7 +246,7 @@ static bool insertResetMux(ImplicitLocOpBuilder &builder, Value target, if (op.getInput() != target) return; auto resetSubValue = - builder.create(resetValue, op.getIndex()); + SubaccessOp::create(builder, resetValue, op.getIndex()); if (insertResetMux(builder, op, reset, resetSubValue)) resetValueUsed = true; else @@ -851,7 +852,7 @@ void InferResetsPass::traceResets(CircuitOp circuit) { // `use.set(...)`. // - `drop_begin` such that the first use can keep the // original op. - auto newOp = builder.create(type); + auto newOp = InvalidValueOp::create(builder, type); use.set(newOp); } }) @@ -1768,8 +1769,8 @@ LogicalResult InferResetsPass::implementFullReset(FModuleOp module, << "- Promoting node to wire for move: " << nodeOp << "\n"); auto builder = ImplicitLocOpBuilder::atBlockBegin(nodeOp.getLoc(), nodeOp->getBlock()); - auto wireOp = builder.create( - nodeOp.getResult().getType(), nodeOp.getNameAttr(), + auto wireOp = WireOp::create( + builder, nodeOp.getResult().getType(), nodeOp.getNameAttr(), nodeOp.getNameKindAttr(), nodeOp.getAnnotationsAttr(), nodeOp.getInnerSymAttr(), nodeOp.getForceableAttr()); // Don't delete the node, since it might be in use in worklists. @@ -1890,10 +1891,11 @@ void InferResetsPass::implementFullReset(Operation *op, FModuleOp module, if (auto regOp = dyn_cast(op)) { LLVM_DEBUG(llvm::dbgs() << "- Adding full reset to " << regOp << "\n"); auto zero = createZeroValue(builder, regOp.getResult().getType()); - auto newRegOp = builder.create( - regOp.getResult().getType(), regOp.getClockVal(), actualReset, zero, - regOp.getNameAttr(), regOp.getNameKindAttr(), regOp.getAnnotations(), - regOp.getInnerSymAttr(), regOp.getForceableAttr()); + auto newRegOp = RegResetOp::create( + builder, regOp.getResult().getType(), regOp.getClockVal(), actualReset, + zero, regOp.getNameAttr(), regOp.getNameKindAttr(), + regOp.getAnnotations(), regOp.getInnerSymAttr(), + regOp.getForceableAttr()); regOp.getResult().replaceAllUsesWith(newRegOp.getResult()); if (regOp.getForceable()) regOp.getRef().replaceAllUsesWith(newRegOp.getRef()); @@ -1924,7 +1926,7 @@ void InferResetsPass::implementFullReset(Operation *op, FModuleOp module, // into a mux in front of the register. insertResetMux(builder, regOp.getResult(), reset, value); builder.setInsertionPointAfterValue(regOp.getResult()); - auto mux = builder.create(reset, value, regOp.getResult()); + auto mux = MuxPrimOp::create(builder, reset, value, regOp.getResult()); emitConnect(builder, regOp.getResult(), mux); // Replace the existing reset with the async reset. diff --git a/lib/Dialect/FIRRTL/Transforms/InjectDUTHierarchy.cpp b/lib/Dialect/FIRRTL/Transforms/InjectDUTHierarchy.cpp index 472685cde7..543f0f2951 100644 --- a/lib/Dialect/FIRRTL/Transforms/InjectDUTHierarchy.cpp +++ b/lib/Dialect/FIRRTL/Transforms/InjectDUTHierarchy.cpp @@ -215,8 +215,8 @@ void InjectDUTHierarchy::runOnOperation() { // just created becomes the "DUT". auto oldDutNameAttr = dut.getNameAttr(); wrapper = dut; - dut = b.create(dut.getLoc(), oldDutNameAttr, - dut.getConventionAttr(), dut.getPorts()); + dut = FModuleOp::create(b, dut.getLoc(), oldDutNameAttr, + dut.getConventionAttr(), dut.getPorts()); // Finish setting up the DUT and the Wrapper. This depends on if we are in // `moveDut` mode or not. If `moveDut=false` (the normal, legacy behavior), @@ -275,11 +275,11 @@ void InjectDUTHierarchy::runOnOperation() { b.setInsertionPointToStart(dut.getBodyBlock()); hw::InnerSymbolNamespace dutNS(dut); auto wrapperInst = - b.create(b.getUnknownLoc(), wrapper, wrapper.getModuleName(), - NameKindEnum::DroppableName, ArrayRef{}, - ArrayRef{}, false, false, - hw::InnerSymAttr::get(b.getStringAttr( - dutNS.newName(wrapper.getModuleName())))); + InstanceOp::create(b, b.getUnknownLoc(), wrapper, wrapper.getModuleName(), + NameKindEnum::DroppableName, ArrayRef{}, + ArrayRef{}, false, false, + hw::InnerSymAttr::get(b.getStringAttr( + dutNS.newName(wrapper.getModuleName())))); for (const auto &pair : llvm::enumerate(wrapperInst.getResults())) { Value lhs = dut.getArgument(pair.index()); Value rhs = pair.value(); diff --git a/lib/Dialect/FIRRTL/Transforms/LinkCircuits.cpp b/lib/Dialect/FIRRTL/Transforms/LinkCircuits.cpp index 59af8a993e..4103782cf6 100644 --- a/lib/Dialect/FIRRTL/Transforms/LinkCircuits.cpp +++ b/lib/Dialect/FIRRTL/Transforms/LinkCircuits.cpp @@ -194,8 +194,9 @@ LogicalResult LinkCircuitsPass::mergeCircuits() { auto builder = OpBuilder(module); builder.setInsertionPointToEnd(module.getBody()); - auto mergedCircuit = builder.create( - module.getLoc(), StringAttr::get(&getContext(), baseCircuitName)); + auto mergedCircuit = + CircuitOp::create(builder, module.getLoc(), + StringAttr::get(&getContext(), baseCircuitName)); SmallVector mergedAnnotations; for (auto circuit : circuits) { diff --git a/lib/Dialect/FIRRTL/Transforms/LowerAnnotations.cpp b/lib/Dialect/FIRRTL/Transforms/LowerAnnotations.cpp index 5b670ba96e..3a50541c3d 100644 --- a/lib/Dialect/FIRRTL/Transforms/LowerAnnotations.cpp +++ b/lib/Dialect/FIRRTL/Transforms/LowerAnnotations.cpp @@ -877,9 +877,9 @@ LogicalResult LowerAnnotationsPass::solveWiringProblems(ApplyState &state) { // Create RefSend/RefResolve if necessary. if (type_isa(dest.getType()) != type_isa(src.getType())) { if (type_isa(dest.getType())) - src = builder.create(src); + src = RefSendOp::create(builder, src); else - src = builder.create(src); + src = RefResolveOp::create(builder, src); } // If the sink is a wire with no users, then convert this to a node. @@ -892,7 +892,7 @@ LogicalResult LowerAnnotationsPass::solveWiringProblems(ApplyState &state) { baseType && baseType.isPassive()) { // Note that the wire is replaced with the source type // regardless, continue this behavior. - builder.create(src, destOp.getName()) + NodeOp::create(builder, src, destOp.getName()) .setAnnotationsAttr(destOp.getAnnotations()); opsToErase.push_back(destOp); return success(); diff --git a/lib/Dialect/FIRRTL/Transforms/LowerCHIRRTL.cpp b/lib/Dialect/FIRRTL/Transforms/LowerCHIRRTL.cpp index e98be4e86d..50b4dc9144 100644 --- a/lib/Dialect/FIRRTL/Transforms/LowerCHIRRTL.cpp +++ b/lib/Dialect/FIRRTL/Transforms/LowerCHIRRTL.cpp @@ -67,7 +67,7 @@ struct LowerCHIRRTLPass auto module = getOperation(); auto builder = OpBuilder::atBlockBegin(module.getBodyBlock()); auto u1Type = UIntType::get(builder.getContext(), /*width*/ 1); - value = builder.create(module.getLoc(), u1Type, APInt(1, c)); + value = ConstantOp::create(builder, module.getLoc(), u1Type, APInt(1, c)); } return value; } @@ -133,10 +133,10 @@ static void forEachLeaf(ImplicitLocOpBuilder &builder, Value value, auto type = value.getType(); if (auto bundleType = type_dyn_cast(type)) { for (size_t i = 0, e = bundleType.getNumElements(); i < e; ++i) - forEachLeaf(builder, builder.create(value, i), func); + forEachLeaf(builder, SubfieldOp::create(builder, value, i), func); } else if (auto vectorType = type_dyn_cast(type)) { for (size_t i = 0, e = vectorType.getNumElements(); i != e; ++i) - forEachLeaf(builder, builder.create(value, i), func); + forEachLeaf(builder, SubindexOp::create(builder, value, i), func); } else { func(value); } @@ -158,7 +158,7 @@ void LowerCHIRRTLPass::emitInvalid(ImplicitLocOpBuilder &builder, Value value) { auto &invalid = invalidCache[type]; if (!invalid) { auto builder = OpBuilder::atBlockBegin(getOperation().getBodyBlock()); - invalid = builder.create(getOperation().getLoc(), type); + invalid = InvalidValueOp::create(builder, getOperation().getLoc(), type); } emitConnect(builder, value, invalid); } @@ -356,8 +356,8 @@ void LowerCHIRRTLPass::replaceMem(Operation *cmem, StringRef name, // Create the memory. ImplicitLocOpBuilder memBuilder(cmem->getLoc(), cmem); auto symOp = cast(cmem); - auto memory = memBuilder.create( - resultTypes, readLatency, writeLatency, depth, ruw, + auto memory = MemOp::create( + memBuilder, resultTypes, readLatency, writeLatency, depth, ruw, memBuilder.getArrayAttr(resultNames), name, cmem->getAttrOfType("nameKind").getValue(), annotations, memBuilder.getArrayAttr(portAnnotations), @@ -385,11 +385,11 @@ void LowerCHIRRTLPass::replaceMem(Operation *cmem, StringRef name, // Initialization at the MemoryOp. ImplicitLocOpBuilder portBuilder(cmemoryPortAccess.getLoc(), cmemoryPortAccess); - auto address = memBuilder.create(memoryPort, "addr"); + auto address = SubfieldOp::create(memBuilder, memoryPort, "addr"); emitInvalid(memBuilder, address); - auto enable = memBuilder.create(memoryPort, "en"); + auto enable = SubfieldOp::create(memBuilder, memoryPort, "en"); emitConnect(memBuilder, enable, getConst(0)); - auto clock = memBuilder.create(memoryPort, "clk"); + auto clock = SubfieldOp::create(memBuilder, memoryPort, "clk"); emitInvalid(memBuilder, clock); // Initialization at the MemoryPortOp. @@ -410,13 +410,13 @@ void LowerCHIRRTLPass::replaceMem(Operation *cmem, StringRef name, if (portKind == MemOp::PortKind::Read) { // Store the read information for updating subfield ops. - auto data = memBuilder.create(memoryPort, "data"); + auto data = SubfieldOp::create(memBuilder, memoryPort, "data"); rdataValues[cmemoryPort.getData()] = data; } else if (portKind == MemOp::PortKind::Write) { // Initialization at the MemoryOp. - auto data = memBuilder.create(memoryPort, "data"); + auto data = SubfieldOp::create(memBuilder, memoryPort, "data"); emitInvalid(memBuilder, data); - auto mask = memBuilder.create(memoryPort, "mask"); + auto mask = SubfieldOp::create(memBuilder, memoryPort, "mask"); emitInvalid(memBuilder, mask); // Initialization at the MemoryPortOp. @@ -426,12 +426,12 @@ void LowerCHIRRTLPass::replaceMem(Operation *cmem, StringRef name, wdataValues[cmemoryPort.getData()] = {data, mask, nullptr}; } else if (portKind == MemOp::PortKind::ReadWrite) { // Initialization at the MemoryOp. - auto rdata = memBuilder.create(memoryPort, "rdata"); - auto wmode = memBuilder.create(memoryPort, "wmode"); + auto rdata = SubfieldOp::create(memBuilder, memoryPort, "rdata"); + auto wmode = SubfieldOp::create(memBuilder, memoryPort, "wmode"); emitConnect(memBuilder, wmode, getConst(0)); - auto wdata = memBuilder.create(memoryPort, "wdata"); + auto wdata = SubfieldOp::create(memBuilder, memoryPort, "wdata"); emitInvalid(memBuilder, wdata); - auto wmask = memBuilder.create(memoryPort, "wmask"); + auto wmask = SubfieldOp::create(memBuilder, memoryPort, "wmask"); emitInvalid(memBuilder, wmask); // Initialization at the MemoryPortOp. @@ -586,7 +586,8 @@ void LowerCHIRRTLPass::cloneSubindexOpForMemory(OpType op, Value input, if (iter != rdataValues.end()) { opsToDelete.push_back(op); ImplicitLocOpBuilder builder(op->getLoc(), op); - rdataValues[op] = builder.create(rdataValues[input], operands...); + rdataValues[op] = + OpType::create(builder, rdataValues[input], operands...); } return; } @@ -603,15 +604,15 @@ void LowerCHIRRTLPass::cloneSubindexOpForMemory(OpType op, Value input, // If the subaccess operation is used to read from a memory port, we need to // clone it to read from the rdata field. if (direction == MemDirAttr::Read || direction == MemDirAttr::ReadWrite) { - rdataValues[op] = builder.create(rdataValues[input], operands...); + rdataValues[op] = OpType::create(builder, rdataValues[input], operands...); } // If the subaccess operation is used to write to the memory, we need to clone // it to write to the wdata and the wmask fields. if (direction == MemDirAttr::Write || direction == MemDirAttr::ReadWrite) { auto writeData = wdataValues[input]; - auto write = builder.create(writeData.data, operands...); - auto mask = builder.create(writeData.mask, operands...); + auto write = OpType::create(builder, writeData.data, operands...); + auto mask = OpType::create(builder, writeData.mask, operands...); wdataValues[op] = {write, mask, writeData.mode}; } } diff --git a/lib/Dialect/FIRRTL/Transforms/LowerClasses.cpp b/lib/Dialect/FIRRTL/Transforms/LowerClasses.cpp index c04a6e36ea..2dbe849679 100644 --- a/lib/Dialect/FIRRTL/Transforms/LowerClasses.cpp +++ b/lib/Dialect/FIRRTL/Transforms/LowerClasses.cpp @@ -379,8 +379,8 @@ static void createRtlPorts(const RtlPortsInfo &rtlPortToCreate, FlatSymbolRefAttr portPathRef = hierPathCache.getRefFor(ArrayAttr::get(ctx, {portSym})); - auto portPath = builder.create( - loc, om::PathType::get(ctx), + auto portPath = om::PathCreateOp::create( + builder, loc, om::PathType::get(ctx), om::TargetKindAttr::get(ctx, om::TargetKind::DontTouch), basePath, portPathRef); @@ -389,22 +389,22 @@ static void createRtlPorts(const RtlPortsInfo &rtlPortToCreate, StringRef portDirectionName = mod.getPortDirection(i) == Direction::Out ? "Output" : "Input"; - auto portDirection = builder.create( - loc, om::StringType::get(ctx), + auto portDirection = om::ConstantOp::create( + builder, loc, om::StringType::get(ctx), StringAttr::get(portDirectionName, om::StringType::get(ctx))); // Get a width attribute. - auto portWidth = builder.create( - loc, om::OMIntegerType::get(ctx), + auto portWidth = om::ConstantOp::create( + builder, loc, om::OMIntegerType::get(ctx), om::IntegerAttr::get( ctx, mlir::IntegerAttr::get(mlir::IntegerType::get(ctx, 64), portType.getBitWidthOrSentinel()))); // Create an RtlPort object for this port, and add it to the list. - auto portObj = builder.create( - loc, portClassType, portClassName, + auto portObj = om::ObjectOp::create( + builder, loc, portClassType, portClassName, ArrayRef{portPath, portDirection, portWidth}); ports.push_back(portObj); @@ -412,9 +412,9 @@ static void createRtlPorts(const RtlPortsInfo &rtlPortToCreate, // Create a list of RtlPort objects to be included with the containingModule. - auto portsList = builder.create( - UnknownLoc::get(builder.getContext()), - getRtlPortsType(builder.getContext()), ports); + auto portsList = + om::ListCreateOp::create(builder, UnknownLoc::get(builder.getContext()), + getRtlPortsType(builder.getContext()), ports); object.getActualParamsMutable().append({portsList}); } @@ -997,8 +997,8 @@ static om::ClassLike convertExtClass(FModuleLike moduleLike, OpBuilder builder, } checkAddContainingModulePorts(hasContainingModule, builder, fieldNames, fieldTypes); - return builder.create( - moduleLike.getLoc(), name, formalParamNames, fieldNames, fieldTypes); + return om::ClassExternOp::create(builder, moduleLike.getLoc(), name, + formalParamNames, fieldNames, fieldTypes); } static om::ClassLike convertClass(FModuleLike moduleLike, OpBuilder builder, @@ -1023,8 +1023,8 @@ static om::ClassLike convertClass(FModuleLike moduleLike, OpBuilder builder, checkAddContainingModulePorts(hasContainingModule, builder, fieldNames, fieldTypes); - return builder.create(moduleLike.getLoc(), name, - formalParamNames, fieldNames, fieldTypes); + return om::ClassOp::create(builder, moduleLike.getLoc(), name, + formalParamNames, fieldNames, fieldTypes); } // Create an OM Class op from a FIRRTL Class op or Module op with properties. @@ -1332,8 +1332,8 @@ static LogicalResult updateObjectInClass( // Create the new Object op. OpBuilder builder(firrtlObject); - auto object = builder.create( - firrtlObject.getLoc(), classType, firrtlObject.getClassNameAttr(), args); + auto object = om::ObjectOp::create(builder, firrtlObject.getLoc(), classType, + firrtlObject.getClassNameAttr(), args); // If there is a 'containingModule', track that we need to add 'ports'. if (containingModuleRef) { @@ -1369,8 +1369,8 @@ updateInstanceInClass(InstanceOp firrtlInstance, hw::HierPathOp hierPath, // The 0'th argument is the base path. auto basePath = firrtlInstance->getBlock()->getArgument(0); auto symRef = FlatSymbolRefAttr::get(hierPath.getSymNameAttr()); - auto rebasedPath = builder.create( - firrtlInstance->getLoc(), basePath, symRef); + auto rebasedPath = om::BasePathCreateOp::create( + builder, firrtlInstance->getLoc(), basePath, symRef); actualParameters.push_back(rebasedPath); @@ -1419,8 +1419,8 @@ updateInstanceInClass(InstanceOp firrtlInstance, hw::HierPathOp hierPath, // Create the new Object op. auto object = - builder.create(firrtlInstance.getLoc(), classType, - className.getAttr(), actualParameters); + om::ObjectOp::create(builder, firrtlInstance.getLoc(), classType, + className.getAttr(), actualParameters); // Replace uses of the FIRRTL instance outputs with field access into // the OM Object. The later dialect conversion will take care of @@ -1440,8 +1440,8 @@ updateInstanceInClass(InstanceOp firrtlInstance, hw::HierPathOp hierPath, firrtlInstance.getPortName(result.getResultNumber()))}); // Create the field access. - auto objectField = builder.create( - object.getLoc(), result.getType(), object, objectFieldPath); + auto objectField = ObjectFieldOp::create( + builder, object.getLoc(), result.getType(), object, objectFieldPath); result.replaceAllUsesWith(objectField); } @@ -2116,7 +2116,7 @@ static void populateTypeConverter(TypeConverter &converter) { converter.addTargetMaterialization( [](OpBuilder &builder, Type type, ValueRange values, Location loc) { assert(values.size() == 1); - return builder.create(loc, type, values[0]) + return UnrealizedConversionCastOp::create(builder, loc, type, values[0]) ->getResult(0); }); @@ -2125,7 +2125,7 @@ static void populateTypeConverter(TypeConverter &converter) { converter.addSourceMaterialization( [](OpBuilder &builder, Type type, ValueRange values, Location loc) { assert(values.size() == 1); - return builder.create(loc, type, values[0]) + return UnrealizedConversionCastOp::create(builder, loc, type, values[0]) ->getResult(0); }); } diff --git a/lib/Dialect/FIRRTL/Transforms/LowerDPI.cpp b/lib/Dialect/FIRRTL/Transforms/LowerDPI.cpp index e31998a33b..5f07b44877 100644 --- a/lib/Dialect/FIRRTL/Transforms/LowerDPI.cpp +++ b/lib/Dialect/FIRRTL/Transforms/LowerDPI.cpp @@ -116,15 +116,16 @@ static Value convertToUnpackedArray(ImplicitLocOpBuilder &builder, // Create an unpacked array from a packed array. for (int i = length - 1; i >= 0; --i) { - auto index = builder.create(APInt(width, i)); + auto index = hw::ConstantOp::create(builder, APInt(width, i)); auto elem = convertToUnpackedArray( - builder, builder.create(loweredValue, index)); + builder, hw::ArrayGetOp::create(builder, loweredValue, index)); if (!elem) return {}; values.push_back(elem); } - return builder.create( + return sv::UnpackedArrayCreateOp::create( + builder, hw::UnpackedArrayType::get(lowerType(array.getElementType()), length), values); } @@ -135,7 +136,7 @@ static Value getLowered(ImplicitLocOpBuilder &builder, Value value) { return value; auto type = lowerType(value.getType()); - Value result = builder.create(type, value) + Value result = mlir::UnrealizedConversionCastOp::create(builder, type, value) ->getResult(0); // We may need to cast the lowered value to a DPI specific type (e.g. open @@ -152,7 +153,7 @@ static Value getLowered(ImplicitLocOpBuilder &builder, Value value) { return {}; } - return builder.create(dpiType, result); + return sv::UnpackedOpenArrayCastOp::create(builder, dpiType, result); } LogicalResult LowerDPI::lower() { @@ -183,14 +184,15 @@ LogicalResult LowerDPI::lower() { outputTypes.push_back( lowerDPIArgumentType(dpiOp.getResult().getType())); - auto call = builder.create( - outputTypes, firstDPIDecl.getSymNameAttr(), clock, enable, inputs); + auto call = sim::DPICallOp::create(builder, outputTypes, + firstDPIDecl.getSymNameAttr(), clock, + enable, inputs); if (!call.getResults().empty()) { // Insert unrealized conversion cast HW type to FIRRTL type. - auto result = builder - .create( - dpiOp.getResult().getType(), call.getResult(0)) - ->getResult(0); + auto result = + mlir::UnrealizedConversionCastOp::create( + builder, dpiOp.getResult().getType(), call.getResult(0)) + ->getResult(0); dpiOp.getResult().replaceAllUsesWith(result); } return success(); @@ -269,8 +271,9 @@ sim::DPIFuncOp LowerDPI::getOrCreateDPIFuncDecl(DPICallIntrinsicOp op) { return it->second; auto funcSymbol = nameSpace.newName(op.getFunctionNameAttr().getValue()); - auto funcOp = builder.create( - funcSymbol, modType, ArrayAttr(), ArrayAttr(), op.getFunctionNameAttr()); + auto funcOp = + sim::DPIFuncOp::create(builder, funcSymbol, modType, ArrayAttr(), + ArrayAttr(), op.getFunctionNameAttr()); // External function must have a private linkage. funcOp.setPrivate(); functionSignatureToDPIFuncOp[{op.getFunctionNameAttr(), modType}] = funcOp; diff --git a/lib/Dialect/FIRRTL/Transforms/LowerIntmodules.cpp b/lib/Dialect/FIRRTL/Transforms/LowerIntmodules.cpp index 8017e06b41..eb4442a738 100644 --- a/lib/Dialect/FIRRTL/Transforms/LowerIntmodules.cpp +++ b/lib/Dialect/FIRRTL/Transforms/LowerIntmodules.cpp @@ -90,7 +90,7 @@ void LowerIntmodulesPass::runOnOperation() { for (auto [idx, result] : llvm::enumerate(inst.getResults())) { // Replace inputs with wires that will be used as operands. if (inst.getPortDirection(idx) != Direction::Out) { - auto w = builder.create(result.getLoc(), result.getType()) + auto w = WireOp::create(builder, result.getLoc(), result.getType()) .getResult(); result.replaceAllUsesWith(w); inputs.push_back(w); @@ -115,26 +115,28 @@ void LowerIntmodulesPass::runOnOperation() { // Create the replacement operation. if (outputs.empty()) { // If no outputs, just create the operation. - builder.create(/*result=*/Type(), - op.getIntrinsicAttr(), inputs, - op.getParameters()); + GenericIntrinsicOp::create(builder, /*result=*/Type(), + op.getIntrinsicAttr(), inputs, + op.getParameters()); } else if (outputs.size() == 1) { // For single output, the result is the output. auto resultType = outputs.front().element.type; - auto intop = builder.create( - resultType, op.getIntrinsicAttr(), inputs, op.getParameters()); + auto intop = GenericIntrinsicOp::create(builder, resultType, + op.getIntrinsicAttr(), inputs, + op.getParameters()); outputs.front().result.replaceAllUsesWith(intop.getResult()); } else { // For multiple outputs, create a bundle with fields for each output // and replace users with subfields. auto resultType = builder.getType(llvm::map_to_vector( outputs, [](const auto &info) { return info.element; })); - auto intop = builder.create( - resultType, op.getIntrinsicAttr(), inputs, op.getParameters()); + auto intop = GenericIntrinsicOp::create(builder, resultType, + op.getIntrinsicAttr(), inputs, + op.getParameters()); for (auto &output : outputs) - output.result.replaceAllUsesWith(builder.create( - intop.getResult(), output.element.name)); + output.result.replaceAllUsesWith(SubfieldOp::create( + builder, intop.getResult(), output.element.name)); } // Remove instance from IR and instance graph. use->erase(); @@ -178,7 +180,7 @@ void LowerIntmodulesPass::runOnOperation() { ImplicitLocOpBuilder builder(op.getLoc(), inst); auto replaceResults = [](OpBuilder &b, auto &&range) { return llvm::map_to_vector(range, [&b](auto v) { - auto w = b.create(v.getLoc(), v.getType()).getResult(); + auto w = WireOp::create(b, v.getLoc(), v.getType()).getResult(); v.replaceAllUsesWith(w); return w; }); @@ -199,8 +201,8 @@ void LowerIntmodulesPass::runOnOperation() { } else std::swap(inputs[1], inputs[2]); } - auto intop = builder.create( - builder.getType(), "circt_clock_gate", inputs, + auto intop = GenericIntrinsicOp::create( + builder, builder.getType(), "circt_clock_gate", inputs, op.getParameters()); inst.getResults().back().replaceAllUsesWith(intop.getResult()); diff --git a/lib/Dialect/FIRRTL/Transforms/LowerLayers.cpp b/lib/Dialect/FIRRTL/Transforms/LowerLayers.cpp index 7929a50732..15328d9004 100644 --- a/lib/Dialect/FIRRTL/Transforms/LowerLayers.cpp +++ b/lib/Dialect/FIRRTL/Transforms/LowerLayers.cpp @@ -298,8 +298,8 @@ FModuleOp LowerLayersPass::buildNewModule(OpBuilder &builder, auto location = layerBlock.getLoc(); auto namehint = layerBlockGlobals.lookup(layerBlock).moduleName; llvm::sys::SmartScopedLock instrumentationLock(*circuitMutex); - FModuleOp newModule = builder.create( - location, builder.getStringAttr(namehint), + FModuleOp newModule = FModuleOp::create( + builder, location, builder.getStringAttr(namehint), ConventionAttr::get(builder.getContext(), Convention::Internal), ArrayRef{}, ArrayAttr{}); if (auto dir = getOutputFile(layerBlock.getLayerNameAttr())) { @@ -386,7 +386,7 @@ void LowerLayersPass::lowerInlineLayerBlock(LayerOp layer, LayerBlockOp layerBlock) { OpBuilder builder(layerBlock); auto macroName = macroNames[layer]; - auto ifDef = builder.create(layerBlock.getLoc(), macroName); + auto ifDef = sv::IfDefOp::create(builder, layerBlock.getLoc(), macroName); ifDef.getBodyRegion().takeBody(layerBlock.getBodyRegion()); layerBlock.erase(); } @@ -421,9 +421,9 @@ LogicalResult LowerLayersPass::runOnModuleBody(FModuleOp moduleOp, nameHint.append(opName); } } - return nodeOp = builder.create( - operand.getLoc(), operand, - nameHint.empty() ? "_layer_probe" : StringRef(nameHint)); + return nodeOp = NodeOp::create(builder, operand.getLoc(), operand, + nameHint.empty() ? "_layer_probe" + : StringRef(nameHint)); }; // Determine the replacement for an operand within the current region. Keep a @@ -475,8 +475,8 @@ LogicalResult LowerLayersPass::runOnModuleBody(FModuleOp moduleOp, OpBuilder::InsertionGuard guard(localBuilder); auto zeroUIntType = UIntType::get(localBuilder.getContext(), 0); replacement = localBuilder.createOrFold( - value.getType(), localBuilder.create( - zeroUIntType, getIntZerosAttr(zeroUIntType))); + value.getType(), ConstantOp::create(localBuilder, zeroUIntType, + getIntZerosAttr(zeroUIntType))); } else { auto *definingOp = value.getDefiningOp(); hw::InnerRefAttr innerRef; @@ -509,8 +509,8 @@ LogicalResult LowerLayersPass::runOnModuleBody(FModuleOp moduleOp, hierPathOp.setVisibility(SymbolTable::Visibility::Private); } - replacement = localBuilder.create( - value.getType(), hierPathOp.getSymNameAttr()); + replacement = XMRDerefOp::create(localBuilder, value.getType(), + hierPathOp.getSymNameAttr()); } replacements.insert({value, replacement}); @@ -725,8 +725,8 @@ LogicalResult LowerLayersPass::runOnModuleBody(FModuleOp moduleOp, auto innerSym = hw::InnerSymAttr::get(builder.getStringAttr(ns.newName(instanceName))); - auto instanceOp = builder.create( - layerBlock.getLoc(), /*moduleName=*/newModule, + auto instanceOp = InstanceOp::create( + builder, layerBlock.getLoc(), /*moduleName=*/newModule, /*name=*/ instanceName, NameKindEnum::DroppableName, /*annotations=*/ArrayRef{}, @@ -740,9 +740,11 @@ LogicalResult LowerLayersPass::runOnModuleBody(FModuleOp moduleOp, createdInstances.try_emplace(instanceOp, newModule); // create the bind op. - OpBuilder::atBlockEnd(bindFiles[moduleOp][layer].body) - .create(layerBlock.getLoc(), moduleOp.getModuleNameAttr(), - instanceOp.getInnerSymAttr().getSymName()); + { + auto builder = OpBuilder::atBlockEnd(bindFiles[moduleOp][layer].body); + BindOp::create(builder, layerBlock.getLoc(), moduleOp.getModuleNameAttr(), + instanceOp.getInnerSymAttr().getSymName()); + } LLVM_DEBUG(llvm::dbgs() << " moved inner refs:\n"); for (hw::InnerSymAttr innerSym : innerSyms) { @@ -795,8 +797,8 @@ void LowerLayersPass::preprocessLayers(CircuitNamespace &ns, OpBuilder &b, if (macName != symName) macNameAttr = StringAttr::get(ctx, macName); - b.create(layer->getLoc(), symNameAttr, ArrayAttr(), - macNameAttr); + sv::MacroDeclOp::create(b, layer->getLoc(), symNameAttr, ArrayAttr(), + macNameAttr); macroNames[layer] = FlatSymbolRefAttr::get(&getContext(), symNameAttr); } for (auto child : layer.getOps()) @@ -843,19 +845,19 @@ void LowerLayersPass::buildBindFile(CircuitNamespace &ns, path = filename; // Declare the macro for the include guard. - b.create(loc, macroSymbolAttr, ArrayAttr{}, macroNameAttr); + sv::MacroDeclOp::create(b, loc, macroSymbolAttr, ArrayAttr{}, macroNameAttr); // Create the emit op. - auto bindFile = b.create(loc, path); + auto bindFile = emit::FileOp::create(b, loc, path); OpBuilder::InsertionGuard _(b); b.setInsertionPointToEnd(bindFile.getBody()); // Create the #ifndef for the include guard. - auto includeGuard = b.create(loc, macroSymbolRefAttr); + auto includeGuard = sv::IfDefOp::create(b, loc, macroSymbolRefAttr); b.createBlock(&includeGuard.getElseRegion()); // Create the #define for the include guard. - b.create(loc, macroSymbolRefAttr); + sv::MacroDefOp::create(b, loc, macroSymbolRefAttr); // Create IR to enable any parent layers. auto parent = layer->getParentOfType(); @@ -864,14 +866,14 @@ void LowerLayersPass::buildBindFile(CircuitNamespace &ns, // The parent bindfile will enable all ancestors. if (parent.getConvention() == LayerConvention::Bind) { auto target = bindFiles[module][parent].filename; - b.create(loc, IncludeStyle::Local, target); + sv::IncludeOp::create(b, loc, IncludeStyle::Local, target); break; } // If the parent layer is inline, we enable it by defining a macro. // We will also have to manually enable any subsequent ancestors. auto parentMacroSymbol = macroNames[parent]; - b.create(loc, parentMacroSymbol); + sv::MacroDefOp::create(b, loc, parentMacroSymbol); parent = layer->getParentOfType(); } @@ -885,8 +887,8 @@ void LowerLayersPass::buildBindFile(CircuitNamespace &ns, auto files = bindFiles[child]; auto lookup = files.find(layer); if (lookup != files.end()) - b.create(loc, IncludeStyle::Local, - lookup->second.filename); + sv::IncludeOp::create(b, loc, IncludeStyle::Local, + lookup->second.filename); } // Save the bind file information for later. diff --git a/lib/Dialect/FIRRTL/Transforms/LowerMatches.cpp b/lib/Dialect/FIRRTL/Transforms/LowerMatches.cpp index 6e2af9acb4..099bee1411 100644 --- a/lib/Dialect/FIRRTL/Transforms/LowerMatches.cpp +++ b/lib/Dialect/FIRRTL/Transforms/LowerMatches.cpp @@ -46,8 +46,8 @@ static void lowerMatch(MatchOp match) { auto input = match.getInput(); for (size_t i = 0; i < numCases - 1; ++i) { // Create a WhenOp which tests the enum's tag. - auto condition = b.create(input, match.getFieldIndexAttr(i)); - auto when = b.create(condition, /*withElse=*/true); + auto condition = IsTagOp::create(b, input, match.getFieldIndexAttr(i)); + auto when = WhenOp::create(b, condition, /*withElse=*/true); // Move the case block to the WhenOp. auto *thenBlock = &when.getThenBlock(); @@ -57,7 +57,7 @@ static void lowerMatch(MatchOp match) { // Replace the block argument with a subtag op. b.setInsertionPointToStart(caseBlock); - auto data = b.create(input, match.getFieldIndexAttr(i)); + auto data = SubtagOp::create(b, input, match.getFieldIndexAttr(i)); caseBlock->getArgument(0).replaceAllUsesWith(data); caseBlock->eraseArgument(0); @@ -69,7 +69,7 @@ static void lowerMatch(MatchOp match) { // if there was only 1 variant, right before the match operation. // Replace the block argument with a subtag op. - auto data = b.create(input, match.getFieldIndexAttr(numCases - 1)); + auto data = SubtagOp::create(b, input, match.getFieldIndexAttr(numCases - 1)); // Get the final block from the match statement, and splice it into the // current insertion point. diff --git a/lib/Dialect/FIRRTL/Transforms/LowerMemory.cpp b/lib/Dialect/FIRRTL/Transforms/LowerMemory.cpp index e896178e81..8650ddc0a1 100644 --- a/lib/Dialect/FIRRTL/Transforms/LowerMemory.cpp +++ b/lib/Dialect/FIRRTL/Transforms/LowerMemory.cpp @@ -203,8 +203,8 @@ LowerMemoryPass::emitMemoryModule(MemOp op, const FirMemory &mem, // Insert the memory module just above the current module. OpBuilder b(op->getParentOfType()); ++numCreatedMemModules; - auto moduleOp = b.create( - mem.loc, moduleName, ports, mem.numReadPorts, mem.numWritePorts, + auto moduleOp = FMemModuleOp::create( + b, mem.loc, moduleName, ports, mem.numReadPorts, mem.numWritePorts, mem.numReadWritePorts, mem.dataWidth, mem.maskBits, mem.readLatency, mem.writeLatency, mem.depth); SymbolTable::setSymbolVisibility(moduleOp, SymbolTable::Visibility::Private); @@ -250,8 +250,8 @@ void LowerMemoryPass::lowerMemory(MemOp mem, const FirMemory &summary, // Create the wrapper module, inserting it just before the current module. OpBuilder b(mem->getParentOfType()); - auto wrapper = b.create( - mem->getLoc(), wrapperName, + auto wrapper = FModuleOp::create( + b, mem->getLoc(), wrapperName, ConventionAttr::get(context, Convention::Internal), ports); SymbolTable::setSymbolVisibility(wrapper, SymbolTable::Visibility::Private); @@ -259,17 +259,17 @@ void LowerMemoryPass::lowerMemory(MemOp mem, const FirMemory &summary, // same name as the target module. auto memModule = getOrCreateMemModule(mem, summary, ports, shouldDedup); b.setInsertionPointToStart(wrapper.getBodyBlock()); - auto memInst = b.create( - mem->getLoc(), memModule, (mem.getName() + "_ext").str(), + auto memInst = InstanceOp::create( + b, mem->getLoc(), memModule, (mem.getName() + "_ext").str(), mem.getNameKind(), mem.getAnnotations().getValue()); // Wire all the ports together. for (auto [dst, src] : llvm::zip(wrapper.getBodyBlock()->getArguments(), memInst.getResults())) { if (wrapper.getPortDirection(dst.getArgNumber()) == Direction::Out) - b.create(mem->getLoc(), dst, src); + MatchingConnectOp::create(b, mem->getLoc(), dst, src); else - b.create(mem->getLoc(), src, dst); + MatchingConnectOp::create(b, mem->getLoc(), src, dst); } // Create an instance of the wrapper memory module, which will replace the @@ -445,8 +445,9 @@ InstanceOp LowerMemoryPass::emitMemoryInstance(MemOp op, FModuleOp module, if (domInfo.dominates(maskConnect, enConnect)) b.setInsertionPoint(enConnect); // 'and' the enable and mask signals together and use it as the enable. - auto andOp = b.create( - op->getLoc(), maskConnect->getOperand(1), enConnect->getOperand(1)); + auto andOp = + AndPrimOp::create(b, op->getLoc(), maskConnect->getOperand(1), + enConnect->getOperand(1)); enConnect->setOperand(1, andOp); enConnect->moveAfter(andOp); // Erase the old mask connect. @@ -491,9 +492,9 @@ InstanceOp LowerMemoryPass::emitMemoryInstance(MemOp op, FModuleOp module, // Create the instance to replace the memop. The instance name matches the // name of the original memory module before deduplication. // TODO: how do we lower port annotations? - auto inst = builder.create( - op.getLoc(), portTypes, module.getNameAttr(), summary.getFirMemoryName(), - op.getNameKind(), portDirections, portNames, + auto inst = InstanceOp::create( + builder, op.getLoc(), portTypes, module.getNameAttr(), + summary.getFirMemoryName(), op.getNameKind(), portDirections, portNames, /*annotations=*/ArrayRef(), /*portAnnotations=*/ArrayRef(), /*layers=*/ArrayRef(), /*lowerToBind=*/false, diff --git a/lib/Dialect/FIRRTL/Transforms/LowerOpenAggs.cpp b/lib/Dialect/FIRRTL/Transforms/LowerOpenAggs.cpp index 83a32f5d30..2ef5f82385 100644 --- a/lib/Dialect/FIRRTL/Transforms/LowerOpenAggs.cpp +++ b/lib/Dialect/FIRRTL/Transforms/LowerOpenAggs.cpp @@ -445,7 +445,7 @@ LogicalResult Visitor::visitExpr(OpenSubfieldOp op) { assert(newFieldIndex.has_value()); ImplicitLocOpBuilder builder(op.getLoc(), op); - auto newOp = builder.create(newInput, *newFieldIndex); + auto newOp = SubfieldOp::create(builder, newInput, *newFieldIndex); if (auto name = op->getAttrOfType("name")) newOp->setAttr("name", name); @@ -485,7 +485,7 @@ LogicalResult Visitor::visitExpr(OpenSubindexOp op) { assert(newInput); ImplicitLocOpBuilder builder(op.getLoc(), op); - auto newOp = builder.create(newInput, op.getIndex()); + auto newOp = SubindexOp::create(builder, newInput, op.getIndex()); if (auto name = op->getAttrOfType("name")) newOp->setAttr("name", name); @@ -667,19 +667,16 @@ LogicalResult Visitor::visitDecl(WireOp op) { // Create the new HW wire. if (mappings.hwType) hwOnlyAggMap[op.getResult()] = - builder - .create(mappings.hwType, op.getName(), op.getNameKind(), - op.getAnnotations(), mappings.newSym, - op.getForceable()) + WireOp::create(builder, mappings.hwType, op.getName(), op.getNameKind(), + op.getAnnotations(), mappings.newSym, op.getForceable()) .getResult(); // Create the non-HW wires. Non-HW wire names are always droppable. for (auto &[type, fieldID, _, suffix] : mappings.fields) nonHWValues[FieldRef(op.getResult(), fieldID)] = - builder - .create(type, - builder.getStringAttr(Twine(op.getName()) + suffix), - NameKindEnum::DroppableName) + WireOp::create(builder, type, + builder.getStringAttr(Twine(op.getName()) + suffix), + NameKindEnum::DroppableName) .getResult(); for (auto fieldID : mappings.mapToNullInteriors) diff --git a/lib/Dialect/FIRRTL/Transforms/LowerSignatures.cpp b/lib/Dialect/FIRRTL/Transforms/LowerSignatures.cpp index 1d17e61ace..9ae9dcc8a0 100644 --- a/lib/Dialect/FIRRTL/Transforms/LowerSignatures.cpp +++ b/lib/Dialect/FIRRTL/Transforms/LowerSignatures.cpp @@ -278,10 +278,9 @@ static LogicalResult lowerModuleSignature(FModuleLike module, Convention conv, if (p.fieldID != 0) { auto &wire = bounceWires[p.portID]; if (!wire) - wire = theBuilder - .create(module.getPortType(p.portID), - module.getPortNameAttr(p.portID), - NameKindEnum::InterestingName) + wire = WireOp::create(theBuilder, module.getPortType(p.portID), + module.getPortNameAttr(p.portID), + NameKindEnum::InterestingName) .getResult(); } else { bounceWires[p.portID] = newArg; @@ -291,9 +290,8 @@ static LogicalResult lowerModuleSignature(FModuleLike module, Convention conv, // zero-length vectors. for (auto idx = 0U; idx < oldNumArgs; ++idx) { if (!bounceWires[idx]) { - bounceWires[idx] = theBuilder - .create(module.getPortType(idx), - module.getPortNameAttr(idx)) + bounceWires[idx] = WireOp::create(theBuilder, module.getPortType(idx), + module.getPortNameAttr(idx)) .getResult(); } body->getArgument(idx).replaceAllUsesWith(bounceWires[idx]); @@ -400,10 +398,10 @@ static void lowerModuleBody(FModuleOp mod, instPorts.push_back(p); } auto annos = inst.getAnnotations(); - auto newOp = theBuilder.create( - instPorts, inst.getModuleName(), inst.getName(), inst.getNameKind(), - annos.getValue(), inst.getLayers(), inst.getLowerToBind(), - inst.getDoNotPrint(), inst.getInnerSymAttr()); + auto newOp = InstanceOp::create( + theBuilder, instPorts, inst.getModuleName(), inst.getName(), + inst.getNameKind(), annos.getValue(), inst.getLayers(), + inst.getLowerToBind(), inst.getDoNotPrint(), inst.getInnerSymAttr()); auto oldDict = inst->getDiscardableAttrDictionary(); auto newDict = newOp->getDiscardableAttrDictionary(); @@ -423,8 +421,8 @@ static void lowerModuleBody(FModuleOp mod, continue; } if (!bounce[p.portID]) { - bounce[p.portID] = theBuilder.create( - inst.getResult(p.portID).getType(), + bounce[p.portID] = WireOp::create( + theBuilder, inst.getResult(p.portID).getType(), theBuilder.getStringAttr( inst.getName() + "." + cast(oldNames[p.portID]).getValue())); diff --git a/lib/Dialect/FIRRTL/Transforms/LowerXMR.cpp b/lib/Dialect/FIRRTL/Transforms/LowerXMR.cpp index 30bb9a431d..16ea456ab8 100644 --- a/lib/Dialect/FIRRTL/Transforms/LowerXMR.cpp +++ b/lib/Dialect/FIRRTL/Transforms/LowerXMR.cpp @@ -103,7 +103,7 @@ public: else builder.setInsertionPointToStart(body); - Value xmr = builder.create(type, symbol, suffix); + Value xmr = XMRRefOp::create(builder, type, symbol, suffix); xmrRefCache.insert({{type, symbol, suffix}, xmr}); xmrRefPoint = builder.saveInsertionPoint(); @@ -192,7 +192,7 @@ class LowerXMRPass : public circt::firrtl::impl::LowerXMRBase { nameKind = NameKindEnum::InterestingName; } } - xmrDef = b.create(xmrDef, opName, nameKind).getResult(); + xmrDef = NodeOp::create(b, xmrDef, opName, nameKind).getResult(); // Create a new entry for this RefSendOp. The path is currently // local. @@ -560,8 +560,8 @@ class LowerXMRPass : public circt::firrtl::impl::LowerXMRBase { ImplicitLocOpBuilder builder(resolve.getLoc(), resolve); auto zeroUintType = UIntType::get(builder.getContext(), 0); auto zeroC = builder.createOrFold( - resolve.getType(), builder.create( - zeroUintType, getIntZerosAttr(zeroUintType))); + resolve.getType(), ConstantOp::create(builder, zeroUintType, + getIntZerosAttr(zeroUintType))); resolve.getResult().replaceAllUsesWith(zeroC); return success(); } @@ -572,7 +572,7 @@ class LowerXMRPass : public circt::firrtl::impl::LowerXMRBase { if (failed(resolveReference(resolve.getRef(), builder, ref, str))) return failure(); - Value result = builder.create(resolve.getType(), ref, str); + Value result = XMRDerefOp::create(builder, resolve.getType(), ref, str); resolve.getResult().replaceAllUsesWith(result); return success(); } @@ -702,7 +702,8 @@ class LowerXMRPass : public circt::firrtl::impl::LowerXMRBase { getRefABIPrefix(module, circuitRefPrefix); auto macroName = getRefABIMacroForPort(module, portIndex, circuitRefPrefix); - declBuilder.create(macroName, ArrayAttr(), StringAttr()); + sv::MacroDeclOp::create(declBuilder, macroName, ArrayAttr(), + StringAttr()); ports.emplace_back(macroName, declBuilder.getStringAttr(formatString), ref ? declBuilder.getArrayAttr({ref}) : ArrayAttr{}); } @@ -714,10 +715,10 @@ class LowerXMRPass : public circt::firrtl::impl::LowerXMRBase { // The macros will be exported to a `ref_.sv` file. // In the IR, the file is inserted before the module. auto fileBuilder = ImplicitLocOpBuilder(module.getLoc(), module); - fileBuilder.create(circuitRefPrefix + ".sv", [&] { + emit::FileOp::create(fileBuilder, circuitRefPrefix + ".sv", [&] { for (auto [macroName, formatString, symbols] : ports) { - fileBuilder.create(FlatSymbolRefAttr::get(macroName), - formatString, symbols); + sv::MacroDefOp::create(fileBuilder, FlatSymbolRefAttr::get(macroName), + formatString, symbols); } }); @@ -812,8 +813,8 @@ class LowerXMRPass : public circt::firrtl::impl::LowerXMRBase { portAnnotations.push_back(mem.getPortAnnotation(res.index())); oldResults.push_back(res.value()); } - auto newMem = builder.create( - resultTypes, mem.getReadLatency(), mem.getWriteLatency(), + auto newMem = MemOp::create( + builder, resultTypes, mem.getReadLatency(), mem.getWriteLatency(), mem.getDepth(), RUWAttr::Undefined, builder.getArrayAttr(resultNames), mem.getNameAttr(), mem.getNameKind(), mem.getAnnotations(), diff --git a/lib/Dialect/FIRRTL/Transforms/MaterializeDebugInfo.cpp b/lib/Dialect/FIRRTL/Transforms/MaterializeDebugInfo.cpp index 1444691d29..498443b632 100644 --- a/lib/Dialect/FIRRTL/Transforms/MaterializeDebugInfo.cpp +++ b/lib/Dialect/FIRRTL/Transforms/MaterializeDebugInfo.cpp @@ -65,8 +65,8 @@ void MaterializeDebugInfoPass::materializeVariable(OpBuilder &builder, if (name.getValue().starts_with("_")) return; if (auto dbgValue = convertToDebugAggregates(builder, value)) - builder.create(value.getLoc(), name, dbgValue, - /*scope=*/Value{}); + debug::VariableOp::create(builder, value.getLoc(), name, dbgValue, + /*scope=*/Value{}); } /// Unpack all aggregates in a FIRRTL value and repack them as debug aggregates. @@ -79,15 +79,16 @@ Value MaterializeDebugInfoPass::convertToDebugAggregates(OpBuilder &builder, SmallVector names; SmallVector subOps; for (auto [index, element] : llvm::enumerate(type.getElements())) { - auto subOp = builder.create(value.getLoc(), value, index); + auto subOp = + SubfieldOp::create(builder, value.getLoc(), value, index); subOps.push_back(subOp); if (auto dbgValue = convertToDebugAggregates(builder, subOp)) { fields.push_back(dbgValue); names.push_back(element.name); } } - auto result = builder.create( - value.getLoc(), fields, builder.getArrayAttr(names)); + auto result = debug::StructOp::create(builder, value.getLoc(), fields, + builder.getArrayAttr(names)); for (auto *subOp : subOps) if (subOp->use_empty()) subOp->erase(); @@ -97,14 +98,15 @@ Value MaterializeDebugInfoPass::convertToDebugAggregates(OpBuilder &builder, SmallVector elements; SmallVector subOps; for (unsigned index = 0; index < type.getNumElements(); ++index) { - auto subOp = builder.create(value.getLoc(), value, index); + auto subOp = + SubindexOp::create(builder, value.getLoc(), value, index); subOps.push_back(subOp); if (auto dbgValue = convertToDebugAggregates(builder, subOp)) elements.push_back(dbgValue); } Value result; if (!elements.empty() && elements.size() == type.getNumElements()) - result = builder.create(value.getLoc(), elements); + result = debug::ArrayOp::create(builder, value.getLoc(), elements); for (auto *subOp : subOps) if (subOp->use_empty()) subOp->erase(); diff --git a/lib/Dialect/FIRRTL/Transforms/MemToRegOfVec.cpp b/lib/Dialect/FIRRTL/Transforms/MemToRegOfVec.cpp index d85c8a19f8..ef2c0dcecf 100644 --- a/lib/Dialect/FIRRTL/Transforms/MemToRegOfVec.cpp +++ b/lib/Dialect/FIRRTL/Transforms/MemToRegOfVec.cpp @@ -86,13 +86,12 @@ struct MemToRegOfVecPass return pipeInput; while (stages--) { - auto reg = b.create(pipeInput.getType(), clock, name).getResult(); + auto reg = RegOp::create(b, pipeInput.getType(), clock, name).getResult(); if (gate) { - b.create(gate, /*withElseRegion*/ false, [&]() { - b.create(reg, pipeInput); - }); + WhenOp::create(b, gate, /*withElseRegion*/ false, + [&]() { MatchingConnectOp::create(b, reg, pipeInput); }); } else - b.create(reg, pipeInput); + MatchingConnectOp::create(b, reg, pipeInput); pipeInput = reg; } @@ -101,36 +100,36 @@ struct MemToRegOfVecPass } Value getClock(ImplicitLocOpBuilder &builder, Value bundle) { - return builder.create(bundle, "clk"); + return SubfieldOp::create(builder, bundle, "clk"); } Value getAddr(ImplicitLocOpBuilder &builder, Value bundle) { - return builder.create(bundle, "addr"); + return SubfieldOp::create(builder, bundle, "addr"); } Value getWmode(ImplicitLocOpBuilder &builder, Value bundle) { - return builder.create(bundle, "wmode"); + return SubfieldOp::create(builder, bundle, "wmode"); } Value getEnable(ImplicitLocOpBuilder &builder, Value bundle) { - return builder.create(bundle, "en"); + return SubfieldOp::create(builder, bundle, "en"); } Value getMask(ImplicitLocOpBuilder &builder, Value bundle) { auto bType = type_cast(bundle.getType()); if (bType.getElement("mask")) - return builder.create(bundle, "mask"); - return builder.create(bundle, "wmask"); + return SubfieldOp::create(builder, bundle, "mask"); + return SubfieldOp::create(builder, bundle, "wmask"); } Value getData(ImplicitLocOpBuilder &builder, Value bundle, bool getWdata = false) { auto bType = type_cast(bundle.getType()); if (bType.getElement("data")) - return builder.create(bundle, "data"); + return SubfieldOp::create(builder, bundle, "data"); if (bType.getElement("rdata") && !getWdata) - return builder.create(bundle, "rdata"); - return builder.create(bundle, "wdata"); + return SubfieldOp::create(builder, bundle, "rdata"); + return SubfieldOp::create(builder, bundle, "wdata"); } void generateRead(const FirMemory &firMem, Value clock, Value addr, @@ -155,18 +154,18 @@ struct MemToRegOfVecPass } // Read the register[address] into a temporary. - Value rdata = builder.create(regOfVec, addr); + Value rdata = SubaccessOp::create(builder, regOfVec, addr); if (!ignoreReadEnable) { // Initialize read data out with invalid. - builder.create( - data, builder.create(data.getType())); + MatchingConnectOp::create( + builder, data, InvalidValueOp::create(builder, data.getType())); // If enable is true, then connect the data read from memory register. - builder.create(enable, /*withElseRegion*/ false, [&]() { - builder.create(data, rdata); + WhenOp::create(builder, enable, /*withElseRegion*/ false, [&]() { + MatchingConnectOp::create(builder, data, rdata); }); } else { // Ignore read enable signal. - builder.create(data, rdata); + MatchingConnectOp::create(builder, data, rdata); } } @@ -182,7 +181,7 @@ struct MemToRegOfVecPass wdataIn = addPipelineStages(builder, numStages, clock, wdataIn, "wdata"); maskBits = addPipelineStages(builder, numStages, clock, maskBits, "wmask"); // Create the register access. - FIRRTLBaseValue rdata = builder.create(regOfVec, addr); + FIRRTLBaseValue rdata = SubaccessOp::create(builder, regOfVec, addr); // The tuple for the access to individual fields of an aggregate data type. // Tuple:: @@ -211,15 +210,15 @@ struct MemToRegOfVecPass return; } // If enable: - builder.create(enable, /*withElseRegion*/ false, [&]() { + WhenOp::create(builder, enable, /*withElseRegion*/ false, [&]() { // For each data field. Only one field if not aggregate. for (auto regDataMask : loweredRegDataMaskFields) { auto regField = std::get<0>(regDataMask); auto dataField = std::get<1>(regDataMask); auto maskField = std::get<2>(regDataMask); // If mask, then update the register field. - builder.create(maskField, /*withElseRegion*/ false, [&]() { - builder.create(regField, dataField); + WhenOp::create(builder, maskField, /*withElseRegion*/ false, [&]() { + MatchingConnectOp::create(builder, regField, dataField); }); } }); @@ -239,7 +238,7 @@ struct MemToRegOfVecPass maskBits = addPipelineStages(builder, numStages, clock, maskBits, "wmask"); // Read the register[address] into a temporary. - Value rdata = builder.create(regOfVec, addr); + Value rdata = SubaccessOp::create(builder, regOfVec, addr); SmallVector, 8> loweredRegDataMaskFields; if (!getFields(rdata, wdataIn, maskBits, loweredRegDataMaskFields, @@ -249,13 +248,13 @@ struct MemToRegOfVecPass return; } // Initialize read data out with invalid. - builder.create( - rdataOut, builder.create(rdataOut.getType())); + MatchingConnectOp::create( + builder, rdataOut, InvalidValueOp::create(builder, rdataOut.getType())); // If enable: - builder.create(enable, /*withElseRegion*/ false, [&]() { + WhenOp::create(builder, enable, /*withElseRegion*/ false, [&]() { // If write mode: - builder.create( - wmode, true, + WhenOp::create( + builder, wmode, true, // Write block: [&]() { // For each data field. Only one field if not aggregate. @@ -264,14 +263,14 @@ struct MemToRegOfVecPass auto dataField = std::get<1>(regDataMask); auto maskField = std::get<2>(regDataMask); // If mask true, then set the field. - builder.create( - maskField, /*withElseRegion*/ false, [&]() { - builder.create(regField, dataField); + WhenOp::create( + builder, maskField, /*withElseRegion*/ false, [&]() { + MatchingConnectOp::create(builder, regField, dataField); }); } }, // Read block: - [&]() { builder.create(rdataOut, rdata); }); + [&]() { MatchingConnectOp::create(builder, rdataOut, rdata); }); }); } @@ -309,9 +308,9 @@ struct MemToRegOfVecPass return FIRRTLTypeSwitch(inType) .Case([&](BundleType bundle) { for (size_t i = 0, e = bundle.getNumElements(); i != e; ++i) { - auto regField = builder.create(reg, i); - auto inputField = builder.create(input, i); - auto maskField = builder.create(mask, i); + auto regField = SubfieldOp::create(builder, reg, i); + auto inputField = SubfieldOp::create(builder, input, i); + auto maskField = SubfieldOp::create(builder, mask, i); if (!flatAccess(regField, inputField, maskField)) return false; } @@ -319,9 +318,9 @@ struct MemToRegOfVecPass }) .Case([&](auto vector) { for (size_t i = 0, e = vector.getNumElements(); i != e; ++i) { - auto regField = builder.create(reg, i); - auto inputField = builder.create(input, i); - auto maskField = builder.create(mask, i); + auto regField = SubindexOp::create(builder, reg, i); + auto inputField = SubindexOp::create(builder, input, i); + auto maskField = SubindexOp::create(builder, mask, i); if (!flatAccess(regField, inputField, maskField)) return false; } @@ -385,8 +384,8 @@ struct MemToRegOfVecPass } // Create a temporary wire to replace the memory port. This makes it // simpler to delete the memOp. - auto wire = builder.create( - result.getType(), + auto wire = WireOp::create( + builder, result.getType(), (memOp.getName() + "_" + memOp.getPortName(index).getValue()).str(), memOp.getNameKind()); result.replaceAllUsesWith(wire.getResult()); @@ -399,8 +398,9 @@ struct MemToRegOfVecPass // IF the register is not yet created. if (!regOfVec) { // Create the register corresponding to the memory. - regOfVec = builder.create( - FVectorType::get(dataType, firMem.depth), clk, memOp.getNameAttr()); + regOfVec = + RegOp::create(builder, FVectorType::get(dataType, firMem.depth), + clk, memOp.getNameAttr()); // Copy all the memory annotations. if (!memOp.getAnnotationsAttr().empty()) @@ -428,7 +428,7 @@ struct MemToRegOfVecPass // RefSend on the register. if (regOfVec) for (auto r : debugPorts) - r.replaceAllUsesWith(builder.create(regOfVec.getResult())); + r.replaceAllUsesWith(RefSendOp::create(builder, regOfVec.getResult())); } }; } // end anonymous namespace diff --git a/lib/Dialect/FIRRTL/Transforms/ModuleInliner.cpp b/lib/Dialect/FIRRTL/Transforms/ModuleInliner.cpp index 78c529119f..e19d0408db 100644 --- a/lib/Dialect/FIRRTL/Transforms/ModuleInliner.cpp +++ b/lib/Dialect/FIRRTL/Transforms/ModuleInliner.cpp @@ -208,8 +208,8 @@ public: else namepath.push_back(FlatSymbolRefAttr::get(modPart)); - auto hp = b.create(b.getUnknownLoc(), sym, - b.getArrayAttr(namepath)); + auto hp = hw::HierPathOp::create(b, b.getUnknownLoc(), sym, + b.getArrayAttr(namepath)); hp.setVisibility(nla.getVisibility()); return hp; }; @@ -865,13 +865,12 @@ void Inliner::mapPortsToWires(StringRef prefix, InliningLevel &il, } Value wire = - il.mic.b - .create( - target.getLoc(), type, - StringAttr::get(context, (prefix + portInfo[i].getName())), - NameKindEnumAttr::get(context, NameKindEnum::DroppableName), - ArrayAttr::get(context, newAnnotations), newSymAttr, - /*forceable=*/UnitAttr{}) + WireOp::create( + il.mic.b, target.getLoc(), type, + StringAttr::get(context, (prefix + portInfo[i].getName())), + NameKindEnumAttr::get(context, NameKindEnum::DroppableName), + ArrayAttr::get(context, newAnnotations), newSymAttr, + /*forceable=*/UnitAttr{}) .getResult(); il.wires.push_back(wire); mapper.map(arg, wire); @@ -1363,8 +1362,8 @@ LogicalResult Inliner::inlineInstances(FModuleOp module) { void Inliner::createDebugScope(InliningLevel &il, InstanceOp instance, Value parentScope) { - auto op = il.mic.b.create( - instance.getLoc(), instance.getInstanceNameAttr(), + auto op = debug::ScopeOp::create( + il.mic.b, instance.getLoc(), instance.getInstanceNameAttr(), instance.getModuleNameAttr().getAttr(), parentScope); debugScopes.push_back(op); il.debugScope = op; diff --git a/lib/Dialect/FIRRTL/Transforms/ProbesToSignals.cpp b/lib/Dialect/FIRRTL/Transforms/ProbesToSignals.cpp index 2792f0a6db..10065835c9 100644 --- a/lib/Dialect/FIRRTL/Transforms/ProbesToSignals.cpp +++ b/lib/Dialect/FIRRTL/Transforms/ProbesToSignals.cpp @@ -233,7 +233,7 @@ LogicalResult ProbeVisitor::visit(FModuleLike mod) { newPortTypes.push_back(TypeAttr::get(newType)); if (block) { auto builder = OpBuilder::atBlockBegin(block); - wires.emplace_back(idx, builder.create(loc, newType)); + wires.emplace_back(idx, WireOp::create(builder, loc, newType)); probeToHWMap[block->getArgument(idx)] = wires.back().second.getData(); } } else @@ -351,21 +351,21 @@ ProbeVisitor::visitMemoryDebugPortOp(chirrtl::MemoryDebugPortOp op) { builder.setInsertionPointToEnd(mem->getBlock()); Type uintType = builder.getType(); for (uint64_t i = 0, e = mem.getType().getNumElements(); i != e; ++i) { - auto port = builder.create( - mem.getType().getElementType(), + auto port = chirrtl::MemoryPortOp::create( + builder, mem.getType().getElementType(), chirrtl::CMemoryPortType::get(builder.getContext()), mem.getResult(), MemDirAttr::Read, builder.getStringAttr("memTap_" + Twine(i)), builder.getArrayAttr({})); - builder.create( - port.getPort(), - builder.create(uintType, APSInt::getUnsigned(i)), clock); + chirrtl::MemoryPortAccessOp::create( + builder, port.getPort(), + ConstantOp::create(builder, uintType, APSInt::getUnsigned(i)), clock); data.push_back(port.getData()); } // Package up all the reads into a vector. assert(vectype == FVectorType::get(mem.getType().getElementType(), mem.getType().getNumElements())); - auto vecData = builder.create(vectype, data); + auto vecData = VectorCreateOp::create(builder, vectype, data); // While the new ports are added as late as possible, the debug port // operation we're replacing likely has users and those are before @@ -373,7 +373,7 @@ ProbeVisitor::visitMemoryDebugPortOp(chirrtl::MemoryDebugPortOp op) { // and the new port access operations added above. This will be used for // the existing users of the debug port. builder.setInsertionPoint(mem); - auto wire = builder.create(vectype); + auto wire = WireOp::create(builder, vectype); builder.setInsertionPointToEnd(mem->getBlock()); emitConnect(builder, wire.getData(), vecData); probeToHWMap[op.getResult()] = wire.getData(); @@ -431,7 +431,7 @@ LogicalResult ProbeVisitor::visitActiveForceableDecl(Forceable fop) { if (newType != data.getType()) { ImplicitLocOpBuilder builder(fop.getLoc(), fop); builder.setInsertionPointAfterValue(data); - auto wire = builder.create(newType); + auto wire = WireOp::create(builder, newType); emitConnect(builder, wire.getData(), data); data = wire.getData(); } @@ -517,7 +517,7 @@ LogicalResult ProbeVisitor::visitExpr(RWProbeOp op) { assert(cast(data.getType()).getPassiveType() == op.getType().getType()); if (newType != data.getType()) { - auto wire = builder.create(newType); + auto wire = WireOp::create(builder, newType); emitConnect(builder, wire.getData(), data); data = wire.getData(); } @@ -541,7 +541,7 @@ LogicalResult ProbeVisitor::visitExpr(RefCastOp op) { ImplicitLocOpBuilder builder(op.getLoc(), op); builder.setInsertionPointAfterValue(input); - auto wire = builder.create(newType); + auto wire = WireOp::create(builder, newType); emitConnect(builder, wire.getData(), input); probeToHWMap[op.getResult()] = wire.getData(); toDelete.push_back(op); @@ -566,7 +566,7 @@ LogicalResult ProbeVisitor::visitExpr(RefSendOp op) { assert(newType == op.getBase().getType().getPassiveType()); ImplicitLocOpBuilder builder(op.getLoc(), op); builder.setInsertionPointAfterValue(op.getBase()); - auto wire = builder.create(newType); + auto wire = WireOp::create(builder, newType); emitConnect(builder, wire.getData(), op.getBase()); probeToHWMap[op.getResult()] = wire.getData(); return success(); diff --git a/lib/Dialect/FIRRTL/Transforms/RegisterOptimizer.cpp b/lib/Dialect/FIRRTL/Transforms/RegisterOptimizer.cpp index 83b1ff4264..97276fd342 100644 --- a/lib/Dialect/FIRRTL/Transforms/RegisterOptimizer.cpp +++ b/lib/Dialect/FIRRTL/Transforms/RegisterOptimizer.cpp @@ -64,8 +64,9 @@ void RegisterOptimizerPass::checkReg(mlir::DominanceInfo &dom, // Register is only written by itself, replace with invalid. if (con.getSrc() == reg.getResult()) { - auto inv = OpBuilder(reg).create(reg.getLoc(), - reg.getResult().getType()); + auto builder = OpBuilder(reg); + auto inv = InvalidValueOp::create(builder, reg.getLoc(), + reg.getResult().getType()); reg.getResult().replaceAllUsesWith(inv.getResult()); toErase.push_back(reg); toErase.push_back(con); @@ -98,8 +99,9 @@ void RegisterOptimizerPass::checkReg(mlir::DominanceInfo &dom, reg.getResult().replaceAllUsesWith(con.getSrc()); toErase.push_back(con); } else { - auto bounce = OpBuilder(reg).create(reg.getLoc(), - reg.getResult().getType()); + auto builder = OpBuilder(reg); + auto bounce = + WireOp::create(builder, reg.getLoc(), reg.getResult().getType()); reg.replaceAllUsesWith(bounce); } } diff --git a/lib/Dialect/FIRRTL/Transforms/RemoveUnusedPorts.cpp b/lib/Dialect/FIRRTL/Transforms/RemoveUnusedPorts.cpp index 69b9052220..a2916c06db 100644 --- a/lib/Dialect/FIRRTL/Transforms/RemoveUnusedPorts.cpp +++ b/lib/Dialect/FIRRTL/Transforms/RemoveUnusedPorts.cpp @@ -103,7 +103,7 @@ void RemoveUnusedPortsPass::removeUnusedModulePorts( // Replace the port with a wire if it is unused. auto builder = ImplicitLocOpBuilder::atBlockBegin( arg.getLoc(), module.getBodyBlock()); - auto wire = builder.create(arg.getType()); + auto wire = WireOp::create(builder, arg.getType()); arg.replaceAllUsesWith(wire.getResult()); outputPortConstants.push_back(std::nullopt); } else if (arg.hasOneUse()) { @@ -160,7 +160,7 @@ void RemoveUnusedPortsPass::removeUnusedModulePorts( // If the port is input, replace the port with an unwritten wire // so that we can remove use-chains in SV dialect canonicalization. if (ports[index].isInput()) { - WireOp wire = builder.create(result.getType()); + WireOp wire = WireOp::create(builder, result.getType()); // Check that the input port is only written. Sometimes input ports are // used as temporary wires. In that case, we cannot erase connections. @@ -191,9 +191,9 @@ void RemoveUnusedPortsPass::removeUnusedModulePorts( auto portConstant = outputPortConstants[outputPortIndex++]; Value value; if (portConstant) - value = builder.create(*portConstant); + value = ConstantOp::create(builder, *portConstant); else - value = builder.create(result.getType()); + value = InvalidValueOp::create(builder, result.getType()); result.replaceAllUsesWith(value); } diff --git a/lib/Dialect/FIRRTL/Transforms/ResolvePaths.cpp b/lib/Dialect/FIRRTL/Transforms/ResolvePaths.cpp index fdfe29a6ff..e6a3d9b5c8 100644 --- a/lib/Dialect/FIRRTL/Transforms/ResolvePaths.cpp +++ b/lib/Dialect/FIRRTL/Transforms/ResolvePaths.cpp @@ -114,7 +114,7 @@ struct PathResolver { // - i.e. the id is not attached to any target. auto targetKind = TargetKindAttr::get(context, TargetKind::Reference); auto id = DistinctAttr::create(UnitAttr::get(context)); - auto resolved = b.create(targetKind, id); + auto resolved = PathOp::create(b, targetKind, id); unresolved->replaceAllUsesWith(resolved); unresolved.erase(); return success(); @@ -209,7 +209,7 @@ struct PathResolver { // Create a PathOp using the id in the annotation we added to the target. auto dictAttr = cast(annotation); auto id = cast(dictAttr.get("id")); - auto resolved = b.create(targetKindAttr, id); + auto resolved = PathOp::create(b, targetKindAttr, id); // Replace the unresolved path with the PathOp. unresolved->replaceAllUsesWith(resolved); diff --git a/lib/Dialect/FIRRTL/Transforms/ResolveTraces.cpp b/lib/Dialect/FIRRTL/Transforms/ResolveTraces.cpp index d1a8020f4a..043eba2fe5 100644 --- a/lib/Dialect/FIRRTL/Transforms/ResolveTraces.cpp +++ b/lib/Dialect/FIRRTL/Transforms/ResolveTraces.cpp @@ -417,9 +417,9 @@ void ResolveTracesPass::runOnOperation() { else fileAttr = builder.getStringAttr(outputAnnotationFilename); - builder.create(fileAttr, [&] { - builder.create(jsonBuffer, ValueRange{}, - builder.getArrayAttr(symbols)); + emit::FileOp::create(builder, fileAttr, [&] { + sv::VerbatimOp::create(builder, jsonBuffer, ValueRange{}, + builder.getArrayAttr(symbols)); }); return markAllAnalysesPreserved(); diff --git a/lib/Dialect/FIRRTL/Transforms/SFCCompat.cpp b/lib/Dialect/FIRRTL/Transforms/SFCCompat.cpp index 1094ece4c7..779f0d8db1 100644 --- a/lib/Dialect/FIRRTL/Transforms/SFCCompat.cpp +++ b/lib/Dialect/FIRRTL/Transforms/SFCCompat.cpp @@ -82,9 +82,9 @@ void SFCCompatPass::runOnOperation() { return src.isa(); })) { ImplicitLocOpBuilder builder(reg.getLoc(), reg); - RegOp newReg = builder.create( - reg.getResult().getType(), reg.getClockVal(), reg.getNameAttr(), - reg.getNameKindAttr(), reg.getAnnotationsAttr(), + RegOp newReg = RegOp::create( + builder, reg.getResult().getType(), reg.getClockVal(), + reg.getNameAttr(), reg.getNameKindAttr(), reg.getAnnotationsAttr(), reg.getInnerSymAttr(), reg.getForceableAttr()); reg.replaceAllUsesWith(newReg); reg.erase(); @@ -137,17 +137,17 @@ void SFCCompatPass::runOnOperation() { FIRRTLTypeSwitch(inv.getType()) .Case( [&](auto type) -> Value { - return builder.create( - type, builder.getBoolAttr(false)); + return SpecialConstantOp::create(builder, type, + builder.getBoolAttr(false)); }) .Case([&](IntType type) -> Value { - return builder.create(type, getIntZerosAttr(type)); + return ConstantOp::create(builder, type, getIntZerosAttr(type)); }) .Case([&](auto type) -> Value { auto width = circt::firrtl::getBitWidth(type); assert(width && "width must be inferred"); - auto zero = builder.create(APSInt(*width)); - return builder.create(type, zero); + auto zero = ConstantOp::create(builder, APSInt(*width)); + return BitCastOp::create(builder, type, zero); }) .Default([&](auto) { llvm_unreachable("all types are supported"); diff --git a/lib/Dialect/FIRRTL/Transforms/SpecializeOption.cpp b/lib/Dialect/FIRRTL/Transforms/SpecializeOption.cpp index 143880bbc9..e49762737f 100644 --- a/lib/Dialect/FIRRTL/Transforms/SpecializeOption.cpp +++ b/lib/Dialect/FIRRTL/Transforms/SpecializeOption.cpp @@ -79,8 +79,8 @@ struct SpecializeOptionPass target = inst.getTargetOrDefaultAttr(it->second); ImplicitLocOpBuilder builder(inst.getLoc(), inst); - auto newInst = builder.create( - inst->getResultTypes(), target, inst.getNameAttr(), + auto newInst = InstanceOp::create( + builder, inst->getResultTypes(), target, inst.getNameAttr(), inst.getNameKindAttr(), inst.getPortDirectionsAttr(), inst.getPortNamesAttr(), inst.getAnnotationsAttr(), inst.getPortAnnotationsAttr(), builder.getArrayAttr({}), diff --git a/lib/Dialect/FIRRTL/Transforms/VBToBV.cpp b/lib/Dialect/FIRRTL/Transforms/VBToBV.cpp index e7aaaa6e4d..8c2ff1b9fa 100644 --- a/lib/Dialect/FIRRTL/Transforms/VBToBV.cpp +++ b/lib/Dialect/FIRRTL/Transforms/VBToBV.cpp @@ -297,7 +297,7 @@ Value Visitor::getSubfield(Value input, unsigned index) { OpBuilder builder(context); builder.setInsertionPointAfterValue(input); - result = builder.create(input.getLoc(), input, index); + result = SubfieldOp::create(builder, input.getLoc(), input, index); return result; } @@ -308,7 +308,7 @@ Value Visitor::getSubindex(Value input, unsigned index) { OpBuilder builder(context); builder.setInsertionPointAfterValue(input); - result = builder.create(input.getLoc(), input, index); + result = SubindexOp::create(builder, input.getLoc(), input, index); return result; } @@ -317,7 +317,7 @@ Value Visitor::getSubaccess(Operation *place, Value input, Value index) { if (result) return result; OpBuilder builder(place); - result = builder.create(input.getLoc(), input, index); + result = SubaccessOp::create(builder, input.getLoc(), input, index); return result; } @@ -327,7 +327,7 @@ Value Visitor::getRefSub(Value input, unsigned index) { return result; OpBuilder builder(context); builder.setInsertionPointAfterValue(input); - result = builder.create(input.getLoc(), input, index); + result = RefSubOp::create(builder, input.getLoc(), input, index); return result; } @@ -342,7 +342,7 @@ void Visitor::explodeRef(Value value, SmallVectorImpl &output) { for (size_t i = 0, e = bundleType.getNumElements(); i < e; ++i) { OpBuilder builder(context); builder.setInsertionPointAfterValue(value); - auto field = builder.create(value.getLoc(), value, i); + auto field = RefSubOp::create(builder, value.getLoc(), value, i); explodeRef(field, output); } return; @@ -631,7 +631,7 @@ void Visitor::emitExplodedConnect(ImplicitLocOpBuilder &builder, Type type, auto rhs = *rhsIt++; if (flip) std::swap(lhs, rhs); - builder.create(lhs, rhs); + Op::create(builder, lhs, rhs); }; explodeConnect(explodeConnect, type); } @@ -645,7 +645,7 @@ Value Visitor::emitBundleCreate(ImplicitLocOpBuilder &builder, Type type, for (auto element : bundleType.getElements()) { fields.push_back(self(self, element.type)); } - return builder.create(type, fields); + return BundleCreateOp::create(builder, type, fields); } return *(it++); }; @@ -677,12 +677,12 @@ void Visitor::handleConnect(Op op) { if (rhsExploded) { if (auto baseType = type_dyn_cast(type); baseType && baseType.isPassive()) { - builder.create(lhs[0], emitBundleCreate(builder, type, rhs)); + Op::create(builder, lhs[0], emitBundleCreate(builder, type, rhs)); } else { emitExplodedConnect(builder, type, explode(lhs[0]), rhs); } } else { - builder.create(lhs[0], rhs[0]); + Op::create(builder, lhs[0], rhs[0]); } } @@ -777,7 +777,7 @@ LogicalResult Visitor::visitExpr(AggregateConstantOp op) { OpBuilder builder(op); auto newOp = - builder.create(op.getLoc(), newType, fields); + AggregateConstantOp::create(builder, op.getLoc(), newType, fields); valueMap[oldValue] = newOp.getResult(); toDelete.push_back(op); @@ -807,11 +807,11 @@ Value Visitor::sinkVecDimIntoOperands(ImplicitLocOpBuilder &builder, type_cast(newField.getType())); } auto newType = BundleType::get(builder.getContext(), newElements); - auto newBundle = builder.create(newType, newFields); + auto newBundle = BundleCreateOp::create(builder, newType, newFields); return newBundle; } auto newType = FVectorType::get(type, length); - return builder.create(newType, values); + return VectorCreateOp::create(builder, newType, values); } LogicalResult Visitor::visitExpr(VectorCreateOp op) { @@ -837,7 +837,7 @@ LogicalResult Visitor::visitExpr(VectorCreateOp op) { } auto newOp = - builder.create(op.getLoc(), newType, newFields); + VectorCreateOp::create(builder, op.getLoc(), newType, newFields); valueMap[op.getResult()] = newOp.getResult(); toDelete.push_back(op); return success(); @@ -895,7 +895,7 @@ LogicalResult Visitor::visitExpr(RefResolveOp op) { valueMap[op.getResult()] = op.getResult(); return success(); } - auto value = builder.create(convertType(op.getType()), ref) + auto value = RefResolveOp::create(builder, convertType(op.getType()), ref) .getResult(); valueMap[op.getResult()] = value; toDelete.push_back(op); @@ -905,10 +905,10 @@ LogicalResult Visitor::visitExpr(RefResolveOp op) { auto type = convertType(op.getType()); SmallVector values; for (auto ref : refs) { - values.push_back(builder - .create( + values.push_back( + RefResolveOp::create(builder, type_cast(ref.getType()).getType(), ref) - .getResult()); + .getResult()); } auto value = emitBundleCreate(builder, type, values); valueMap[op.getResult()] = value; diff --git a/lib/Dialect/FSM/FSMGraph.cpp b/lib/Dialect/FSM/FSMGraph.cpp index b896dbcc18..eaf8fa87bc 100644 --- a/lib/Dialect/FSM/FSMGraph.cpp +++ b/lib/Dialect/FSM/FSMGraph.cpp @@ -85,7 +85,7 @@ FSMStateNode *FSMGraph::createState(OpBuilder &builder, Location loc, StringRef name) { OpBuilder::InsertionGuard g(builder); builder.setInsertionPointToEnd(&getMachine().getBody().front()); - auto stateOp = builder.create(loc, name); + auto stateOp = StateOp::create(builder, loc, name); return getOrAddState(stateOp); } @@ -96,7 +96,7 @@ FSMTransitionEdge *FSMGraph::createTransition(OpBuilder &builder, Location loc, OpBuilder::InsertionGuard g(builder); // Set the insertion point to the end of the transitions. builder.setInsertionPointToEnd(&from.getTransitions().getBlocks().front()); - auto transition = builder.create(loc, to); + auto transition = TransitionOp::create(builder, loc, to); return currentStateNode->addTransitionEdge(nextStateNode, transition); } diff --git a/lib/Dialect/FSM/FSMOps.cpp b/lib/Dialect/FSM/FSMOps.cpp index e79d2c42e8..b288e4dab9 100644 --- a/lib/Dialect/FSM/FSMOps.cpp +++ b/lib/Dialect/FSM/FSMOps.cpp @@ -315,7 +315,7 @@ void StateOp::build(OpBuilder &builder, OperationState &state, Region *output = state.addRegion(); output->push_back(new Block()); builder.setInsertionPointToEnd(&output->back()); - builder.create(state.location); + fsm::OutputOp::create(builder, state.location); Region *transitions = state.addRegion(); transitions->push_back(new Block()); state.addAttribute("sym_name", builder.getStringAttr(stateName)); @@ -327,7 +327,7 @@ void StateOp::build(OpBuilder &builder, OperationState &state, Region *output = state.addRegion(); output->push_back(new Block()); builder.setInsertionPointToEnd(&output->back()); - builder.create(state.location, outputs); + fsm::OutputOp::create(builder, state.location, outputs); Region *transitions = state.addRegion(); transitions->push_back(new Block()); state.addAttribute("sym_name", builder.getStringAttr(stateName)); @@ -382,7 +382,7 @@ Block *StateOp::ensureOutput(OpBuilder &builder) { auto *block = new Block(); getOutput().push_back(block); builder.setInsertionPointToStart(block); - builder.create(getLoc()); + fsm::OutputOp::create(builder, getLoc()); } return &getOutput().front(); } @@ -445,7 +445,7 @@ Block *TransitionOp::ensureGuard(OpBuilder &builder) { auto *block = new Block(); getGuard().push_back(block); builder.setInsertionPointToStart(block); - builder.create(getLoc()); + fsm::ReturnOp::create(builder, getLoc()); } return &getGuard().front(); } @@ -492,7 +492,7 @@ LogicalResult TransitionOp::canonicalize(TransitionOp op, // Replace the original return op with a new one without any operands // if the constant is TRUE. rewriter.setInsertionPoint(guardReturn); - rewriter.create(guardReturn.getLoc()); + fsm::ReturnOp::create(rewriter, guardReturn.getLoc()); rewriter.eraseOp(guardReturn); } else { // Erase the whole transition op if the constant is FALSE, because the diff --git a/lib/Dialect/HW/HWDialect.cpp b/lib/Dialect/HW/HWDialect.cpp index 2fb0e4a55f..8b4efdc21e 100644 --- a/lib/Dialect/HW/HWDialect.cpp +++ b/lib/Dialect/HW/HWDialect.cpp @@ -93,24 +93,24 @@ Operation *HWDialect::materializeConstant(OpBuilder &builder, Attribute value, // Integer constants can materialize into hw.constant if (auto intType = dyn_cast(type)) if (auto attrValue = dyn_cast(value)) - return builder.create(loc, type, attrValue); + return ConstantOp::create(builder, loc, type, attrValue); // Aggregate constants. if (auto arrayAttr = dyn_cast(value)) { if (type_isa(type)) - return builder.create(loc, type, arrayAttr); + return AggregateConstantOp::create(builder, loc, type, arrayAttr); } // Parameter expressions materialize into hw.param.value. Block *block = builder.getBlock(); if (!block) return nullptr; - auto parentOp = block->getParentOp(); + auto *parentOp = block->getParentOp(); auto curModule = dyn_cast(parentOp); if (!curModule) curModule = parentOp->getParentOfType(); if (curModule && isValidParameterExpression(value, curModule)) - return builder.create(loc, type, value); + return ParamValueOp::create(builder, loc, type, value); return nullptr; } diff --git a/lib/Dialect/HW/HWOps.cpp b/lib/Dialect/HW/HWOps.cpp index b468eeb16a..6fb1d1b420 100644 --- a/lib/Dialect/HW/HWOps.cpp +++ b/lib/Dialect/HW/HWOps.cpp @@ -792,7 +792,7 @@ void HWModuleOp::build(OpBuilder &builder, OperationState &odsState, modBuilder(builder, accessor); // Create output operands. llvm::SmallVector outputOperands = accessor.getOutputOperands(); - builder.create(odsState.location, outputOperands); + hw::OutputOp::create(builder, odsState.location, outputOperands); } void HWModuleOp::modifyPorts( @@ -1970,8 +1970,8 @@ LogicalResult ArraySliceOp::canonicalize(ArraySliceOp op, if (sliceSize == 1) { // slice(a, n) -> create(a[n]) - auto get = rewriter.create(op.getLoc(), op.getInput(), - op.getLowIndex()); + auto get = ArrayGetOp::create(rewriter, op.getLoc(), op.getInput(), + op.getLowIndex()); rewriter.replaceOpWithNewOp(op, op.getType(), get.getResult()); return success(); @@ -1981,7 +1981,7 @@ LogicalResult ArraySliceOp::canonicalize(ArraySliceOp op, if (!offsetOpt) return failure(); - auto inputOp = op.getInput().getDefiningOp(); + auto *inputOp = op.getInput().getDefiningOp(); if (auto inputSlice = dyn_cast_or_null(inputOp)) { // slice(slice(a, n), m) -> slice(a, n + m) if (inputSlice == op) @@ -1994,7 +1994,7 @@ LogicalResult ArraySliceOp::canonicalize(ArraySliceOp op, uint64_t offset = *offsetOpt + *inputOffsetOpt; auto lowIndex = - rewriter.create(op.getLoc(), inputIndex.getType(), offset); + ConstantOp::create(rewriter, op.getLoc(), inputIndex.getType(), offset); rewriter.replaceOpWithNewOp(op, op.getType(), inputSlice.getInput(), lowIndex); return success(); @@ -2035,10 +2035,11 @@ LogicalResult ArraySliceOp::canonicalize(ArraySliceOp op, } else { // Slice the required bits from the input. unsigned width = inputSize == 1 ? 1 : llvm::Log2_64_Ceil(inputSize); - auto lowIndex = rewriter.create( - op.getLoc(), rewriter.getIntegerType(width), sliceStart); - chunks.push_back(rewriter.create( - op.getLoc(), hw::ArrayType::get(elemTy, cutSize), input, lowIndex)); + auto lowIndex = ConstantOp::create( + rewriter, op.getLoc(), rewriter.getIntegerType(width), sliceStart); + chunks.push_back(ArraySliceOp::create( + rewriter, op.getLoc(), hw::ArrayType::get(elemTy, cutSize), input, + lowIndex)); } sliceStart = 0; @@ -2575,7 +2576,7 @@ OpFoldResult StructExtractOp::fold(FoldAdaptor adaptor) { LogicalResult StructExtractOp::canonicalize(StructExtractOp op, PatternRewriter &rewriter) { - auto inputOp = op.getInput().getDefiningOp(); + auto *inputOp = op.getInput().getDefiningOp(); // b = extract(inject(x["a"], v0)["b"]) => extract(x, "b") if (auto structInject = dyn_cast_or_null(inputOp)) { @@ -2710,8 +2711,8 @@ LogicalResult StructInjectOp::canonicalize(StructInjectOp op, auto it = fields.find(elements[fieldIndex].name); if (it == fields.end()) continue; - input = rewriter.create(op.getLoc(), ty, input, fieldIndex, - it->second); + input = StructInjectOp::create(rewriter, op.getLoc(), ty, input, fieldIndex, + it->second); } rewriter.replaceOp(op, input); @@ -2901,7 +2902,7 @@ LogicalResult ArrayGetOp::canonicalize(ArrayGetOp op, uint64_t offset = *offsetOpt + *idxOpt; auto newOffset = - rewriter.create(op.getLoc(), offsetOp.getType(), offset); + ConstantOp::create(rewriter, op.getLoc(), offsetOp.getType(), offset); rewriter.replaceOpWithNewOp(op, inputSlice.getInput(), newOffset); return success(); @@ -2918,8 +2919,9 @@ LogicalResult ArrayGetOp::canonicalize(ArrayGetOp op, } unsigned indexWidth = size == 1 ? 1 : llvm::Log2_64_Ceil(size); - auto newIdxOp = rewriter.create( - op.getLoc(), rewriter.getIntegerType(indexWidth), elemIndex); + auto newIdxOp = + ConstantOp::create(rewriter, op.getLoc(), + rewriter.getIntegerType(indexWidth), elemIndex); rewriter.replaceOpWithNewOp(op, input, newIdxOp); return success(); diff --git a/lib/Dialect/HW/HWReductions.cpp b/lib/Dialect/HW/HWReductions.cpp index 7f0e2fe985..10d34c9b7e 100644 --- a/lib/Dialect/HW/HWReductions.cpp +++ b/lib/Dialect/HW/HWReductions.cpp @@ -68,9 +68,8 @@ struct ModuleExternalizer : public OpReduction { LogicalResult rewrite(HWModuleOp op) override { OpBuilder builder(op); - builder.create(op->getLoc(), op.getModuleNameAttr(), - op.getPortList(), StringRef(), - op.getParameters()); + HWModuleExternOp::create(builder, op->getLoc(), op.getModuleNameAttr(), + op.getPortList(), StringRef(), op.getParameters()); op->erase(); return success(); } @@ -126,7 +125,7 @@ struct HWConstantifier : public Reduction { OpBuilder builder(op); for (auto result : op->getResults()) { auto type = cast(result.getType()); - auto newOp = builder.create(op->getLoc(), type, 0); + auto newOp = hw::ConstantOp::create(builder, op->getLoc(), type, 0); result.replaceAllUsesWith(newOp); } reduce::pruneUnusedOps(op, *this); diff --git a/lib/Dialect/HW/HierPathCache.cpp b/lib/Dialect/HW/HierPathCache.cpp index a4fe68ba82..03c7f8fd42 100644 --- a/lib/Dialect/HW/HierPathCache.cpp +++ b/lib/Dialect/HW/HierPathCache.cpp @@ -53,8 +53,9 @@ HierPathOp HierPathCache::getOrCreatePath(ArrayAttr pathArray, Location loc, // Create the new HierPathOp and insert it into the pathCache. hw::HierPathOp path = pathCache - .insert({pathArray, builder.create( - loc, ns->newName(nameHint), pathArray)}) + .insert({pathArray, + hw::HierPathOp::create(builder, loc, ns->newName(nameHint), + pathArray)}) .first->second; path.setVisibility(SymbolTable::Visibility::Private); diff --git a/lib/Dialect/HW/PortConverter.cpp b/lib/Dialect/HW/PortConverter.cpp index 748bcabb8c..7252cd2216 100644 --- a/lib/Dialect/HW/PortConverter.cpp +++ b/lib/Dialect/HW/PortConverter.cpp @@ -229,8 +229,8 @@ void PortConverterImpl::updateInstance(hw::InstanceOp inst) { assert(llvm::none_of(newOperands, [](Value v) { return !v; })); b.setInsertionPointAfter(inst); auto newInst = - b.create(mod, inst.getInstanceNameAttr(), newOperands, - inst.getParameters(), inst.getInnerSymAttr()); + InstanceOp::create(b, mod, inst.getInstanceNameAttr(), newOperands, + inst.getParameters(), inst.getInnerSymAttr()); newInst->setDialectAttrs(inst->getDialectAttrs()); // Assign the backedges to the new results. diff --git a/lib/Dialect/HW/Transforms/FlattenIO.cpp b/lib/Dialect/HW/Transforms/FlattenIO.cpp index 9eea25ea82..26e0a72897 100644 --- a/lib/Dialect/HW/Transforms/FlattenIO.cpp +++ b/lib/Dialect/HW/Transforms/FlattenIO.cpp @@ -68,8 +68,8 @@ struct OutputOpConversion : public OpConversionPattern { // Flatten the operands. for (auto operand : adaptor.getOperands()) { if (auto structType = getStructType(operand.getType())) { - auto explodedStruct = rewriter.create( - op.getLoc(), getInnerTypes(structType), operand); + auto explodedStruct = hw::StructExplodeOp::create( + rewriter, op.getLoc(), getInnerTypes(structType), operand); llvm::copy(explodedStruct.getResults(), std::back_inserter(convOperands)); } else { @@ -91,8 +91,8 @@ struct OutputOpConversion : public OpConversionPattern { // Flatten the operands. for (auto operand : flattenValues(adaptor.getOperands())) { if (auto structType = getStructType(operand.getType())) { - auto explodedStruct = rewriter.create( - op.getLoc(), getInnerTypes(structType), operand); + auto explodedStruct = hw::StructExplodeOp::create( + rewriter, op.getLoc(), getInnerTypes(structType), operand); llvm::copy(explodedStruct.getResults(), std::back_inserter(convOperands)); } else { @@ -129,8 +129,8 @@ struct InstanceOpConversion : public OpConversionPattern { llvm::SmallVector convOperands; for (auto operand : flattenValues(adaptor.getOperands())) { if (auto structType = getStructType(operand.getType())) { - auto explodedStruct = rewriter.create( - loc, getInnerTypes(structType), operand); + auto explodedStruct = hw::StructExplodeOp::create( + rewriter, loc, getInnerTypes(structType), operand); llvm::copy(explodedStruct.getResults(), std::back_inserter(convOperands)); } else { @@ -150,8 +150,8 @@ struct InstanceOpConversion : public OpConversionPattern { // Create the new instance with the flattened module, attributes will be // adjusted later. - auto newInstance = rewriter.create( - loc, newResultTypes, op.getInstanceNameAttr(), + auto newInstance = hw::InstanceOp::create( + rewriter, loc, newResultTypes, op.getInstanceNameAttr(), FlatSymbolRefAttr::get(referencedMod), convOperands, op.getArgNamesAttr(), op.getResultNamesAttr(), op.getParametersAttr(), op.getInnerSymAttr(), op.getDoNotPrintAttr()); @@ -164,8 +164,8 @@ struct InstanceOpConversion : public OpConversionPattern { Type oldResultType = op.getResultTypes()[oldResultCntr]; if (auto structType = getStructType(oldResultType)) { size_t nElements = structType.getElements().size(); - auto implodedStruct = rewriter.create( - loc, structType, + auto implodedStruct = hw::StructCreateOp::create( + rewriter, loc, structType, newInstance.getResults().slice(resIndex, nElements)); convResults.push_back(implodedStruct.getResult()); resIndex += nElements - 1; @@ -214,18 +214,18 @@ public: if (inputs.size() != 1 && !isStructType(inputs[0].getType())) return ValueRange(); - auto explodeOp = builder.create(loc, inputs[0]); + auto explodeOp = hw::StructExplodeOp::create(builder, loc, inputs[0]); return ValueRange(explodeOp.getResults()); }); addTargetMaterialization([](OpBuilder &builder, hw::StructType type, ValueRange inputs, Location loc) { - auto result = builder.create(loc, type, inputs); + auto result = hw::StructCreateOp::create(builder, loc, type, inputs); return result.getResult(); }); addTargetMaterialization([](OpBuilder &builder, hw::TypeAliasType type, ValueRange inputs, Location loc) { - auto result = builder.create(loc, type, inputs); + auto result = hw::StructCreateOp::create(builder, loc, type, inputs); return result.getResult(); }); @@ -237,7 +237,7 @@ public: // which persist beyond the conversion. addSourceMaterialization([](OpBuilder &builder, hw::StructType type, ValueRange inputs, Location loc) { - auto result = builder.create(loc, type, inputs); + auto result = hw::StructCreateOp::create(builder, loc, type, inputs); return result.getResult(); }); } diff --git a/lib/Dialect/HW/Transforms/HWAggregateToComb.cpp b/lib/Dialect/HW/Transforms/HWAggregateToComb.cpp index 2004e49065..c9ac7661e0 100644 --- a/lib/Dialect/HW/Transforms/HWAggregateToComb.cpp +++ b/lib/Dialect/HW/Transforms/HWAggregateToComb.cpp @@ -130,7 +130,7 @@ public: if (inputs.size() != 1) return Value(); - return builder.create(loc, resultType, inputs[0]) + return hw::BitcastOp::create(builder, loc, resultType, inputs[0]) ->getResult(0); }); @@ -140,7 +140,7 @@ public: if (inputs.size() != 1) return Value(); - return builder.create(loc, resultType, inputs[0]) + return hw::BitcastOp::create(builder, loc, resultType, inputs[0]) ->getResult(0); }); } diff --git a/lib/Dialect/HW/Transforms/HWSpecialize.cpp b/lib/Dialect/HW/Transforms/HWSpecialize.cpp index 42a3362287..23bb03a7f3 100644 --- a/lib/Dialect/HW/Transforms/HWSpecialize.cpp +++ b/lib/Dialect/HW/Transforms/HWSpecialize.cpp @@ -70,13 +70,11 @@ static FailureOr narrowValueToArrayWidth(OpBuilder &builder, Value array, unsigned hiBit = llvm::Log2_64_Ceil(arrayType.getNumElements()); return hiBit == 0 - ? builder - .create(value.getLoc(), - APInt(arrayType.getNumElements(), 0)) + ? hw::ConstantOp::create(builder, value.getLoc(), + APInt(arrayType.getNumElements(), 0)) .getResult() - : builder - .create(value.getLoc(), value, - /*lowBit=*/0, hiBit) + : comb::ExtractOp::create(builder, value.getLoc(), value, + /*lowBit=*/0, hiBit) .getResult(); } @@ -299,8 +297,8 @@ static LogicalResult specializeModule( } // Create the specialized module using the evaluated port info. - target = builder.create( - source.getLoc(), + target = HWModuleOp::create( + builder, source.getLoc(), StringAttr::get(ctx, generateModuleName(ns, source, parameters)), ports); // Erase the default created hw.output op - we'll copy the correct operation diff --git a/lib/Dialect/Handshake/HandshakeOps.cpp b/lib/Dialect/Handshake/HandshakeOps.cpp index b20a666810..04b0daf338 100644 --- a/lib/Dialect/Handshake/HandshakeOps.cpp +++ b/lib/Dialect/Handshake/HandshakeOps.cpp @@ -206,8 +206,8 @@ struct EliminateUnusedForkResultsPattern : mlir::OpRewritePattern { // Create a new fork op, dropping the unused results. rewriter.setInsertionPoint(op); auto operand = op.getOperand(); - auto newFork = rewriter.create( - op.getLoc(), operand, op.getNumResults() - unusedIndexes.size()); + auto newFork = ForkOp::create(rewriter, op.getLoc(), operand, + op.getNumResults() - unusedIndexes.size()); unsigned i = 0; for (auto oldRes : llvm::enumerate(op.getResults())) if (unusedIndexes.count(oldRes.index()) == 0) @@ -233,8 +233,9 @@ struct EliminateForkToForkPattern : mlir::OpRewritePattern { unsigned totalNumOuts = op.getSize() + parentForkOp.getSize(); /// Create a new parent fork op which produces all of the fork outputs and /// replace all of the uses of the old results. - auto newParentForkOp = rewriter.create( - parentForkOp.getLoc(), parentForkOp.getOperand(), totalNumOuts); + auto newParentForkOp = + ForkOp::create(rewriter, parentForkOp.getLoc(), + parentForkOp.getOperand(), totalNumOuts); for (auto it : llvm::zip(parentForkOp->getResults(), newParentForkOp.getResults())) @@ -730,7 +731,7 @@ LogicalResult EliminateSimpleControlMergesPattern::matchAndRewrite( return failure(); } - auto merge = rewriter.create(op.getLoc(), op.getDataOperands()); + auto merge = MergeOp::create(rewriter, op.getLoc(), op.getDataOperands()); for (auto &use : llvm::make_early_inc_range(dataResult.getUses())) { auto *user = use.getOwner(); diff --git a/lib/Dialect/Handshake/HandshakeUtils.cpp b/lib/Dialect/Handshake/HandshakeUtils.cpp index d4aa8465eb..12398841a9 100644 --- a/lib/Dialect/Handshake/HandshakeUtils.cpp +++ b/lib/Dialect/Handshake/HandshakeUtils.cpp @@ -256,9 +256,9 @@ void circt::handshake::insertFork(Value result, bool isLazy, auto forkSize = opsToProcess.size(); Operation *newOp; if (isLazy) - newOp = rewriter.create(result.getLoc(), result, forkSize); + newOp = LazyForkOp::create(rewriter, result.getLoc(), result, forkSize); else - newOp = rewriter.create(result.getLoc(), result, forkSize); + newOp = ForkOp::create(rewriter, result.getLoc(), result, forkSize); // Modify operands of successor // opsToProcess may have multiple instances of same operand diff --git a/lib/Dialect/Handshake/Transforms/Buffers.cpp b/lib/Dialect/Handshake/Transforms/Buffers.cpp index 1c88100764..311de804cf 100644 --- a/lib/Dialect/Handshake/Transforms/Buffers.cpp +++ b/lib/Dialect/Handshake/Transforms/Buffers.cpp @@ -73,7 +73,7 @@ static void insertBuffer(Location loc, Value operand, OpBuilder &builder, auto ip = builder.saveInsertionPoint(); builder.setInsertionPointAfterValue(operand); auto bufferOp = - builder.create(loc, operand, numSlots, bufferType); + handshake::BufferOp::create(builder, loc, operand, numSlots, bufferType); operand.replaceUsesWithIf( bufferOp, function_ref([](OpOperand &operand) -> bool { return !isa(operand.getOwner()); diff --git a/lib/Dialect/Handshake/Transforms/LegalizeMemrefs.cpp b/lib/Dialect/Handshake/Transforms/LegalizeMemrefs.cpp index e70ba9c2af..77b407d80e 100644 --- a/lib/Dialect/Handshake/Transforms/LegalizeMemrefs.cpp +++ b/lib/Dialect/Handshake/Transforms/LegalizeMemrefs.cpp @@ -71,25 +71,25 @@ struct HandshakeLegalizeMemrefsPass auto emitLoadStore = [&](Value index) { llvm::SmallVector indices = {index}; - auto loadValue = b.create(loc, src, indices); - b.create(loc, loadValue, dst, indices); + auto loadValue = memref::LoadOp::create(b, loc, src, indices); + memref::StoreOp::create(b, loc, loadValue, dst, indices); }; auto n = memrefType.getShape()[0]; if (n > 1) { - auto lb = b.create(loc, 0).getResult(); - auto ub = b.create(loc, n).getResult(); - auto step = b.create(loc, 1).getResult(); + auto lb = arith::ConstantIndexOp::create(b, loc, 0).getResult(); + auto ub = arith::ConstantIndexOp::create(b, loc, n).getResult(); + auto step = arith::ConstantIndexOp::create(b, loc, 1).getResult(); - b.create( - loc, lb, ub, step, llvm::SmallVector(), + scf::ForOp::create( + b, loc, lb, ub, step, llvm::SmallVector(), [&](OpBuilder &b, Location loc, Value iv, ValueRange loopState) { emitLoadStore(iv); - b.create(loc); + scf::YieldOp::create(b, loc); }); } else - emitLoadStore(b.create(loc, 0)); + emitLoadStore(arith::ConstantIndexOp::create(b, loc, 0)); copy.erase(); } diff --git a/lib/Dialect/Handshake/Transforms/LockFunctions.cpp b/lib/Dialect/Handshake/Transforms/LockFunctions.cpp index fea4635b9c..e1639e5747 100644 --- a/lib/Dialect/Handshake/Transforms/LockFunctions.cpp +++ b/lib/Dialect/Handshake/Transforms/LockFunctions.cpp @@ -45,8 +45,8 @@ static LogicalResult lockRegion(Region &r, OpBuilder &rewriter) { BackedgeBuilder bebuilder(rewriter, loc); auto backEdge = bebuilder.get(rewriter.getNoneType()); - auto buff = rewriter.create(loc, backEdge, 1, - BufferTypeEnum::seq); + auto buff = handshake::BufferOp::create(rewriter, loc, backEdge, 1, + BufferTypeEnum::seq); // Dummy value that causes a buffer initialization, but itself does not have a // semantic meaning. @@ -55,7 +55,7 @@ static LogicalResult lockRegion(Region &r, OpBuilder &rewriter) { SmallVector inSyncOperands = llvm::to_vector_of(entry->getArguments()); inSyncOperands.push_back(buff); - auto sync = rewriter.create(loc, inSyncOperands); + auto sync = SyncOp::create(rewriter, loc, inSyncOperands); // replace all func arg usages with the synced ones // TODO is this UB? @@ -67,7 +67,7 @@ static LogicalResult lockRegion(Region &r, OpBuilder &rewriter) { SmallVector endJoinOperands = llvm::to_vector(ret->getOperands()); // Add the axilirary control signal output to the end-join endJoinOperands.push_back(sync.getResults().back()); - auto endJoin = rewriter.create(loc, endJoinOperands); + auto endJoin = JoinOp::create(rewriter, loc, endJoinOperands); backEdge.setValue(endJoin); return success(); diff --git a/lib/Dialect/Handshake/Transforms/LowerExtmemToHW.cpp b/lib/Dialect/Handshake/Transforms/LowerExtmemToHW.cpp index cd6894b60b..3051688916 100644 --- a/lib/Dialect/Handshake/Transforms/LowerExtmemToHW.cpp +++ b/lib/Dialect/Handshake/Transforms/LowerExtmemToHW.cpp @@ -152,8 +152,8 @@ LogicalResult HandshakeLowerExtmemToHWPass::wrapESI( b.setInsertionPoint(func); auto newPortInfo = handshake::getPortInfoForOpTypes( func, func.getArgumentTypes(), func.getResultTypes()); - auto extMod = b.create( - loc, StringAttr::get(ctx, "__" + func.getName() + "_hw"), newPortInfo); + auto extMod = hw::HWModuleExternOp::create( + b, loc, StringAttr::get(ctx, "__" + func.getName() + "_hw"), newPortInfo); // Add an attribute to the original handshake function to indicate that it // needs to resolve to extMod in a later pass. @@ -168,8 +168,8 @@ LogicalResult HandshakeLowerExtmemToHWPass::wrapESI( [](auto &pair) { return pair.first; }); for (auto i : llvm::reverse(argReplacementsIdxs)) wrapperModPortInfo.eraseInput(i); - auto wrapperMod = b.create( - loc, StringAttr::get(ctx, func.getName() + "_esi_wrapper"), + auto wrapperMod = hw::HWModuleOp::create( + b, loc, StringAttr::get(ctx, func.getName() + "_esi_wrapper"), wrapperModPortInfo); Value clk = wrapperMod.getBodyBlock()->getArgument( wrapperMod.getBodyBlock()->getNumArguments() - 2); @@ -204,8 +204,8 @@ LogicalResult HandshakeLowerExtmemToHWPass::wrapESI( auto dataType = memType.memRefType.getElementType(); assert(memrefShape.size() == 1 && "Only 1D memrefs are supported"); unsigned memrefSize = memrefShape[0]; - auto memServiceDecl = b.create( - loc, origPortInfo.name, TypeAttr::get(dataType), + auto memServiceDecl = esi::RandomAccessMemoryDeclOp::create( + b, loc, origPortInfo.name, TypeAttr::get(dataType), b.getI64IntegerAttr(memrefSize)); esi::ServicePortInfo writePortInfo = memServiceDecl.writePortInfo(); esi::ServicePortInfo readPortInfo = memServiceDecl.readPortInfo(); @@ -218,11 +218,11 @@ LogicalResult HandshakeLowerExtmemToHWPass::wrapESI( // Load ports: for (unsigned i = 0; i < memType.loadPorts; ++i) { - auto req = b.create( - loc, readPortInfo.type, readPortInfo.port, + auto req = esi::RequestConnectionOp::create( + b, loc, readPortInfo.type, readPortInfo.port, esi::AppIDAttr::get(ctx, b.getStringAttr("load"), resIdx)); - auto reqUnpack = b.create( - loc, req.getToClient(), ValueRange{backedges[resIdx]}); + auto reqUnpack = esi::UnpackBundleOp::create( + b, loc, req.getToClient(), ValueRange{backedges[resIdx]}); instanceArgsFromThisMem.push_back( reqUnpack.getToChannels() [esi::RandomAccessMemoryDeclOp::RespDirChannelIdx]); @@ -231,11 +231,11 @@ LogicalResult HandshakeLowerExtmemToHWPass::wrapESI( // Store ports: for (unsigned i = 0; i < memType.storePorts; ++i) { - auto req = b.create( - loc, writePortInfo.type, writePortInfo.port, + auto req = esi::RequestConnectionOp::create( + b, loc, writePortInfo.type, writePortInfo.port, esi::AppIDAttr::get(ctx, b.getStringAttr("store"), resIdx)); - auto reqUnpack = b.create( - loc, req.getToClient(), ValueRange{backedges[resIdx]}); + auto reqUnpack = esi::UnpackBundleOp::create( + b, loc, req.getToClient(), ValueRange{backedges[resIdx]}); instanceArgsFromThisMem.push_back( reqUnpack.getToChannels() [esi::RandomAccessMemoryDeclOp::RespDirChannelIdx]); @@ -280,7 +280,7 @@ LogicalResult HandshakeLowerExtmemToHWPass::wrapESI( // Instantiate the inner module. auto instance = - b.create(loc, extMod, func.getName(), instanceArgs); + hw::InstanceOp::create(b, loc, extMod, func.getName(), instanceArgs); // And resolve the backedges. for (auto [res, be] : llvm::zip(instance.getResults(), backedges)) @@ -291,8 +291,8 @@ LogicalResult HandshakeLowerExtmemToHWPass::wrapESI( auto outputOp = cast(wrapperMod.getBodyBlock()->getTerminator()); b.setInsertionPoint(outputOp); - b.create( - outputOp.getLoc(), + hw::OutputOp::create( + b, outputOp.getLoc(), instance.getResults().take_front(wrapperMod.getNumOutputPorts())); outputOp.erase(); @@ -307,7 +307,7 @@ static Value truncateToMemoryWidth(Location loc, OpBuilder &b, Value v, MemRefType memRefType) { assert(isa(v.getType()) && "Expected an index-typed value"); auto addrWidth = llvm::Log2_64_Ceil(memRefType.getShape().front()); - return b.create(loc, b.getIntegerType(addrWidth), v); + return arith::IndexCastOp::create(b, loc, b.getIntegerType(addrWidth), v); } static Value plumbLoadPort(Location loc, OpBuilder &b, @@ -316,11 +316,11 @@ static Value plumbLoadPort(Location loc, OpBuilder &b, // We need to feed both the load data and the load done outputs. // Fork the extracted load data into two, and 'join' the second one to // generate a none-typed output to drive the load done. - auto dataFork = b.create(loc, loadData, 2); + auto dataFork = ForkOp::create(b, loc, loadData, 2); auto dataOut = dataFork.getResult()[0]; llvm::SmallVector joinArgs = {dataFork.getResult()[1]}; - auto dataDone = b.create(loc, joinArgs); + auto dataDone = JoinOp::create(b, loc, joinArgs); ldif.dataOut.replaceAllUsesWith(dataOut); ldif.doneOut.replaceAllUsesWith(dataDone); @@ -339,9 +339,8 @@ static Value plumbStorePort(Location loc, OpBuilder &b, llvm::SmallVector structArgs = { truncateToMemoryWidth(loc, b, stif.addressIn, memrefType), stif.dataIn}; - return b - .create(loc, cast(outType), - structArgs) + return hw::StructCreateOp::create(b, loc, cast(outType), + structArgs) .getResult(); } @@ -469,7 +468,7 @@ HandshakeLowerExtmemToHWPass::lowerExtmemToHW(handshake::FuncOp func) { // Replace the return op of the function with a new one that returns the // memory output struct. b.setInsertionPoint(oldReturnOp); - b.create(arg.getLoc(), newReturnOperands); + ReturnOp::create(b, arg.getLoc(), newReturnOperands); oldReturnOp.erase(); // Erase the extmemory operation since I/O plumbing has replaced all of its diff --git a/lib/Dialect/Handshake/Transforms/Materialization.cpp b/lib/Dialect/Handshake/Transforms/Materialization.cpp index 4617c28024..7b9c613609 100644 --- a/lib/Dialect/Handshake/Transforms/Materialization.cpp +++ b/lib/Dialect/Handshake/Transforms/Materialization.cpp @@ -43,7 +43,7 @@ using BlockValues = DenseMap>; static void insertSink(Value val, OpBuilder &rewriter) { rewriter.setInsertionPointAfterValue(val); - rewriter.create(val.getLoc(), val); + SinkOp::create(rewriter, val.getLoc(), val); } /// Insert Fork Operation for every operation and function argument with more diff --git a/lib/Dialect/Handshake/Transforms/SplitMerges.cpp b/lib/Dialect/Handshake/Transforms/SplitMerges.cpp index fe14184a59..bdff15d44e 100644 --- a/lib/Dialect/Handshake/Transforms/SplitMerges.cpp +++ b/lib/Dialect/Handshake/Transforms/SplitMerges.cpp @@ -46,8 +46,9 @@ struct DeconstructMergePattern : public OpRewritePattern { while (mergeInputs.size() > 1) { llvm::SmallVector newMergeInputs; for (unsigned i = 0, e = mergeInputs.size(); i < ((e / 2) * 2); i += 2) { - auto cm2 = rewriter.create( - mergeOp.getLoc(), ValueRange{mergeInputs[i], mergeInputs[i + 1]}); + auto cm2 = handshake::MergeOp::create( + rewriter, mergeOp.getLoc(), + ValueRange{mergeInputs[i], mergeInputs[i + 1]}); newMergeInputs.push_back(cm2.getResult()); } if (mergeInputs.size() % 2 != 0) @@ -79,20 +80,21 @@ struct DeconstructCMergePattern // tuple from two operands and an index offset. auto mergeTwoOperands = [&](Value op0, Value op1, unsigned idxOffset) -> Value { - auto cm2 = rewriter.create( - loc, ValueRange{op0, op1}, cmergeIndexType); + auto cm2 = handshake::ControlMergeOp::create( + rewriter, loc, ValueRange{op0, op1}, cmergeIndexType); Value idxOperand = cm2.getIndex(); if (idxOffset != 0) { // Non-zero index offset; add it to the index operand. - idxOperand = rewriter.create( - loc, idxOperand, - rewriter.create( - loc, rewriter.getIntegerAttr(cmergeIndexType, idxOffset))); + idxOperand = arith::AddIOp::create( + rewriter, loc, idxOperand, + arith::ConstantOp::create( + rewriter, loc, + rewriter.getIntegerAttr(cmergeIndexType, idxOffset))); } // Pack index and data into a tuple s.t. they share control. - return rewriter.create( - loc, ValueRange{cm2.getResult(), idxOperand}); + return handshake::PackOp::create(rewriter, loc, + ValueRange{cm2.getResult(), idxOperand}); }; llvm::SmallVector packedTuples; @@ -106,16 +108,17 @@ struct DeconstructCMergePattern // If there is an odd number of operands, the last operand becomes a tuple // of itself with an index of the number of operands - 1. unsigned lastIdx = cmergeOp.getNumOperands() - 1; - packedTuples.push_back(rewriter.create( - loc, ValueRange{cmergeOp.getOperand(lastIdx), - rewriter.create( - loc, rewriter.getIntegerAttr(cmergeIndexType, - lastIdx))})); + packedTuples.push_back(handshake::PackOp::create( + rewriter, loc, + ValueRange{cmergeOp.getOperand(lastIdx), + arith::ConstantOp::create( + rewriter, loc, + rewriter.getIntegerAttr(cmergeIndexType, lastIdx))})); } // Non-deterministically merge the tuples and unpack the result. auto mergedTuple = - rewriter.create(loc, ValueRange(packedTuples)); + handshake::MergeOp::create(rewriter, loc, ValueRange(packedTuples)); // And finally, replace the original cmerge with the unpacked result. rewriter.replaceOpWithNewOp(cmergeOp, diff --git a/lib/Dialect/Kanagawa/Transforms/KanagawaAddOperatorLibrary.cpp b/lib/Dialect/Kanagawa/Transforms/KanagawaAddOperatorLibrary.cpp index 88c3304656..5582508dde 100644 --- a/lib/Dialect/Kanagawa/Transforms/KanagawaAddOperatorLibrary.cpp +++ b/lib/Dialect/Kanagawa/Transforms/KanagawaAddOperatorLibrary.cpp @@ -47,8 +47,8 @@ struct AddOperatorLibraryPass // avoid passing the builder around. template void addOperator(ImplicitLocOpBuilder &b, int latency) { - b.create( - b.getStringAttr(TOp::getOperationName()), + ssp::OperatorTypeOp::create( + b, b.getStringAttr(TOp::getOperationName()), b.getArrayAttr({b.getAttr(latency)})); } @@ -57,7 +57,7 @@ void addOperator(ImplicitLocOpBuilder &b, int latency) { void AddOperatorLibraryPass::runOnOperation() { auto b = ImplicitLocOpBuilder::atBlockBegin(getOperation().getLoc(), getOperation().getBody()); - auto opLib = b.create(); + auto opLib = ssp::OperatorLibraryOp::create(b); opLib.setSymNameAttr(b.getStringAttr(kKanagawaOperatorLibName)); b.setInsertionPointToStart(opLib.getBodyBlock()); diff --git a/lib/Dialect/Kanagawa/Transforms/KanagawaArgifyBlocksPass.cpp b/lib/Dialect/Kanagawa/Transforms/KanagawaArgifyBlocksPass.cpp index 6c5cb750bc..4cb5aa34c2 100644 --- a/lib/Dialect/Kanagawa/Transforms/KanagawaArgifyBlocksPass.cpp +++ b/lib/Dialect/Kanagawa/Transforms/KanagawaArgifyBlocksPass.cpp @@ -57,9 +57,9 @@ struct BlockConversionPattern : public OpConversionPattern { getExternallyDefinedOperands(blockOp, mapping); Block *bodyBlock = blockOp.getBodyBlock(); - auto isolatedBlock = rewriter.create( - blockOp.getLoc(), blockOp.getResultTypes(), blockOp.getOperands(), - blockOp.getMaxThreadsAttr()); + auto isolatedBlock = IsolatedStaticBlockOp::create( + rewriter, blockOp.getLoc(), blockOp.getResultTypes(), + blockOp.getOperands(), blockOp.getMaxThreadsAttr()); // Erase the default terminator. Block *isolatedBlockBody = isolatedBlock.getBodyBlock(); rewriter.eraseOp(isolatedBlockBody->getTerminator()); diff --git a/lib/Dialect/Kanagawa/Transforms/KanagawaCallPrep.cpp b/lib/Dialect/Kanagawa/Transforms/KanagawaCallPrep.cpp index 3f4ccca8ca..5541eabb2b 100644 --- a/lib/Dialect/Kanagawa/Transforms/KanagawaCallPrep.cpp +++ b/lib/Dialect/Kanagawa/Transforms/KanagawaCallPrep.cpp @@ -140,8 +140,8 @@ MergeCallArgs::matchAndRewrite(CallOp call, OpAdaptor adaptor, auto [argStruct, argLoc] = argStructEntry->second; // Pack all of the operands into it. - auto newArg = rewriter.create(loc, argStruct, - adaptor.getOperands()); + auto newArg = hw::StructCreateOp::create(rewriter, loc, argStruct, + adaptor.getOperands()); newArg->setAttr("sv.namehint", rewriter.getStringAttr(call.getCallee().getName().getValue() + "_args_called_from_" + @@ -190,8 +190,8 @@ MergeMethodArgs::matchAndRewrite(MethodOp func, OpAdaptor adaptor, FunctionType::get(ctxt, {argStruct}, funcType.getResults()); auto newArgNames = ArrayAttr::get(ctxt, {StringAttr::get(ctxt, "arg")}); auto newMethod = - rewriter.create(loc, func.getInnerSym(), newFuncType, - newArgNames, ArrayAttr(), ArrayAttr()); + MethodOp::create(rewriter, loc, func.getInnerSym(), newFuncType, + newArgNames, ArrayAttr(), ArrayAttr()); if (func->getNumRegions() > 0) { // Create a body block with a struct explode to the arg struct into the @@ -200,7 +200,7 @@ MergeMethodArgs::matchAndRewrite(MethodOp func, OpAdaptor adaptor, rewriter.createBlock(&newMethod.getRegion(), {}, {argStruct}, {argLoc}); rewriter.setInsertionPointToStart(b); auto replacementArgs = - rewriter.create(loc, b->getArgument(0)); + hw::StructExplodeOp::create(rewriter, loc, b->getArgument(0)); // Merge the original method body, rewiring the args. Block *funcBody = &func.getBody().front(); diff --git a/lib/Dialect/Kanagawa/Transforms/KanagawaCleanSelfdrivers.cpp b/lib/Dialect/Kanagawa/Transforms/KanagawaCleanSelfdrivers.cpp index fbb91faf0e..4ec5c1d33c 100644 --- a/lib/Dialect/Kanagawa/Transforms/KanagawaCleanSelfdrivers.cpp +++ b/lib/Dialect/Kanagawa/Transforms/KanagawaCleanSelfdrivers.cpp @@ -151,8 +151,8 @@ struct InputPortOpConversionPattern : public OpConversionPattern { } // Create a `hw.wire` to ensure that the input port name is maintained. - auto wire = rewriter.create(op.getLoc(), writer.getValue(), - op.getInnerSymAttrName()); + auto wire = hw::WireOp::create(rewriter, op.getLoc(), writer.getValue(), + op.getInnerSymAttrName()); // Replace all reads of the input port with the wire. for (auto reader : readers) @@ -176,9 +176,10 @@ struct InputPortOpConversionPattern : public OpConversionPattern { }); if (anyOutsideReads) { - auto outputPort = rewriter.create( - op.getLoc(), op.getInnerSym(), op.getType(), op.getNameAttr()); - rewriter.create(op.getLoc(), outputPort, wire); + auto outputPort = + OutputPortOp::create(rewriter, op.getLoc(), op.getInnerSym(), + op.getType(), op.getNameAttr()); + PortWriteOp::create(rewriter, op.getLoc(), outputPort, wire); } } diff --git a/lib/Dialect/Kanagawa/Transforms/KanagawaContainerize.cpp b/lib/Dialect/Kanagawa/Transforms/KanagawaContainerize.cpp index 50aef7cc41..a423666224 100644 --- a/lib/Dialect/Kanagawa/Transforms/KanagawaContainerize.cpp +++ b/lib/Dialect/Kanagawa/Transforms/KanagawaContainerize.cpp @@ -53,16 +53,16 @@ struct OutlineContainerPattern : public OpConversionPattern { StringAttr newContainerName = rewriter.getStringAttr( ns.newName(parentClass.getInnerNameAttr().strref() + "_" + op.getInnerNameAttr().strref())); - auto newContainer = rewriter.create( - op.getLoc(), newContainerName, /*isTopLevel=*/false); + auto newContainer = ContainerOp::create( + rewriter, op.getLoc(), newContainerName, /*isTopLevel=*/false); rewriter.mergeBlocks(op.getBodyBlock(), newContainer.getBodyBlock(), {}); // Create a container instance op in the parent class. rewriter.setInsertionPoint(op); - rewriter.create( - parentClass.getLoc(), hw::InnerSymAttr::get(newContainerName), - newContainer.getInnerRef()); + ContainerInstanceOp::create(rewriter, parentClass.getLoc(), + hw::InnerSymAttr::get(newContainerName), + newContainer.getInnerRef()); rewriter.eraseOp(op); return success(); } @@ -78,8 +78,8 @@ struct ClassToContainerPattern : public OpConversionPattern { ConversionPatternRewriter &rewriter) const override { // Replace the class by a container of the same name. auto newContainer = - rewriter.create(op.getLoc(), op.getInnerSymAttr(), - /*topLevel*/ false, op.getNameAttr()); + ContainerOp::create(rewriter, op.getLoc(), op.getInnerSymAttr(), + /*topLevel*/ false, op.getNameAttr()); rewriter.mergeBlocks(op.getBodyBlock(), newContainer.getBodyBlock(), {}); rewriter.eraseOp(op); return success(); diff --git a/lib/Dialect/Kanagawa/Transforms/KanagawaContainersToHW.cpp b/lib/Dialect/Kanagawa/Transforms/KanagawaContainersToHW.cpp index 18f211c8a3..3693871cb1 100644 --- a/lib/Dialect/Kanagawa/Transforms/KanagawaContainersToHW.cpp +++ b/lib/Dialect/Kanagawa/Transforms/KanagawaContainersToHW.cpp @@ -137,7 +137,7 @@ struct ContainerOpConversionPattern : public OpConversionPattern { const ContainerPortInfo &cpi = portOrder.at(op.getInnerRef()); auto hwMod = - rewriter.create(op.getLoc(), hwmodName, *cpi.hwPorts); + hw::HWModuleOp::create(rewriter, op.getLoc(), hwmodName, *cpi.hwPorts); modSymMap[op.getInnerRef()] = hwMod.getSymNameAttr(); hw::OutputOp outputOp = @@ -183,7 +183,7 @@ struct ContainerOpConversionPattern : public OpConversionPattern { // Rewrite the hw.output op. rewriter.eraseOp(outputOp); rewriter.setInsertionPointToEnd(hwMod.getBodyBlock()); - outputOp = rewriter.create(op.getLoc(), outputValues); + outputOp = hw::OutputOp::create(rewriter, op.getLoc(), outputValues); rewriter.eraseOp(op); return success(); } @@ -299,9 +299,9 @@ struct ContainerInstanceOpConversionPattern // Create the hw.instance op. StringRef moduleName = modSymMap[op.getTargetNameAttr()]; - auto hwInst = rewriter.create( - op.getLoc(), retTypes, op.getInnerSym().getSymName(), moduleName, - operands, rewriter.getArrayAttr(argNames), + auto hwInst = hw::InstanceOp::create( + rewriter, op.getLoc(), retTypes, op.getInnerSym().getSymName(), + moduleName, operands, rewriter.getArrayAttr(argNames), rewriter.getArrayAttr(resNames), /*parameters*/ rewriter.getArrayAttr({}), /*innerSym*/ nullptr); diff --git a/lib/Dialect/Kanagawa/Transforms/KanagawaConvertCFToHandshake.cpp b/lib/Dialect/Kanagawa/Transforms/KanagawaConvertCFToHandshake.cpp index 8ce9742a33..bd659a4377 100644 --- a/lib/Dialect/Kanagawa/Transforms/KanagawaConvertCFToHandshake.cpp +++ b/lib/Dialect/Kanagawa/Transforms/KanagawaConvertCFToHandshake.cpp @@ -52,8 +52,8 @@ LogicalResult ConvertCFToHandshakePass::convertMethod(MethodOp method) { newArgTypes.push_back(b.getNoneType()); newResTypes.push_back(b.getNoneType()); auto newFuncType = b.getFunctionType(newArgTypes, newResTypes); - auto dataflowMethodOp = b.create( - method.getLoc(), method.getInnerSymAttr(), TypeAttr::get(newFuncType), + auto dataflowMethodOp = DataflowMethodOp::create( + b, method.getLoc(), method.getInnerSymAttr(), TypeAttr::get(newFuncType), method.getArgNamesAttr(), method.getArgAttrsAttr(), method.getResAttrsAttr()); dataflowMethodOp.getFunctionBody().takeBody(method.getBody()); diff --git a/lib/Dialect/Kanagawa/Transforms/KanagawaConvertHandshakeToDC.cpp b/lib/Dialect/Kanagawa/Transforms/KanagawaConvertHandshakeToDC.cpp index cd7bf62c1f..09a1a4479b 100644 --- a/lib/Dialect/Kanagawa/Transforms/KanagawaConvertHandshakeToDC.cpp +++ b/lib/Dialect/Kanagawa/Transforms/KanagawaConvertHandshakeToDC.cpp @@ -65,8 +65,8 @@ struct StaticBlockOpConversion if (failed( getTypeConverter()->convertTypes(op.getResultTypes(), resultTypes))) return failure(); - auto dcBlock = rewriter.create(op.getLoc(), resultTypes, - adaptor.getOperands()); + auto dcBlock = DCBlockOp::create(rewriter, op.getLoc(), resultTypes, + adaptor.getOperands()); rewriter.eraseOp(dcBlock.getBodyBlock()->getTerminator()); rewriter.mergeBlocks(op.getBodyBlock(), dcBlock.getBodyBlock(), dcBlock.getBodyBlock()->getArguments()); diff --git a/lib/Dialect/Kanagawa/Transforms/KanagawaInlineSBlocksPass.cpp b/lib/Dialect/Kanagawa/Transforms/KanagawaInlineSBlocksPass.cpp index dcec9fcb07..897881f986 100644 --- a/lib/Dialect/Kanagawa/Transforms/KanagawaInlineSBlocksPass.cpp +++ b/lib/Dialect/Kanagawa/Transforms/KanagawaInlineSBlocksPass.cpp @@ -60,7 +60,7 @@ public: if (hasAttributes) { // Start the inline block... auto inlineStart = - rewriter.create(loc); + kanagawa::InlineStaticBlockBeginOp::create(rewriter, loc); inlineStart->setAttrs(op->getAttrs()); } @@ -77,7 +77,7 @@ public: if (hasAttributes) { // Close the inline block rewriter.setInsertionPoint(ret); - rewriter.create(loc); + kanagawa::InlineStaticBlockEndOp::create(rewriter, loc); } rewriter.eraseOp(ret); diff --git a/lib/Dialect/Kanagawa/Transforms/KanagawaMethodsToContainers.cpp b/lib/Dialect/Kanagawa/Transforms/KanagawaMethodsToContainers.cpp index 3fe5e937a8..bde40ae692 100644 --- a/lib/Dialect/Kanagawa/Transforms/KanagawaMethodsToContainers.cpp +++ b/lib/Dialect/Kanagawa/Transforms/KanagawaMethodsToContainers.cpp @@ -40,26 +40,29 @@ struct DataflowMethodOpConversion matchAndRewrite(DataflowMethodOp op, OpAdaptor adaptor, ConversionPatternRewriter &rewriter) const override { // Replace the class by a container of the same name. - auto newContainer = rewriter.create( - op.getLoc(), op.getInnerSym(), /*isTopLevel=*/false); + auto newContainer = ContainerOp::create( + rewriter, op.getLoc(), op.getInnerSym(), /*isTopLevel=*/false); rewriter.setInsertionPointToStart(newContainer.getBodyBlock()); // Create in- and output ports. llvm::SmallVector argValues; for (auto [arg, name] : llvm::zip_equal( op.getArguments(), op.getArgNames().getAsRange())) { - auto port = rewriter.create( - arg.getLoc(), hw::InnerSymAttr::get(name), arg.getType(), name); - argValues.push_back(rewriter.create(arg.getLoc(), port)); + auto port = + InputPortOp::create(rewriter, arg.getLoc(), + hw::InnerSymAttr::get(name), arg.getType(), name); + argValues.push_back(PortReadOp::create(rewriter, arg.getLoc(), port)); } ReturnOp returnOp = cast(op.getBodyBlock()->getTerminator()); for (auto [idx, resType] : llvm::enumerate( cast(op.getOperation()).getResultTypes())) { auto portName = rewriter.getStringAttr("out" + std::to_string(idx)); - auto port = rewriter.create( - op.getLoc(), hw::InnerSymAttr::get(portName), resType, portName); - rewriter.create(op.getLoc(), port, returnOp.getOperand(idx)); + auto port = OutputPortOp::create(rewriter, op.getLoc(), + hw::InnerSymAttr::get(portName), resType, + portName); + PortWriteOp::create(rewriter, op.getLoc(), port, + returnOp.getOperand(idx)); } rewriter.mergeBlocks(op.getBodyBlock(), newContainer.getBodyBlock(), diff --git a/lib/Dialect/Kanagawa/Transforms/KanagawaPortrefLowering.cpp b/lib/Dialect/Kanagawa/Transforms/KanagawaPortrefLowering.cpp index 2c416cd125..5096d3eac4 100644 --- a/lib/Dialect/Kanagawa/Transforms/KanagawaPortrefLowering.cpp +++ b/lib/Dialect/Kanagawa/Transforms/KanagawaPortrefLowering.cpp @@ -76,8 +76,8 @@ public: rewriter.setInsertionPoint(op); if (d == Direction::Input) { // references to inputs becomes outputs (write from this container) - auto rawOutput = rewriter.create( - op.getLoc(), op.getInnerSym(), innerType, op.getNameAttr()); + auto rawOutput = OutputPortOp::create( + rewriter, op.getLoc(), op.getInnerSym(), innerType, op.getNameAttr()); // Replace writes to the unwrapped port with writes to the new port. for (auto *unwrappedPortUser : @@ -92,8 +92,8 @@ public: } } else { // References to outputs becomes inputs (read from this container) - auto rawInput = rewriter.create( - op.getLoc(), op.getInnerSym(), innerType, op.getNameAttr()); + auto rawInput = InputPortOp::create( + rewriter, op.getLoc(), op.getInnerSym(), innerType, op.getNameAttr()); // TODO: RewriterBase::replaceAllUsesWith is not currently supported by // DialectConversion. Using it may lead to assertions about mutating // replaced/erased ops. For now, do this RAUW directly, until @@ -157,19 +157,18 @@ public: // Outputs of inputs are inputs (external driver into this container). // Create the raw input port and write the input port reference with a // read of the raw input port. - auto rawInput = rewriter.create( - op.getLoc(), op.getInnerSym(), innerType, op.getNameAttr()); - rewriter.create( - op.getLoc(), portWrapper.getValue(), - rewriter.create(op.getLoc(), rawInput)); + auto rawInput = InputPortOp::create( + rewriter, op.getLoc(), op.getInnerSym(), innerType, op.getNameAttr()); + PortWriteOp::create(rewriter, op.getLoc(), portWrapper.getValue(), + PortReadOp::create(rewriter, op.getLoc(), rawInput)); } else { // Outputs of outputs are outputs (external driver out of this container). // Create the raw output port and do a read of the input port reference. - auto rawOutput = rewriter.create( - op.getLoc(), op.getInnerSym(), innerType, op.getNameAttr()); - rewriter.create( - op.getLoc(), rawOutput, - rewriter.create(op.getLoc(), portWrapper.getValue())); + auto rawOutput = OutputPortOp::create( + rewriter, op.getLoc(), op.getInnerSym(), innerType, op.getNameAttr()); + PortWriteOp::create( + rewriter, op.getLoc(), rawOutput, + PortReadOp::create(rewriter, op.getLoc(), portWrapper.getValue())); } // Finally, remove the port wrapper and the original output port. @@ -221,20 +220,20 @@ class GetPortConversionPattern : public OpConversionPattern { if (innerDirection == Direction::Input) { // The portref> is now an output port. auto newGetPort = - rewriter.create(op.getLoc(), op.getInstance(), portName, - innerType, Direction::Output); + GetPortOp::create(rewriter, op.getLoc(), op.getInstance(), portName, + innerType, Direction::Output); auto newGetPortVal = - rewriter.create(op.getLoc(), newGetPort); - rewriter.create(op.getLoc(), getPortWrapper.getValue(), - newGetPortVal); + PortReadOp::create(rewriter, op.getLoc(), newGetPort); + PortWriteOp::create(rewriter, op.getLoc(), getPortWrapper.getValue(), + newGetPortVal); } else { // The portref> is now an input port. auto newGetPort = - rewriter.create(op.getLoc(), op.getInstance(), portName, - innerType, Direction::Input); - auto writeValue = - rewriter.create(op.getLoc(), getPortWrapper.getValue()); - rewriter.create(op.getLoc(), newGetPort, writeValue); + GetPortOp::create(rewriter, op.getLoc(), op.getInstance(), portName, + innerType, Direction::Input); + auto writeValue = PortReadOp::create(rewriter, op.getLoc(), + getPortWrapper.getValue()); + PortWriteOp::create(rewriter, op.getLoc(), newGetPort, writeValue); } } else { PortReadOp getPortUnwrapper; @@ -313,9 +312,9 @@ class GetPortConversionPattern : public OpConversionPattern { // forwarding is resolved through reading/writing the intermediate // inputs. auto fwPortName = rewriter.getStringAttr(portName.strref() + "_fw"); - auto forwardedInputPort = rewriter.create( - op.getLoc(), hw::InnerSymAttr::get(fwPortName), innerType, - fwPortName); + auto forwardedInputPort = InputPortOp::create( + rewriter, op.getLoc(), hw::InnerSymAttr::get(fwPortName), + innerType, fwPortName); // TODO: RewriterBase::replaceAllUsesWith is not currently supported // by DialectConversion. Using it may lead to assertions about @@ -323,8 +322,8 @@ class GetPortConversionPattern : public OpConversionPattern { // ConversionPatternRewriter properly supports RAUW. // See https://github.com/llvm/circt/issues/6795. getPortUnwrapper.getResult().replaceAllUsesWith(forwardedInputPort); - portDriverValue = rewriter.create( - op.getLoc(), forwardedInputPort.getPort()); + portDriverValue = PortReadOp::create(rewriter, op.getLoc(), + forwardedInputPort.getPort()); } else { // Direct assignmenet - the driver value will be the value of // the driver. @@ -335,9 +334,9 @@ class GetPortConversionPattern : public OpConversionPattern { // Perform assignment to the input port of the target instance using // the driver value. auto rawPort = - rewriter.create(op.getLoc(), op.getInstance(), portName, - innerType, Direction::Input); - rewriter.create(op.getLoc(), rawPort, portDriverValue); + GetPortOp::create(rewriter, op.getLoc(), op.getInstance(), portName, + innerType, Direction::Input); + PortWriteOp::create(rewriter, op.getLoc(), rawPort, portDriverValue); } else { // In this situation, we're retrieving an output port that is sent as an // output of the container: %rr = kanagawa.get_port %c %c_in : @@ -354,8 +353,8 @@ class GetPortConversionPattern : public OpConversionPattern { // We then replace the read op with the actual output port of the // container. auto rawPort = - rewriter.create(op.getLoc(), op.getInstance(), portName, - innerType, Direction::Output); + GetPortOp::create(rewriter, op.getLoc(), op.getInstance(), portName, + innerType, Direction::Output); // TODO: RewriterBase::replaceAllUsesWith is not currently supported by // DialectConversion. Using it may lead to assertions about mutating diff --git a/lib/Dialect/Kanagawa/Transforms/KanagawaPrepareScheduling.cpp b/lib/Dialect/Kanagawa/Transforms/KanagawaPrepareScheduling.cpp index f3813ed3d2..89e1660794 100644 --- a/lib/Dialect/Kanagawa/Transforms/KanagawaPrepareScheduling.cpp +++ b/lib/Dialect/Kanagawa/Transforms/KanagawaPrepareScheduling.cpp @@ -55,7 +55,7 @@ PrepareSchedulingPass::prepareSBlock(IsolatedStaticBlockOp sblock) { Location loc = sblock.getLoc(); Block *bodyBlock = sblock.getBodyBlock(); auto b = OpBuilder::atBlockBegin(bodyBlock); - auto ph = b.create(loc); + auto ph = kanagawa::PipelineHeaderOp::create(b, loc); // Create a pipeline.unscheduled operation which returns the same types // as that returned by the sblock. @@ -69,8 +69,8 @@ PrepareSchedulingPass::prepareSBlock(IsolatedStaticBlockOp sblock) { for (size_t i = 0, e = retTypes.size(); i < e; ++i) outNames.push_back(b.getStringAttr("out" + std::to_string(i))); - auto pipeline = b.create( - loc, retTypes, bodyBlock->getArguments(), b.getArrayAttr(inNames), + auto pipeline = pipeline::UnscheduledPipelineOp::create( + b, loc, retTypes, bodyBlock->getArguments(), b.getArrayAttr(inNames), b.getArrayAttr(outNames), ph.getClock(), ph.getGo(), ph.getReset(), ph.getStall()); b.setInsertionPointToEnd(pipeline.getEntryStage()); @@ -81,7 +81,8 @@ PrepareSchedulingPass::prepareSBlock(IsolatedStaticBlockOp sblock) { // sblock is still being passed through the pipeline. While doing so, we // sneakily also set the pipeline return values so that it will reflect the // later value replacements. - auto pipelineRet = b.create(loc, sblockRet.getOperands()); + auto pipelineRet = + pipeline::ReturnOp::create(b, loc, sblockRet.getOperands()); for (size_t i = 0, e = retTypes.size(); i < e; ++i) sblockRet.setOperand(i, pipeline.getResult(i)); diff --git a/lib/Dialect/Kanagawa/Transforms/KanagawaReblockPass.cpp b/lib/Dialect/Kanagawa/Transforms/KanagawaReblockPass.cpp index 9f9ac030d9..76c3316a38 100644 --- a/lib/Dialect/Kanagawa/Transforms/KanagawaReblockPass.cpp +++ b/lib/Dialect/Kanagawa/Transforms/KanagawaReblockPass.cpp @@ -121,7 +121,7 @@ LogicalResult ReblockPass::reblock(ArrayRef ops, auto b = OpBuilder(beginOp); auto kanagawaBlock = - b.create(beginOp->getLoc(), blockRetTypes, ValueRange{}); + StaticBlockOp::create(b, beginOp->getLoc(), blockRetTypes, ValueRange{}); // The new `kanagawa.sblock` should inherit the attributes of the block begin // op, if provided. diff --git a/lib/Dialect/Kanagawa/Transforms/KanagawaTunneling.cpp b/lib/Dialect/Kanagawa/Transforms/KanagawaTunneling.cpp index 690acf8529..c9f95f5b20 100644 --- a/lib/Dialect/Kanagawa/Transforms/KanagawaTunneling.cpp +++ b/lib/Dialect/Kanagawa/Transforms/KanagawaTunneling.cpp @@ -214,12 +214,13 @@ Value Tunneler::portForwardIfNeeded(PortOpInterface actualPort, // provides a writeable input port, and assign the wire output to the // output port. if (requestedDir == Direction::Input) { - auto wireOp = rewriter.create( - op.getLoc(), rewriter.getStringAttr(*actualPort.getInnerName() + ".wr"), + auto wireOp = InputWireOp::create( + rewriter, op.getLoc(), + rewriter.getStringAttr(*actualPort.getInnerName() + ".wr"), portInfo.getInnerType()); - rewriter.create(op.getLoc(), actualPort.getPort(), - wireOp.getOutput()); + PortWriteOp::create(rewriter, op.getLoc(), actualPort.getPort(), + wireOp.getOutput()); return wireOp.getPort(); } @@ -228,9 +229,9 @@ Value Tunneler::portForwardIfNeeded(PortOpInterface actualPort, // provides a readable output port, and read the input port as the value // of the wire. Value inputValue = - rewriter.create(op.getLoc(), actualPort.getPort()); - auto wireOp = rewriter.create( - op.getLoc(), + PortReadOp::create(rewriter, op.getLoc(), actualPort.getPort()); + auto wireOp = OutputWireOp::create( + rewriter, op.getLoc(), hw::InnerSymAttr::get( rewriter.getStringAttr(*actualPort.getInnerName() + ".rd")), inputValue, rewriter.getStringAttr(actualPort.getNameHint() + ".rd")); @@ -282,8 +283,8 @@ LogicalResult Tunneler::tunnelDown(InstanceGraphNode *currentContainer, rewriter.setInsertionPointAfter(tunnelInstance); for (PortInfo &pi : portInfos) { auto targetGetPortOp = - rewriter.create(op.getLoc(), pi.getType(), tunnelInstance, - pi.getPortOp.getPortSymbol()); + GetPortOp::create(rewriter, op.getLoc(), pi.getType(), tunnelInstance, + pi.getPortOp.getPortSymbol()); portMapping[&pi] = targetGetPortOp.getResult(); } return success(); @@ -298,9 +299,9 @@ LogicalResult Tunneler::tunnelDown(InstanceGraphNode *currentContainer, rewriter.setInsertionPointToEnd(tunnelScope.getBodyBlock()); llvm::DenseMap outputPortOps; for (PortInfo &pi : portInfos) { - outputPortOps[pi.portName] = rewriter.create( - op.getLoc(), circt::hw::InnerSymAttr::get(pi.portName), pi.getType(), - pi.portName); + outputPortOps[pi.portName] = OutputPortOp::create( + rewriter, op.getLoc(), circt::hw::InnerSymAttr::get(pi.portName), + pi.getType(), pi.portName); } // Recurse into the tunnel instance container. @@ -313,17 +314,17 @@ LogicalResult Tunneler::tunnelDown(InstanceGraphNode *currentContainer, // Write the target value to the output port. rewriter.setInsertionPointToEnd(tunnelScope.getBodyBlock()); - rewriter.create(op.getLoc(), outputPortOps[portInfo.portName], - res); + PortWriteOp::create(rewriter, op.getLoc(), outputPortOps[portInfo.portName], + res); // Back in the current container, read the new output port of the child // instance and assign it to the port mapping. rewriter.setInsertionPointAfter(tunnelInstance); - auto getPortOp = rewriter.create( - op.getLoc(), tunnelInstance, portInfo.portName, portInfo.getType(), - Direction::Output); + auto getPortOp = GetPortOp::create(rewriter, op.getLoc(), tunnelInstance, + portInfo.portName, portInfo.getType(), + Direction::Output); portMapping[pi] = - rewriter.create(op.getLoc(), getPortOp).getResult(); + PortReadOp::create(rewriter, op.getLoc(), getPortOp).getResult(); } return success(); @@ -368,23 +369,24 @@ LogicalResult Tunneler::tunnelUp(InstanceGraphNode *currentContainer, auto instance = use->getInstance(); rewriter.setInsertionPointAfter(instance); for (PortInfo &pi : portInfos) { - auto getPortOp = rewriter.create( - op.getLoc(), instance, pi.portName, pi.getType(), Direction::Input); - rewriter.create(op.getLoc(), getPortOp, - targetPortMapping[&pi]); + auto getPortOp = + GetPortOp::create(rewriter, op.getLoc(), instance, pi.portName, + pi.getType(), Direction::Input); + PortWriteOp::create(rewriter, op.getLoc(), getPortOp, + targetPortMapping[&pi]); } } // Create input ports for the requested portrefs. rewriter.setInsertionPointToEnd(scopeOp.getBodyBlock()); for (PortInfo &pi : portInfos) { - auto inputPort = rewriter.create( - op.getLoc(), hw::InnerSymAttr::get(pi.portName), pi.getType(), - pi.portName); + auto inputPort = InputPortOp::create(rewriter, op.getLoc(), + hw::InnerSymAttr::get(pi.portName), + pi.getType(), pi.portName); // Read the input port of the current container to forward the portref. portMapping[&pi] = - rewriter.create(op.getLoc(), inputPort.getResult()) + PortReadOp::create(rewriter, op.getLoc(), inputPort.getResult()) .getResult(); } diff --git a/lib/Dialect/LLHD/IR/LLHDDialect.cpp b/lib/Dialect/LLHD/IR/LLHDDialect.cpp index a284de799b..1ca0fb59c5 100644 --- a/lib/Dialect/LLHD/IR/LLHDDialect.cpp +++ b/lib/Dialect/LLHD/IR/LLHDDialect.cpp @@ -64,10 +64,10 @@ void LLHDDialect::initialize() { Operation *LLHDDialect::materializeConstant(OpBuilder &builder, Attribute value, Type type, Location loc) { if (auto timeAttr = dyn_cast(value)) - return builder.create(loc, type, timeAttr); + return llhd::ConstantTimeOp::create(builder, loc, type, timeAttr); if (auto intAttr = dyn_cast(value)) - return builder.create(loc, type, intAttr); + return hw::ConstantOp::create(builder, loc, type, intAttr); return nullptr; } diff --git a/lib/Dialect/LLHD/IR/LLHDOps.cpp b/lib/Dialect/LLHD/IR/LLHDOps.cpp index fe35761b96..b6ba5c905f 100644 --- a/lib/Dialect/LLHD/IR/LLHDOps.cpp +++ b/lib/Dialect/LLHD/IR/LLHDOps.cpp @@ -70,15 +70,15 @@ static Value getValueAtIndex(OpBuilder &builder, Location loc, Value val, unsigned index) { return TypeSwitch(val.getType()) .Case([&](hw::StructType ty) -> Value { - return builder.create( - loc, val, ty.getElements()[index].name); + return hw::StructExtractOp::create(builder, loc, val, + ty.getElements()[index].name); }) .Case([&](hw::ArrayType ty) -> Value { - Value idx = builder.create( - loc, + Value idx = hw::ConstantOp::create( + builder, loc, builder.getIntegerType(llvm::Log2_64_Ceil(ty.getNumElements())), index); - return builder.create(loc, val, idx); + return hw::ArrayGetOp::create(builder, loc, val, idx); }); } @@ -123,7 +123,7 @@ DenseMap SignalOp::destructure( for (auto [index, type] : indices) { Value init = getValueAtIndex(builder, getLoc(), getInit(), index); - auto sigOp = builder.create(getLoc(), getNameAttr(), init); + auto sigOp = SignalOp::create(builder, getLoc(), getNameAttr(), init); newAllocators.push_back(sigOp); slotMap.try_emplace( IntegerAttr::get(IndexType::get(getContext()), index), @@ -208,8 +208,8 @@ static LogicalResult canonicalizeSigPtrArraySliceOp(Op op, auto sliceOp = op.getInput().template getDefiningOp(); rewriter.modifyOpInPlace(op, [&]() { op.getInputMutable().assign(sliceOp.getInput()); - Value newIndex = rewriter.create( - op->getLoc(), a.getValue() + indexAttr.getValue()); + Value newIndex = hw::ConstantOp::create( + rewriter, op->getLoc(), a.getValue() + indexAttr.getValue()); op.getLowIndexMutable().assign(newIndex); }); @@ -391,16 +391,17 @@ DeletionKind PrbOp::rewire(const DestructurableMemorySlot &slot, SmallVector probed; getSortedPtrs(subslots, elements); for (auto [_, val] : elements) - probed.push_back(builder.create(getLoc(), val)); + probed.push_back(PrbOp::create(builder, getLoc(), val)); - Value repl = TypeSwitch(getType()) - .Case([&](auto ty) { - return builder.create( - getLoc(), getType(), probed); - }) - .Case([&](auto ty) { - return builder.create(getLoc(), probed); - }); + Value repl = + TypeSwitch(getType()) + .Case([&](auto ty) { + return hw::StructCreateOp::create(builder, getLoc(), getType(), + probed); + }) + .Case([&](auto ty) { + return hw::ArrayCreateOp::create(builder, getLoc(), probed); + }); replaceAllUsesWith(repl); return DeletionKind::Delete; @@ -467,9 +468,9 @@ DeletionKind DrvOp::rewire(const DestructurableMemorySlot &slot, getSortedPtrs(subslots, driven); for (auto [idx, sig] : driven) - builder.create(getLoc(), sig, - getValueAtIndex(builder, getLoc(), getValue(), idx), - getTime(), getEnable()); + DrvOp::create(builder, getLoc(), sig, + getValueAtIndex(builder, getLoc(), getValue(), idx), + getTime(), getEnable()); return DeletionKind::Delete; } diff --git a/lib/Dialect/LLHD/Transforms/CombineDrives.cpp b/lib/Dialect/LLHD/Transforms/CombineDrives.cpp index 33e1171d9c..984a1d61de 100644 --- a/lib/Dialect/LLHD/Transforms/CombineDrives.cpp +++ b/lib/Dialect/LLHD/Transforms/CombineDrives.cpp @@ -460,26 +460,28 @@ void ModuleContext::addDefaultDriveSlices(Signal &signal, // Handle integers. if (auto intType = dyn_cast(type)) { assert(slice.length > 0); - slice.value = builder.create( - builder.getIntegerType(slice.length), defaultValue, slice.offset); + slice.value = + comb::ExtractOp::create(builder, builder.getIntegerType(slice.length), + defaultValue, slice.offset); continue; } // Handle structs. if (auto structType = dyn_cast(type)) { assert(slice.length == 0); - slice.value = builder.create( - defaultValue, structType.getElements()[slice.offset]); + slice.value = hw::StructExtractOp::create( + builder, defaultValue, structType.getElements()[slice.offset]); continue; } // Handle arrays. if (auto arrayType = dyn_cast(type)) { assert(slice.length > 0); - auto offset = builder.create( + auto offset = hw::ConstantOp::create( + builder, APInt(llvm::Log2_64_Ceil(arrayType.getNumElements()), slice.offset)); - slice.value = builder.create( - hw::ArrayType::get(arrayType.getElementType(), slice.length), + slice.value = hw::ArraySliceOp::create( + builder, hw::ArrayType::get(arrayType.getElementType(), slice.length), defaultValue, offset); continue; } @@ -548,7 +550,7 @@ void ModuleContext::aggregateDriveSlices(Signal &signal, Value driveDelay, for (auto slice : slices) operands.push_back(slice.value); std::reverse(operands.begin(), operands.end()); // why, just why - result = builder.create(operands); + result = comb::ConcatOp::create(builder, operands); LLVM_DEBUG(llvm::dbgs() << " - Created " << result << "\n"); } @@ -559,7 +561,7 @@ void ModuleContext::aggregateDriveSlices(Signal &signal, Value driveDelay, SmallVector operands; for (auto slice : slices) operands.push_back(slice.value); - result = builder.create(structType, operands); + result = hw::StructCreateOp::create(builder, structType, operands); LLVM_DEBUG(llvm::dbgs() << " - Created " << result << "\n"); } @@ -574,7 +576,7 @@ void ModuleContext::aggregateDriveSlices(Signal &signal, Value driveDelay, if (scalars.empty()) return; std::reverse(scalars.begin(), scalars.end()); // why, just why - auto aggregate = builder.create(scalars); + auto aggregate = hw::ArrayCreateOp::create(builder, scalars); aggregates.push_back(aggregate); scalars.clear(); LLVM_DEBUG(llvm::dbgs() << " - Created " << aggregate << "\n"); @@ -594,7 +596,7 @@ void ModuleContext::aggregateDriveSlices(Signal &signal, Value driveDelay, result = aggregates.back(); if (aggregates.size() != 1) { std::reverse(aggregates.begin(), aggregates.end()); // why, just why - result = builder.create(aggregates); + result = hw::ArrayConcatOp::create(builder, aggregates); LLVM_DEBUG(llvm::dbgs() << " - Created " << result << "\n"); } } @@ -602,7 +604,7 @@ void ModuleContext::aggregateDriveSlices(Signal &signal, Value driveDelay, // Create the single drive with the aggregate result. assert(result); auto driveOp = - builder.create(signal.value, result, driveDelay, driveEnable); + DrvOp::create(builder, signal.value, result, driveDelay, driveEnable); signal.completeDrives.push_back(driveOp); LLVM_DEBUG(llvm::dbgs() << " - Created " << driveOp << "\n"); diff --git a/lib/Dialect/LLHD/Transforms/Deseq.cpp b/lib/Dialect/LLHD/Transforms/Deseq.cpp index a1f3736592..7b2023fb2f 100644 --- a/lib/Dialect/LLHD/Transforms/Deseq.cpp +++ b/lib/Dialect/LLHD/Transforms/Deseq.cpp @@ -1019,12 +1019,12 @@ void Deseq::implementRegister(DriveInfo &drive) { // negedge clocks. auto &clockCast = materializedClockCasts[drive.clock.clock]; if (!clockCast) - clockCast = builder.create(loc, drive.clock.clock); + clockCast = seq::ToClockOp::create(builder, loc, drive.clock.clock); auto clock = clockCast; if (!drive.clock.risingEdge) { auto &clockInv = materializedClockInverters[clock]; if (!clockInv) - clockInv = builder.create(loc, clock); + clockInv = seq::ClockInverterOp::create(builder, loc, clock); clock = clockInv; } @@ -1041,8 +1041,8 @@ void Deseq::implementRegister(DriveInfo &drive) { if (!drive.reset.activeHigh) { auto &inv = materializedInverters[reset]; if (!inv) { - auto one = builder.create(loc, builder.getI1Type(), 1); - inv = builder.create(loc, reset, one); + auto one = hw::ConstantOp::create(builder, loc, builder.getI1Type(), 1); + inv = comb::XorOp::create(builder, loc, reset, one); } reset = inv; } @@ -1104,10 +1104,10 @@ void Deseq::implementRegister(DriveInfo &drive) { name = builder.getStringAttr(""); // Create the register op. - auto reg = - builder.create(loc, value, clock, name, hw::InnerSymAttr{}, - /*preset=*/IntegerAttr{}, reset, resetValue, - /*isAsync=*/reset != Value{}); + auto reg = seq::FirRegOp::create(builder, loc, value, clock, name, + hw::InnerSymAttr{}, + /*preset=*/IntegerAttr{}, reset, resetValue, + /*isAsync=*/reset != Value{}); // If the register has an enable, insert a self-mux in front of the register. // Set the `bin` flag on the mux specifically to make up for a subtle @@ -1116,8 +1116,8 @@ void Deseq::implementRegister(DriveInfo &drive) { if (enable) { OpBuilder::InsertionGuard guard(builder); builder.setInsertionPoint(reg); - reg.getNextMutable().assign(builder.create( - loc, enable, reg.getNext(), reg.getResult(), true)); + reg.getNextMutable().assign(comb::MuxOp::create( + builder, loc, enable, reg.getNext(), reg.getResult(), true)); } // Make the original `llhd.drv` drive the register value unconditionally. @@ -1131,7 +1131,7 @@ void Deseq::implementRegister(DriveInfo &drive) { attr.getTime() == 0 && attr.getDelta() == 1 && attr.getEpsilon() == 0) { if (!epsilonDelay) epsilonDelay = - builder.create(process.getLoc(), 0, "ns", 0, 1); + ConstantTimeOp::create(builder, process.getLoc(), 0, "ns", 0, 1); drive.op.getTimeMutable().assign(epsilonDelay); } } @@ -1180,8 +1180,8 @@ ValueRange Deseq::specializeProcess(FixedValues fixedValues) { // the register operation that consumes the result of this specialized // process, such that we can make the process purely combinational. OpBuilder builder(process); - auto executeOp = builder.create(process.getLoc(), - process.getResultTypes()); + auto executeOp = CombinationalOp::create(builder, process.getLoc(), + process.getResultTypes()); IRMapping mapping; SmallVector> worklist; @@ -1203,8 +1203,8 @@ ValueRange Deseq::specializeProcess(FixedValues fixedValues) { auto &entryBlock = executeOp.getRegion().emplaceBlock(); builder.setInsertionPointToStart(&entryBlock); auto i1 = builder.getI1Type(); - auto trueValue = builder.create(process.getLoc(), i1, 1); - auto falseValue = builder.create(process.getLoc(), i1, 0); + auto trueValue = hw::ConstantOp::create(builder, process.getLoc(), i1, 1); + auto falseValue = hw::ConstantOp::create(builder, process.getLoc(), i1, 0); SmallDenseMap, 2> materializedFixedValues; for (auto fixedValue : fixedValues) { @@ -1243,7 +1243,7 @@ ValueRange Deseq::specializeProcess(FixedValues fixedValues) { SmallVector operands; for (auto operand : waitOp.getYieldOperands()) operands.push_back(mapping.lookupOrDefault(operand)); - builder.create(waitOp.getLoc(), operands); + YieldOp::create(builder, waitOp.getLoc(), operands); continue; } @@ -1254,17 +1254,17 @@ ValueRange Deseq::specializeProcess(FixedValues fixedValues) { if (matchPattern(condition, m_NonZero())) { for (auto operand : condBranchOp.getTrueDestOperands()) operands.push_back(mapping.lookupOrDefault(operand)); - builder.create( - condBranchOp.getLoc(), - scheduleBlock(condBranchOp.getTrueDest()), operands); + cf::BranchOp::create(builder, condBranchOp.getLoc(), + scheduleBlock(condBranchOp.getTrueDest()), + operands); continue; } if (matchPattern(condition, m_Zero())) { for (auto operand : condBranchOp.getFalseOperands()) operands.push_back(mapping.lookupOrDefault(operand)); - builder.create( - condBranchOp.getLoc(), - scheduleBlock(condBranchOp.getFalseDest()), operands); + cf::BranchOp::create(builder, condBranchOp.getLoc(), + scheduleBlock(condBranchOp.getFalseDest()), + operands); continue; } } @@ -1342,7 +1342,7 @@ ValueRange Deseq::specializeProcess(FixedValues fixedValues) { assert(pastValues.size() == wait.getDestOperands().size()); for (auto pastValue : pastValues) destOperands.push_back(materializedFixedValues.lookup(pastValue).first); - builder.create(wait.getLoc(), dest, destOperands); + cf::BranchOp::create(builder, wait.getLoc(), dest, destOperands); } // Clone everything after the wait operation. diff --git a/lib/Dialect/LLHD/Transforms/DesequentializationPass.cpp b/lib/Dialect/LLHD/Transforms/DesequentializationPass.cpp index 12235120a5..7ede8b5ddc 100644 --- a/lib/Dialect/LLHD/Transforms/DesequentializationPass.cpp +++ b/lib/Dialect/LLHD/Transforms/DesequentializationPass.cpp @@ -365,7 +365,7 @@ private: void materializeTriggerEnables(OpBuilder &builder, Location loc) { Value trueVal = - builder.create(loc, builder.getBoolAttr(true)); + hw::ConstantOp::create(builder, loc, builder.getBoolAttr(true)); for (uint64_t i = 0, e = 1ULL << primitives.size(); i < e; ++i) { if (!result[i]) continue; @@ -391,7 +391,7 @@ private: continue; } conjuncts.push_back( - builder.create(loc, primitives[k], trueVal)); + comb::XorOp::create(builder, loc, primitives[k], trueVal)); } if (!conjuncts.empty()) enableMap[key] = @@ -477,7 +477,7 @@ private: for (auto *iter2 = iter1 + 1; iter2 != triggers.end(); ++iter2) { if (iter1->clocks == iter2->clocks && iter1->kinds == iter2->kinds) { iter1->enable = - builder.create(loc, iter1->enable, iter2->enable); + comb::OrOp::create(builder, loc, iter1->enable, iter2->enable); triggers.erase(iter2--); } } @@ -669,14 +669,14 @@ void DesequentializationPass::runOnProcess(llhd::ProcessOp procOp) const { })) return WalkResult::interrupt(); - Value clock = builder.create(loc, triggers[0].clocks[0]); + Value clock = seq::ToClockOp::create(builder, loc, triggers[0].clocks[0]); Value reset, resetValue; if (triggers[0].kinds[0] == Trigger::Kind::NegEdge) - clock = builder.create(loc, clock); + clock = seq::ClockInverterOp::create(builder, loc, clock); if (triggers[0].enable) - clock = builder.create(loc, clock, triggers[0].enable); + clock = seq::ClockGateOp::create(builder, loc, clock, triggers[0].enable); if (triggers.size() == 2) { // TODO: add support @@ -702,20 +702,20 @@ void DesequentializationPass::runOnProcess(llhd::ProcessOp procOp) const { if (triggers[1].kinds[0] == Trigger::Kind::NegEdge) { Value trueVal = - builder.create(loc, builder.getBoolAttr(true)); - reset = builder.create(loc, reset, trueVal); + hw::ConstantOp::create(builder, loc, builder.getBoolAttr(true)); + reset = comb::XorOp::create(builder, loc, reset, trueVal); } } // FIXME: this adds async resets as sync resets and might also add the reset // as clock and clock as reset. - Value regOut = builder.create(loc, op.getValue(), clock, - reset, resetValue); + Value regOut = seq::CompRegOp::create(builder, loc, op.getValue(), clock, + reset, resetValue); op.getEnableMutable().clear(); op.getValueMutable().assign(regOut); Value epsilonTime = - builder.create(loc, 0, "ns", 0, 1); + llhd::ConstantTimeOp::create(builder, loc, 0, "ns", 0, 1); op.getTimeMutable().assign(epsilonTime); LLVM_DEBUG( diff --git a/lib/Dialect/LLHD/Transforms/HoistSignals.cpp b/lib/Dialect/LLHD/Transforms/HoistSignals.cpp index deb6dde2a0..71b43810c4 100644 --- a/lib/Dialect/LLHD/Transforms/HoistSignals.cpp +++ b/lib/Dialect/LLHD/Transforms/HoistSignals.cpp @@ -489,25 +489,25 @@ void DriveHoister::hoistDrives() { .Case([&](auto attr) { auto &slot = materializedConstants[attr]; if (!slot) - slot = builder.create(processOp.getLoc(), attr); + slot = hw::ConstantOp::create(builder, processOp.getLoc(), attr); return slot; }) .Case([&](auto attr) { auto &slot = materializedConstants[attr]; if (!slot) slot = - builder.create(processOp.getLoc(), attr); + llhd::ConstantTimeOp::create(builder, processOp.getLoc(), attr); return slot; }) .Case([&](auto type) { // TODO: This should probably create something like a `llhd.dontcare`. unsigned numBits = hw::getBitWidth(type); assert(numBits >= 0); - Value value = builder.create( - processOp.getLoc(), builder.getIntegerType(numBits), 0); + Value value = hw::ConstantOp::create( + builder, processOp.getLoc(), builder.getIntegerType(numBits), 0); if (value.getType() != type) value = - builder.create(processOp.getLoc(), type, value); + hw::BitcastOp::create(builder, processOp.getLoc(), type, value); return value; }); }; @@ -550,9 +550,9 @@ void DriveHoister::hoistDrives() { addResultType(driveSet.uniform.delay, operands.delay); addResultType(driveSet.uniform.enable, operands.enable); } - auto newProcessOp = builder.create(processOp.getLoc(), resultTypes, - processOp->getOperands(), - processOp->getAttrs()); + auto newProcessOp = + ProcessOp::create(builder, processOp.getLoc(), resultTypes, + processOp->getOperands(), processOp->getAttrs()); newProcessOp.getBody().takeBody(processOp.getBody()); processOp.replaceAllUsesWith( newProcessOp->getResults().slice(0, oldNumResults)); @@ -589,7 +589,7 @@ void DriveHoister::hoistDrives() { ? useResultValue(driveSet.uniform.enable) : Value{}; auto newDrive = - builder.create(slot.getLoc(), slot, value, delay, enable); + DrvOp::create(builder, slot.getLoc(), slot, value, delay, enable); LLVM_DEBUG(llvm::dbgs() << "- Add " << newDrive << "\n"); // Remove the old drives inside of the process. diff --git a/lib/Dialect/LLHD/Transforms/LowerProcesses.cpp b/lib/Dialect/LLHD/Transforms/LowerProcesses.cpp index 445c680a15..010694f9de 100644 --- a/lib/Dialect/LLHD/Transforms/LowerProcesses.cpp +++ b/lib/Dialect/LLHD/Transforms/LowerProcesses.cpp @@ -55,8 +55,8 @@ void Lowering::lower() { // Replace the process. OpBuilder builder(processOp); - auto executeOp = builder.create(processOp.getLoc(), - processOp.getResultTypes()); + auto executeOp = CombinationalOp::create(builder, processOp.getLoc(), + processOp.getResultTypes()); executeOp.getRegion().takeBody(processOp.getBody()); processOp.replaceAllUsesWith(executeOp); processOp.erase(); @@ -64,7 +64,7 @@ void Lowering::lower() { // Replace the `llhd.wait` with an `llhd.yield`. builder.setInsertionPoint(waitOp); - builder.create(waitOp.getLoc(), waitOp.getYieldOperands()); + YieldOp::create(builder, waitOp.getLoc(), waitOp.getYieldOperands()); waitOp.erase(); // Simplify the execute op body region since disconnecting the control flow diff --git a/lib/Dialect/LLHD/Transforms/Mem2Reg.cpp b/lib/Dialect/LLHD/Transforms/Mem2Reg.cpp index 896d7741b2..55739dc62e 100644 --- a/lib/Dialect/LLHD/Transforms/Mem2Reg.cpp +++ b/lib/Dialect/LLHD/Transforms/Mem2Reg.cpp @@ -142,9 +142,8 @@ struct Def { Value Def::getValueOrPlaceholder() { if (!value) { auto builder = OpBuilder::atBlockBegin(block); - value = builder - .create(builder.getUnknownLoc(), - type, ValueRange{}) + value = UnrealizedConversionCastOp::create(builder, builder.getUnknownLoc(), + type, ValueRange{}) .getResult(0); valueIsPlaceholder = true; } @@ -160,17 +159,16 @@ Value Def::getConditionOrPlaceholder() { auto builder = OpBuilder::atBlockBegin(block); Value value; if (condition.isNever()) { - value = builder.create(builder.getUnknownLoc(), - builder.getI1Type(), 0); + value = hw::ConstantOp::create(builder, builder.getUnknownLoc(), + builder.getI1Type(), 0); } else if (condition.isAlways()) { - value = builder.create(builder.getUnknownLoc(), - builder.getI1Type(), 1); + value = hw::ConstantOp::create(builder, builder.getUnknownLoc(), + builder.getI1Type(), 1); } else { - value = builder - .create(builder.getUnknownLoc(), - builder.getI1Type(), - ValueRange{}) - .getResult(0); + value = + UnrealizedConversionCastOp::create(builder, builder.getUnknownLoc(), + builder.getI1Type(), ValueRange{}) + .getResult(0); conditionIsPlaceholder = true; } condition.setCondition(value); @@ -1256,8 +1254,8 @@ void Promoter::insertProbeBlocks() { auto *newBlock = builder.createBlock(successor->block); for (auto oldArg : successor->block->getArguments()) newBlock->addArgument(oldArg.getType(), oldArg.getLoc()); - builder.create(predecessor->terminator->getLoc(), - successor->block, newBlock->getArguments()); + cf::BranchOp::create(builder, predecessor->terminator->getLoc(), + successor->block, newBlock->getArguments()); for (auto &blockOp : predecessor->terminator->getBlockOperands()) if (blockOp.get() == successor->block) blockOp.set(newBlock); @@ -1304,7 +1302,7 @@ void Promoter::insertProbes(BlockEntry *node) { if (op->getBlock() == node->block) builder.setInsertionPointAfterValue(neededDef); } - auto value = builder.create(neededDef.getLoc(), neededDef); + auto value = PrbOp::create(builder, neededDef.getLoc(), neededDef); auto *def = lattice.createDef(value, DriveCondition::never()); node->insertedProbes.push_back({neededDef, def}); } @@ -1346,8 +1344,8 @@ void Promoter::insertDriveBlocks() { auto *newBlock = builder.createBlock(successor->block); for (auto oldArg : successor->block->getArguments()) newBlock->addArgument(oldArg.getType(), oldArg.getLoc()); - builder.create(predecessor->terminator->getLoc(), - successor->block, newBlock->getArguments()); + cf::BranchOp::create(builder, predecessor->terminator->getLoc(), + successor->block, newBlock->getArguments()); for (auto &blockOp : predecessor->terminator->getBlockOperands()) if (blockOp.get() == successor->block) blockOp.set(newBlock); @@ -1387,13 +1385,13 @@ void Promoter::insertDrives(BlockExit *node) { auto getTime = [&](bool delta) { if (delta) { if (!deltaTime) - deltaTime = builder.create(node->terminator->getLoc(), - 0, "ns", 1, 0); + deltaTime = ConstantTimeOp::create(builder, node->terminator->getLoc(), + 0, "ns", 1, 0); return deltaTime; } if (!epsilonTime) - epsilonTime = builder.create(node->terminator->getLoc(), - 0, "ns", 0, 1); + epsilonTime = ConstantTimeOp::create(builder, node->terminator->getLoc(), + 0, "ns", 0, 1); return epsilonTime; }; @@ -1414,7 +1412,7 @@ void Promoter::insertDrives(BlockExit *node) { auto enable = reachingDef->condition.isConditional() ? reachingDef->getConditionOrPlaceholder() : Value{}; - builder.create(getLoc(slot), getSlot(slot), value, time, enable); + DrvOp::create(builder, getLoc(slot), getSlot(slot), value, time, enable); }; for (auto slot : slots) @@ -1658,9 +1656,9 @@ bool Promoter::insertBlockArgs(BlockEntry *node) { auto type = getStoredType(slot); auto flatType = builder.getIntegerType(hw::getBitWidth(type)); Value value = - builder.create(getLoc(slot), flatType, 0); + hw::ConstantOp::create(builder, getLoc(slot), flatType, 0); if (type != flatType) - value = builder.create(getLoc(slot), type, value); + value = hw::BitcastOp::create(builder, getLoc(slot), type, value); args.push_back(value); } break; @@ -1668,8 +1666,8 @@ bool Promoter::insertBlockArgs(BlockEntry *node) { if (def) { args.push_back(def->getConditionOrPlaceholder()); } else { - args.push_back(builder.create( - getLoc(slot), builder.getI1Type(), 0)); + args.push_back(hw::ConstantOp::create(builder, getLoc(slot), + builder.getI1Type(), 0)); } break; } diff --git a/lib/Dialect/LLHD/Transforms/MemoryToBlockArgumentPass.cpp b/lib/Dialect/LLHD/Transforms/MemoryToBlockArgumentPass.cpp index 8bf4fe161e..76b676bf48 100644 --- a/lib/Dialect/LLHD/Transforms/MemoryToBlockArgumentPass.cpp +++ b/lib/Dialect/LLHD/Transforms/MemoryToBlockArgumentPass.cpp @@ -151,8 +151,8 @@ void MemoryToBlockArgumentPass::runOnProcess(llhd::ProcessOp operation) { for (Block *pred : jp->getPredecessors()) { // Set insertion point before terminator to insert the load operation builder.setInsertionPoint(pred->getTerminator()); - Value load = builder.create( - pred->getTerminator()->getLoc(), + Value load = llhd::LoadOp::create( + builder, pred->getTerminator()->getLoc(), cast(var.getType()).getElementType(), var); // Add the loaded value as additional block argument addBlockOperandToTerminator(pred->getTerminator(), jp, load); @@ -160,7 +160,7 @@ void MemoryToBlockArgumentPass::runOnProcess(llhd::ProcessOp operation) { // Insert a store at the beginning of the join point to make removal of // all the memory operations easier later on builder.setInsertionPointToStart(jp); - builder.create(jp->front().getLoc(), var, phi); + llhd::StoreOp::create(builder, jp->front().getLoc(), var, phi); } // Basically reaching definitions analysis and replacing the loaded values diff --git a/lib/Dialect/LLHD/Transforms/RemoveControlFlow.cpp b/lib/Dialect/LLHD/Transforms/RemoveControlFlow.cpp index 2de7fce2b6..b56607c364 100644 --- a/lib/Dialect/LLHD/Transforms/RemoveControlFlow.cpp +++ b/lib/Dialect/LLHD/Transforms/RemoveControlFlow.cpp @@ -61,9 +61,9 @@ struct Condition { /// condition is a constant. Value materialize(OpBuilder &builder, Location loc) const { if (isTrue()) - return builder.create(loc, APInt(1, 1)); + return hw::ConstantOp::create(builder, loc, APInt(1, 1)); if (isFalse()) - return builder.create(loc, APInt(1, 0)); + return hw::ConstantOp::create(builder, loc, APInt(1, 0)); return pair.getPointer(); } @@ -223,11 +223,11 @@ void CFRemover::run() { yieldOps[0].getOperandTypes(), locs); sortedBlocks.push_back(yieldBlock); yieldOp = - builder.create(region.getLoc(), yieldBlock->getArguments()); + YieldOp::create(builder, region.getLoc(), yieldBlock->getArguments()); for (auto yieldOp : yieldOps) { builder.setInsertionPoint(yieldOp); - builder.create(yieldOp.getLoc(), yieldBlock, - yieldOp.getOperands()); + cf::BranchOp::create(builder, yieldOp.getLoc(), yieldBlock, + yieldOp.getOperands()); yieldOp.erase(); } } diff --git a/lib/Dialect/LLHD/Transforms/Sig2RegPass.cpp b/lib/Dialect/LLHD/Transforms/Sig2RegPass.cpp index d63dfc8c37..7e323405c4 100644 --- a/lib/Dialect/LLHD/Transforms/Sig2RegPass.cpp +++ b/lib/Dialect/LLHD/Transforms/Sig2RegPass.cpp @@ -230,12 +230,12 @@ public: // Handle the writes by starting with the signal init value and injecting // the written values at the right offsets. for (auto interval : intervals) { - Value invMask = builder.create( - loc, APInt::getAllOnes(interval.bitwidth)); + Value invMask = hw::ConstantOp::create( + builder, loc, APInt::getAllOnes(interval.bitwidth)); if (uint64_t(bw) > interval.bitwidth) { - Value pad = builder.create( - loc, APInt::getZero(bw - interval.bitwidth)); + Value pad = hw::ConstantOp::create( + builder, loc, APInt::getZero(bw - interval.bitwidth)); invMask = builder.createOrFold(loc, pad, invMask); } @@ -243,7 +243,7 @@ public: interval.low.dynamic, bw); invMask = builder.createOrFold(loc, invMask, amt); Value allOnes = - builder.create(loc, APInt::getAllOnes(bw)); + hw::ConstantOp::create(builder, loc, APInt::getAllOnes(bw)); Value mask = builder.createOrFold(loc, invMask, allOnes); val = builder.createOrFold(loc, val, mask); @@ -251,8 +251,8 @@ public: loc, builder.getIntegerType(interval.bitwidth), interval.value); if (uint64_t(bw) > interval.bitwidth) { - Value pad = builder.create( - loc, APInt::getZero(bw - interval.bitwidth)); + Value pad = hw::ConstantOp::create( + builder, loc, APInt::getZero(bw - interval.bitwidth)); assignVal = builder.createOrFold(loc, pad, assignVal); } @@ -299,13 +299,13 @@ private: Value buildDynamicIndex(OpBuilder &builder, Location loc, uint64_t constOffset, ArrayRef indices, uint64_t width) { - Value index = builder.create( - loc, builder.getIntegerType(width), constOffset); + Value index = hw::ConstantOp::create( + builder, loc, builder.getIntegerType(width), constOffset); for (auto idx : indices) { auto bw = hw::getBitWidth(idx.getType()); Value pad = - builder.create(loc, APInt::getZero(width - bw)); + hw::ConstantOp::create(builder, loc, APInt::getZero(width - bw)); idx = builder.createOrFold(loc, pad, idx); index = builder.createOrFold(loc, index, idx); } diff --git a/lib/Dialect/LLHD/Transforms/TemporalCodeMotionPass.cpp b/lib/Dialect/LLHD/Transforms/TemporalCodeMotionPass.cpp index 9230810eb3..4ffb19674a 100644 --- a/lib/Dialect/LLHD/Transforms/TemporalCodeMotionPass.cpp +++ b/lib/Dialect/LLHD/Transforms/TemporalCodeMotionPass.cpp @@ -49,7 +49,7 @@ getBranchDecisionsFromDominatorToTarget(OpBuilder &builder, Block *driveBlock, if (curr == dominator || curr->getPredecessors().empty()) { if (!mem.count(curr)) - mem[curr] = builder.create(loc, APInt(1, 1)); + mem[curr] = hw::ConstantOp::create(builder, loc, APInt(1, 1)); worklist.pop_back(); continue; @@ -66,19 +66,19 @@ getBranchDecisionsFromDominatorToTarget(OpBuilder &builder, Block *driveBlock, if (addedSomething) continue; - Value runner = builder.create(loc, APInt(1, 0)); + Value runner = hw::ConstantOp::create(builder, loc, APInt(1, 0)); for (auto *predBlock : curr->getPredecessors()) { if (predBlock->getTerminator()->getNumSuccessors() != 1) { auto condBr = cast(predBlock->getTerminator()); Value cond = condBr.getCondition(); if (condBr.getFalseDest() == curr) { - Value trueVal = builder.create(loc, APInt(1, 1)); - cond = builder.create(loc, cond, trueVal); + Value trueVal = hw::ConstantOp::create(builder, loc, APInt(1, 1)); + cond = comb::XorOp::create(builder, loc, cond, trueVal); } - Value next = builder.create(loc, mem[predBlock], cond); - runner = builder.create(loc, runner, next); + Value next = comb::AndOp::create(builder, loc, mem[predBlock], cond); + runner = comb::OrOp::create(builder, loc, runner, next); } else { - runner = builder.create(loc, runner, mem[predBlock]); + runner = comb::OrOp::create(builder, loc, runner, mem[predBlock]); } } mem[curr] = runner; @@ -103,8 +103,8 @@ static void moveDriveOpBefore(llhd::DrvOp drvOp, Block *dominator, builder, drvParentBlock, dominator, mem); if (drvOp.getEnable()) - finalValue = builder.create(drvOp.getLoc(), drvOp.getEnable(), - finalValue); + finalValue = comb::AndOp::create(builder, drvOp.getLoc(), drvOp.getEnable(), + finalValue); drvOp.getEnableMutable().assign(finalValue); drvOp->moveBefore(moveBefore); @@ -251,8 +251,8 @@ LogicalResult TemporalCodeMotionPass::runOnProcess(llhd::ProcessOp procOp) { // temporal region entry block OpBuilder b(procOp); b.setInsertionPointToEnd(auxBlock); - b.create(procOp.getLoc(), succTREntry, - auxBlock->getArguments()); + cf::BranchOp::create(b, procOp.getLoc(), succTREntry, + auxBlock->getArguments()); } //===--------------------------------------------------------------------===// @@ -366,14 +366,15 @@ LogicalResult TemporalCodeMotionPass::runOnProcess(llhd::ProcessOp procOp) { if (op.getEnable()) { // Multiplex value to be driven auto firstDrive = sigToDrv[sigTimePair]; - Value muxValue = builder.create( - op.getLoc(), op.getEnable(), op.getValue(), firstDrive.getValue()); + Value muxValue = + comb::MuxOp::create(builder, op.getLoc(), op.getEnable(), + op.getValue(), firstDrive.getValue()); op.getValueMutable().assign(muxValue); // Take the disjunction of the enable conditions if (firstDrive.getEnable()) { - Value orVal = builder.create(op.getLoc(), op.getEnable(), - firstDrive.getEnable()); + Value orVal = comb::OrOp::create(builder, op.getLoc(), op.getEnable(), + firstDrive.getEnable()); op.getEnableMutable().assign(orVal); } else { // No enable is equivalent to a constant 'true' enable diff --git a/lib/Dialect/LLHD/Transforms/UnrollLoops.cpp b/lib/Dialect/LLHD/Transforms/UnrollLoops.cpp index 17b69a3598..5b1c91020b 100644 --- a/lib/Dialect/LLHD/Transforms/UnrollLoops.cpp +++ b/lib/Dialect/LLHD/Transforms/UnrollLoops.cpp @@ -268,7 +268,7 @@ void Loop::unroll(CFGLoopInfo &cfgLoopInfo) { pruner.eraseLaterIfUnused(iterIndVar); builder.setInsertionPointAfterValue(iterIndVar); iterIndVar.replaceAllUsesWith( - builder.create(iterIndVar.getLoc(), indValue)); + hw::ConstantOp::create(builder, iterIndVar.getLoc(), indValue)); // Update all edges to the original loop header to point to the cloned loop // header. Leave the original back-edge untouched. @@ -293,8 +293,8 @@ void Loop::unroll(CFGLoopInfo &cfgLoopInfo) { continueDestOperands = exitBranchOp.getFalseDestOperands(); } builder.setInsertionPoint(exitBranchOp); - builder.create(exitBranchOp.getLoc(), continueDest, - continueDestOperands); + cf::BranchOp::create(builder, exitBranchOp.getLoc(), continueDest, + continueDestOperands); pruner.eraseLaterIfUnused(exitBranchOp.getOperands()); exitBranchOp.erase(); @@ -314,7 +314,7 @@ void Loop::unroll(CFGLoopInfo &cfgLoopInfo) { pruner.eraseLaterIfUnused(indVar); builder.setInsertionPointAfterValue(indVar); indVar.replaceAllUsesWith( - builder.create(indVar.getLoc(), indValue)); + hw::ConstantOp::create(builder, indVar.getLoc(), indValue)); indVar = {}; // Remove the continue edge of the exit branch in the loop body, since we @@ -327,8 +327,8 @@ void Loop::unroll(CFGLoopInfo &cfgLoopInfo) { exitDestOperands = exitBranchOp.getFalseDestOperands(); } builder.setInsertionPoint(exitBranchOp); - builder.create(exitBranchOp.getLoc(), exitDest, - exitDestOperands); + cf::BranchOp::create(builder, exitBranchOp.getLoc(), exitDest, + exitDestOperands); pruner.eraseLaterIfUnused(exitBranchOp.getOperands()); exitBranchOp.erase(); exitEdge = nullptr; diff --git a/lib/Dialect/LLHD/Transforms/WrapProceduralOps.cpp b/lib/Dialect/LLHD/Transforms/WrapProceduralOps.cpp index 9438ee1250..60889c5ad0 100644 --- a/lib/Dialect/LLHD/Transforms/WrapProceduralOps.cpp +++ b/lib/Dialect/LLHD/Transforms/WrapProceduralOps.cpp @@ -34,11 +34,11 @@ void WrapProceduralOpsPass::runOnOperation() { if (!isa(op.getDialect()) && !isa(op)) continue; auto builder = OpBuilder(&op); - auto wrapperOp = - builder.create(op.getLoc(), op.getResultTypes()); + auto wrapperOp = llhd::CombinationalOp::create(builder, op.getLoc(), + op.getResultTypes()); op.replaceAllUsesWith(wrapperOp); builder.createBlock(&wrapperOp.getBody()); - auto yieldOp = builder.create(op.getLoc(), op.getResults()); + auto yieldOp = llhd::YieldOp::create(builder, op.getLoc(), op.getResults()); op.moveBefore(yieldOp); ++numOpsWrapped; } diff --git a/lib/Dialect/LoopSchedule/LoopScheduleOps.cpp b/lib/Dialect/LoopSchedule/LoopScheduleOps.cpp index 9d42864d98..976721e915 100644 --- a/lib/Dialect/LoopSchedule/LoopScheduleOps.cpp +++ b/lib/Dialect/LoopSchedule/LoopScheduleOps.cpp @@ -202,14 +202,15 @@ void LoopSchedulePipelineOp::build(OpBuilder &builder, OperationState &state, argLocs.push_back(arg.getLoc()); condBlock.addArguments(iterArgs.getTypes(), argLocs); builder.setInsertionPointToEnd(&condBlock); - builder.create(builder.getUnknownLoc(), ValueRange()); + LoopScheduleRegisterOp::create(builder, builder.getUnknownLoc(), + ValueRange()); Region *stagesRegion = state.addRegion(); Block &stagesBlock = stagesRegion->emplaceBlock(); stagesBlock.addArguments(iterArgs.getTypes(), argLocs); builder.setInsertionPointToEnd(&stagesBlock); - builder.create(builder.getUnknownLoc(), - ValueRange(), ValueRange()); + LoopScheduleTerminatorOp::create(builder, builder.getUnknownLoc(), + ValueRange(), ValueRange()); } //===----------------------------------------------------------------------===// @@ -235,7 +236,8 @@ void LoopSchedulePipelineStageOp::build(OpBuilder &builder, Region *region = state.addRegion(); Block &block = region->emplaceBlock(); builder.setInsertionPointToEnd(&block); - builder.create(builder.getUnknownLoc(), ValueRange()); + LoopScheduleRegisterOp::create(builder, builder.getUnknownLoc(), + ValueRange()); } unsigned LoopSchedulePipelineStageOp::getStageNumber() { diff --git a/lib/Dialect/MSFT/DeviceDB.cpp b/lib/Dialect/MSFT/DeviceDB.cpp index fcdb2750fb..69e75a7709 100644 --- a/lib/Dialect/MSFT/DeviceDB.cpp +++ b/lib/Dialect/MSFT/DeviceDB.cpp @@ -89,10 +89,9 @@ PDPhysLocationOp PlacementDB::place(DynamicInstanceOp inst, StringAttr subPathAttr; if (!subPath.empty()) subPathAttr = StringAttr::get(inst->getContext(), subPath); - PDPhysLocationOp locOp = - OpBuilder(inst.getBody()) - .create(srcLoc, loc, subPathAttr, - FlatSymbolRefAttr()); + auto builder = OpBuilder(inst.getBody()); + PDPhysLocationOp locOp = PDPhysLocationOp::create( + builder, srcLoc, loc, subPathAttr, FlatSymbolRefAttr()); if (succeeded(insertPlacement(locOp, locOp.getLoc()))) return locOp; locOp->erase(); @@ -101,9 +100,9 @@ PDPhysLocationOp PlacementDB::place(DynamicInstanceOp inst, PDRegPhysLocationOp PlacementDB::place(DynamicInstanceOp inst, LocationVectorAttr locs, Location srcLoc) { + auto builder = OpBuilder(inst.getBody()); PDRegPhysLocationOp locOp = - OpBuilder(inst.getBody()) - .create(srcLoc, locs, FlatSymbolRefAttr()); + PDRegPhysLocationOp::create(builder, srcLoc, locs, FlatSymbolRefAttr()); for (PhysLocationAttr loc : locs.getLocs()) if (failed(insertPlacement(locOp, loc))) { locOp->erase(); @@ -136,10 +135,10 @@ PDPhysRegionOp PlacementDB::placeIn(DynamicInstanceOp inst, StringAttr subPathAttr; if (!subPath.empty()) subPathAttr = StringAttr::get(inst->getContext(), subPath); - PDPhysRegionOp regOp = - OpBuilder::atBlockEnd(&inst.getBody().front()) - .create(srcLoc, FlatSymbolRefAttr::get(physregion), - subPathAttr, FlatSymbolRefAttr()); + auto builder = OpBuilder::atBlockEnd(&inst.getBody().front()); + PDPhysRegionOp regOp = PDPhysRegionOp::create( + builder, srcLoc, FlatSymbolRefAttr::get(physregion), subPathAttr, + FlatSymbolRefAttr()); regionPlacements.push_back(regOp); return regOp; } diff --git a/lib/Dialect/MSFT/ExportQuartusTcl.cpp b/lib/Dialect/MSFT/ExportQuartusTcl.cpp index 44ddfe4412..be04789129 100644 --- a/lib/Dialect/MSFT/ExportQuartusTcl.cpp +++ b/lib/Dialect/MSFT/ExportQuartusTcl.cpp @@ -335,9 +335,9 @@ LogicalResult TclEmitter::emit(Operation *hwMod, StringRef outputFile) { // Create a verbatim op containing the Tcl and symbol references. auto builder = ImplicitLocOpBuilder::atBlockEnd( UnknownLoc::get(hwMod->getContext()), hwMod->getBlock()); - builder.create(outputFile, [&] { - builder.create(os.str(), ValueRange{}, - builder.getArrayAttr(state.symbolRefs)); + emit::FileOp::create(builder, outputFile, [&] { + sv::VerbatimOp::create(builder, os.str(), ValueRange{}, + builder.getArrayAttr(state.symbolRefs)); }); return success(); diff --git a/lib/Dialect/MSFT/Transforms/MSFTLowerConstructs.cpp b/lib/Dialect/MSFT/Transforms/MSFTLowerConstructs.cpp index f92cf07461..1357042be2 100644 --- a/lib/Dialect/MSFT/Transforms/MSFTLowerConstructs.cpp +++ b/lib/Dialect/MSFT/Transforms/MSFTLowerConstructs.cpp @@ -87,9 +87,9 @@ public: for (size_t rowNum = 0, numRows = rowInputs.getNumElements(); rowNum < numRows; ++rowNum) { Value rowNumVal = - rewriter.create(loc, rowIdxType, rowNum); - auto rowValue = - rewriter.create(loc, array.getRowInputs(), rowNumVal); + hw::ConstantOp::create(rewriter, loc, rowIdxType, rowNum); + auto rowValue = hw::ArrayGetOp::create(rewriter, loc, + array.getRowInputs(), rowNumVal); rowValue->setAttr("sv.namehint", StringAttr::get(ctxt, "row_" + Twine(rowNum))); rowValues.push_back(rowValue); @@ -105,9 +105,9 @@ public: for (size_t colNum = 0, numCols = colInputs.getNumElements(); colNum < numCols; ++colNum) { Value colNumVal = - rewriter.create(loc, colIdxType, colNum); - auto colValue = - rewriter.create(loc, array.getColInputs(), colNumVal); + hw::ConstantOp::create(rewriter, loc, colIdxType, colNum); + auto colValue = hw::ArrayGetOp::create(rewriter, loc, + array.getColInputs(), colNumVal); colValue->setAttr("sv.namehint", StringAttr::get(ctxt, "col_" + Twine(colNum))); colValues.push_back(colValue); @@ -154,12 +154,12 @@ public: // vectors. std::reverse(colPEOutputs.begin(), colPEOutputs.end()); peOutputs.push_back( - rewriter.create(loc, colPEOutputs)); + hw::ArrayCreateOp::create(rewriter, loc, colPEOutputs)); } std::reverse(peOutputs.begin(), peOutputs.end()); rewriter.replaceOp(array, - rewriter.create(loc, peOutputs)); + hw::ArrayCreateOp::create(rewriter, loc, peOutputs)); return success(); } }; diff --git a/lib/Dialect/MSFT/Transforms/MSFTLowerInstances.cpp b/lib/Dialect/MSFT/Transforms/MSFTLowerInstances.cpp index af68aad147..d86c0452f5 100644 --- a/lib/Dialect/MSFT/Transforms/MSFTLowerInstances.cpp +++ b/lib/Dialect/MSFT/Transforms/MSFTLowerInstances.cpp @@ -73,7 +73,7 @@ LogicalResult LowerInstancesPass::lower(DynamicInstanceOp inst, // Create a hierpath to replace us. ArrayAttr hierPath = inst.getPath(); - ref = b.create(inst.getLoc(), refSym, hierPath); + ref = hw::HierPathOp::create(b, inst.getLoc(), refSym, hierPath); // Add the new symbol to the symbol cache. topSyms.addDefinition(refSym, ref); diff --git a/lib/Dialect/Moore/MooreDialect.cpp b/lib/Dialect/Moore/MooreDialect.cpp index 64341d36e3..7bb17beb3f 100644 --- a/lib/Dialect/Moore/MooreDialect.cpp +++ b/lib/Dialect/Moore/MooreDialect.cpp @@ -37,7 +37,7 @@ Operation *MooreDialect::materializeConstant(OpBuilder &builder, Location loc) { if (auto intType = dyn_cast(type)) if (auto intValue = dyn_cast(value)) - return builder.create(loc, intType, intValue); + return ConstantOp::create(builder, loc, intType, intValue); return nullptr; } diff --git a/lib/Dialect/Moore/MooreOps.cpp b/lib/Dialect/Moore/MooreOps.cpp index 07e1f768b3..c1b565031f 100644 --- a/lib/Dialect/Moore/MooreOps.cpp +++ b/lib/Dialect/Moore/MooreOps.cpp @@ -268,7 +268,7 @@ LogicalResult VariableOp::canonicalize(VariableOp op, if (initial && mlir::mayHaveSSADominance(*op->getParentRegion())) { rewriter.modifyOpInPlace(op, [&] { op.getInitialMutable().clear(); }); rewriter.setInsertionPointAfter(op); - rewriter.create(initial.getLoc(), op, initial); + BlockingAssignOp::create(rewriter, initial.getLoc(), op, initial); return success(); } @@ -301,8 +301,8 @@ LogicalResult VariableOp::canonicalize(VariableOp op, // replacement. Otherwise substitute the assigned value directly. Value assignedValue = uniqueAssignOp.getSrc(); if (auto name = op.getNameAttr(); name && !name.empty()) - assignedValue = rewriter.create( - op.getLoc(), name, uniqueAssignOp.getSrc()); + assignedValue = AssignedVariableOp::create(rewriter, op.getLoc(), name, + uniqueAssignOp.getSrc()); // Remove the assign op and replace all reads with the new assigned var op. rewriter.eraseOp(uniqueAssignOp); @@ -341,11 +341,11 @@ Value VariableOp::getDefaultValue(const MemorySlot &slot, OpBuilder &builder) { auto fvint = packedType.getDomain() == Domain::FourValued ? FVInt::getAllX(*bitWidth) : FVInt::getZero(*bitWidth); - Value value = builder.create( - getLoc(), IntType::get(getContext(), *bitWidth, packedType.getDomain()), - fvint); + Value value = ConstantOp::create( + builder, getLoc(), + IntType::get(getContext(), *bitWidth, packedType.getDomain()), fvint); if (value.getType() != packedType) - builder.create(getLoc(), packedType, value); + ConversionOp::create(builder, getLoc(), packedType, value); return value; } @@ -398,7 +398,7 @@ DenseMap VariableOp::destructure( varName = StringAttr::get( getContext(), (*name) + "." + cast(index).getValue()); auto varOp = - builder.create(getLoc(), elemType, varName, Value()); + VariableOp::create(builder, getLoc(), elemType, varName, Value()); newAllocators.push_back(varOp); slotMap.try_emplace(index, {varOp.getResult(), elemType}); } @@ -467,8 +467,8 @@ LogicalResult NetOp::canonicalize(NetOp op, PatternRewriter &rewriter) { // replacement. Otherwise substitute the assigned value directly. auto assignedValue = op.getAssignment(); if (auto name = op.getNameAttr(); name && !name.empty()) - assignedValue = - rewriter.create(op.getLoc(), name, assignedValue); + assignedValue = AssignedVariableOp::create(rewriter, op.getLoc(), name, + assignedValue); // Replace all reads with the new assigned var op and remove the original // net op. @@ -908,8 +908,8 @@ LogicalResult StructInjectOp::canonicalize(StructInjectOp op, // of field values contains the last assigned value for each field. for (auto member : members) if (auto value = fieldValues.lookup(member.name)) - input = rewriter.create(op.getLoc(), op.getType(), input, - member.name, value); + input = StructInjectOp::create(rewriter, op.getLoc(), op.getType(), input, + member.name, value); rewriter.replaceOp(op, input); return success(); } @@ -1147,18 +1147,18 @@ LogicalResult PowSOp::canonicalize(PowSOp op, PatternRewriter &rewriter) { auto intType = cast(op.getRhs().getType()); if (auto baseOp = op.getLhs().getDefiningOp()) { if (baseOp.getValue() == 2) { - Value constOne = rewriter.create(loc, intType, 1); - Value constZero = rewriter.create(loc, intType, 0); - Value shift = rewriter.create(loc, constOne, op.getRhs()); - Value isNegative = rewriter.create(loc, op.getRhs(), constZero); + Value constOne = ConstantOp::create(rewriter, loc, intType, 1); + Value constZero = ConstantOp::create(rewriter, loc, intType, 0); + Value shift = ShlOp::create(rewriter, loc, constOne, op.getRhs()); + Value isNegative = SltOp::create(rewriter, loc, op.getRhs(), constZero); auto condOp = rewriter.replaceOpWithNewOp( op, op.getLhs().getType(), isNegative); Block *thenBlock = rewriter.createBlock(&condOp.getTrueRegion()); rewriter.setInsertionPointToStart(thenBlock); - rewriter.create(loc, constZero); + YieldOp::create(rewriter, loc, constZero); Block *elseBlock = rewriter.createBlock(&condOp.getFalseRegion()); rewriter.setInsertionPointToStart(elseBlock); - rewriter.create(loc, shift); + YieldOp::create(rewriter, loc, shift); return success(); } } @@ -1179,7 +1179,7 @@ LogicalResult PowUOp::canonicalize(PowUOp op, PatternRewriter &rewriter) { auto intType = cast(op.getRhs().getType()); if (auto baseOp = op.getLhs().getDefiningOp()) { if (baseOp.getValue() == 2) { - Value constOne = rewriter.create(loc, intType, 1); + Value constOne = ConstantOp::create(rewriter, loc, intType, 1); rewriter.replaceOpWithNewOp(op, constOne, op.getRhs()); return success(); } diff --git a/lib/Dialect/Moore/Transforms/LowerConcatRef.cpp b/lib/Dialect/Moore/Transforms/LowerConcatRef.cpp index 262de67036..46e8007660 100644 --- a/lib/Dialect/Moore/Transforms/LowerConcatRef.cpp +++ b/lib/Dialect/Moore/Transforms/LowerConcatRef.cpp @@ -64,14 +64,14 @@ struct ConcatRefLowering : public OpConversionPattern { // small or vice versa. Like "logic [7:0] or [0:7]". // Only able to correctly handle the situation like "[7:0]" now. - auto extract = rewriter.create(op.getLoc(), type, op.getSrc(), - srcWidth - width); + auto extract = ExtractOp::create(rewriter, op.getLoc(), type, op.getSrc(), + srcWidth - width); // Update the real bit width of RHS of assignment. Like "c" the above // description mentioned. srcWidth = srcWidth - width; - rewriter.create(op.getLoc(), operand, extract); + OpTy::create(rewriter, op.getLoc(), operand, extract); } rewriter.eraseOp(op); return success(); diff --git a/lib/Dialect/Moore/Transforms/SimplifyProcedures.cpp b/lib/Dialect/Moore/Transforms/SimplifyProcedures.cpp index c80f3e731a..e587ea5c39 100644 --- a/lib/Dialect/Moore/Transforms/SimplifyProcedures.cpp +++ b/lib/Dialect/Moore/Transforms/SimplifyProcedures.cpp @@ -63,12 +63,13 @@ void SimplifyProceduresPass::runOnOperation() { nestedOp.getOperand(0).getDefiningOp())) { auto resultType = varOp.getResult().getType(); builder.setInsertionPointToStart(&procedureOp.getBody().front()); - auto readOp = builder.create( - nestedOp.getLoc(), cast(resultType).getNestedType(), - varOp.getResult()); - auto newVarOp = builder.create( - nestedOp.getLoc(), resultType, StringAttr{}, Value{}); - builder.create(nestedOp.getLoc(), newVarOp, readOp); + auto readOp = ReadOp::create( + builder, nestedOp.getLoc(), + cast(resultType).getNestedType(), varOp.getResult()); + auto newVarOp = VariableOp::create(builder, nestedOp.getLoc(), + resultType, StringAttr{}, Value{}); + BlockingAssignOp::create(builder, nestedOp.getLoc(), newVarOp, + readOp); builder.clearInsertionPoint(); // Replace the users of the global variable with a corresponding @@ -86,8 +87,8 @@ void SimplifyProceduresPass::runOnOperation() { // has a new value. for (auto [assignOp, localVar, var] : assignOps) { builder.setInsertionPointAfter(assignOp); - auto readOp = builder.create(assignOp.getLoc(), localVar); - builder.create(assignOp.getLoc(), var, readOp); + auto readOp = ReadOp::create(builder, assignOp.getLoc(), localVar); + BlockingAssignOp::create(builder, assignOp.getLoc(), var, readOp); builder.clearInsertionPoint(); } }); diff --git a/lib/Dialect/OM/OMOps.cpp b/lib/Dialect/OM/OMOps.cpp index aba3a97458..01d8070e98 100644 --- a/lib/Dialect/OM/OMOps.cpp +++ b/lib/Dialect/OM/OMOps.cpp @@ -299,8 +299,8 @@ circt::om::ClassOp circt::om::ClassOp::buildSimpleClassOp( OpBuilder &odsBuilder, Location loc, Twine name, ArrayRef formalParamNames, ArrayRef fieldNames, ArrayRef fieldTypes) { - circt::om::ClassOp classOp = odsBuilder.create( - loc, odsBuilder.getStringAttr(name), + circt::om::ClassOp classOp = circt::om::ClassOp::create( + odsBuilder, loc, odsBuilder.getStringAttr(name), odsBuilder.getStrArrayAttr(formalParamNames), odsBuilder.getStrArrayAttr(fieldNames), odsBuilder.getDictionaryAttr(llvm::map_to_vector( @@ -314,12 +314,13 @@ circt::om::ClassOp circt::om::ClassOp::buildSimpleClassOp( mlir::SmallVector locAttrs(fieldNames.size(), LocationAttr(loc)); - odsBuilder.create( - loc, - llvm::map_to_vector( - fieldTypes, - [&](Type type) -> Value { return body->addArgument(type, loc); }), - odsBuilder.getArrayAttr(locAttrs)); + ClassFieldsOp::create(odsBuilder, loc, + llvm::map_to_vector(fieldTypes, + [&](Type type) -> Value { + return body->addArgument(type, + loc); + }), + odsBuilder.getArrayAttr(locAttrs)); odsBuilder.restoreInsertionPoint(prevLoc); @@ -442,8 +443,8 @@ void circt::om::ClassOp::addNewFieldsOp(mlir::OpBuilder &builder, } // Also store the locations incase there's some other analysis that might // be able to use the default FusedLoc representation. - builder.create(builder.getFusedLoc(locs), values, - builder.getArrayAttr(locAttrs)); + ClassFieldsOp::create(builder, builder.getFusedLoc(locs), values, + builder.getArrayAttr(locAttrs)); } mlir::Location circt::om::ClassOp::getFieldLocByIndex(size_t i) { diff --git a/lib/Dialect/OM/Transforms/FreezePaths.cpp b/lib/Dialect/OM/Transforms/FreezePaths.cpp index 2ac161d28a..af3842770a 100644 --- a/lib/Dialect/OM/Transforms/FreezePaths.cpp +++ b/lib/Dialect/OM/Transforms/FreezePaths.cpp @@ -213,9 +213,9 @@ LogicalResult PathVisitor::process(PathCreateOp path) { // Replace the old path operation. OpBuilder builder(path); - auto frozenPath = builder.create( - path.getLoc(), path.getTargetKindAttr(), path->getOperand(0), targetPath, - bottomModule, ref, field); + auto frozenPath = FrozenPathCreateOp::create( + builder, path.getLoc(), path.getTargetKindAttr(), path->getOperand(0), + targetPath, bottomModule, ref, field); path.replaceAllUsesWith(frozenPath.getResult()); path->erase(); @@ -240,8 +240,8 @@ LogicalResult PathVisitor::process(BasePathCreateOp path) { // Replace the old path operation. OpBuilder builder(path); - auto frozenPath = builder.create( - path.getLoc(), path->getOperand(0), targetPath); + auto frozenPath = FrozenBasePathCreateOp::create( + builder, path.getLoc(), path->getOperand(0), targetPath); path.replaceAllUsesWith(frozenPath.getResult()); path->erase(); @@ -250,7 +250,7 @@ LogicalResult PathVisitor::process(BasePathCreateOp path) { LogicalResult PathVisitor::process(EmptyPathOp path) { OpBuilder builder(path); - auto frozenPath = builder.create(path.getLoc()); + auto frozenPath = FrozenEmptyPathOp::create(builder, path.getLoc()); path.replaceAllUsesWith(frozenPath.getResult()); path->erase(); return success(); @@ -290,8 +290,8 @@ LogicalResult PathVisitor::process(ObjectFieldOp objectFieldOp) { // Create a new op with the result type updated to replace path types. OpBuilder builder(objectFieldOp); - auto newObjectFieldOp = builder.create( - objectFieldOp.getLoc(), newResultType, objectFieldOp.getObject(), + auto newObjectFieldOp = ObjectFieldOp::create( + builder, objectFieldOp.getLoc(), newResultType, objectFieldOp.getObject(), objectFieldOp.getFieldPath()); objectFieldOp.replaceAllUsesWith(newObjectFieldOp.getResult()); objectFieldOp->erase(); diff --git a/lib/Dialect/Pipeline/Transforms/ExplicitRegs.cpp b/lib/Dialect/Pipeline/Transforms/ExplicitRegs.cpp index ca4001bd53..1e32203542 100644 --- a/lib/Dialect/Pipeline/Transforms/ExplicitRegs.cpp +++ b/lib/Dialect/Pipeline/Transforms/ExplicitRegs.cpp @@ -271,9 +271,9 @@ void ExplicitRegsPass::runOnPipeline(ScheduledPipelineOp pipeline) { StageOp terminator = cast(predecessorStage->getTerminator()); b.setInsertionPoint(terminator); llvm::SmallVector> clockGates; - b.create(terminator.getLoc(), terminator.getNextStage(), regIns, - passIns, clockGates, b.getArrayAttr(regNames), - b.getArrayAttr(passNames)); + StageOp::create(b, terminator.getLoc(), terminator.getNextStage(), regIns, + passIns, clockGates, b.getArrayAttr(regNames), + b.getArrayAttr(passNames)); terminator.erase(); // ... and add arguments to the next stage. Registers first, then diff --git a/lib/Dialect/Pipeline/Transforms/ScheduleLinearPipeline.cpp b/lib/Dialect/Pipeline/Transforms/ScheduleLinearPipeline.cpp index c57dc066ab..e3fff2d947 100644 --- a/lib/Dialect/Pipeline/Transforms/ScheduleLinearPipeline.cpp +++ b/lib/Dialect/Pipeline/Transforms/ScheduleLinearPipeline.cpp @@ -148,8 +148,8 @@ ScheduleLinearPipelinePass::schedulePipeline(UnscheduledPipelineOp pipeline) { // Create the scheduled pipeline. b.setInsertionPoint(pipeline); - auto schedPipeline = b.template create( - pipeline.getLoc(), pipeline.getDataOutputs().getTypes(), + auto schedPipeline = pipeline::ScheduledPipelineOp::create( + b, pipeline.getLoc(), pipeline.getDataOutputs().getTypes(), pipeline.getInputs(), pipeline.getInputNames(), pipeline.getOutputNames(), pipeline.getClock(), pipeline.getGo(), pipeline.getReset(), pipeline.getStall(), pipeline.getNameAttr()); @@ -180,8 +180,8 @@ ScheduleLinearPipelinePass::schedulePipeline(UnscheduledPipelineOp pipeline) { // Create a StageOp in the new stage, and branch it to the newly created // stage. b.setInsertionPointToEnd(currentStage); - b.create(pipeline.getLoc(), newStage, ValueRange{}, - ValueRange{}); + pipeline::StageOp::create(b, pipeline.getLoc(), newStage, ValueRange{}, + ValueRange{}); currentStage = newStage; } } @@ -207,7 +207,7 @@ ScheduleLinearPipelinePass::schedulePipeline(UnscheduledPipelineOp pipeline) { if (it == sourceOps.end()) { b.setInsertionPoint(opOperand.getOwner()); it = sourceOps - .try_emplace(v, b.create(v.getLoc(), v).getResult()) + .try_emplace(v, SourceOp::create(b, v.getLoc(), v).getResult()) .first; } return it->second; diff --git a/lib/Dialect/SV/SVOps.cpp b/lib/Dialect/SV/SVOps.cpp index 77eeb28250..896480fb28 100644 --- a/lib/Dialect/SV/SVOps.cpp +++ b/lib/Dialect/SV/SVOps.cpp @@ -1112,9 +1112,9 @@ void ForOp::build(OpBuilder &builder, OperationState &result, int64_t lowerBound, int64_t upperBound, int64_t step, IntegerType type, StringRef name, llvm::function_ref body) { - auto lb = builder.create(result.location, type, lowerBound); - auto ub = builder.create(result.location, type, upperBound); - auto st = builder.create(result.location, type, step); + auto lb = hw::ConstantOp::create(builder, result.location, type, lowerBound); + auto ub = hw::ConstantOp::create(builder, result.location, type, upperBound); + auto st = hw::ConstantOp::create(builder, result.location, type, step); build(builder, result, lb, ub, st, name, body); } void ForOp::build(OpBuilder &builder, OperationState &result, Value lowerBound, @@ -1338,10 +1338,10 @@ static LogicalResult mergeNeiboringAssignments(AssignTy op, auto resultType = hw::ArrayType::get( hw::type_cast(src.array.getType()).getElementType(), src.size); - auto newDest = rewriter.create( - op.getLoc(), dest.array, dest.start, dest.size); - auto newSrc = rewriter.create(op.getLoc(), resultType, - src.array, src.start); + auto newDest = sv::IndexedPartSelectInOutOp::create( + rewriter, op.getLoc(), dest.array, dest.start, dest.size); + auto newSrc = hw::ArraySliceOp::create(rewriter, op.getLoc(), resultType, + src.array, src.start); auto newLoc = rewriter.getFusedLoc(loc); auto newOp = rewriter.replaceOpWithNewOp(op, newDest, newSrc); newOp->setLoc(newLoc); @@ -1391,7 +1391,7 @@ Type InterfaceOp::getSignalType(StringRef signalName) { static ParseResult parseModportStructs(OpAsmParser &parser, ArrayAttr &portsAttr) { - auto context = parser.getBuilder().getContext(); + auto *context = parser.getBuilder().getContext(); SmallVector ports; auto parseElement = [&]() -> ParseResult { @@ -1670,8 +1670,8 @@ LogicalResult WireOp::canonicalize(WireOp wire, PatternRewriter &rewriter) { // If no write and only reads, then replace with ZOp. // SV 6.6: "If no driver is connected to a net, its // value shall be high-impedance (z) unless the net is a trireg" - connected = rewriter.create( - wire.getLoc(), + connected = ConstantZOp::create( + rewriter, wire.getLoc(), cast(wire.getResult().getType()).getElementType()); } else if (isa(write->getParentOp())) connected = write.getSrc(); @@ -1930,7 +1930,7 @@ BindInterfaceOp::getReferencedInstance(const hw::HWSymbolCache *cache) { /// Ensure that the symbol being instantiated exists and is an InterfaceOp. LogicalResult BindInterfaceOp::verifySymbolUses(SymbolTableCollection &symbolTable) { - auto parentOp = + auto *parentOp = symbolTable.lookupNearestSymbolFrom(*this, getInstance().getModule()); if (!parentOp) return emitError("Referenced module doesn't exist ") diff --git a/lib/Dialect/SV/Transforms/GeneratorCallout.cpp b/lib/Dialect/SV/Transforms/GeneratorCallout.cpp index fb8870fd16..3fd4e46394 100644 --- a/lib/Dialect/SV/Transforms/GeneratorCallout.cpp +++ b/lib/Dialect/SV/Transforms/GeneratorCallout.cpp @@ -159,9 +159,10 @@ void HWGeneratorCalloutPass::processGenerator( // Only extract the first line from the output. auto fileContent = (*bufferRead)->getBuffer().split('\n').first.str(); OpBuilder builder(generatedModuleOp); - auto extMod = builder.create( - generatedModuleOp.getLoc(), generatedModuleOp.getVerilogModuleNameAttr(), - generatedModuleOp.getPortList()); + auto extMod = + hw::HWModuleExternOp::create(builder, generatedModuleOp.getLoc(), + generatedModuleOp.getVerilogModuleNameAttr(), + generatedModuleOp.getPortList()); // Attach an attribute to which file the definition of the external // module exists in. extMod->setAttr("filenames", builder.getStringAttr(fileContent)); diff --git a/lib/Dialect/SV/Transforms/HWEliminateInOutPorts.cpp b/lib/Dialect/SV/Transforms/HWEliminateInOutPorts.cpp index 1396599a51..024e668a68 100644 --- a/lib/Dialect/SV/Transforms/HWEliminateInOutPorts.cpp +++ b/lib/Dialect/SV/Transforms/HWEliminateInOutPorts.cpp @@ -145,14 +145,14 @@ void HWInOutPortConversion::mapInputSignals(OpBuilder &b, Operation *inst, // Create a read_inout op at the instantiation point. This effectively // pushes the read_inout op from the module to the instantiation site. newOperands[readPort.argNum] = - b.create(inst->getLoc(), instValue).getResult(); + ReadInOutOp::create(b, inst->getLoc(), instValue).getResult(); } if (hasWriters()) { // Create a sv::AssignOp at the instantiation point. This effectively // pushes the write op from the module to the instantiation site. Value writeFromInsideMod = newResults[writePort.argNum]; - b.create(inst->getLoc(), instValue, writeFromInsideMod); + sv::AssignOp::create(b, inst->getLoc(), instValue, writeFromInsideMod); } } diff --git a/lib/Dialect/SV/Transforms/HWExportModuleHierarchy.cpp b/lib/Dialect/SV/Transforms/HWExportModuleHierarchy.cpp index f0751a0854..233b5d08b6 100644 --- a/lib/Dialect/SV/Transforms/HWExportModuleHierarchy.cpp +++ b/lib/Dialect/SV/Transforms/HWExportModuleHierarchy.cpp @@ -134,9 +134,9 @@ void HWExportModuleHierarchyPass::runOnOperation() { auto builder = ImplicitLocOpBuilder::atBlockEnd( UnknownLoc::get(mlirModule.getContext()), mlirModule.getBody()); - builder.create(file.getFilename(), [&] { - builder.create(jsonBuffer, ValueRange{}, - builder.getArrayAttr(symbols)); + emit::FileOp::create(builder, file.getFilename(), [&] { + sv::VerbatimOp::create(builder, jsonBuffer, ValueRange{}, + builder.getArrayAttr(symbols)); }); } } diff --git a/lib/Dialect/SV/Transforms/HWLegalizeModules.cpp b/lib/Dialect/SV/Transforms/HWLegalizeModules.cpp index 74ff3bb66e..142f3cc85c 100644 --- a/lib/Dialect/SV/Transforms/HWLegalizeModules.cpp +++ b/lib/Dialect/SV/Transforms/HWLegalizeModules.cpp @@ -74,10 +74,11 @@ bool HWLegalizeModulesPass::tryLoweringPackedArrayOp(Operation &op) { for (auto field : llvm::reverse(constOp.getFields())) { if (auto intAttr = dyn_cast(field)) inputs.push_back( - builder.create(constOp.getLoc(), intAttr)); + hw::ConstantOp::create(builder, constOp.getLoc(), intAttr)); else - inputs.push_back(builder.create( - constOp.getLoc(), constOp.getType(), cast(field))); + inputs.push_back(hw::AggregateConstantOp::create( + builder, constOp.getLoc(), constOp.getType(), + cast(field))); } if (!processUsers(op, constOp.getResult(), inputs)) return false; @@ -151,7 +152,7 @@ bool HWLegalizeModulesPass::tryLoweringPackedArrayOp(Operation &op) { auto index = builder.createOrFold( loc, APInt(llvm::Log2_64_Ceil(e), i)); auto element = - builder.create(loc, getOp.getInput(), index); + hw::ArrayGetOp::create(builder, loc, getOp.getInput(), index); caseValues.push_back(element); } @@ -162,7 +163,7 @@ bool HWLegalizeModulesPass::tryLoweringPackedArrayOp(Operation &op) { // Emit the read from the wire, replace uses and clean up. builder.setInsertionPoint(getOp); auto readWire = - builder.create(getOp.getLoc(), theWire); + sv::ReadInOutOp::create(builder, getOp.getLoc(), theWire); getOp.getResult().replaceAllUsesWith(readWire); return true; }) @@ -186,9 +187,9 @@ bool HWLegalizeModulesPass::tryLoweringPackedArrayOp(Operation &op) { auto loc = op.getLoc(); auto index = builder.createOrFold( loc, APInt(llvm::Log2_64_Ceil(e), i)); - auto element = builder.create( - loc, indexOp.getInput(), index); - auto readElement = builder.create(loc, element); + auto element = sv::ArrayIndexInOutOp::create( + builder, loc, indexOp.getInput(), index); + auto readElement = sv::ReadInOutOp::create(builder, loc, element); caseValues.push_back(readElement); } @@ -213,11 +214,11 @@ bool HWLegalizeModulesPass::tryLoweringPackedArrayOp(Operation &op) { auto loc = op.getLoc(); auto index = builder.createOrFold( loc, APInt(llvm::Log2_64_Ceil(e), i)); - auto dstElement = builder.create( - loc, assignOp.getDest(), index); + auto dstElement = sv::ArrayIndexInOutOp::create( + builder, loc, assignOp.getDest(), index); auto srcElement = - builder.create(loc, assignOp.getSrc(), index); - builder.create(loc, dstElement, srcElement); + hw::ArrayGetOp::create(builder, loc, assignOp.getSrc(), index); + sv::PAssignOp::create(builder, loc, dstElement, srcElement); } // Remove original assignment. @@ -234,7 +235,7 @@ bool HWLegalizeModulesPass::tryLoweringPackedArrayOp(Operation &op) { SmallVector elements; for (size_t i = 0, e = ty.getNumElements(); i < e; i++) { auto loc = op.getLoc(); - auto element = builder.create(loc, ty.getElementType()); + auto element = sv::RegOp::create(builder, loc, ty.getElementType()); if (auto nameAttr = regOp->getAttrOfType(name)) { element.setNameAttr( StringAttr::get(regOp.getContext(), nameAttr.getValue())); @@ -259,8 +260,8 @@ Value HWLegalizeModulesPass::lowerLookupToCasez(Operation &op, Value input, // Create the wire for the result of the casez in the // hw.module. OpBuilder builder(&op); - auto theWire = builder.create(op.getLoc(), elementType, - builder.getStringAttr("casez_tmp")); + auto theWire = sv::RegOp::create(builder, op.getLoc(), elementType, + builder.getStringAttr("casez_tmp")); builder.setInsertionPoint(&op); auto loc = input.getLoc(); @@ -268,23 +269,23 @@ Value HWLegalizeModulesPass::lowerLookupToCasez(Operation &op, Value input, // non-procedural region we need to inject an always_comb // block. if (!op.getParentOp()->hasTrait()) { - auto alwaysComb = builder.create(loc); + auto alwaysComb = sv::AlwaysCombOp::create(builder, loc); builder.setInsertionPointToEnd(alwaysComb.getBodyBlock()); } // If we are missing elements in the array (it is non-power of // two), then add a default 'X' value. if (1ULL << index.getType().getIntOrFloatBitWidth() != caseValues.size()) { - caseValues.push_back(builder.create( - op.getLoc(), op.getResult(0).getType())); + caseValues.push_back(sv::ConstantXOp::create(builder, op.getLoc(), + op.getResult(0).getType())); } APInt caseValue(index.getType().getIntOrFloatBitWidth(), 0); auto *context = builder.getContext(); // Create the casez itself. - builder.create( - loc, CaseStmtType::CaseZStmt, index, caseValues.size(), + sv::CaseOp::create( + builder, loc, CaseStmtType::CaseZStmt, index, caseValues.size(), [&](size_t caseIdx) -> std::unique_ptr { // Use a default pattern for the last value, even if we // are complete. This avoids tools thinking they need to @@ -299,7 +300,7 @@ Value HWLegalizeModulesPass::lowerLookupToCasez(Operation &op, Value input, else thePattern = std::make_unique(caseValue, context); ++caseValue; - builder.create(loc, theWire, theValue); + sv::BPAssignOp::create(builder, loc, theWire, theValue); return thePattern; }); diff --git a/lib/Dialect/SV/Transforms/HWStubExternalModules.cpp b/lib/Dialect/SV/Transforms/HWStubExternalModules.cpp index 4bb211cbdf..0cab92b2a8 100644 --- a/lib/Dialect/SV/Transforms/HWStubExternalModules.cpp +++ b/lib/Dialect/SV/Transforms/HWStubExternalModules.cpp @@ -45,15 +45,15 @@ void HWStubExternalModulesPass::runOnOperation() { if (auto module = dyn_cast(op)) { hw::ModulePortInfo ports(module.getPortList()); auto nameAttr = module.getNameAttr(); - auto newModule = builder.create( - module.getLoc(), nameAttr, ports, module.getParameters()); + auto newModule = hw::HWModuleOp::create( + builder, module.getLoc(), nameAttr, ports, module.getParameters()); auto outputOp = newModule.getBodyBlock()->getTerminator(); OpBuilder innerBuilder(outputOp); SmallVector outputs; // All output ports need values, use x for (auto &p : ports.getOutputs()) { outputs.push_back( - innerBuilder.create(outputOp->getLoc(), p.type)); + sv::ConstantXOp::create(innerBuilder, outputOp->getLoc(), p.type)); } outputOp->setOperands(outputs); diff --git a/lib/Dialect/SV/Transforms/PrettifyVerilog.cpp b/lib/Dialect/SV/Transforms/PrettifyVerilog.cpp index c8114f50ad..8769bc4ab5 100644 --- a/lib/Dialect/SV/Transforms/PrettifyVerilog.cpp +++ b/lib/Dialect/SV/Transforms/PrettifyVerilog.cpp @@ -151,9 +151,9 @@ bool PrettifyVerilogPass::splitStructAssignment(OpBuilder &builder, continue; auto &[loc, value] = it->second; - auto ref = builder.create(loc, dst, name); + auto ref = sv::StructFieldInOutOp::create(builder, loc, dst, name); if (!splitAssignment(builder, ref, value)) - builder.create(loc, ref, value); + sv::PAssignOp::create(builder, loc, ref, value); } return true; } @@ -173,11 +173,11 @@ bool PrettifyVerilogPass::splitArrayAssignment(OpBuilder &builder, Value value = op.getInputs()[0]; auto loc = op.getLoc(); - auto index = builder.create(loc, zero); + auto index = hw::ConstantOp::create(builder, loc, zero); - auto field = builder.create(loc, dst, index); + auto field = sv::ArrayIndexInOutOp::create(builder, loc, dst, index); if (!splitAssignment(builder, field, value)) - builder.create(loc, field, value); + sv::PAssignOp::create(builder, loc, field, value); return true; } @@ -263,10 +263,10 @@ bool PrettifyVerilogPass::splitArrayAssignment(OpBuilder &builder, for (auto &[i, loc, value] : fields) { if (i == last) continue; - auto index = builder.create(loc, i); - auto field = builder.create(loc, dst, index); + auto index = hw::ConstantOp::create(builder, loc, i); + auto field = sv::ArrayIndexInOutOp::create(builder, loc, dst, index); if (!splitAssignment(builder, field, value)) - builder.create(loc, field, value); + sv::PAssignOp::create(builder, loc, field, value); last = i; } return true; diff --git a/lib/Dialect/SV/Transforms/SVExtractTestCode.cpp b/lib/Dialect/SV/Transforms/SVExtractTestCode.cpp index 1387ad8ab7..a69d84a9cc 100644 --- a/lib/Dialect/SV/Transforms/SVExtractTestCode.cpp +++ b/lib/Dialect/SV/Transforms/SVExtractTestCode.cpp @@ -227,8 +227,8 @@ static hw::HWModuleOp createModuleForCut(hw::HWModuleOp op, } // Create the module, setting the output path if indicated. - auto newMod = b.create( - op.getLoc(), + auto newMod = hw::HWModuleOp::create( + b, op.getLoc(), b.getStringAttr(getVerilogModuleNameAttr(op).getValue() + suffix), ports); if (path) newMod->setAttr("output_file", path); @@ -247,8 +247,8 @@ static hw::HWModuleOp createModuleForCut(hw::HWModuleOp op, // Add an instance in the old module for the extracted module b = OpBuilder::atBlockTerminator(op.getBodyBlock()); - auto inst = b.create( - op.getLoc(), newMod, newMod.getName(), realInputs, ArrayAttr(), + auto inst = hw::InstanceOp::create( + b, op.getLoc(), newMod, newMod.getName(), realInputs, ArrayAttr(), hw::InnerSymAttr::get(b.getStringAttr( ("__ETC_" + getVerilogModuleNameAttr(op).getValue() + suffix) .str()))); @@ -256,8 +256,8 @@ static hw::HWModuleOp createModuleForCut(hw::HWModuleOp op, b = OpBuilder::atBlockEnd( &op->getParentOfType()->getRegion(0).front()); - auto bindOp = b.create(op.getLoc(), op.getNameAttr(), - inst.getInnerSymAttr().getSymName()); + auto bindOp = sv::BindOp::create(b, op.getLoc(), op.getNameAttr(), + inst.getInnerSymAttr().getSymName()); bindTable[op.getNameAttr()][inst.getInnerSymAttr().getSymName()] = bindOp; if (fileName) bindOp->setAttr("output_file", fileName); diff --git a/lib/Dialect/SV/Transforms/SVTraceIVerilog.cpp b/lib/Dialect/SV/Transforms/SVTraceIVerilog.cpp index 4dd0e55615..7d35ba8264 100644 --- a/lib/Dialect/SV/Transforms/SVTraceIVerilog.cpp +++ b/lib/Dialect/SV/Transforms/SVTraceIVerilog.cpp @@ -74,7 +74,7 @@ void SVTraceIVerilogPass::runOnOperation() { ss << "initial begin\n $dumpfile (\"" << directoryName.getValue() << modName << ".vcd\");\n $dumpvars (0, " << modName << ");\n #1;\nend\n"; - builder.create(hwmod.getLoc(), ss.str()); + sv::VerbatimOp::create(builder, hwmod.getLoc(), ss.str()); } } diff --git a/lib/Dialect/Seq/SeqDialect.cpp b/lib/Dialect/Seq/SeqDialect.cpp index 89e9d566d1..7cb8f53ff9 100644 --- a/lib/Dialect/Seq/SeqDialect.cpp +++ b/lib/Dialect/Seq/SeqDialect.cpp @@ -47,11 +47,11 @@ Operation *SeqDialect::materializeConstant(OpBuilder &builder, Attribute value, // Integer constants. if (auto intType = dyn_cast(type)) if (auto attrValue = dyn_cast(value)) - return builder.create(loc, type, attrValue); + return hw::ConstantOp::create(builder, loc, type, attrValue); if (isa(type)) if (auto attrValue = dyn_cast(value)) - return builder.create(loc, attrValue); + return seq::ConstClockOp::create(builder, loc, attrValue); return nullptr; } diff --git a/lib/Dialect/Seq/SeqOps.cpp b/lib/Dialect/Seq/SeqOps.cpp index 63ab450fa3..9ba325767d 100644 --- a/lib/Dialect/Seq/SeqOps.cpp +++ b/lib/Dialect/Seq/SeqOps.cpp @@ -626,8 +626,8 @@ LogicalResult FirRegOp::canonicalize(FirRegOp op, PatternRewriter &rewriter) { rewriter.replaceOpWithNewOp( op, seq::ClockConstAttr::get(rewriter.getContext(), ClockConst::Low)); } else { - auto constant = rewriter.create( - op.getLoc(), APInt::getZero(hw::getBitWidth(op.getType()))); + auto constant = hw::ConstantOp::create( + rewriter, op.getLoc(), APInt::getZero(hw::getBitWidth(op.getType()))); rewriter.replaceOpWithNewOp(op, op.getType(), constant); } return success(); @@ -704,8 +704,8 @@ LogicalResult FirRegOp::canonicalize(FirRegOp op, PatternRewriter &rewriter) { matchPattern(arrayGet.getIndex(), m_ConstantInt(&elementIndex)) && elementIndex == index) { - nextOperands.push_back(rewriter.create( - op.getLoc(), + nextOperands.push_back(hw::ConstantOp::create( + rewriter, op.getLoc(), APInt::getZero(hw::getBitWidth(arrayGet.getType())))); changed = true; continue; @@ -714,8 +714,8 @@ LogicalResult FirRegOp::canonicalize(FirRegOp op, PatternRewriter &rewriter) { } // If one of the operands is self loop, update the next value. if (changed) { - auto newNextVal = rewriter.create( - arrayCreate.getLoc(), nextOperands); + auto newNextVal = hw::ArrayCreateOp::create( + rewriter, arrayCreate.getLoc(), nextOperands); if (arrayCreate->hasOneUse()) // If the original next value has a single use, we can replace the // value directly. @@ -889,11 +889,12 @@ LogicalResult FirMemOp::canonicalize(FirMemOp op, PatternRewriter &rewriter) { // Replace all read ports with a constant 0. for (auto *user : llvm::make_early_inc_range(op->getUsers())) { auto readOp = cast(user); - Value zero = rewriter.create( - readOp.getLoc(), APInt::getZero(hw::getBitWidth(readOp.getType()))); + Value zero = hw::ConstantOp::create( + rewriter, readOp.getLoc(), + APInt::getZero(hw::getBitWidth(readOp.getType()))); if (readOp.getType() != zero.getType()) - zero = rewriter.create(readOp.getLoc(), readOp.getType(), - zero); + zero = hw::BitcastOp::create(rewriter, readOp.getLoc(), + readOp.getType(), zero); rewriter.replaceOp(readOp, zero); } rewriter.eraseOp(op); @@ -1157,9 +1158,9 @@ void InitialOp::build(OpBuilder &builder, OperationState &result, TypedValue circt::seq::createConstantInitialValue(OpBuilder builder, Location loc, mlir::IntegerAttr attr) { - auto initial = builder.create(loc, attr.getType(), [&]() { - auto constant = builder.create(loc, attr); - builder.create(loc, ArrayRef{constant}); + auto initial = seq::InitialOp::create(builder, loc, attr.getType(), [&]() { + auto constant = hw::ConstantOp::create(builder, loc, attr); + seq::YieldOp::create(builder, loc, ArrayRef{constant}); }); return cast>(initial->getResult(0)); } @@ -1168,10 +1169,10 @@ mlir::TypedValue circt::seq::createConstantInitialValue(OpBuilder builder, Operation *op) { assert(op->getNumResults() == 1 && op->hasTrait()); - auto initial = - builder.create(op->getLoc(), op->getResultTypes(), [&]() { + auto initial = seq::InitialOp::create( + builder, op->getLoc(), op->getResultTypes(), [&]() { auto clonedOp = builder.clone(*op); - builder.create(op->getLoc(), clonedOp->getResults()); + seq::YieldOp::create(builder, op->getLoc(), clonedOp->getResults()); }); return cast>(initial.getResult(0)); } @@ -1254,7 +1255,7 @@ FailureOr circt::seq::mergeInitialOps(Block *block) { // Create a new initial op which accumulates the results of the merged initial // ops. - auto newInitial = builder.create(initialOp.getLoc(), types); + auto newInitial = seq::InitialOp::create(builder, initialOp.getLoc(), types); newInitial.getInputsMutable().append(initialOp.getInputs()); for (auto [resultAndOperand, newResult] : diff --git a/lib/Dialect/Seq/Transforms/ExternalizeClockGate.cpp b/lib/Dialect/Seq/Transforms/ExternalizeClockGate.cpp index a15a93613e..2e7e0acfdd 100644 --- a/lib/Dialect/Seq/Transforms/ExternalizeClockGate.cpp +++ b/lib/Dialect/Seq/Transforms/ExternalizeClockGate.cpp @@ -64,9 +64,9 @@ void ExternalizeClockGatePass::runOnOperation() { modulePorts.push_back({{builder.getStringAttr(testEnableName), i1Type, ModulePort::Direction::Input}}); - auto externModuleOp = builder.create( - getOperation().getLoc(), builder.getStringAttr(moduleName), modulePorts, - moduleName); + auto externModuleOp = HWModuleExternOp::create( + builder, getOperation().getLoc(), builder.getStringAttr(moduleName), + modulePorts, moduleName); symtbl.insert(externModuleOp); // Replace all clock gates with an instance of the external module. @@ -84,7 +84,7 @@ void ExternalizeClockGatePass::runOnOperation() { // constant 0 input. if (hasTestEnable && !testEnable) { if (!cstFalse) { - cstFalse = builder.create(i1Type, 0); + cstFalse = ConstantOp::create(builder, i1Type, 0); } testEnable = cstFalse; } @@ -102,7 +102,7 @@ void ExternalizeClockGatePass::runOnOperation() { if (it.second) { ImplicitLocOpBuilder builder(input.getLoc(), &getContext()); builder.setInsertionPointAfterValue(input); - it.first->second = builder.create(input); + it.first->second = seq::FromClockOp::create(builder, input); } instPorts.push_back(it.first->second); } else { @@ -112,13 +112,13 @@ void ExternalizeClockGatePass::runOnOperation() { if (testEnable) instPorts.push_back(testEnable); - auto instOp = builder.create( - externModuleOp, builder.getStringAttr(instName), instPorts, + auto instOp = InstanceOp::create( + builder, externModuleOp, builder.getStringAttr(instName), instPorts, builder.getArrayAttr({}), ckgOp.getInnerSymAttr()); Value output = instOp.getResult(0); if (hw::type_isa(input.getType())) - output = builder.create(output); + output = seq::ToClockOp::create(builder, output); ckgOp.replaceAllUsesWith(output); ckgOp.erase(); diff --git a/lib/Dialect/Seq/Transforms/HWMemSimImpl.cpp b/lib/Dialect/Seq/Transforms/HWMemSimImpl.cpp index cf098f9b00..853de3b21d 100644 --- a/lib/Dialect/Seq/Transforms/HWMemSimImpl.cpp +++ b/lib/Dialect/Seq/Transforms/HWMemSimImpl.cpp @@ -108,8 +108,8 @@ static bool valueDefinedBeforeOp(Value value, Operation *op) { // annotations. static Value getMemoryRead(ImplicitLocOpBuilder &b, Value memory, Value addr, bool addMuxPragmas) { - auto slot = - b.create(b.create(memory, addr)); + auto slot = sv::ReadInOutOp::create( + b, sv::ArrayIndexInOutOp::create(b, memory, addr)); // If we don't want to add mux pragmas, just return the read value. if (!addMuxPragmas || cast( @@ -119,14 +119,14 @@ static Value getMemoryRead(ImplicitLocOpBuilder &b, Value memory, Value addr, circt::sv::setSVAttributes( slot, sv::SVAttributeAttr::get(b.getContext(), "cadence map_to_mux", /*emitAsComment=*/true)); - auto valWire = b.create(slot.getType()); - auto assignOp = b.create(valWire, slot); + auto valWire = sv::WireOp::create(b, slot.getType()); + auto assignOp = sv::AssignOp::create(b, valWire, slot); sv::setSVAttributes(assignOp, sv::SVAttributeAttr::get(b.getContext(), "synopsys infer_mux_override", /*emitAsComment=*/true)); - return b.create(valWire); + return sv::ReadInOutOp::create(b, valWire); } Value HWMemSimImpl::addPipelineStages(ImplicitLocOpBuilder &b, @@ -146,7 +146,7 @@ Value HWMemSimImpl::addPipelineStages(ImplicitLocOpBuilder &b, alwaysOp = {}; } if (!alwaysOp) - alwaysOp = b.create(sv::EventControl::AtPosEdge, clock); + alwaysOp = sv::AlwaysOp::create(b, sv::EventControl::AtPosEdge, clock); // Add the necessary registers. auto savedIP = b.saveInsertionPoint(); @@ -155,8 +155,8 @@ Value HWMemSimImpl::addPipelineStages(ImplicitLocOpBuilder &b, for (unsigned i = 0; i < stages; ++i) { auto regName = b.getStringAttr(moduleNamespace.newName("_" + name + "_d" + Twine(i))); - auto reg = b.create(data.getType(), regName, - hw::InnerSymAttr::get(regName)); + auto reg = sv::RegOp::create(b, data.getType(), regName, + hw::InnerSymAttr::get(regName)); regs.push_back(reg); registers.push_back(reg); } @@ -165,17 +165,17 @@ Value HWMemSimImpl::addPipelineStages(ImplicitLocOpBuilder &b, b.setInsertionPointToEnd(alwaysOp.getBodyBlock()); for (unsigned i = 0; i < stages; ++i) { if (i > 0) - data = b.create(data); - auto emitAssign = [&] { b.create(regs[i], data); }; + data = sv::ReadInOutOp::create(b, data); + auto emitAssign = [&] { sv::PAssignOp::create(b, regs[i], data); }; if (gate) - b.create(gate, [&]() { emitAssign(); }); + sv::IfOp::create(b, gate, [&]() { emitAssign(); }); else emitAssign(); data = regs[i]; gate = {}; } b.restoreInsertionPoint(savedIP); - data = b.create(data); + data = sv::ReadInOutOp::create(b, data); lastPipelineAlwaysOp = alwaysOp; return data; @@ -199,8 +199,9 @@ void HWMemSimImpl::generateMemory(HWModuleOp op, FirMemory mem) { mem.numReadPorts + mem.numWritePorts + mem.numReadWritePorts; // Create registers for the memory. - sv::RegOp reg = b.create( - UnpackedArrayType::get(dataType, mem.depth), b.getStringAttr("Memory")); + sv::RegOp reg = + sv::RegOp::create(b, UnpackedArrayType::get(dataType, mem.depth), + b.getStringAttr("Memory")); if (addVivadoRAMAddressConflictSynthesisBugWorkaround) { if (mem.readLatency == 0) { @@ -252,13 +253,13 @@ void HWMemSimImpl::generateMemory(HWModuleOp op, FirMemory mem) { Value rdata = getMemoryRead(b, reg, addr, addMuxPragmas); switch (readEnableMode) { case ReadEnableMode::Undefined: { - Value x = b.create(rdata.getType()); - rdata = b.create(en, rdata, x, false); + Value x = sv::ConstantXOp::create(b, rdata.getType()); + rdata = comb::MuxOp::create(b, en, rdata, x, false); break; } case ReadEnableMode::Zero: { - Value x = b.create(rdata.getType(), 0); - rdata = b.create(en, rdata, x, false); + Value x = hw::ConstantOp::create(b, rdata.getType(), 0); + rdata = comb::MuxOp::create(b, en, rdata, x, false); break; } case ReadEnableMode::Ignore: @@ -282,7 +283,7 @@ void HWMemSimImpl::generateMemory(HWModuleOp op, FirMemory mem) { if (isMasked) wmaskBits = op.getBody().getArgument(inArg++); else - wmaskBits = b.create(b.getIntegerAttr(en.getType(), 1)); + wmaskBits = ConstantOp::create(b, b.getIntegerAttr(en.getType(), 1)); // Add common pipeline stages. addr = addPipelineStages(b, moduleNamespace, numCommonStages, clock, addr, @@ -344,8 +345,8 @@ void HWMemSimImpl::generateMemory(HWModuleOp op, FirMemory mem) { } // wire to store read result - auto rWire = b.create(wdataIn.getType()); - Value rdata = b.create(rWire); + auto rWire = sv::WireOp::create(b, wdataIn.getType()); + Value rdata = sv::ReadInOutOp::create(b, rWire); // Read logic. Value rcond = b.createOrFold( @@ -359,30 +360,31 @@ void HWMemSimImpl::generateMemory(HWModuleOp op, FirMemory mem) { switch (readEnableMode) { case ReadEnableMode::Undefined: { - Value x = b.create(val.getType()); - val = b.create(rcond, val, x, false); + Value x = sv::ConstantXOp::create(b, val.getType()); + val = comb::MuxOp::create(b, rcond, val, x, false); break; } case ReadEnableMode::Zero: { - Value x = b.create(val.getType(), 0); - val = b.create(rcond, val, x, false); + Value x = hw::ConstantOp::create(b, val.getType(), 0); + val = comb::MuxOp::create(b, rcond, val, x, false); break; } case ReadEnableMode::Ignore: break; } - b.create(rWire, val); + sv::AssignOp::create(b, rWire, val); // Write logic gaurded by the corresponding mask bit. for (auto wmask : llvm::enumerate(maskValues)) { - b.create(sv::EventControl::AtPosEdge, clock, [&]() { + sv::AlwaysOp::create(b, sv::EventControl::AtPosEdge, clock, [&]() { auto wcond = b.createOrFold( writeEn, b.createOrFold(wmask.value(), writeWMode, false), false); - b.create(wcond, [&]() { - Value slotReg = b.create(reg, writeAddr); - b.create( + sv::IfOp::create(b, wcond, [&]() { + Value slotReg = sv::ArrayIndexInOutOp::create(b, reg, writeAddr); + sv::PAssignOp::create( + b, b.createOrFold( slotReg, b.createOrFold(b.getIntegerType(32), @@ -408,7 +410,7 @@ void HWMemSimImpl::generateMemory(HWModuleOp op, FirMemory mem) { if (isMasked) wmaskBits = op.getBody().getArgument(inArg++); else - wmaskBits = b.create(b.getIntegerAttr(en.getType(), 1)); + wmaskBits = ConstantOp::create(b, b.getIntegerAttr(en.getType(), 1)); // Add pipeline stages addr = addPipelineStages(b, moduleNamespace, numStages, clock, addr, "W" + Twine(i) + "addr"); @@ -437,9 +439,10 @@ void HWMemSimImpl::generateMemory(HWModuleOp op, FirMemory mem) { for (auto wmask : llvm::enumerate(maskValues)) { // Guard by corresponding mask bit. auto wcond = b.createOrFold(en, wmask.value(), false); - b.create(wcond, [&]() { - auto slot = b.create(reg, addr); - b.create( + sv::IfOp::create(b, wcond, [&]() { + auto slot = sv::ArrayIndexInOutOp::create(b, reg, addr); + sv::PAssignOp::create( + b, b.createOrFold( slot, b.createOrFold(b.getIntegerType(32), @@ -452,8 +455,8 @@ void HWMemSimImpl::generateMemory(HWModuleOp op, FirMemory mem) { // Build a new always block with write port logic. auto alwaysBlock = [&] { - return b.create(sv::EventControl::AtPosEdge, clock, - [&]() { writeLogic(); }); + return sv::AlwaysOp::create(b, sv::EventControl::AtPosEdge, clock, + [&]() { writeLogic(); }); }; switch (mem.writeUnderWrite) { @@ -489,12 +492,11 @@ void HWMemSimImpl::generateMemory(HWModuleOp op, FirMemory mem) { b.getStringAttr(moduleNamespace.newName(reg.getName())))); if (mem.initIsInline) { - b.create("ENABLE_INITIAL_MEM_", [&]() { - b.create([&]() { - b.create(reg, mem.initFilename, - mem.initIsBinary - ? MemBaseTypeAttr::MemBaseBin - : MemBaseTypeAttr::MemBaseHex); + sv::IfDefOp::create(b, "ENABLE_INITIAL_MEM_", [&]() { + sv::InitialOp::create(b, [&]() { + sv::ReadMemOp::create(b, reg, mem.initFilename, + mem.initIsBinary ? MemBaseTypeAttr::MemBaseBin + : MemBaseTypeAttr::MemBaseHex); }); }); } else { @@ -522,26 +524,27 @@ void HWMemSimImpl::generateMemory(HWModuleOp op, FirMemory mem) { // Create a new module with the readmem op. b.setInsertionPointAfter(op); auto boundModule = - b.create(boundModuleName, ArrayRef()); + HWModuleOp::create(b, boundModuleName, ArrayRef()); // Build the hierpathop - auto path = b.create( - mlirModuleNamespace.newName(op.getName() + "_path"), + auto path = hw::HierPathOp::create( + b, mlirModuleNamespace.newName(op.getName() + "_path"), b.getArrayAttr( ::InnerRefAttr::get(op.getNameAttr(), reg.getInnerNameAttr()))); b.setInsertionPointToStart(boundModule.getBodyBlock()); - b.create([&]() { - auto xmr = b.create(reg.getType(), path.getSymNameAttr()); - b.create(xmr, mem.initFilename, - mem.initIsBinary ? MemBaseTypeAttr::MemBaseBin - : MemBaseTypeAttr::MemBaseHex); + sv::InitialOp::create(b, [&]() { + auto xmr = + sv::XMRRefOp::create(b, reg.getType(), path.getSymNameAttr()); + sv::ReadMemOp::create(b, xmr, mem.initFilename, + mem.initIsBinary ? MemBaseTypeAttr::MemBaseBin + : MemBaseTypeAttr::MemBaseHex); }); // Instantiate this new module inside the memory module. b.setInsertionPointAfter(reg); - auto boundInstance = b.create( - boundModule, boundModule.getName(), ArrayRef()); + auto boundInstance = hw::InstanceOp::create( + b, boundModule, boundModule.getName(), ArrayRef()); boundInstance->setAttr( "inner_sym", hw::InnerSymAttr::get(b.getStringAttr( @@ -550,10 +553,12 @@ void HWMemSimImpl::generateMemory(HWModuleOp op, FirMemory mem) { // Build the file container and reference the module from it. b.setInsertionPointAfter(op); - b.create(filename, [&] { - b.create(FlatSymbolRefAttr::get(boundModuleName)); - b.create(hw::InnerRefAttr::get( - op.getNameAttr(), boundInstance.getInnerSymAttr().getSymName())); + emit::FileOp::create(b, filename, [&] { + emit::RefOp::create(b, FlatSymbolRefAttr::get(boundModuleName)); + sv::BindOp::create(b, + hw::InnerRefAttr::get( + op.getNameAttr(), + boundInstance.getInnerSymAttr().getSymName())); }); } } @@ -564,33 +569,34 @@ void HWMemSimImpl::generateMemory(HWModuleOp op, FirMemory mem) { return; constexpr unsigned randomWidth = 32; - b.create("ENABLE_INITIAL_MEM_", [&]() { + sv::IfDefOp::create(b, "ENABLE_INITIAL_MEM_", [&]() { sv::RegOp randReg; SmallVector randRegs; if (!disableRegRandomization) { - b.create("RANDOMIZE_REG_INIT", [&]() { + sv::IfDefOp::create(b, "RANDOMIZE_REG_INIT", [&]() { signed totalWidth = 0; for (sv::RegOp ® : registers) totalWidth += reg.getElementType().getIntOrFloatBitWidth(); while (totalWidth > 0) { auto name = b.getStringAttr(moduleNamespace.newName("_RANDOM")); auto innerSym = hw::InnerSymAttr::get(name); - randRegs.push_back(b.create(b.getIntegerType(randomWidth), - name, innerSym)); + randRegs.push_back(sv::RegOp::create(b, b.getIntegerType(randomWidth), + name, innerSym)); totalWidth -= randomWidth; } }); } - auto randomMemReg = b.create( + auto randomMemReg = sv::RegOp::create( + b, b.getIntegerType(llvm::divideCeil(mem.dataWidth, randomWidth) * randomWidth), b.getStringAttr("_RANDOM_MEM")); - b.create([&]() { - b.create("`INIT_RANDOM_PROLOG_"); + sv::InitialOp::create(b, [&]() { + sv::VerbatimOp::create(b, "`INIT_RANDOM_PROLOG_"); // Memory randomization logic. The entire memory is randomized. if (!disableMemRandomization) { - b.create("RANDOMIZE_MEM_INIT", [&]() { + sv::IfDefProceduralOp::create(b, "RANDOMIZE_MEM_INIT", [&]() { auto outerLoopIndVarType = b.getIntegerType(llvm::Log2_64_Ceil(mem.depth + 1)); auto innerUpperBoundWidth = @@ -605,24 +611,25 @@ void HWMemSimImpl::generateMemory(HWModuleOp op, FirMemory mem) { // randomMem[j[mem.width-1: +: 32] = `RANDOM // Memory[i] = randomMem[mem.dataWidth - 1: 0]; // ``` - b.create( - 0, mem.depth, 1, outerLoopIndVarType, "i", + sv::ForOp::create( + b, 0, mem.depth, 1, outerLoopIndVarType, "i", [&](BlockArgument outerIndVar) { - b.create( - 0, innerUpperBoundWidth, randomWidth, innerLoopIndVarType, - "j", [&](BlockArgument innerIndVar) { - auto rhs = b.create( - b.getIntegerType(randomWidth), "RANDOM"); + sv::ForOp::create( + b, 0, innerUpperBoundWidth, randomWidth, + innerLoopIndVarType, "j", [&](BlockArgument innerIndVar) { + auto rhs = sv::MacroRefExprSEOp::create( + b, b.getIntegerType(randomWidth), "RANDOM"); Value truncInnerIndVar; if (mem.dataWidth <= 1) truncInnerIndVar = - b.create(b.getI1Type(), 0); + hw::ConstantOp::create(b, b.getI1Type(), 0); else truncInnerIndVar = b.createOrFold( innerIndVar, 0, llvm::Log2_64_Ceil(mem.dataWidth)); - auto lhs = b.create( - randomMemReg, truncInnerIndVar, randomWidth, false); - b.create(lhs, rhs); + auto lhs = sv::IndexedPartSelectInOutOp::create( + b, randomMemReg, truncInnerIndVar, randomWidth, + false); + sv::BPAssignOp::create(b, lhs, rhs); }); Value iterValue = outerIndVar; @@ -631,10 +638,10 @@ void HWMemSimImpl::generateMemory(HWModuleOp op, FirMemory mem) { llvm::Log2_64_Ceil(mem.depth))) iterValue = b.createOrFold( iterValue, 0, llvm::Log2_64_Ceil(mem.depth)); - auto lhs = b.create(reg, iterValue); + auto lhs = sv::ArrayIndexInOutOp::create(b, reg, iterValue); auto rhs = b.createOrFold( - b.create(randomMemReg), 0, mem.dataWidth); - b.create(lhs, rhs); + sv::ReadInOutOp::create(b, randomMemReg), 0, mem.dataWidth); + sv::BPAssignOp::create(b, lhs, rhs); }); }); } @@ -645,11 +652,11 @@ void HWMemSimImpl::generateMemory(HWModuleOp op, FirMemory mem) { // TODO: This shares a lot of common logic with LowerToHW. Combine // these two in a common randomization utility. if (!disableRegRandomization) { - b.create("RANDOMIZE_REG_INIT", [&]() { + sv::IfDefProceduralOp::create(b, "RANDOMIZE_REG_INIT", [&]() { unsigned bits = randomWidth; for (sv::RegOp ® : randRegs) - b.create( - b.getStringAttr("{{0}} = {`RANDOM};"), ValueRange{}, + sv::VerbatimOp::create( + b, b.getStringAttr("{{0}} = {`RANDOM};"), ValueRange{}, b.getArrayAttr(hw::InnerRefAttr::get(op.getNameAttr(), reg.getInnerNameAttr()))); auto randRegIdx = 0; @@ -703,8 +710,8 @@ void HWMemSimImpl::generateMemory(HWModuleOp op, FirMemory mem) { if (values.size() > 1) rhs.append("}"); rhs.append(";"); - b.create(rhs, ValueRange{}, - b.getArrayAttr(symbols)); + sv::VerbatimOp::create(b, rhs, ValueRange{}, + b.getArrayAttr(symbols)); } }); } @@ -744,11 +751,11 @@ void HWMemSimImplPass::runOnOperation() { // 2. undefined read-under-write behavior. if (replSeqMem && ((mem.readLatency == 1 && mem.writeLatency == 1) && mem.dataWidth > 0)) { - builder.create(oldModule.getLoc(), nameAttr, - oldModule.getPortList()); + HWModuleExternOp::create(builder, oldModule.getLoc(), nameAttr, + oldModule.getPortList()); } else { - auto newModule = builder.create( - oldModule.getLoc(), nameAttr, oldModule.getPortList()); + auto newModule = HWModuleOp::create(builder, oldModule.getLoc(), + nameAttr, oldModule.getPortList()); if (auto outdir = oldModule->getAttr("output_file")) newModule->setAttr("output_file", outdir); newModule.setCommentAttr( diff --git a/lib/Dialect/Seq/Transforms/LowerSeqFIFO.cpp b/lib/Dialect/Seq/Transforms/LowerSeqFIFO.cpp index 9141086cd6..b3b514d1f4 100644 --- a/lib/Dialect/Seq/Transforms/LowerSeqFIFO.cpp +++ b/lib/Dialect/Seq/Transforms/LowerSeqFIFO.cpp @@ -48,104 +48,107 @@ public: Backedge nextCount = bb.get(countType); // ====== Some constants ====== - Value countTcFull = rewriter.create(loc, countType, depth); - Value countTc1 = rewriter.create(loc, countType, 1); - Value countTc0 = rewriter.create(loc, countType, 0); - Value ptrTc0 = rewriter.create(loc, ptrType, 0); - Value ptrTc1 = rewriter.create(loc, ptrType, 1); - Value ptrTcFull = rewriter.create(loc, ptrType, depth); + Value countTcFull = hw::ConstantOp::create(rewriter, loc, countType, depth); + Value countTc1 = hw::ConstantOp::create(rewriter, loc, countType, 1); + Value countTc0 = hw::ConstantOp::create(rewriter, loc, countType, 0); + Value ptrTc0 = hw::ConstantOp::create(rewriter, loc, ptrType, 0); + Value ptrTc1 = hw::ConstantOp::create(rewriter, loc, ptrType, 1); + Value ptrTcFull = hw::ConstantOp::create(rewriter, loc, ptrType, depth); // ====== Hardware units ====== - Value count = rewriter.create( - loc, nextCount, clk, rst, - rewriter.create(loc, countType, 0), "fifo_count"); - seq::HLMemOp hlmem = rewriter.create( - loc, clk, rst, "fifo_mem", + Value count = seq::CompRegOp::create( + rewriter, loc, nextCount, clk, rst, + hw::ConstantOp::create(rewriter, loc, countType, 0), "fifo_count"); + seq::HLMemOp hlmem = seq::HLMemOp::create( + rewriter, loc, clk, rst, "fifo_mem", llvm::SmallVector{static_cast(depth)}, eltType); - Value rdAddr = rewriter.create( - loc, rdAddrNext, clk, rst, - rewriter.create(loc, ptrType, 0), "fifo_rd_addr"); - Value wrAddr = rewriter.create( - loc, wrAddrNext, clk, rst, - rewriter.create(loc, ptrType, 0), "fifo_wr_addr"); + Value rdAddr = seq::CompRegOp::create( + rewriter, loc, rdAddrNext, clk, rst, + hw::ConstantOp::create(rewriter, loc, ptrType, 0), "fifo_rd_addr"); + Value wrAddr = seq::CompRegOp::create( + rewriter, loc, wrAddrNext, clk, rst, + hw::ConstantOp::create(rewriter, loc, ptrType, 0), "fifo_wr_addr"); - Value readData = rewriter.create( - loc, hlmem, llvm::SmallVector{rdAddr}, adaptor.getRdEn(), - mem.getRdLatency()); - rewriter.create(loc, hlmem, - llvm::SmallVector{wrAddr}, - adaptor.getInput(), adaptor.getWrEn(), - /*latency*/ 1); + Value readData = seq::ReadPortOp::create( + rewriter, loc, hlmem, llvm::SmallVector{rdAddr}, + adaptor.getRdEn(), mem.getRdLatency()); + seq::WritePortOp::create(rewriter, loc, hlmem, + llvm::SmallVector{wrAddr}, + adaptor.getInput(), adaptor.getWrEn(), + /*latency*/ 1); // ====== some more constants ===== - comb::ICmpOp fifoFull = rewriter.create( - loc, comb::ICmpPredicate::eq, count, countTcFull); + comb::ICmpOp fifoFull = comb::ICmpOp::create( + rewriter, loc, comb::ICmpPredicate::eq, count, countTcFull); fifoFull->setAttr("sv.namehint", rewriter.getStringAttr("fifo_full")); - comb::ICmpOp fifoEmpty = rewriter.create( - loc, comb::ICmpPredicate::eq, count, countTc0); + comb::ICmpOp fifoEmpty = comb::ICmpOp::create( + rewriter, loc, comb::ICmpPredicate::eq, count, countTc0); fifoEmpty->setAttr("sv.namehint", rewriter.getStringAttr("fifo_empty")); // ====== Next-state count ====== auto notRdEn = comb::createOrFoldNot(loc, adaptor.getRdEn(), rewriter); auto notWrEn = comb::createOrFoldNot(loc, adaptor.getWrEn(), rewriter); - Value rdEnNandWrEn = rewriter.create(loc, notRdEn, notWrEn); + Value rdEnNandWrEn = comb::AndOp::create(rewriter, loc, notRdEn, notWrEn); Value rdEnAndNotWrEn = - rewriter.create(loc, adaptor.getRdEn(), notWrEn); + comb::AndOp::create(rewriter, loc, adaptor.getRdEn(), notWrEn); Value wrEnAndNotRdEn = - rewriter.create(loc, adaptor.getWrEn(), notRdEn); + comb::AndOp::create(rewriter, loc, adaptor.getWrEn(), notRdEn); - auto countEqTcFull = rewriter.create( - loc, comb::ICmpPredicate::eq, count, countTcFull); - auto addCountTc1 = rewriter.create(loc, count, countTc1); - Value wrEnNext = rewriter.create(loc, countEqTcFull, - // keep value - count, - // increment - addCountTc1); - auto countEqTc0 = rewriter.create( - loc, comb::ICmpPredicate::eq, count, countTc0); - auto subCountTc1 = rewriter.create(loc, count, countTc1); + auto countEqTcFull = comb::ICmpOp::create( + rewriter, loc, comb::ICmpPredicate::eq, count, countTcFull); + auto addCountTc1 = comb::AddOp::create(rewriter, loc, count, countTc1); + Value wrEnNext = comb::MuxOp::create(rewriter, loc, countEqTcFull, + // keep value + count, + // increment + addCountTc1); + auto countEqTc0 = comb::ICmpOp::create( + rewriter, loc, comb::ICmpPredicate::eq, count, countTc0); + auto subCountTc1 = comb::SubOp::create(rewriter, loc, count, countTc1); - Value rdEnNext = rewriter.create(loc, countEqTc0, - // keep value - count, - // decrement - subCountTc1); + Value rdEnNext = comb::MuxOp::create(rewriter, loc, countEqTc0, + // keep value + count, + // decrement + subCountTc1); auto nextInnerMux = - rewriter.create(loc, rdEnAndNotWrEn, rdEnNext, count); - auto nextMux = rewriter.create(loc, wrEnAndNotRdEn, wrEnNext, - nextInnerMux); - nextCount.setValue(rewriter.create( - loc, rdEnNandWrEn, /*keep value*/ count, nextMux)); + comb::MuxOp::create(rewriter, loc, rdEnAndNotWrEn, rdEnNext, count); + auto nextMux = comb::MuxOp::create(rewriter, loc, wrEnAndNotRdEn, wrEnNext, + nextInnerMux); + nextCount.setValue(comb::MuxOp::create(rewriter, loc, rdEnNandWrEn, + /*keep value*/ count, nextMux)); static_cast(nextCount).getDefiningOp()->setAttr( "sv.namehint", rewriter.getStringAttr("fifo_count_next")); // ====== Read/write pointers ====== - Value wrAndNotFull = rewriter.create( - loc, adaptor.getWrEn(), comb::createOrFoldNot(loc, fifoFull, rewriter)); - auto addWrAddrPtrTc1 = rewriter.create(loc, wrAddr, ptrTc1); + Value wrAndNotFull = + comb::AndOp::create(rewriter, loc, adaptor.getWrEn(), + comb::createOrFoldNot(loc, fifoFull, rewriter)); + auto addWrAddrPtrTc1 = comb::AddOp::create(rewriter, loc, wrAddr, ptrTc1); - auto wrAddrNextNoRollover = rewriter.create( - loc, wrAndNotFull, addWrAddrPtrTc1, wrAddr); - auto isMaxAddrWr = rewriter.create( - loc, comb::ICmpPredicate::eq, wrAddrNextNoRollover, ptrTcFull); - wrAddrNext.setValue(rewriter.create(loc, isMaxAddrWr, ptrTc0, - wrAddrNextNoRollover)); + auto wrAddrNextNoRollover = comb::MuxOp::create(rewriter, loc, wrAndNotFull, + addWrAddrPtrTc1, wrAddr); + auto isMaxAddrWr = + comb::ICmpOp::create(rewriter, loc, comb::ICmpPredicate::eq, + wrAddrNextNoRollover, ptrTcFull); + wrAddrNext.setValue(comb::MuxOp::create(rewriter, loc, isMaxAddrWr, ptrTc0, + wrAddrNextNoRollover)); static_cast(wrAddrNext) .getDefiningOp() ->setAttr("sv.namehint", rewriter.getStringAttr("fifo_wr_addr_next")); auto notFifoEmpty = comb::createOrFoldNot(loc, fifoEmpty, rewriter); Value rdAndNotEmpty = - rewriter.create(loc, adaptor.getRdEn(), notFifoEmpty); - auto addRdAddrPtrTc1 = rewriter.create(loc, rdAddr, ptrTc1); - auto rdAddrNextNoRollover = rewriter.create( - loc, rdAndNotEmpty, addRdAddrPtrTc1, rdAddr); - auto isMaxAddrRd = rewriter.create( - loc, comb::ICmpPredicate::eq, rdAddrNextNoRollover, ptrTcFull); - rdAddrNext.setValue(rewriter.create(loc, isMaxAddrRd, ptrTc0, - rdAddrNextNoRollover)); + comb::AndOp::create(rewriter, loc, adaptor.getRdEn(), notFifoEmpty); + auto addRdAddrPtrTc1 = comb::AddOp::create(rewriter, loc, rdAddr, ptrTc1); + auto rdAddrNextNoRollover = comb::MuxOp::create( + rewriter, loc, rdAndNotEmpty, addRdAddrPtrTc1, rdAddr); + auto isMaxAddrRd = + comb::ICmpOp::create(rewriter, loc, comb::ICmpPredicate::eq, + rdAddrNextNoRollover, ptrTcFull); + rdAddrNext.setValue(comb::MuxOp::create(rewriter, loc, isMaxAddrRd, ptrTc0, + rdAddrNextNoRollover)); static_cast(rdAddrNext) .getDefiningOp() ->setAttr("sv.namehint", rewriter.getStringAttr("fifo_rd_addr_next")); @@ -161,37 +164,39 @@ public: results.push_back(fifoEmpty); if (auto almostFull = mem.getAlmostFullThreshold()) { - results.push_back(rewriter.create( - loc, comb::ICmpPredicate::uge, count, - rewriter.create(loc, countType, almostFull.value()))); + results.push_back( + comb::ICmpOp::create(rewriter, loc, comb::ICmpPredicate::uge, count, + hw::ConstantOp::create(rewriter, loc, countType, + almostFull.value()))); static_cast(results.back()) .getDefiningOp() ->setAttr("sv.namehint", rewriter.getStringAttr("fifo_almost_full")); } if (auto almostEmpty = mem.getAlmostEmptyThreshold()) { - results.push_back(rewriter.create( - loc, comb::ICmpPredicate::ule, count, - rewriter.create(loc, countType, - almostEmpty.value()))); + results.push_back( + comb::ICmpOp::create(rewriter, loc, comb::ICmpPredicate::ule, count, + hw::ConstantOp::create(rewriter, loc, countType, + almostEmpty.value()))); static_cast(results.back()) .getDefiningOp() ->setAttr("sv.namehint", rewriter.getStringAttr("fifo_almost_empty")); } // ====== Protocol checks ===== - Value clkI1 = rewriter.create(loc, clk); + Value clkI1 = seq::FromClockOp::create(rewriter, loc, clk); Value notEmptyAndRden = comb::createOrFoldNot( - loc, rewriter.create(loc, adaptor.getRdEn(), fifoEmpty), + loc, comb::AndOp::create(rewriter, loc, adaptor.getRdEn(), fifoEmpty), rewriter); - rewriter.create( - loc, notEmptyAndRden, verif::ClockEdge::Pos, clkI1, /*enable=*/Value(), + verif::ClockedAssertOp::create( + rewriter, loc, notEmptyAndRden, verif::ClockEdge::Pos, clkI1, + /*enable=*/Value(), rewriter.getStringAttr("FIFO empty when read enabled")); Value notFullAndWren = comb::createOrFoldNot( - loc, rewriter.create(loc, adaptor.getWrEn(), fifoFull), + loc, comb::AndOp::create(rewriter, loc, adaptor.getWrEn(), fifoFull), rewriter); - rewriter.create( - loc, notFullAndWren, verif::ClockEdge::Pos, clkI1, + verif::ClockedAssertOp::create( + rewriter, loc, notFullAndWren, verif::ClockEdge::Pos, clkI1, /*enable=*/Value(), rewriter.getStringAttr("FIFO full when write enabled")); diff --git a/lib/Dialect/Seq/Transforms/LowerSeqHLMem.cpp b/lib/Dialect/Seq/Transforms/LowerSeqHLMem.cpp index 91eb4b8471..af5f0795b5 100644 --- a/lib/Dialect/Seq/Transforms/LowerSeqHLMem.cpp +++ b/lib/Dialect/Seq/Transforms/LowerSeqHLMem.cpp @@ -75,7 +75,7 @@ public: hw::UnpackedArrayType memArrType = hw::UnpackedArrayType::get(memType.getElementType(), size); auto svMem = - rewriter.create(mem.getLoc(), memArrType, mem.getNameAttr()) + sv::RegOp::create(rewriter, mem.getLoc(), memArrType, mem.getNameAttr()) .getResult(); // Create write ports by gathering up the write port inputs and @@ -98,18 +98,18 @@ public: rewriter.eraseOp(writeOp); } - auto hwClk = rewriter.create(clk.getLoc(), clk); - rewriter.create( - mem.getLoc(), sv::EventControl::AtPosEdge, hwClk, + auto hwClk = seq::FromClockOp::create(rewriter, clk.getLoc(), clk); + sv::AlwaysFFOp::create( + rewriter, mem.getLoc(), sv::EventControl::AtPosEdge, hwClk, sv::ResetType::SyncReset, sv::EventControl::AtPosEdge, rst, [&] { for (auto [loc, address, data, en] : writeTuples) { Value a = address, d = data; // So the lambda can capture. Location l = loc; // Perform write upon write enable being high. - rewriter.create(loc, en, [&] { + sv::IfOp::create(rewriter, loc, en, [&] { Value memLoc = - rewriter.create(l, svMem, a); - rewriter.create(l, memLoc, d); + sv::ArrayIndexInOutOp::create(rewriter, l, svMem, a); + sv::PAssignOp::create(rewriter, l, memLoc, d); }); } }); @@ -130,8 +130,8 @@ public: if (latency > 0) { // Materialize any delays on the read address. for (unsigned i = 0; i < addressDelayCycles; ++i) { - readAddress = rewriter.create( - loc, readAddress, clk, + readAddress = seq::CompRegOp::create( + rewriter, loc, readAddress, clk, rewriter.getStringAttr(memName + "_rdaddr" + std::to_string(ri) + "_dly" + std::to_string(i))); } @@ -139,12 +139,12 @@ public: // Create a combinational read. Value memLoc = - rewriter.create(loc, svMem, readAddress); - Value readData = rewriter.create(loc, memLoc); + sv::ArrayIndexInOutOp::create(rewriter, loc, svMem, readAddress); + Value readData = sv::ReadInOutOp::create(rewriter, loc, memLoc); if (latency > 0) { // Register the read data. - readData = rewriter.create( - loc, readData, clk, + readData = seq::CompRegOp::create( + rewriter, loc, readData, clk, rewriter.getStringAttr(memName + "_rd" + std::to_string(ri) + "_reg")); } diff --git a/lib/Dialect/Seq/Transforms/LowerSeqShiftReg.cpp b/lib/Dialect/Seq/Transforms/LowerSeqShiftReg.cpp index 8eace7fe6b..b0ec3a04b6 100644 --- a/lib/Dialect/Seq/Transforms/LowerSeqShiftReg.cpp +++ b/lib/Dialect/Seq/Transforms/LowerSeqShiftReg.cpp @@ -51,8 +51,8 @@ public: StringAttr name; if (baseName.has_value()) name = rewriter.getStringAttr(baseName.value() + "_sh" + Twine(i + 1)); - in = rewriter.create( - op.getLoc(), in, adaptor.getClk(), adaptor.getClockEnable(), + in = seq::CompRegClockEnabledOp::create( + rewriter, op.getLoc(), in, adaptor.getClk(), adaptor.getClockEnable(), adaptor.getReset(), adaptor.getResetValue(), name, init); } diff --git a/lib/Dialect/Seq/Transforms/RegOfVecToMem.cpp b/lib/Dialect/Seq/Transforms/RegOfVecToMem.cpp index c73b086749..acc33b9abd 100644 --- a/lib/Dialect/Seq/Transforms/RegOfVecToMem.cpp +++ b/lib/Dialect/Seq/Transforms/RegOfVecToMem.cpp @@ -186,8 +186,8 @@ bool RegOfVecToMemPass::createFirMemory(MemoryPattern &pattern) { // Create FirMem auto memType = FirMemType::get(builder.getContext(), depth, width, /*maskWidth=*/1); - auto firMem = builder.create( - memType, /*readLatency=*/0, /*writeLatency=*/1, + auto firMem = seq::FirMemOp::create( + builder, memType, /*readLatency=*/0, /*writeLatency=*/1, /*readUnderWrite=*/seq::RUW::Undefined, /*writeUnderWrite=*/seq::WUW::Undefined, /*name=*/builder.getStringAttr("mem"), /*innerSym=*/hw::InnerSymAttr{}, @@ -195,17 +195,17 @@ bool RegOfVecToMemPass::createFirMemory(MemoryPattern &pattern) { /*outputFile=*/Attribute{}); // Create read port - Value readData = builder.create( - firMem, pattern.readAddr, pattern.clock, - /*enable=*/builder.create(builder.getI1Type(), 1)); + Value readData = FirMemReadOp::create( + builder, firMem, pattern.readAddr, pattern.clock, + /*enable=*/hw::ConstantOp::create(builder, builder.getI1Type(), 1)); LLVM_DEBUG(llvm::dbgs() << " Created read port\n" << firMem << "\n " << readData); Value mask; // Create write port - builder.create(firMem, pattern.writeAddr, pattern.clock, - pattern.writeEnable, pattern.writeData, mask); + FirMemWriteOp::create(builder, firMem, pattern.writeAddr, pattern.clock, + pattern.writeEnable, pattern.writeData, mask); LLVM_DEBUG(llvm::dbgs() << " Created write port\n"); diff --git a/lib/Dialect/Sim/SimDialect.cpp b/lib/Dialect/Sim/SimDialect.cpp index a05f160036..45cc3f9d41 100644 --- a/lib/Dialect/Sim/SimDialect.cpp +++ b/lib/Dialect/Sim/SimDialect.cpp @@ -41,7 +41,7 @@ Operation *SimDialect::materializeConstant(::mlir::OpBuilder &builder, ::mlir::Location loc) { if (auto fmtStrType = llvm::dyn_cast(type)) - return builder.create(loc, fmtStrType, - llvm::cast(value)); + return FormatLitOp::create(builder, loc, fmtStrType, + llvm::cast(value)); return nullptr; } diff --git a/lib/Dialect/Sim/Transforms/LowerDPIFunc.cpp b/lib/Dialect/Sim/Transforms/LowerDPIFunc.cpp index dd65b2bcaa..1968bbd1a9 100644 --- a/lib/Dialect/Sim/Transforms/LowerDPIFunc.cpp +++ b/lib/Dialect/Sim/Transforms/LowerDPIFunc.cpp @@ -103,16 +103,18 @@ LogicalResult LowerDPIFuncPass::lowerDPIFuncOp(sim::DPIFuncOp simFunc, // If a referred function is not in the same module, create an external // function declaration. if (!func) { - func = builder.create(simFunc.getVerilogName() - ? *simFunc.getVerilogName() - : simFunc.getSymName(), - funcType); + func = func::FuncOp::create(builder, + simFunc.getVerilogName() + ? *simFunc.getVerilogName() + : simFunc.getSymName(), + funcType); // External function needs to be private. func.setPrivate(); } // Create a wrapper module that calls a DPI function. - auto funcOp = builder.create( + auto funcOp = func::FuncOp::create( + builder, loweringState.nameSpace.newName(simFunc.getSymName() + "_wrapper"), moduleType.getFuncType()); @@ -133,22 +135,23 @@ LogicalResult LowerDPIFuncPass::lowerDPIFuncOp(sim::DPIFuncOp simFunc, ++inputIndex; } else { // Allocate an output placeholder. - auto one = builder.create(builder.getI64IntegerAttr(1)); - auto alloca = builder.create( - builder.getType(), arg.type, one); + auto one = + LLVM::ConstantOp::create(builder, builder.getI64IntegerAttr(1)); + auto alloca = LLVM::AllocaOp::create( + builder, builder.getType(), arg.type, one); functionInputs.push_back(alloca); functionOutputAllocas.push_back(alloca); } } - builder.create(func, functionInputs); + func::CallOp::create(builder, func, functionInputs); SmallVector results; for (auto functionOutputAlloca : functionOutputAllocas) - results.push_back(builder.create( - functionOutputAlloca.getElemType(), functionOutputAlloca)); + results.push_back(LLVM::LoadOp::create( + builder, functionOutputAlloca.getElemType(), functionOutputAlloca)); - builder.create(results); + func::ReturnOp::create(builder, results); simFunc.erase(); return success(); diff --git a/lib/Dialect/Sim/Transforms/ProceduralizeSim.cpp b/lib/Dialect/Sim/Transforms/ProceduralizeSim.cpp index 8622b25bd4..8c7b9baa15 100644 --- a/lib/Dialect/Sim/Transforms/ProceduralizeSim.cpp +++ b/lib/Dialect/Sim/Transforms/ProceduralizeSim.cpp @@ -124,8 +124,8 @@ LogicalResult ProceduralizeSimPass::proceduralizePrintOps( SmallVector argVec = arguments.takeVector(); auto clockConv = builder.createOrFold(fusedLoc, clock); - auto trigOp = builder.create( - fusedLoc, + auto trigOp = hw::TriggeredOp::create( + builder, fusedLoc, hw::EventControlAttr::get(builder.getContext(), hw::EventControl::AtPosEdge), clockConv, argVec); @@ -189,10 +189,10 @@ LogicalResult ProceduralizeSimPass::proceduralizePrintOps( // If not, create a new scf::IfOp for the condition. if (!condBlock) { builder.setInsertionPointToEnd(trigOp.getBodyBlock()); - auto ifOp = builder.create(printOp.getLoc(), TypeRange{}, - condArg, true, false); + auto ifOp = mlir::scf::IfOp::create(builder, printOp.getLoc(), + TypeRange{}, condArg, true, false); builder.setInsertionPointToStart(&ifOp.getThenRegion().front()); - builder.create(printOp.getLoc()); + mlir::scf::YieldOp::create(builder, printOp.getLoc()); condBlock = builder.getBlock(); prevConditionValue = condArg; prevConditionBlock = condBlock; @@ -201,7 +201,7 @@ LogicalResult ProceduralizeSimPass::proceduralizePrintOps( // Create the procedural print operation and prune the operations outside of // the TriggeredOp. builder.setInsertionPoint(condBlock->getTerminator()); - builder.create(printOp.getLoc(), procPrintInput); + PrintFormattedProcOp::create(builder, printOp.getLoc(), procPrintInput); cleanupList.push_back(printOp.getInput().getDefiningOp()); printOp.erase(); } diff --git a/lib/Dialect/SystemC/SystemCOps.cpp b/lib/Dialect/SystemC/SystemCOps.cpp index af6ead8980..4255df2029 100644 --- a/lib/Dialect/SystemC/SystemCOps.cpp +++ b/lib/Dialect/SystemC/SystemCOps.cpp @@ -332,7 +332,8 @@ CtorOp SCModuleOp::getOrCreateCtor() { if (ctor) return ctor; - return OpBuilder(getBody()).create(getLoc()); + auto builder = OpBuilder(getBody()); + return CtorOp::create(builder, getLoc()); } DestructorOp SCModuleOp::getOrCreateDestructor() { @@ -347,7 +348,8 @@ DestructorOp SCModuleOp::getOrCreateDestructor() { if (destructor) return destructor; - return OpBuilder::atBlockEnd(getBodyBlock()).create(getLoc()); + auto builder = OpBuilder::atBlockEnd(getBodyBlock()); + return DestructorOp::create(builder, getLoc()); } //===----------------------------------------------------------------------===// diff --git a/lib/Dialect/SystemC/Transforms/SystemCLowerInstanceInterop.cpp b/lib/Dialect/SystemC/Transforms/SystemCLowerInstanceInterop.cpp index 991700e9d9..6287f18d36 100644 --- a/lib/Dialect/SystemC/Transforms/SystemCLowerInstanceInterop.cpp +++ b/lib/Dialect/SystemC/Transforms/SystemCLowerInstanceInterop.cpp @@ -57,13 +57,12 @@ public: auto *hwModule = SymbolTable::lookupNearestSymbolFrom(op, op.getModuleNameAttr()); OpBuilder includeBuilder(hwModule); - includeBuilder.create( - loc, (verilatedModuleName + ".h").str(), false); + emitc::IncludeOp::create(includeBuilder, loc, + (verilatedModuleName + ".h").str(), false); // Request a pointer to the verilated module as persistent state. - Value state = rewriter - .create(loc, stateType, - InteropMechanism::CPP) + Value state = interop::ProceduralAllocOp::create(rewriter, loc, stateType, + InteropMechanism::CPP) .getStates()[0]; insertStateInitialization(rewriter, loc, state); @@ -85,13 +84,13 @@ private: /// module on the heap and let the above requested pointer point to it. void insertStateInitialization(PatternRewriter &rewriter, Location loc, Value state) const { - auto initOp = rewriter.create( - loc, state, InteropMechanism::CPP); + auto initOp = interop::ProceduralInitOp::create(rewriter, loc, state, + InteropMechanism::CPP); OpBuilder initBuilder = OpBuilder::atBlockBegin(initOp.getBody()); Value newState = - initBuilder.create(loc, state.getType(), ValueRange()); - initBuilder.create(loc, newState); + NewOp::create(initBuilder, loc, state.getType(), ValueRange()); + interop::ReturnOp::create(initBuilder, loc, newState); } /// Create an update interop operation to assign the input values to the input @@ -101,8 +100,8 @@ private: Value stateValue, ValueRange inputValues, ValueRange resultValues, ArrayAttr inputNames, ArrayAttr resultNames) const { - auto updateOp = rewriter.create( - loc, resultValues.getTypes(), inputValues, stateValue, + auto updateOp = interop::ProceduralUpdateOp::create( + rewriter, loc, resultValues.getTypes(), inputValues, stateValue, InteropMechanism::CPP); OpBuilder updateBuilder = OpBuilder::atBlockBegin(updateOp.getBody()); @@ -110,33 +109,34 @@ private: // Write to the verilated module's input ports. Value state = updateOp.getBody()->getArguments().front(); for (size_t i = 0; i < inputValues.size(); ++i) { - Value member = updateBuilder.create( - loc, inputValues[i].getType(), state, cast(inputNames[i]), - MemberAccessKind::Arrow); - updateBuilder.create(loc, member, - updateOp.getBody()->getArgument(i + 1)); + Value member = MemberAccessOp::create( + updateBuilder, loc, inputValues[i].getType(), state, + cast(inputNames[i]), MemberAccessKind::Arrow); + AssignOp::create(updateBuilder, loc, member, + updateOp.getBody()->getArgument(i + 1)); } // Call 'eval'. - auto evalFunc = updateBuilder.create( - loc, FunctionType::get(updateBuilder.getContext(), {}, {}), state, - "eval", MemberAccessKind::Arrow); + auto evalFunc = MemberAccessOp::create( + updateBuilder, loc, + FunctionType::get(updateBuilder.getContext(), {}, {}), state, "eval", + MemberAccessKind::Arrow); // TODO: this has to be changed to a systemc::CallIndirectOp once the PR is // merged, also remove the dependency to the func dialect from the cmake, // header include, pass dependent dialects - updateBuilder.create(loc, evalFunc.getResult()); + func::CallIndirectOp::create(updateBuilder, loc, evalFunc.getResult()); // Read the verilated module's output ports. SmallVector results; for (size_t i = 0; i < resultValues.size(); ++i) { - results.push_back(updateBuilder.create( - loc, resultValues[i].getType(), state, + results.push_back(MemberAccessOp::create( + updateBuilder, loc, resultValues[i].getType(), state, cast(resultNames[i]).getValue(), MemberAccessKind::Arrow)); } - updateBuilder.create(loc, results); + interop::ReturnOp::create(updateBuilder, loc, results); return updateOp->getResults(); } @@ -144,11 +144,11 @@ private: /// Deallocate the memory allocated in the interop init operation. void insertStateDeallocation(PatternRewriter &rewriter, Location loc, Value state) const { - auto deallocOp = rewriter.create( - loc, state, InteropMechanism::CPP); + auto deallocOp = interop::ProceduralDeallocOp::create( + rewriter, loc, state, InteropMechanism::CPP); OpBuilder deallocBuilder = OpBuilder::atBlockBegin(deallocOp.getBody()); - deallocBuilder.create(loc, deallocOp.getBody()->getArgument(0)); + DeleteOp::create(deallocBuilder, loc, deallocOp.getBody()->getArgument(0)); } }; } // namespace diff --git a/lib/Dialect/Verif/Transforms/LowerContracts.cpp b/lib/Dialect/Verif/Transforms/LowerContracts.cpp index 53a9898b24..6ffe8be0c9 100644 --- a/lib/Dialect/Verif/Transforms/LowerContracts.cpp +++ b/lib/Dialect/Verif/Transforms/LowerContracts.cpp @@ -49,10 +49,10 @@ Operation *replaceContractOp(OpBuilder &builder, RequireLike op, if ((isa(op) && !assumeContract) || (isa(op) && assumeContract)) - return builder.create(loc, property, enableValue, labelAttr); + return AssertOp::create(builder, loc, property, enableValue, labelAttr); if ((isa(op) && assumeContract) || (isa(op) && !assumeContract)) - return builder.create(loc, property, enableValue, labelAttr); + return AssumeOp::create(builder, loc, property, enableValue, labelAttr); return nullptr; } @@ -85,7 +85,7 @@ void assumeContractHolds(OpBuilder &builder, IRMapping &mapping, // contract ops with the assume variant for (auto result : contract.getResults()) { auto sym = - builder.create(result.getLoc(), result.getType()); + SymbolicValueOp::create(builder, result.getLoc(), result.getType()); mapping.map(result, sym); } auto &contractOps = contract.getBody().front().getOperations(); @@ -107,8 +107,8 @@ void buildOpsToClone(OpBuilder &builder, IRMapping &mapping, Operation *op, workList.push(definingOp); } else { // Create symbolic values for arguments - auto sym = builder.create(operand.getLoc(), - operand.getType()); + auto sym = verif::SymbolicValueOp::create(builder, operand.getLoc(), + operand.getType()); mapping.map(operand, sym); } } @@ -174,7 +174,7 @@ LogicalResult inlineContract(ContractOp &contract, OpBuilder &builder, // Create symbolic values for results for (auto result : contract.getResults()) { auto sym = - builder.create(result.getLoc(), result.getType()); + SymbolicValueOp::create(builder, result.getLoc(), result.getType()); mapping.map(result, sym); } } else { @@ -214,8 +214,9 @@ LogicalResult runOnHWModule(HWModuleOp hwModule, ModuleOp mlirModule) { // Create verif.formal op auto name = mlirModuleBuilder.getStringAttr( hwModule.getNameAttr().getValue() + "_CheckContract_" + Twine(i)); - auto formalOp = mlirModuleBuilder.create( - contract.getLoc(), name, mlirModuleBuilder.getDictionaryAttr({})); + auto formalOp = + verif::FormalOp::create(mlirModuleBuilder, contract.getLoc(), name, + mlirModuleBuilder.getDictionaryAttr({})); // Fill in verif.formal body OpBuilder formalBuilder(formalOp); diff --git a/lib/Dialect/Verif/Transforms/LowerFormalToHW.cpp b/lib/Dialect/Verif/Transforms/LowerFormalToHW.cpp index a14c80fe72..68c358c28e 100644 --- a/lib/Dialect/Verif/Transforms/LowerFormalToHW.cpp +++ b/lib/Dialect/Verif/Transforms/LowerFormalToHW.cpp @@ -44,7 +44,7 @@ static LogicalResult lowerFormalToHW(FormalOp op) { } auto moduleOp = - rewriter.create(op.getLoc(), op.getNameAttr(), ports); + hw::HWModuleOp::create(rewriter, op.getLoc(), op.getNameAttr(), ports); rewriter.inlineBlockBefore(&op.getBody().front(), &moduleOp.getBodyBlock()->front(), diff --git a/lib/Dialect/Verif/Transforms/LowerSymbolicValues.cpp b/lib/Dialect/Verif/Transforms/LowerSymbolicValues.cpp index e2fdf3fbd3..649ac22a45 100644 --- a/lib/Dialect/Verif/Transforms/LowerSymbolicValues.cpp +++ b/lib/Dialect/Verif/Transforms/LowerSymbolicValues.cpp @@ -62,8 +62,8 @@ LogicalResult LowerSymbolicValuesPass::lowerToExtModule() { auto flatType = builder.getIntegerType(numBits); auto &extmoduleOp = extmoduleOps[flatType]; if (!extmoduleOp) { - extmoduleOp = builder.create( - op.getLoc(), + extmoduleOp = HWModuleExternOp::create( + builder, op.getLoc(), builder.getStringAttr(Twine("circt.symbolic_value.") + Twine(numBits)), PortInfo{{builder.getStringAttr("z"), flatType, ModulePort::Output}}, @@ -77,9 +77,9 @@ LogicalResult LowerSymbolicValuesPass::lowerToExtModule() { // Instantiate the extmodule as a means of generating a symbolic value with // the correct number of bits. builder.setInsertionPoint(op); - auto instOp = builder.create( - op.getLoc(), extmoduleOp, builder.getStringAttr("symbolic_value"), - ArrayRef{}, + auto instOp = InstanceOp::create( + builder, op.getLoc(), extmoduleOp, + builder.getStringAttr("symbolic_value"), ArrayRef{}, builder.getArrayAttr(ParamDeclAttr::get( builder.getContext(), builder.getStringAttr("WIDTH"), builder.getI32Type(), builder.getI32IntegerAttr(numBits)))); @@ -87,7 +87,7 @@ LogicalResult LowerSymbolicValuesPass::lowerToExtModule() { // Insert a bit cast if needed to obtain the original symbolic value's type. if (op.getType() != value.getType()) - value = builder.create(op.getLoc(), op.getType(), value); + value = BitcastOp::create(builder, op.getLoc(), op.getType(), value); // Replace the `verif.symbolic_value` op. op.replaceAllUsesWith(value); @@ -103,12 +103,12 @@ void LowerSymbolicValuesPass::lowerToAnySeqWire() { // Create a replacement wire declaration with a `(* anyseq *)` Verilog // attribute. OpBuilder builder(op); - auto wireOp = builder.create(op.getLoc(), op.getType()); + auto wireOp = sv::WireOp::create(builder, op.getLoc(), op.getType()); sv::addSVAttributes(wireOp, sv::SVAttributeAttr::get(&getContext(), "anyseq")); // Create a read from the wire and replace the `verif.symbolic_value` op. - Value value = builder.create(op.getLoc(), wireOp); + Value value = sv::ReadInOutOp::create(builder, op.getLoc(), wireOp); op.replaceAllUsesWith(value); op.erase(); }); diff --git a/lib/Dialect/Verif/VerifDialect.cpp b/lib/Dialect/Verif/VerifDialect.cpp index 7c8cab8c07..1d92ce8774 100644 --- a/lib/Dialect/Verif/VerifDialect.cpp +++ b/lib/Dialect/Verif/VerifDialect.cpp @@ -27,7 +27,7 @@ Operation *VerifDialect::materializeConstant(OpBuilder &builder, Location loc) { if (auto intType = dyn_cast(type)) if (auto attrValue = dyn_cast(value)) - return builder.create(loc, type, attrValue); + return hw::ConstantOp::create(builder, loc, type, attrValue); return nullptr; } diff --git a/lib/Support/BackedgeBuilder.cpp b/lib/Support/BackedgeBuilder.cpp index 3be244bf46..216c7d3022 100644 --- a/lib/Support/BackedgeBuilder.cpp +++ b/lib/Support/BackedgeBuilder.cpp @@ -40,7 +40,7 @@ LogicalResult BackedgeBuilder::clearOrEmitError() { if (!op->use_empty()) { auto diag = op->emitError("backedge of type ") << op->getResult(0).getType() << " still in use"; - for (auto user : op->getUsers()) + for (auto *user : op->getUsers()) diag.attachNote(user->getLoc()) << "used by " << *user; ++numInUse; continue; @@ -65,8 +65,8 @@ BackedgeBuilder::BackedgeBuilder(PatternRewriter &rewriter, Location loc) Backedge BackedgeBuilder::get(Type t, mlir::LocationAttr optionalLoc) { if (!optionalLoc) optionalLoc = loc; - Operation *op = builder.create( - optionalLoc, t, ValueRange{}); + Operation *op = mlir::UnrealizedConversionCastOp::create(builder, optionalLoc, + t, ValueRange{}); edges.push_back(op); return Backedge(op); } diff --git a/lib/Support/InstanceGraph.cpp b/lib/Support/InstanceGraph.cpp index f5f447804f..dbbe7b1ccd 100644 --- a/lib/Support/InstanceGraph.cpp +++ b/lib/Support/InstanceGraph.cpp @@ -183,7 +183,7 @@ InstanceGraph::getInferredTopLevelNodes() { return true; } marked.insert(node); - for (auto use : *node) { + for (auto *use : *node) { InstanceGraphNode *targetModule = use->getTarget(); candidateTopLevels.remove(targetModule); if (cycleUtil(targetModule, trace)) @@ -195,7 +195,7 @@ InstanceGraph::getInferredTopLevelNodes() { }; bool cyclic = false; - for (auto moduleIt : *this) { + for (auto *moduleIt : *this) { if (visited.contains(moduleIt)) continue; diff --git a/lib/Tools/circt-bmc/ExternalizeRegisters.cpp b/lib/Tools/circt-bmc/ExternalizeRegisters.cpp index 192cc560ab..a67f53ae0e 100644 --- a/lib/Tools/circt-bmc/ExternalizeRegisters.cpp +++ b/lib/Tools/circt-bmc/ExternalizeRegisters.cpp @@ -178,12 +178,12 @@ void ExternalizeRegistersPass::runOnOperation() { } SmallVector resTypes(instanceOp->getResultTypes()); resTypes.append(newOutputs); - auto newInst = builder.create( - instanceOp.getLoc(), resTypes, instanceOp.getInstanceNameAttr(), - instanceOp.getModuleNameAttr(), instanceOp.getInputs(), - builder.getArrayAttr(argNames), builder.getArrayAttr(resultNames), - instanceOp.getParametersAttr(), instanceOp.getInnerSymAttr(), - instanceOp.getDoNotPrintAttr()); + auto newInst = InstanceOp::create( + builder, instanceOp.getLoc(), resTypes, + instanceOp.getInstanceNameAttr(), instanceOp.getModuleNameAttr(), + instanceOp.getInputs(), builder.getArrayAttr(argNames), + builder.getArrayAttr(resultNames), instanceOp.getParametersAttr(), + instanceOp.getInnerSymAttr(), instanceOp.getDoNotPrintAttr()); for (auto [output, name] : zip(newInst->getResults().take_back(newOutputs.size()), newOutputNames)) @@ -244,8 +244,8 @@ LogicalResult ExternalizeRegistersPass::externalizeReg( return failure(); } // Sync reset - auto mux = builder.create(op->getLoc(), regType, reset, - resetValue, next); + auto mux = comb::MuxOp::create(builder, op->getLoc(), regType, reset, + resetValue, next); module.appendOutput(newOutputName, mux); } else { // No reset diff --git a/lib/Tools/circt-bmc/LowerToBMC.cpp b/lib/Tools/circt-bmc/LowerToBMC.cpp index 94c9a5602f..c1ce8408fc 100644 --- a/lib/Tools/circt-bmc/LowerToBMC.cpp +++ b/lib/Tools/circt-bmc/LowerToBMC.cpp @@ -89,15 +89,15 @@ void LowerToBMCPass::runOnOperation() { } // Replace the top-module with a function performing the BMC - auto entryFunc = builder.create( - loc, topModule, builder.getFunctionType({}, {})); + auto entryFunc = func::FuncOp::create(builder, loc, topModule, + builder.getFunctionType({}, {})); builder.createBlock(&entryFunc.getBody()); { OpBuilder::InsertionGuard guard(builder); auto *terminator = hwModule.getBody().front().getTerminator(); builder.setInsertionPoint(terminator); - builder.create(loc, terminator->getOperands()); + verif::YieldOp::create(builder, loc, terminator->getOperands()); terminator->erase(); } @@ -114,8 +114,8 @@ void LowerToBMCPass::runOnOperation() { return signalPassFailure(); } } - bmcOp = builder.create( - loc, risingClocksOnly ? bound : 2 * bound, + bmcOp = verif::BoundedModelCheckingOp::create( + builder, loc, risingClocksOnly ? bound : 2 * bound, cast(numRegs).getValue().getZExtValue(), initialValues); // Annotate the op with how many cycles to ignore - again, we may need to // double this to account for rising and falling edges @@ -163,12 +163,12 @@ void LowerToBMCPass::runOnOperation() { auto *initBlock = builder.createBlock(&bmcOp.getInit()); builder.setInsertionPointToStart(initBlock); if (hasClk) { - auto initVal = builder.create(loc, builder.getI1Type(), - risingClocksOnly ? 1 : 0); - auto toClk = builder.create(loc, initVal); - builder.create(loc, ValueRange{toClk}); + auto initVal = hw::ConstantOp::create(builder, loc, builder.getI1Type(), + risingClocksOnly ? 1 : 0); + auto toClk = seq::ToClockOp::create(builder, loc, initVal); + verif::YieldOp::create(builder, loc, ValueRange{toClk}); } else { - builder.create(loc, ValueRange{}); + verif::YieldOp::create(builder, loc, ValueRange{}); } // Toggle clock in loop region if it exists, otherwise just yield nothing @@ -178,20 +178,20 @@ void LowerToBMCPass::runOnOperation() { loopBlock->addArgument(seq::ClockType::get(ctx), loc); if (risingClocksOnly) { // In rising clocks only mode we don't need to toggle the clock - builder.create(loc, - ValueRange{loopBlock->getArgument(0)}); + verif::YieldOp::create(builder, loc, + ValueRange{loopBlock->getArgument(0)}); } else { auto fromClk = - builder.create(loc, loopBlock->getArgument(0)); + seq::FromClockOp::create(builder, loc, loopBlock->getArgument(0)); auto cNeg1 = - builder.create(loc, builder.getI1Type(), -1); - auto nClk = builder.create(loc, fromClk, cNeg1); - auto toClk = builder.create(loc, nClk); + hw::ConstantOp::create(builder, loc, builder.getI1Type(), -1); + auto nClk = comb::XorOp::create(builder, loc, fromClk, cNeg1); + auto toClk = seq::ToClockOp::create(builder, loc, nClk); // Only yield clock value - builder.create(loc, ValueRange{toClk}); + verif::YieldOp::create(builder, loc, ValueRange{toClk}); } } else { - builder.create(loc, ValueRange{}); + verif::YieldOp::create(builder, loc, ValueRange{}); } } bmcOp.getCircuit().takeBody(hwModule.getBody()); @@ -203,8 +203,8 @@ void LowerToBMCPass::runOnOperation() { OpBuilder b = OpBuilder::atBlockEnd(moduleOp.getBody()); auto arrayTy = LLVM::LLVMArrayType::get(b.getI8Type(), str.size() + 1); - auto global = b.create( - loc, arrayTy, /*isConstant=*/true, LLVM::linkage::Linkage::Private, + auto global = LLVM::GlobalOp::create( + b, loc, arrayTy, /*isConstant=*/true, LLVM::linkage::Linkage::Private, "resultString", StringAttr::get(b.getContext(), Twine(str).concat(Twine('\00')))); SymbolTable symTable(moduleOp); @@ -213,7 +213,7 @@ void LowerToBMCPass::runOnOperation() { } return success( - builder.create(loc, global)->getResult(0)); + LLVM::AddressOfOp::create(builder, loc, global)->getResult(0)); }; auto successStrAddr = @@ -226,21 +226,22 @@ void LowerToBMCPass::runOnOperation() { return signalPassFailure(); } - auto formatString = builder.create( - loc, bmcOp.getResult(), successStrAddr.value(), failureStrAddr.value()); - builder.create(loc, printfFunc.value(), - ValueRange{formatString}); - builder.create(loc); + auto formatString = + LLVM::SelectOp::create(builder, loc, bmcOp.getResult(), + successStrAddr.value(), failureStrAddr.value()); + LLVM::CallOp::create(builder, loc, printfFunc.value(), + ValueRange{formatString}); + func::ReturnOp::create(builder, loc); if (insertMainFunc) { builder.setInsertionPointToEnd(getOperation().getBody()); Type i32Ty = builder.getI32Type(); - auto mainFunc = builder.create( - loc, "main", builder.getFunctionType({i32Ty, ptrTy}, {i32Ty})); + auto mainFunc = func::FuncOp::create( + builder, loc, "main", builder.getFunctionType({i32Ty, ptrTy}, {i32Ty})); builder.createBlock(&mainFunc.getBody(), {}, {i32Ty, ptrTy}, {loc, loc}); - builder.create(loc, entryFunc, ValueRange{}); + func::CallOp::create(builder, loc, entryFunc, ValueRange{}); // TODO: don't use LLVM here - Value constZero = builder.create(loc, i32Ty, 0); - builder.create(loc, constZero); + Value constZero = LLVM::ConstantOp::create(builder, loc, i32Ty, 0); + func::ReturnOp::create(builder, loc, constZero); } } diff --git a/lib/Tools/circt-lec/ConstructLEC.cpp b/lib/Tools/circt-lec/ConstructLEC.cpp index 8cd7ee6694..4b5f60a1a6 100644 --- a/lib/Tools/circt-lec/ConstructLEC.cpp +++ b/lib/Tools/circt-lec/ConstructLEC.cpp @@ -46,15 +46,15 @@ static Value lookupOrCreateStringGlobal(OpBuilder &builder, ModuleOp moduleOp, if (!global) { OpBuilder b = OpBuilder::atBlockEnd(moduleOp.getBody()); auto arrayTy = LLVM::LLVMArrayType::get(b.getI8Type(), str.size() + 1); - global = b.create( - loc, arrayTy, /*isConstant=*/true, LLVM::linkage::Linkage::Private, str, - StringAttr::get(b.getContext(), Twine(str).concat(Twine('\00')))); + global = LLVM::GlobalOp::create( + b, loc, arrayTy, /*isConstant=*/true, LLVM::linkage::Linkage::Private, + str, StringAttr::get(b.getContext(), Twine(str).concat(Twine('\00')))); } // FIXME: sanity check the fetched global: do all the attributes match what // we expect? - return builder.create(loc, global); + return LLVM::AddressOfOp::create(builder, loc, global); } hw::HWModuleOp ConstructLECPass::lookupModule(StringRef name) { @@ -74,7 +74,7 @@ Value ConstructLECPass::constructMiter(OpBuilder builder, Location loc, // Create the miter circuit that return equivalence result. auto lecOp = - builder.create(loc, withResult); + verif::LogicEquivalenceCheckingOp::create(builder, loc, withResult); builder.cloneRegionBefore(moduleA.getBody(), lecOp.getFirstCircuit(), lecOp.getFirstCircuit().end()); @@ -89,11 +89,11 @@ Value ConstructLECPass::constructMiter(OpBuilder builder, Location loc, auto *term = lecOp.getFirstCircuit().front().getTerminator(); OpBuilder::InsertionGuard guard(builder); builder.setInsertionPoint(term); - builder.create(loc, term->getOperands()); + verif::YieldOp::create(builder, loc, term->getOperands()); term->erase(); term = lecOp.getSecondCircuit().front().getTerminator(); builder.setInsertionPoint(term); - builder.create(loc, term->getOperands()); + verif::YieldOp::create(builder, loc, term->getOperands()); term->erase(); } @@ -143,18 +143,18 @@ void ConstructLECPass::runOnOperation() { // have to do any uniquing and the LEC driver also already knows this name. FunctionType functionType = FunctionType::get(&getContext(), {}, {}); func::FuncOp entryFunc = - builder.create(loc, firstModule, functionType); + func::FuncOp::create(builder, loc, firstModule, functionType); if (insertMode == lec::InsertAdditionalModeEnum::Main) { OpBuilder::InsertionGuard guard(builder); auto i32Ty = builder.getI32Type(); - auto mainFunc = builder.create( - loc, "main", builder.getFunctionType({i32Ty, ptrTy}, {i32Ty})); + auto mainFunc = func::FuncOp::create( + builder, loc, "main", builder.getFunctionType({i32Ty, ptrTy}, {i32Ty})); builder.createBlock(&mainFunc.getBody(), {}, {i32Ty, ptrTy}, {loc, loc}); - builder.create(loc, entryFunc, ValueRange{}); + func::CallOp::create(builder, loc, entryFunc, ValueRange{}); // TODO: don't use LLVM here - Value constZero = builder.create(loc, i32Ty, 0); - builder.create(loc, constZero); + Value constZero = LLVM::ConstantOp::create(builder, loc, i32Ty, 0); + func::ReturnOp::create(builder, loc, constZero); } builder.createBlock(&entryFunc.getBody()); @@ -170,10 +170,10 @@ void ConstructLECPass::runOnOperation() { lookupOrCreateStringGlobal(builder, getOperation(), "c1 == c2\n"); Value neqFormatString = lookupOrCreateStringGlobal(builder, getOperation(), "c1 != c2\n"); - Value formatString = builder.create( - loc, areEquivalent, eqFormatString, neqFormatString); - builder.create(loc, printfFunc.value(), - ValueRange{formatString}); + Value formatString = LLVM::SelectOp::create(builder, loc, areEquivalent, + eqFormatString, neqFormatString); + LLVM::CallOp::create(builder, loc, printfFunc.value(), + ValueRange{formatString}); - builder.create(loc, ValueRange{}); + func::ReturnOp::create(builder, loc, ValueRange{}); } diff --git a/lib/Transforms/FlattenMemRefs.cpp b/lib/Transforms/FlattenMemRefs.cpp index c3d0727632..f6db19308e 100644 --- a/lib/Transforms/FlattenMemRefs.cpp +++ b/lib/Transforms/FlattenMemRefs.cpp @@ -74,7 +74,7 @@ static Value flattenIndices(ConversionPatternRewriter &rewriter, Operation *op, if (indices.empty()) { // Singleton memref (e.g. memref) - return 0. - return rewriter.create(loc, rewriter.getIndexAttr(0)) + return arith::ConstantOp::create(rewriter, loc, rewriter.getIndexAttr(0)) .getResult(); } @@ -92,24 +92,22 @@ static Value flattenIndices(ConversionPatternRewriter &rewriter, Operation *op, // Multiply product by the current index operand. if (llvm::isPowerOf2_64(indexMulFactor)) { - auto constant = - rewriter - .create( - loc, rewriter.getIndexAttr(llvm::Log2_64(indexMulFactor))) - .getResult(); - finalIdx = - rewriter.create(loc, finalIdx, constant).getResult(); - } else { - auto constant = rewriter - .create( - loc, rewriter.getIndexAttr(indexMulFactor)) + auto constant = arith::ConstantOp::create( + rewriter, loc, + rewriter.getIndexAttr(llvm::Log2_64(indexMulFactor))) .getResult(); finalIdx = - rewriter.create(loc, finalIdx, constant).getResult(); + arith::ShLIOp::create(rewriter, loc, finalIdx, constant).getResult(); + } else { + auto constant = arith::ConstantOp::create( + rewriter, loc, rewriter.getIndexAttr(indexMulFactor)) + .getResult(); + finalIdx = + arith::MulIOp::create(rewriter, loc, finalIdx, constant).getResult(); } // Sum up with the prior lower dimension accessors. - auto sumOp = rewriter.create(loc, finalIdx, partialIdx); + auto sumOp = arith::AddIOp::create(rewriter, loc, finalIdx, partialIdx); finalIdx = sumOp.getResult(); } return finalIdx; @@ -324,8 +322,9 @@ struct CallOpConversion : public OpConversionPattern { llvm::SmallVector convResTypes; if (typeConverter->convertTypes(op.getResultTypes(), convResTypes).failed()) return failure(); - auto newCallOp = rewriter.create( - op.getLoc(), adaptor.getCallee(), convResTypes, adaptor.getOperands()); + auto newCallOp = + func::CallOp::create(rewriter, op.getLoc(), adaptor.getCallee(), + convResTypes, adaptor.getOperands()); if (!rewriteFunctions) { rewriter.replaceOp(op, newCallOp); @@ -345,7 +344,7 @@ struct CallOpConversion : public OpConversionPattern { calledFunction, op.getCallee(), funcType); else newFuncOp = - rewriter.create(op.getLoc(), op.getCallee(), funcType); + func::FuncOp::create(rewriter, op.getLoc(), op.getCallee(), funcType); newFuncOp.setVisibility(SymbolTable::Visibility::Private); rewriter.replaceOp(op, newCallOp); @@ -417,8 +416,8 @@ static Value materializeCollapseShapeFlattening(OpBuilder &builder, assert(indices.has_value() && "expected a valid collapse"); // Generate the appropriate return type: - return builder.create(loc, inputs[0], - indices.value()); + return memref::CollapseShapeOp::create(builder, loc, inputs[0], + indices.value()); } static void populateTypeConversionPatterns(TypeConverter &typeConverter) { diff --git a/lib/Transforms/IndexSwitchToIf.cpp b/lib/Transforms/IndexSwitchToIf.cpp index fd28e00e14..359ef0699e 100644 --- a/lib/Transforms/IndexSwitchToIf.cpp +++ b/lib/Transforms/IndexSwitchToIf.cpp @@ -49,12 +49,13 @@ struct SwitchToIfConversion : public OpConversionPattern { rewriter.setInsertionPointToStart(&prevIfOp.getElseRegion().front()); Value caseValue = - rewriter.create(loc, caseValueInt); - Value cond = rewriter.create( - loc, arith::CmpIPredicate::eq, switchOp.getOperand(), caseValue); + arith::ConstantIndexOp::create(rewriter, loc, caseValueInt); + Value cond = + arith::CmpIOp::create(rewriter, loc, arith::CmpIPredicate::eq, + switchOp.getOperand(), caseValue); - auto ifOp = rewriter.create(loc, switchOp.getResultTypes(), - cond, /*hasElseRegion=*/true); + auto ifOp = scf::IfOp::create(rewriter, loc, switchOp.getResultTypes(), + cond, /*hasElseRegion=*/true); Region &caseRegion = switchOp.getCaseRegions()[i]; rewriter.eraseBlock(&ifOp.getThenRegion().front()); @@ -69,7 +70,7 @@ struct SwitchToIfConversion : public OpConversionPattern { if (prevIfOp && hasResults) { rewriter.setInsertionPointToEnd(&prevIfOp.getElseRegion().front()); - rewriter.create(loc, ifOp.getResult(0)); + scf::YieldOp::create(rewriter, loc, ifOp.getResult(0)); } if (i == 0 && hasResults) diff --git a/lib/Transforms/InsertMergeBlocks.cpp b/lib/Transforms/InsertMergeBlocks.cpp index 29eb92be78..f71dd98ede 100644 --- a/lib/Transforms/InsertMergeBlocks.cpp +++ b/lib/Transforms/InsertMergeBlocks.cpp @@ -70,8 +70,8 @@ static FailureOr buildMergeBlock(Block *b1, Block *b2, Block *oldSucc, SmallVector argLocs(blockArgTypes.size(), rewriter.getUnknownLoc()); Block *res = rewriter.createBlock(oldSucc, blockArgTypes, argLocs); - rewriter.create(rewriter.getUnknownLoc(), oldSucc, - res->getArguments()); + cf::BranchOp::create(rewriter, rewriter.getUnknownLoc(), oldSucc, + res->getArguments()); if (failed(changeBranchTarget(b1, oldSucc, res, rewriter))) return failure(); diff --git a/lib/Transforms/MapArithToComb.cpp b/lib/Transforms/MapArithToComb.cpp index fb792dd64f..84e2824ce7 100644 --- a/lib/Transforms/MapArithToComb.cpp +++ b/lib/Transforms/MapArithToComb.cpp @@ -86,10 +86,10 @@ public: size_t outWidth = op.getOut().getType().getIntOrFloatBitWidth(); size_t inWidth = adaptor.getIn().getType().getIntOrFloatBitWidth(); - rewriter.replaceOp(op, rewriter.create( - loc, - rewriter.create( - loc, APInt(outWidth - inWidth, 0)), + rewriter.replaceOp(op, comb::ConcatOp::create( + rewriter, loc, + hw::ConstantOp::create( + rewriter, loc, APInt(outWidth - inWidth, 0)), adaptor.getIn())); return success(); } diff --git a/lib/Transforms/MemoryBanking.cpp b/lib/Transforms/MemoryBanking.cpp index 19107e0997..84d806d301 100644 --- a/lib/Transforms/MemoryBanking.cpp +++ b/lib/Transforms/MemoryBanking.cpp @@ -225,16 +225,16 @@ handleGetGlobalOp(memref::GetGlobalOp getGlobalOp, uint64_t bankingFactor, auto newInitValue = DenseElementsAttr::get(tensorType, subBlocks[bankCnt]); builder.restoreInsertionPoint(globalOpsInsertPt); - auto newGlobalOp = builder.create( - globalOp.getLoc(), builder.getStringAttr(newName), + auto newGlobalOp = memref::GlobalOp::create( + builder, globalOp.getLoc(), builder.getStringAttr(newName), globalOp.getSymVisibilityAttr(), newTypeAttr, newInitValue, globalOp.getConstantAttr(), globalOp.getAlignmentAttr()); builder.setInsertionPointAfter(newGlobalOp); globalOpsInsertPt = builder.saveInsertionPoint(); builder.restoreInsertionPoint(getGlobalOpsInsertPt); - auto newGetGlobalOp = builder.create( - getGlobalOp.getLoc(), newMemRefTy, newGlobalOp.getName()); + auto newGetGlobalOp = memref::GetGlobalOp::create( + builder, getGlobalOp.getLoc(), newMemRefTy, newGlobalOp.getName()); newGetGlobalOp->setAttrs(remainingAttrs); builder.setInsertionPointAfter(newGetGlobalOp); getGlobalOpsInsertPt = builder.saveInsertionPoint(); @@ -437,7 +437,7 @@ SmallVector MemoryBankingPass::createBanks(OpBuilder &builder, .Case([&](memref::AllocOp allocOp) { for (uint64_t bankCnt = 0; bankCnt < currFactor; ++bankCnt) { auto bankAllocOp = - builder.create(loc, newMemRefType); + memref::AllocOp::create(builder, loc, newMemRefType); bankAllocOp->setAttrs(remainingAttrs); banks.push_back(bankAllocOp); } @@ -445,7 +445,7 @@ SmallVector MemoryBankingPass::createBanks(OpBuilder &builder, .Case([&](memref::AllocaOp allocaOp) { for (uint64_t bankCnt = 0; bankCnt < currFactor; ++bankCnt) { auto bankAllocaOp = - builder.create(loc, newMemRefType); + memref::AllocaOp::create(builder, loc, newMemRefType); bankAllocaOp->setAttrs(remainingAttrs); banks.push_back(bankAllocaOp); } @@ -504,9 +504,9 @@ struct BankAffineLoadPattern {rewriter.getAffineDimExpr(currDimension).floorDiv(currFactor)}); Value bankIndex = - rewriter.create(loc, modMap, loadIndices); + affine::AffineApplyOp::create(rewriter, loc, modMap, loadIndices); Value offset = - rewriter.create(loc, divMap, loadIndices); + affine::AffineApplyOp::create(rewriter, loc, divMap, loadIndices); SmallVector newIndices(loadIndices.begin(), loadIndices.end()); newIndices[currDimension] = offset; @@ -517,16 +517,16 @@ struct BankAffineLoadPattern caseValues.push_back(i); rewriter.setInsertionPoint(loadOp); - scf::IndexSwitchOp switchOp = rewriter.create( - loc, resultTypes, bankIndex, caseValues, + scf::IndexSwitchOp switchOp = scf::IndexSwitchOp::create( + rewriter, loc, resultTypes, bankIndex, caseValues, /*numRegions=*/currFactor); for (unsigned i = 0; i < currFactor; ++i) { Region &caseRegion = switchOp.getCaseRegions()[i]; rewriter.setInsertionPointToStart(&caseRegion.emplaceBlock()); - Value bankedLoad = rewriter.create( - loc, banks[i], newIndices); - rewriter.create(loc, bankedLoad); + Value bankedLoad = mlir::affine::AffineLoadOp::create( + rewriter, loc, banks[i], newIndices); + scf::YieldOp::create(rewriter, loc, bankedLoad); } Region &defaultRegion = switchOp.getDefaultRegion(); @@ -535,8 +535,8 @@ struct BankAffineLoadPattern TypedAttr zeroAttr = cast(rewriter.getZeroAttr(loadOp.getType())); - auto defaultValue = rewriter.create(loc, zeroAttr); - rewriter.create(loc, defaultValue.getResult()); + auto defaultValue = arith::ConstantOp::create(rewriter, loc, zeroAttr); + scf::YieldOp::create(rewriter, loc, defaultValue.getResult()); // We track Load's memory reference only if it is a block argument - this is // the only case where the reference isn't replaced. @@ -600,9 +600,9 @@ struct BankAffineStorePattern {rewriter.getAffineDimExpr(currDimension).floorDiv(currFactor)}); Value bankIndex = - rewriter.create(loc, modMap, storeIndices); + affine::AffineApplyOp::create(rewriter, loc, modMap, storeIndices); Value offset = - rewriter.create(loc, divMap, storeIndices); + affine::AffineApplyOp::create(rewriter, loc, divMap, storeIndices); SmallVector newIndices(storeIndices.begin(), storeIndices.end()); newIndices[currDimension] = offset; @@ -613,23 +613,23 @@ struct BankAffineStorePattern caseValues.push_back(i); rewriter.setInsertionPoint(storeOp); - scf::IndexSwitchOp switchOp = rewriter.create( - loc, resultTypes, bankIndex, caseValues, + scf::IndexSwitchOp switchOp = scf::IndexSwitchOp::create( + rewriter, loc, resultTypes, bankIndex, caseValues, /*numRegions=*/currFactor); for (unsigned i = 0; i < currFactor; ++i) { Region &caseRegion = switchOp.getCaseRegions()[i]; rewriter.setInsertionPointToStart(&caseRegion.emplaceBlock()); - rewriter.create( - loc, storeOp.getValueToStore(), banks[i], newIndices); - rewriter.create(loc); + mlir::affine::AffineStoreOp::create( + rewriter, loc, storeOp.getValueToStore(), banks[i], newIndices); + scf::YieldOp::create(rewriter, loc); } Region &defaultRegion = switchOp.getDefaultRegion(); assert(defaultRegion.empty() && "Default region should be empty"); rewriter.setInsertionPointToStart(&defaultRegion.emplaceBlock()); - rewriter.create(loc); + scf::YieldOp::create(rewriter, loc); processedOps.insert(storeOp); opsToErase.insert(storeOp); @@ -671,7 +671,7 @@ struct BankReturnPattern : public OpRewritePattern { func::FuncOp funcOp = returnOp.getParentOp(); rewriter.setInsertionPointToEnd(&funcOp.getBlocks().front()); auto newReturnOp = - rewriter.create(loc, ValueRange(newReturnOperands)); + func::ReturnOp::create(rewriter, loc, ValueRange(newReturnOperands)); TypeRange newReturnType = TypeRange(newReturnOperands); FunctionType newFuncType = FunctionType::get(funcOp.getContext(),