mirror of https://github.com/llvm/circt.git
[ESI] Make RAM delarations' addresses unsigned (#8658)
Using signless ints as the address was just wrong. It was probably done to avoid incomplete lowerings, which have been addressed. Changes RAM declaration addresses to use unsigned integer types throughout the ESI dialect and its tests, updating both the code generator and expected outputs. - Switch address ports to unsigned (uiN) in MLIR tests and service definitions. - Update service port generation and SystemVerilog memory instantiation to use unsigned address types, inserting bitcasts to signless for indexing. - Adjust PyCDE front end and software integration tests to use UInt addressing.
This commit is contained in:
John Demme
GitHub
parent
137b13de04
commit
8c1865c5a9
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@ -36,7 +36,7 @@ assert dummy_info is not None
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def read(addr: int) -> bytearray:
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mem_read_addr.write([addr])
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mem_read_addr.write(addr)
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resp = cast(bytearray, mem_read_data.read())
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print(f"resp: {resp}")
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return resp
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@ -45,7 +45,7 @@ def read(addr: int) -> bytearray:
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# The contents of address 3 are continuously updated to the contents of address
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# 2 by the accelerator.
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data = bytearray([random.randint(0, 2**8 - 1) for _ in range(8)])
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mem_write.write({"address": [2], "data": data})
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mem_write.write({"address": 2, "data": data})
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resp = read(2)
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try_count = 0
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@ -64,6 +64,6 @@ assert resp == data
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# Check this by writing to address 3 and reading from it. Shouldn't have
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# changed.
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zeros = bytearray([0] * 8)
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mem_write.write({"address": [3], "data": zeros})
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mem_write.write({"address": 3, "data": zeros})
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resp = read(3)
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assert resp == data
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@ -465,7 +465,7 @@ def DeclareRandomAccessMemory(inner_type: Type,
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class DeclareRandomAccessMemory(ServiceDecl):
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__name__ = name
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address_width = (depth - 1).bit_length()
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address_type = Bits(address_width)
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address_type = UInt(address_width)
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write_struct = StructType([('address', address_type), ('data', inner_type)])
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read = Bundle([
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@ -366,11 +366,11 @@ def Writer(type):
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# CHECK: hw.module @Ram1(in %clk : !seq.clock, in %rst : i1)
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# CHECK: esi.service.instance #esi.appid<"ram"> svc @ram impl as "sv"(%clk, %rst) : (!seq.clock, i1) -> ()
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# CHECK: [[WR:%.+]] = esi.service.req <@ram::@write>(#esi.appid<"ram_writer"[0]>) : !esi.bundle<[!esi.channel<!hw.struct<address: i3, data: i32>> from "req", !esi.channel<i0> to "ack"]>
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# CHECK: [[WR:%.+]] = esi.service.req <@ram::@write>(#esi.appid<"ram_writer"[0]>) : !esi.bundle<[!esi.channel<!hw.struct<address: ui3, data: i32>> from "req", !esi.channel<i0> to "ack"]>
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# CHECK: %rawOutput, %valid = esi.unwrap.vr %req, %ready : !hw.struct<address: ui3, data: ui32>
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# CHECK: [[CASTED:%.+]] = hw.bitcast %rawOutput : (!hw.struct<address: ui3, data: ui32>) -> !hw.struct<address: i3, data: i32>
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# CHECK: %chanOutput, %ready = esi.wrap.vr [[CASTED]], %valid : !hw.struct<address: i3, data: i32>
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# CHECK: %ack = esi.bundle.unpack %chanOutput from [[WR]] : !esi.bundle<[!esi.channel<!hw.struct<address: i3, data: i32>> from "req", !esi.channel<i0> to "ack"]>
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# CHECK: [[CASTED:%.+]] = hw.bitcast %rawOutput : (!hw.struct<address: ui3, data: ui32>) -> !hw.struct<address: ui3, data: i32>
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# CHECK: %chanOutput, %ready = esi.wrap.vr [[CASTED]], %valid : !hw.struct<address: ui3, data: i32>
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# CHECK: %ack = esi.bundle.unpack %chanOutput from [[WR]] : !esi.bundle<[!esi.channel<!hw.struct<address: ui3, data: i32>> from "req", !esi.channel<i0> to "ack"]>
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# CHECK: %bundle, %req = esi.bundle.pack %ack : !esi.bundle<[!esi.channel<!hw.struct<address: ui3, data: ui32>> from "req", !esi.channel<i0> to "ack"]>
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# CHECK: hw.instance "Writer" sym @Writer @Writer(clk: %clk: !seq.clock, rst: %rst: i1, cmd: %bundle: !esi.bundle<[!esi.channel<!hw.struct<address: ui3, data: ui32>> from "req", !esi.channel<i0> to "ack"]>) -> ()
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@ -93,7 +93,7 @@ hw.module @LoopbackArray() {
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}
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esi.mem.ram @MemA i64 x 20
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!write = !hw.struct<address: i5, data: i64>
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!write = !hw.struct<address: ui5, data: i64>
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!writeBundle = !esi.bundle<[!esi.channel<!write> from "req", !esi.channel<i0> to "ack"]>
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hw.module @MemoryAccess1(in %clk : !seq.clock, in %rst : i1) {
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@ -271,8 +271,11 @@ instantiateSystemVerilogMemory(ServiceImplementReqOp implReq,
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// Unwrap the requested address and read from that memory location.
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auto addressUnwrap =
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b.create<UnwrapValidReadyOp>(toServer, dataChannel.getReady());
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Value memLoc =
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b.create<sv::ArrayIndexInOutOp>(mem, addressUnwrap.getRawOutput());
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Value unsignedAddress = addressUnwrap.getRawOutput();
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Value signlessAddress = b.create<hw::BitcastOp>(
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b.getIntegerType(llvm::Log2_64_Ceil(ramDecl.getDepth())),
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unsignedAddress);
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Value memLoc = b.create<sv::ArrayIndexInOutOp>(mem, signlessAddress);
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auto readData = b.create<sv::ReadInOutOp>(memLoc);
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// Set the data on the response.
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@ -294,7 +297,10 @@ instantiateSystemVerilogMemory(ServiceImplementReqOp implReq,
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Value a = address, d = data; // So the lambda can capture.
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// If we're told to go, do the write.
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b.create<sv::IfOp>(go, [&] {
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Value memLoc = b.create<sv::ArrayIndexInOutOp>(mem, a);
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Value signlessAddress = b.create<hw::BitcastOp>(
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b.getIntegerType(llvm::Log2_64_Ceil(ramDecl.getDepth())), a);
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Value memLoc =
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b.create<sv::ArrayIndexInOutOp>(mem, signlessAddress);
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b.create<sv::PAssignOp>(memLoc, d);
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});
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}
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@ -39,7 +39,9 @@ static ServicePortInfo createReqResp(StringAttr sym, Twine name,
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ServicePortInfo RandomAccessMemoryDeclOp::writePortInfo() {
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auto *ctxt = getContext();
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auto addressType = IntegerType::get(ctxt, llvm::Log2_64_Ceil(getDepth()));
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auto addressType =
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IntegerType::get(ctxt, llvm::Log2_64_Ceil(getDepth()),
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IntegerType::SignednessSemantics::Unsigned);
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// Write port
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hw::StructType writeType = hw::StructType::get(
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@ -53,7 +55,9 @@ ServicePortInfo RandomAccessMemoryDeclOp::writePortInfo() {
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ServicePortInfo RandomAccessMemoryDeclOp::readPortInfo() {
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auto *ctxt = getContext();
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auto addressType = IntegerType::get(ctxt, llvm::Log2_64_Ceil(getDepth()));
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auto addressType =
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IntegerType::get(ctxt, llvm::Log2_64_Ceil(getDepth()),
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IntegerType::SignednessSemantics::Unsigned);
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return createReqResp(getSymNameAttr(), "read", "address", addressType, "data",
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getInnerType());
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@ -121,22 +121,24 @@ esi.pure_module @LoopbackCosimPure {
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}
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// CONN-LABEL: esi.mem.ram @MemA i64 x 20
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// CONN-LABEL: hw.module @MemoryAccess1(in %clk : !seq.clock, in %rst : i1, in %write : !esi.channel<!hw.struct<address: i5, data: i64>>, in %readAddress : !esi.channel<i5>, out readData : !esi.channel<i64>, out writeDone : !esi.channel<i0>) {
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// CONN-LABEL: hw.module @MemoryAccess1(in %clk : !seq.clock, in %rst : i1, in %write : !esi.channel<!hw.struct<address: ui5, data: i64>>, in %readAddress : !esi.channel<ui5>, out readData : !esi.channel<i64>, out writeDone : !esi.channel<i0>) {
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// CONN: %MemA = sv.reg : !hw.inout<uarray<20xi64>>
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// CONN: %chanOutput, %ready = esi.wrap.vr %c0_i0, %write_done : i0
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// CONN: %rawOutput, %valid = esi.unwrap.vr %write, %ready : !hw.struct<address: i5, data: i64>
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// CONN: %address = hw.struct_extract %rawOutput["address"] : !hw.struct<address: i5, data: i64>
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// CONN: %data = hw.struct_extract %rawOutput["data"] : !hw.struct<address: i5, data: i64>
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// CONN: %rawOutput, %valid = esi.unwrap.vr %write, %ready : !hw.struct<address: ui5, data: i64>
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// CONN: %address = hw.struct_extract %rawOutput["address"] : !hw.struct<address: ui5, data: i64>
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// CONN: %data = hw.struct_extract %rawOutput["data"] : !hw.struct<address: ui5, data: i64>
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// CONN: %[[ANDVR:.*]] = comb.and %valid, %ready {sv.namehint = "write_go"} : i1
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// CONN: %write_done = seq.compreg sym @write_done %[[ANDVR]], %clk reset %rst, %false : i1
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// CONN: %chanOutput_0, %ready_1 = esi.wrap.vr %[[MEMREAD:.*]], %valid_3 : i64
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// CONN: %rawOutput_2, %valid_3 = esi.unwrap.vr %readAddress, %ready_1 : i5
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// CONN: %[[MEMREADIO:.*]] = sv.array_index_inout %MemA[%rawOutput_2] : !hw.inout<uarray<20xi64>>, i5
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// CONN: %rawOutput_2, %valid_3 = esi.unwrap.vr %readAddress, %ready_1 : ui5
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// CONN: %[[ADDR:.*]] = hw.bitcast %rawOutput_2 : (ui5) -> i5
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// CONN: %[[MEMREADIO:.*]] = sv.array_index_inout %MemA[%[[ADDR]]] : !hw.inout<uarray<20xi64>>, i5
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// CONN: %[[MEMREAD]] = sv.read_inout %[[MEMREADIO]] : !hw.inout<i64>
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// CONN: %[[CLOCK:.+]] = seq.from_clock %clk
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// CONN: sv.alwaysff(posedge %[[CLOCK]]) {
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// CONN: sv.if %[[ANDVR]] {
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// CONN: %[[ARRIDX:.*]] = sv.array_index_inout %MemA[%address] : !hw.inout<uarray<20xi64>>, i5
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// CONN: %[[ADDR:.*]] = hw.bitcast %address : (ui5) -> i5
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// CONN: %[[ARRIDX:.*]] = sv.array_index_inout %MemA[%[[ADDR]]] : !hw.inout<uarray<20xi64>>, i5
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// CONN: sv.passign %[[ARRIDX]], %data : i64
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// CONN: }
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// CONN: }(syncreset : posedge %rst) {
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@ -144,11 +146,11 @@ esi.pure_module @LoopbackCosimPure {
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// CONN: hw.output %chanOutput_0, %chanOutput : !esi.channel<i64>, !esi.channel<i0>
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esi.mem.ram @MemA i64 x 20
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!write = !hw.struct<address: i5, data: i64>
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!write = !hw.struct<address: ui5, data: i64>
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!writeBundle = !esi.bundle<[!esi.channel<!write> from "req", !esi.channel<i0> to "ack"]>
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!readBundle = !esi.bundle<[!esi.channel<i5> from "address", !esi.channel<i64> to "data"]>
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!readBundle = !esi.bundle<[!esi.channel<ui5> from "address", !esi.channel<i64> to "data"]>
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hw.module @MemoryAccess1(in %clk : !seq.clock, in %rst : i1, in %write : !esi.channel<!write>, in %readAddress : !esi.channel<i5>, out readData : !esi.channel<i64>, out writeDone : !esi.channel<i0>) {
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hw.module @MemoryAccess1(in %clk : !seq.clock, in %rst : i1, in %write : !esi.channel<!write>, in %readAddress : !esi.channel<ui5>, out readData : !esi.channel<i64>, out writeDone : !esi.channel<i0>) {
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esi.service.instance #esi.appid<"mem"> svc @MemA impl as "sv_mem" (%clk, %rst) : (!seq.clock, i1) -> ()
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%writeBundle = esi.service.req <@MemA::@write> (#esi.appid<"write">) : !writeBundle
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%done = esi.bundle.unpack %write from %writeBundle : !writeBundle
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@ -158,11 +160,11 @@ hw.module @MemoryAccess1(in %clk : !seq.clock, in %rst : i1, in %write : !esi.ch
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hw.output %readData, %done : !esi.channel<i64>, !esi.channel<i0>
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}
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// CONN-LABEL: hw.module @MemoryAccess2Read(in %clk : !seq.clock, in %rst : i1, in %write : !esi.channel<!hw.struct<address: i5, data: i64>>, in %readAddress : !esi.channel<i5>, in %readAddress2 : !esi.channel<i5>, out readData : !esi.channel<i64>, out readData2 : !esi.channel<i64>, out writeDone : !esi.channel<i0>) {
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// CONN-LABEL: hw.module @MemoryAccess2Read(in %clk : !seq.clock, in %rst : i1, in %write : !esi.channel<!hw.struct<address: ui5, data: i64>>, in %readAddress : !esi.channel<ui5>, in %readAddress2 : !esi.channel<ui5>, out readData : !esi.channel<i64>, out readData2 : !esi.channel<i64>, out writeDone : !esi.channel<i0>) {
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// CONN: %MemA = sv.reg : !hw.inout<uarray<20xi64>>
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// CONN: hw.output %chanOutput_0, %chanOutput_4, %chanOutput : !esi.channel<i64>, !esi.channel<i64>, !esi.channel<i0>
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hw.module @MemoryAccess2Read(in %clk: !seq.clock, in %rst: i1, in %write: !esi.channel<!write>, in %readAddress: !esi.channel<i5>, in %readAddress2: !esi.channel<i5>, out readData: !esi.channel<i64>, out readData2: !esi.channel<i64>, out writeDone: !esi.channel<i0>) {
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hw.module @MemoryAccess2Read(in %clk: !seq.clock, in %rst: i1, in %write: !esi.channel<!write>, in %readAddress: !esi.channel<ui5>, in %readAddress2: !esi.channel<ui5>, out readData: !esi.channel<i64>, out readData2: !esi.channel<i64>, out writeDone: !esi.channel<i0>) {
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esi.service.instance #esi.appid<"mem"> svc @MemA impl as "sv_mem" (%clk, %rst) : (!seq.clock, i1) -> ()
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%writeBundle = esi.service.req <@MemA::@write> (#esi.appid<"write">) : !writeBundle
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@ -27,10 +27,10 @@
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// CHECK-SAME: in %reset : i1,
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// CHECK-SAME: out out0 : !esi.channel<i0>
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// CHECK-SAME: ) {
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//CHECK-NEXT: [[B0:%.+]] = esi.service.req <@mem::@read>(#esi.appid<"load"[1]>) : !esi.bundle<[!esi.channel<i4> from "address", !esi.channel<i32> to "data"]>
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//CHECK-NEXT: %data = esi.bundle.unpack %main.mem_ld0.addr from [[B0]] : !esi.bundle<[!esi.channel<i4> from "address", !esi.channel<i32> to "data"]>
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//CHECK-NEXT: [[B1:%.+]] = esi.service.req <@mem::@write>(#esi.appid<"store"[2]>) : !esi.bundle<[!esi.channel<!hw.struct<address: i4, data: i32>> from "req", !esi.channel<i0> to "ack"]>
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//CHECK-NEXT: %ack = esi.bundle.unpack %main.mem_st0 from [[B1]] : !esi.bundle<[!esi.channel<!hw.struct<address: i4, data: i32>> from "req", !esi.channel<i0> to "ack"]>
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//CHECK-NEXT: [[B0:%.+]] = esi.service.req <@mem::@read>(#esi.appid<"load"[1]>) : !esi.bundle<[!esi.channel<ui4> from "address", !esi.channel<i32> to "data"]>
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//CHECK-NEXT: %data = esi.bundle.unpack %main.mem_ld0.addr from [[B0]] : !esi.bundle<[!esi.channel<ui4> from "address", !esi.channel<i32> to "data"]>
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//CHECK-NEXT: [[B1:%.+]] = esi.service.req <@mem::@write>(#esi.appid<"store"[2]>) : !esi.bundle<[!esi.channel<!hw.struct<address: ui4, data: i32>> from "req", !esi.channel<i0> to "ack"]>
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//CHECK-NEXT: %ack = esi.bundle.unpack %main.mem_st0 from [[B1]] : !esi.bundle<[!esi.channel<!hw.struct<address: ui4, data: i32>> from "req", !esi.channel<i0> to "ack"]>
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//CHECK-NEXT: %main.out0, %main.mem_ld0.addr, %main.mem_st0 = hw.instance "main" @__main_hw(arg0: %arg0: !esi.channel<i64>, arg1: %arg1: !esi.channel<i64>, v: %v: !esi.channel<i32>, mem_ld0.data: %data: !esi.channel<i32>, mem_st0.done: %ack: !esi.channel<i0>, argCtrl: %argCtrl: !esi.channel<i0>, clock: %clock: !seq.clock, reset: %reset: i1) -> (out0: !esi.channel<i0>, mem_ld0.addr: !esi.channel<i4>, mem_st0: !esi.channel<!hw.struct<address: i4, data: i32>>)
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//CHECK-NEXT: hw.output %main.out0 : !esi.channel<i0>
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//CHECK-NEXT: }
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